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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 527360 (0x80c00)
Types: M200_UCODE
Names: »M207_45.M200_UCODE«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─⟦this⟧ »M207_45.M200_UCODE«
└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
└─⟦this⟧ »M207_45.M200_UCODE«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─⟦this⟧ »M207_45.M200_UCODE«
0100 ; -------------------------------------------------------------------------------------- 0100 ; no details_b223d4 0100 ; Initial Register File (adr, typ, val, frame:offset) where non-zero 0100 ; 000 TR00:00 0000000000000100 VR00:00 0000000008000000 0100 ; 001 TR00:01 00000000c0000000 VR00:01 0000000048000000 0100 ; 002 TR00:02 0000000068000060 VR00:02 0000000088000000 0100 ; 003 TR00:03 00000000a8000060 VR00:03 0000000000000000 0100 ; 004 TR00:04 0000000000000058 VR00:04 0000000000000000 0100 ; 005 TR00:05 0000000000000005 VR00:05 0000000000000000 0100 ; 006 TR00:06 0000000000000000 VR00:06 0000000000000000 0100 ; 007 TR00:07 0000000000000000 VR00:07 0000000000000000 0100 ; 008 TR00:08 0000000000000000 VR00:08 0000000000000000 0100 ; 009 TR00:09 0000000000000000 VR00:09 0000000000000000 0100 ; 00a TR00:0a 0000000000000000 VR00:0a 0000000000000000 0100 ; 00b TR00:0b 0000000000000000 VR00:0b 0000000000000000 0100 ; 00c TR00:0c 0000000000000000 VR00:0c 0000000000000000 0100 ; 00d TR00:0d 0000000000000000 VR00:0d 0000000000000000 0100 ; 00e TR00:0e 0000000000000000 VR00:0e 0000000000000000 0100 ; 00f TR00:0f 0000000000000000 VR00:0f 0000000000000000 0100 ; 010 TR00:10 0000000000000000 VR00:10 0000000000000000 0100 ; 011 TR00:11 0000000000000000 VR00:11 0000000000000000 0100 ; 012 TR00:12 0000000000000000 VR00:12 0000000000000000 0100 ; 013 TR00:13 0000000000000000 VR00:13 0000000000000000 0100 ; 014 TR00:14 0000000000000000 VR00:14 0000000000000000 0100 ; 015 TR00:15 0000000000000000 VR00:15 0000000000000000 0100 ; 016 TR00:16 0000000000000000 VR00:16 0000000000000000 0100 ; 017 TR00:17 0000000000000000 VR00:17 0000000000000000 0100 ; 018 TR00:18 0000000000000000 VR00:18 0000000000000000 0100 ; 019 TR00:19 0000000000000000 VR00:19 0000000000000000 0100 ; 01a TR00:1a 0000000000000000 VR00:1a 0000000000000000 0100 ; 01b TR00:1b 0000000000000000 VR00:1b 0000000000000000 0100 ; 01c TR00:1c 0000000000000000 VR00:1c 0000000000000000 0100 ; 01d TR00:1d 0000000000000000 VR00:1d 0000000000000000 0100 ; 01e TR00:1e 0000000000000000 VR00:1e 0000000000000000 0100 ; 01f TR00:1f 0000000000000000 VR00:1f 0000000000000000 0100 ; 020 TR01:00 ffffffffffffff00 VR01:00 0000000000000000 0100 ; 021 TR01:01 0000000080000000 VR01:01 0000000000000000 0100 ; 022 TR01:02 0000000040000000 VR01:02 0000000000000000 0100 ; 023 TR01:03 0000000020000000 VR01:03 0000000000000000 0100 ; 024 TR01:04 0000000000000000 VR01:04 0000000000000000 0100 ; 025 TR01:05 0000000000000000 VR01:05 0000000000000000 0100 ; 026 TR01:06 0000000000000000 VR01:06 0000000000000000 0100 ; 027 TR01:07 0000000000000000 VR01:07 0000000000000000 0100 ; 028 TR01:08 0000000000000000 VR01:08 0000000000000000 0100 ; 029 TR01:09 0000000000000000 VR01:09 0000000000000000 0100 ; 02a TR01:0a 0000000000000000 VR01:0a 0000000000000000 0100 ; 02b TR01:0b 0000000000000000 VR01:0b 0000000000000000 0100 ; 02c TR01:0c 0000000000000000 VR01:0c 0000000000000000 0100 ; 02d TR01:0d 0000000000000000 VR01:0d 0000000000000000 0100 ; 02e TR01:0e 0000000000000000 VR01:0e 0000000000000000 0100 ; 02f TR01:0f 0000000000000000 VR01:0f 0000000000000000 0100 ; 030 TR01:10 0000000000000000 VR01:10 0000000000000000 0100 ; 031 TR01:11 0000000000000000 VR01:11 0000000000000000 0100 ; 032 TR01:12 0000000000000000 VR01:12 0000000000000000 0100 ; 033 TR01:13 0000000000000000 VR01:13 0000000000000000 0100 ; 034 TR01:14 0000000000000000 VR01:14 0000000000000000 0100 ; 035 TR01:15 0000000000000000 VR01:15 0000000000000000 0100 ; 036 TR01:16 0000000000000000 VR01:16 0000000000000000 0100 ; 037 TR01:17 0000000000000000 VR01:17 0000000000000000 0100 ; 038 TR01:18 0000000000000000 VR01:18 0000000000000000 0100 ; 039 TR01:19 0000000000000000 VR01:19 0000000000000000 0100 ; 03a TR01:1a 0000000000000000 VR01:1a 0000000000000000 0100 ; 03b TR01:1b 0000000000000000 VR01:1b 0000000000000000 0100 ; 03c TR01:1c 0000000000000000 VR01:1c 0000000000000000 0100 ; 03d TR01:1d 0000000000000000 VR01:1d 0000000000000000 0100 ; 03e TR01:1e 0000000000000000 VR01:1e 0000000000000000 0100 ; 03f TR01:1f 0000000000000000 VR01:1f 0000000000000000 0100 ; 040 TR02:00 0000000000000001 VR02:00 0000000000000010 0100 ; 041 TR02:01 000000000000003f VR02:01 0000000000000000 0100 ; 042 TR02:02 0000000000000000 VR02:02 0000000000000000 0100 ; 043 TR02:03 0000000000000021 VR02:03 0000000000000000 0100 ; 044 TR02:04 0000000000000029 VR02:04 0000000000000000 0100 ; 045 TR02:05 0000000000000000 VR02:05 0000000000000000 0100 ; 046 TR02:06 0000000000000300 VR02:06 0000000000000000 0100 ; 047 TR02:07 0000000010000000 VR02:07 0000000000000000 0100 ; 048 TR02:08 0000000018000000 VR02:08 0000000000000000 0100 ; 049 TR02:09 0000000020000000 VR02:09 0000000000000000 0100 ; 04a TR02:0a 0000000000000009 VR02:0a 0000000000000000 0100 ; 04b TR02:0b ffffffffffffff80 VR02:0b 0000000000000000 0100 ; 04c TR02:0c 000007c000000000 VR02:0c 0000000000000000 0100 ; 04d TR02:0d 0000000000000029 VR02:0d 0400000000000000 0100 ; 04e TR02:0e 0000000000000021 VR02:0e ff00000000000000 0100 ; 04f TR02:0f 0000000000000000 VR02:0f 0000000000000000 0100 ; 050 TR02:10 0000000040000000 VR02:10 ffffffffffffffff 0100 ; 051 TR02:11 0000000000000008 VR02:11 0000000000000001 0100 ; 052 TR02:12 0000000000000000 VR02:12 0000000000000040 0100 ; 053 TR02:13 0000000000000400 VR02:13 0000000000001fff 0100 ; 054 TR02:14 0000001000000000 VR02:14 0000000010000000 0100 ; 055 TR02:15 0000000008000000 VR02:15 0000000020000000 0100 ; 056 TR02:16 000000000000007e VR02:16 0000000030000000 0100 ; 057 TR02:17 0000800000000000 VR02:17 00000000f8000080 0100 ; 058 TR02:18 0000000000000000 VR02:18 000000000000007f 0100 ; 059 TR02:19 000000000000007f VR02:19 0000000000000000 0100 ; 05a TR02:1a 000000000000003f VR02:1a 0000000000000002 0100 ; 05b TR02:1b 0000000000000000 VR02:1b 00000000ffffffff 0100 ; 05c TR02:1c 0000000008000000 VR02:1c 0000000000000000 0100 ; 05d TR02:1d 00000000f8000000 VR02:1d 0000000000000010 0100 ; 05e TR02:1e 0000000007ffff80 VR02:1e 0000000007ffff80 0100 ; 05f TR02:1f 0000000000000180 VR02:1f 0000000000000060 0100 ; 060 TR03:00 0000000000000000 VR03:00 0000000000000000 0100 ; 061 TR03:01 0000000000000000 VR03:01 0000000000000000 0100 ; 062 TR03:02 0000000000000000 VR03:02 0000000000000000 0100 ; 063 TR03:03 0000000000000000 VR03:03 0000000000000000 0100 ; 064 TR03:04 0000000000000000 VR03:04 0000000000000000 0100 ; 065 TR03:05 0000000000000000 VR03:05 0000000000000000 0100 ; 066 TR03:06 0000000000000000 VR03:06 0000000000000000 0100 ; 067 TR03:07 0000000000000000 VR03:07 0000000000000000 0100 ; 068 TR03:08 0000000000000000 VR03:08 0000000000000000 0100 ; 069 TR03:09 0000000000000000 VR03:09 0000000000000000 0100 ; 06a TR03:0a 0000000000000000 VR03:0a 0000000000000000 0100 ; 06b TR03:0b 0000000000000000 VR03:0b 0000000000000000 0100 ; 06c TR03:0c 0000000000000000 VR03:0c 0000000000000000 0100 ; 06d TR03:0d 0000000000000000 VR03:0d 0000000000000000 0100 ; 06e TR03:0e 0000000000000000 VR03:0e 0000000000000000 0100 ; 06f TR03:0f 0000000000000000 VR03:0f 0000000000000000 0100 ; 070 TR03:10 0000000000000000 VR03:10 0000000000000004 0100 ; 071 TR03:11 0000000000000000 VR03:11 0000000000000000 0100 ; 072 TR03:12 0000000000000000 VR03:12 0000000000000000 0100 ; 073 TR03:13 0000000000000000 VR03:13 0000000000000000 0100 ; 074 TR03:14 0000000000000000 VR03:14 0000000000000000 0100 ; 075 TR03:15 0000000000000000 VR03:15 0000000000000000 0100 ; 076 TR03:16 0000000000000000 VR03:16 0000000000000000 0100 ; 077 TR03:17 0000000000000000 VR03:17 0bad0bad0bad0bad 0100 ; 078 TR03:18 0404000100000000 VR03:18 0000000000000000 0100 ; 079 TR03:19 0000000000000000 VR03:19 0000000000000000 0100 ; 07a TR03:1a 0000000000000000 VR03:1a 0000000000000000 0100 ; 07b TR03:1b 0000000000000000 VR03:1b 0000200000000000 0100 ; 07c TR03:1c 0000000000000000 VR03:1c 0000000000000000 0100 ; 07d TR03:1d 0000000000000000 VR03:1d 0000000000000000 0100 ; 07e TR03:1e 0000000000000000 VR03:1e 0000000000000004 0100 ; 07f TR03:1f 0000000000000000 VR03:1f 0000000000000000 0100 ; 080 TR04:00 0000000000000000 VR04:00 0000000000000000 0100 ; 081 TR04:01 0000000000000000 VR04:01 0000000000000001 0100 ; 082 TR04:02 0000000000000000 VR04:02 0000000000000000 0100 ; 083 TR04:03 0000000000000000 VR04:03 0000000000000000 0100 ; 084 TR04:04 0000000000000000 VR04:04 0000000000000000 0100 ; 085 TR04:05 0000000000000000 VR04:05 0000000000000000 0100 ; 086 TR04:06 0000000000000000 VR04:06 0000000000000000 0100 ; 087 TR04:07 0000000000000000 VR04:07 0000000000000000 0100 ; 088 TR04:08 0000000000000000 VR04:08 0000000000000000 0100 ; 089 TR04:09 0000000000000000 VR04:09 0000000000000000 0100 ; 08a TR04:0a 0000000000000028 VR04:0a 0000000000000000 0100 ; 08b TR04:0b 0000000000000000 VR04:0b 0000000000000000 0100 ; 08c TR04:0c 0000000000000000 VR04:0c 0000000000000000 0100 ; 08d TR04:0d 0000000000000180 VR04:0d 0000000000000080 0100 ; 08e TR04:0e 0000000000000000 VR04:0e 0000000000000100 0100 ; 08f TR04:0f 0000000000000000 VR04:0f 0000000000000180 0100 ; 090 TR04:10 0000000000000000 VR04:10 0000000000000500 0100 ; 091 TR04:11 0000000000000000 VR04:11 0000000000001f80 0100 ; 092 TR04:12 0000000000000000 VR04:12 000ffcf00000a000 0100 ; 093 TR04:13 0000000000000000 VR04:13 0000000000200000 0100 ; 094 TR04:14 0000000000000000 VR04:14 0000000000000000 0100 ; 095 TR04:15 0000000000000000 VR04:15 0000000000000000 0100 ; 096 TR04:16 0000000000000000 VR04:16 0000000000000000 0100 ; 097 TR04:17 0000000000000000 VR04:17 0000000000000000 0100 ; 098 TR04:18 0000000000000000 VR04:18 0000000000000000 0100 ; 099 TR04:19 0000000000000000 VR04:19 0000000000000000 0100 ; 09a TR04:1a 0000000000000000 VR04:1a 0000000000000000 0100 ; 09b TR04:1b 0000000000000000 VR04:1b 000000000000a000 0100 ; 09c TR04:1c 0000000000000000 VR04:1c 0000040000000000 0100 ; 09d TR04:1d 0000000000000000 VR04:1d 0000000000000000 0100 ; 09e TR04:1e 0000000000000000 VR04:1e 0000000000000000 0100 ; 09f TR04:1f 0000000000000000 VR04:1f 0000000000000000 0100 ; 0a0 TR05:00 0000000000000001 VR05:00 0000000000000001 0100 ; 0a1 TR05:01 0000000000000004 VR05:01 0000000000000003 0100 ; 0a2 TR05:02 0000004000000000 VR05:02 0000000000000005 0100 ; 0a3 TR05:03 0000000000000006 VR05:03 0000000000000006 0100 ; 0a4 TR05:04 000000000000000a VR05:04 0000000000000007 0100 ; 0a5 TR05:05 000000000000000e VR05:05 0000000000000008 0100 ; 0a6 TR05:06 000000000000000f VR05:06 0000000000000009 0100 ; 0a7 TR05:07 0000000000000013 VR05:07 000000000000000a 0100 ; 0a8 TR05:08 0000000000000014 VR05:08 000000000000000b 0100 ; 0a9 TR05:09 0000000000000016 VR05:09 000000000000000c 0100 ; 0aa TR05:0a 0000000000000026 VR05:0a 000000000000000d 0100 ; 0ab TR05:0b 0000000000000036 VR05:0b 000000000000000e 0100 ; 0ac TR05:0c 0000000000000039 VR05:0c 0000000000002300 0100 ; 0ad TR05:0d 0000000000000040 VR05:0d 0000000000000020 0100 ; 0ae TR05:0e 0000000000000046 VR05:0e 0000000000000025 0100 ; 0af TR05:0f 000000000000005f VR05:0f 0000000000000031 0100 ; 0b0 TR05:10 0000000000000060 VR05:10 000000000000003f 0100 ; 0b1 TR05:11 000000f000000000 VR05:11 00000000fff90000 0100 ; 0b2 TR05:12 000000000000007b VR05:12 0000000000000480 0100 ; 0b3 TR05:13 0000000000000680 VR05:13 000000000000006c 0100 ; 0b4 TR05:14 000000000000009e VR05:14 0000000000000074 0100 ; 0b5 TR05:15 0000000000000118 VR05:15 000000000000007c 0100 ; 0b6 TR05:16 0000000000000158 VR05:16 00000000000000ff 0100 ; 0b7 TR05:17 0000000000000200 VR05:17 0000000000000076 0100 ; 0b8 TR05:18 0000000000000300 VR05:18 0000000000000200 0100 ; 0b9 TR05:19 0000000000000380 VR05:19 0000000000000580 0100 ; 0ba TR05:1a 0000000000000800 VR05:1a 00000000000003ff 0100 ; 0bb TR05:1b 0000000000001f80 VR05:1b 0000000000000400 0100 ; 0bc TR05:1c 0000000007ff8000 VR05:1c 0000000000002400 0100 ; 0bd TR05:1d 0000000008000008 VR05:1d 0000010000000000 0100 ; 0be TR05:1e 0000000008000046 VR05:1e 000000000000ffff 0100 ; 0bf TR05:1f 0000000000000047 VR05:1f 5f5f5f5f5f5f5f5f 0100 ; 0c0 TR06:00 000000000800009e VR06:00 0000000040000000 0100 ; 0c1 TR06:01 0000000020000060 VR06:01 000000000000000f 0100 ; 0c2 TR06:02 00000000f6000000 VR06:02 0000000080000000 0100 ; 0c3 TR06:03 0d04000f00000001 VR06:03 0002000000000000 0100 ; 0c4 TR06:04 0000000080000118 VR06:04 fffffeff00000000 0100 ; 0c5 TR06:05 0000000080000158 VR06:05 00000000000000f0 0100 ; 0c6 TR06:06 0000000088000000 VR06:06 0000000000008000 0100 ; 0c7 TR06:07 fffffffffffffe80 VR06:07 00000000c0000000 0100 ; 0c8 TR06:08 0000000000000580 VR06:08 0000000100000001 0100 ; 0c9 TR06:09 0000000000000064 VR06:09 0000004000000040 0100 ; 0ca TR06:0a 0000000000000015 VR06:0a 0000004100000041 0100 ; 0cb TR06:0b 0000000007ffe000 VR06:0b 0000007fffffffff 0100 ; 0cc TR06:0c 000000000800006c VR06:0c 000000000004c4b4 0100 ; 0cd TR06:0d 00000000000002a0 VR06:0d 0000000000000028 0100 ; 0ce TR06:0e 00000000ffff0000 VR06:0e 0004000000000000 0100 ; 0cf TR06:0f 0000000f00000000 VR06:0f 0000000000000032 0100 ; 0d0 TR06:10 ffffffffc0000000 VR06:10 00ffffff0000000f 0100 ; 0d1 TR06:11 ff00000000000000 VR06:11 0200000000000000 0100 ; 0d2 TR06:12 00000000e0000176 VR06:12 8000000000000000 0100 ; 0d3 TR06:13 ffff000000000000 VR06:13 8200000000000000 0100 ; 0d4 TR06:14 00000000000000c0 VR06:14 0000000000000041 0100 ; 0d5 TR06:15 ffffffffffff0000 VR06:15 00000000000002a0 0100 ; 0d6 TR06:16 fffffffffffffe00 VR06:16 000000007fffffff 0100 ; 0d7 TR06:17 000000000000000d VR06:17 ffffffff80000000 0100 ; 0d8 TR06:18 0000000000000076 VR06:18 0000000000000027 0100 ; 0d9 TR06:19 00000000d0000000 VR06:19 00000000000010c0 0100 ; 0da TR06:1a 0000000008000000 VR06:1a 0000000000000042 0100 ; 0db TR06:1b 000000000000002e VR06:1b 00000000000000fe 0100 ; 0dc TR06:1c fffffffffffffd00 VR06:1c 0000000000001008 0100 ; 0dd TR06:1d 0000000000000039 VR06:1d 0000000100000000 0100 ; 0de TR06:1e 00000000c0000116 VR06:1e 0000000200000000 0100 ; 0df TR06:1f 0000000000002000 VR06:1f 0000000000002000 0100 ; 0e0 TR07:00 0000000000000280 VR07:00 ffffffffffffff80 0100 ; 0e1 TR07:01 0000003000000000 VR07:01 000fffff00000000 0100 ; 0e2 TR07:02 ffff00000000000e VR07:02 0100000000000000 0100 ; 0e3 TR07:03 0000000060000000 VR07:03 0000000000000011 0100 ; 0e4 TR07:04 000000000000016c VR07:04 000000000000fff0 0100 ; 0e5 TR07:05 00ff000000000000 VR07:05 0000ffffffffffff 0100 ; 0e6 TR07:06 0001000000000000 VR07:06 000000000000004e 0100 ; 0e7 TR07:07 0000005000000000 VR07:07 0000000000000f80 0100 ; 0e8 TR07:08 00000000f0000000 VR07:08 ffffffff00000000 0100 ; 0e9 TR07:09 0000000048000000 VR07:09 7fffffffffffffff 0100 ; 0ea TR07:0a 0000000030000000 VR07:0a 0000000000000026 0100 ; 0eb TR07:0b 0000000088000011 VR07:0b 0000000000000036 0100 ; 0ec TR07:0c 00000000a8000071 VR07:0c 0000008000000040 0100 ; 0ed TR07:0d 0000000000000174 VR07:0d 0000000000000280 0100 ; 0ee TR07:0e 0000000080000029 VR07:0e 0000000000000380 0100 ; 0ef TR07:0f 0000007f00000000 VR07:0f 0000000000000021 0100 ; 0f0 TR07:10 0100000000000000 VR07:10 0000000000000016 0100 ; 0f1 TR07:11 0200000000000000 VR07:11 00000000ffff00ff 0100 ; 0f2 TR07:12 fec7000000000000 VR07:12 0000000000000012 0100 ; 0f3 TR07:13 0000000000001001 VR07:13 0000000000000043 0100 ; 0f4 TR07:14 000000000ff00000 VR07:14 00000000000000a0 0100 ; 0f5 TR07:15 00000000ffffffff VR07:15 ffffffffffffff00 0100 ; 0f6 TR07:16 0000037000000000 VR07:16 0000800000000000 0100 ; 0f7 TR07:17 000000000000003e VR07:17 0000005500000000 0100 ; 0f8 TR07:18 0000040400000050 VR07:18 8000005500000000 0100 ; 0f9 TR07:19 0000000040000020 VR07:19 0000000000000038 0100 ; 0fa TR07:1a 000000000000004e VR07:1a 0000000088000011 0100 ; 0fb TR07:1b 00000000000000ff VR07:1b ffffff8000000000 0100 ; 0fc TR07:1c 00000001ffffffff VR07:1c 0000008000000000 0100 ; 0fd TR07:1d 00000000f800007f VR07:1d 0000007f00000000 0100 ; 0fe TR07:1e 0000000080000010 VR07:1e 0000000000000045 0100 ; 0ff TR07:1f 0000000000000081 VR07:1f 0000000000000044 0100 ; 100 TR08:00 ffffffffffffffff VR08:00 00fe007f00000000 0100 ; 101 TR08:01 0000000060000060 VR08:01 00000000003fffff 0100 ; 102 TR08:02 0000000000000044 VR08:02 0001000000000000 0100 ; 103 TR08:03 ffffffffffffffe0 VR08:03 000000000000004c 0100 ; 104 TR08:04 000ffc000000a000 VR08:04 0000000000000013 0100 ; 105 TR08:05 0000008000000000 VR08:05 0000000000000030 0100 ; 106 TR08:06 000007c008000000 VR08:06 00000000000005ff 0100 ; 107 TR08:07 ffffffffe0000000 VR08:07 00ff000000000000 0100 ; 108 TR08:08 fffffffffffffecc VR08:08 1000000000000000 0100 ; 109 TR08:09 000000000800014c VR08:09 0000001000000000 0100 ; 10a TR08:0a 0000000007ffbf00 VR08:0a 00008000ffffffff 0100 ; 10b TR08:0b 8000000000000000 VR08:0b 0000808000000000 0100 ; 10c TR08:0c 2000000000000000 VR08:0c 00000000000000e0 0100 ; 10d TR08:0d 0000000000000050 VR08:0d 00000000000000e1 0100 ; 10e TR08:0e 000000003800001f VR08:0e 00000000000000e2 0100 ; 10f TR08:0f 0000000100000000 VR08:0f 00000000000000e3 0100 ; 110 TR08:10 fffff83ff7ffffff VR08:10 00000000000000e4 0100 ; 111 TR08:11 0000000000000054 VR08:11 0000000000000061 0100 ; 112 TR08:12 000000000000017c VR08:12 0000000000000062 0100 ; 113 TR08:13 1020a040101011c0 VR08:13 0000000000000063 0100 ; 114 TR08:14 000000000000001c VR08:14 0000000000000065 0100 ; 115 TR08:15 000000000000001b VR08:15 000000000000002f 0100 ; 116 TR08:16 0000000080000008 VR08:16 000000000000004f 0100 ; 117 TR08:17 0000000000004000 VR08:17 000000000000005f 0100 ; 118 TR08:18 0000000088000008 VR08:18 000000000000fe00 0100 ; 119 TR08:19 0000060000000000 VR08:19 fffe010000000080 0100 ; 11a TR08:1a 00000000a0000068 VR08:1a 0000000000002710 0100 ; 11b TR08:1b 0000000020000068 VR08:1b 0001ff8000000000 0100 ; 11c TR08:1c 0010000000000000 VR08:1c 0000000000000049 0100 ; 11d TR08:1d 000000000000001f VR08:1d 0408000000000000 0100 ; 11e TR08:1e 7ff0000000000000 VR08:1e 8204000000000000 0100 ; 11f TR08:1f 3ff0000000000000 VR08:1f 00000000000000d0 0100 ; 120 TR09:00 7fe0000000000000 VR09:00 000000000000007b 0100 ; 121 TR09:01 00000000000003ff VR09:01 00f0000000000000 0100 ; 122 TR09:02 00000000000007ff VR09:02 0000000000000300 0100 ; 123 TR09:03 ffffffffffffffcd VR09:03 0000000000000034 0100 ; 124 TR09:04 00000000e0000060 VR09:04 000000000000fc00 0100 ; 125 TR09:05 00000000e0000020 VR09:05 fff9000000000000 0100 ; 126 TR09:06 000000000000031f VR09:06 0000000000000070 0100 ; 127 TR09:07 00000000000000a0 VR09:07 1819113111161715 0100 ; 128 TR09:08 00000000e0000000 VR09:08 0000000000000014 0100 ; 129 TR09:09 0000000040000029 VR09:09 0000000008000100 0100 ; 12a TR09:0a 000000000fffff80 VR09:0a 0000000028000160 0100 ; 12b TR09:0b 00000000000000ad VR09:0b 00000000000002d0 0100 ; 12c TR09:0c 00000000e0000040 VR09:0c bff0000000000000 0100 ; 12d TR09:0d 000000000000004c VR09:0d 0006000000000000 0100 ; 12e TR09:0e 0000000020000040 VR09:0e 0000000000e00000 0100 ; 12f TR09:0f 8000000080000000 VR09:0f 0000000007ffff00 0100 ; 130 TR09:10 0000000008000025 VR09:10 0000000000000081 0100 ; 131 TR09:11 0000000020000020 VR09:11 0000000000000052 0100 ; 132 TR09:12 fffff83fffffffff VR09:12 0000000000000320 0100 ; 133 TR09:13 00000000f4000004 VR09:13 0000000000000050 0100 ; 134 TR09:14 0000000000000500 VR09:14 000000000000031f 0100 ; 135 TR09:15 fffffffffffffd80 VR09:15 000000ff00000000 0100 ; 136 TR09:16 0000000001800000 VR09:16 00000fffffffffff 0100 ; 137 TR09:17 ffffffff7fffff88 VR09:17 fffeffffffffffff 0100 ; 138 TR09:18 0000024000000000 VR09:18 fffffffffffeffff 0100 ; 139 TR09:19 0d01000100000001 VR09:19 0000000000000088 0100 ; 13a TR09:1a fffff83fe7ffffff VR09:1a 0000000000520000 0100 ; 13b TR09:1b 0000200000000000 VR09:1b 0000000000000082 0100 ; 13c TR09:1c 0000180000000000 VR09:1c 0000000000000046 0100 ; 13d TR09:1d 00001fc000000000 VR09:1d 0000000001ffe000 0100 ; 13e TR09:1e 0000000000020000 VR09:1e 0000000000000048 0100 ; 13f TR09:1f 0000000007ffff00 VR09:1f 0000000000000051 0100 ; 140 TR0a:00 0000000088000000 VR0a:00 0000000000000000 0100 ; 141 TR0a:01 0000000000000000 VR0a:01 0000000000000000 0100 ; 142 TR0a:02 0000000000000000 VR0a:02 0000000000000000 0100 ; 143 TR0a:03 0000000000000000 VR0a:03 0000000000000000 0100 ; 144 TR0a:04 0000000000000000 VR0a:04 0000000000000000 0100 ; 145 TR0a:05 0000000000000000 VR0a:05 0000000000000000 0100 ; 146 TR0a:06 0000000000000000 VR0a:06 0000000000000000 0100 ; 147 TR0a:07 0000000000000000 VR0a:07 0000000000000000 0100 ; 148 TR0a:08 0000000000000000 VR0a:08 0000000000000000 0100 ; 149 TR0a:09 0000000000000000 VR0a:09 0000000000000000 0100 ; 14a TR0a:0a 0000000000000000 VR0a:0a 0000000000000000 0100 ; 14b TR0a:0b 0000000000000000 VR0a:0b 0000000000000000 0100 ; 14c TR0a:0c 0000000000000000 VR0a:0c 0000000000000000 0100 ; 14d TR0a:0d 0000000000000000 VR0a:0d 0000000000000000 0100 ; 14e TR0a:0e 0000000000000000 VR0a:0e 0000000000000000 0100 ; 14f TR0a:0f 0000000000000000 VR0a:0f 0000000000000000 0100 ; 150 TR0a:10 0000000000000000 VR0a:10 0000000000000000 0100 ; 151 TR0a:11 0000000000000000 VR0a:11 0000000000000000 0100 ; 152 TR0a:12 0000000000000000 VR0a:12 0000000000000000 0100 ; 153 TR0a:13 0000000000000000 VR0a:13 0000000000000000 0100 ; 154 TR0a:14 0000000000000000 VR0a:14 0000000000000000 0100 ; 155 TR0a:15 0000000000000000 VR0a:15 0000000000000000 0100 ; 156 TR0a:16 0000000000000000 VR0a:16 0000000000000000 0100 ; 157 TR0a:17 0000000000000000 VR0a:17 0000000000000000 0100 ; 158 TR0a:18 0000000000000000 VR0a:18 0000000000000000 0100 ; 159 TR0a:19 0000000000000000 VR0a:19 0000000000000000 0100 ; 15a TR0a:1a 0000000000000000 VR0a:1a 0000000000000000 0100 ; 15b TR0a:1b 0000000000000000 VR0a:1b 0000000000000000 0100 ; 15c TR0a:1c 0000000000000000 VR0a:1c 0000000000000000 0100 ; 15d TR0a:1d 0000000000000000 VR0a:1d 0000000000000000 0100 ; 15e TR0a:1e 0000000000000000 VR0a:1e 0000000000000000 0100 ; 15f TR0a:1f 0000000000000000 VR0a:1f 0000000000000000 0100 ; 160 TR0b:00 ffffffffffffffff VR0b:00 ffffffffffffffff 0100 ; 161 TR0b:01 ffffffffffffffff VR0b:01 ffffffffffffffff 0100 ; 162 TR0b:02 ffffffffffffffff VR0b:02 ffffffffffffffff 0100 ; 163 TR0b:03 ffffffffffffffff VR0b:03 ffffffffffffffff 0100 ; 164 TR0b:04 ffffffffffffffff VR0b:04 ffffffffffffffff 0100 ; 165 TR0b:05 ffffffffffffffff VR0b:05 ffffffffffffffff 0100 ; 166 TR0b:06 ffffffffffffffff VR0b:06 ffffffffffffffff 0100 ; 167 TR0b:07 ffffffffffffffff VR0b:07 ffffffffffffffff 0100 ; 168 TR0b:08 ffffffffffffffff VR0b:08 ffffffffffffffff 0100 ; 169 TR0b:09 ffffffffffffffff VR0b:09 ffffffffffffffff 0100 ; 16a TR0b:0a ffffffffffffffff VR0b:0a ffffffffffffffff 0100 ; 16b TR0b:0b ffffffffffffffff VR0b:0b ffffffffffffffff 0100 ; 16c TR0b:0c ffffffffffffffff VR0b:0c ffffffffffffffff 0100 ; 16d TR0b:0d ffffffffffffffff VR0b:0d ffffffffffffffff 0100 ; 16e TR0b:0e ffffffffffffffff VR0b:0e ffffffffffffffff 0100 ; 16f TR0b:0f ffffffffffffffff VR0b:0f ffffffffffffffff 0100 ; 170 TR0b:10 ffffffffffffffff VR0b:10 ffffffffffffffff 0100 ; 171 TR0b:11 ffffffffffffffff VR0b:11 ffffffffffffffff 0100 ; 172 TR0b:12 ffffffffffffffff VR0b:12 ffffffffffffffff 0100 ; 173 TR0b:13 ffffffffffffffff VR0b:13 ffffffffffffffff 0100 ; 174 TR0b:14 ffffffffffffffff VR0b:14 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0000000000000000 VR15:1b 0000000000000000 0100 ; 2bc TR15:1c 0000000000000000 VR15:1c 0000000000000000 0100 ; 2bd TR15:1d 0000000000000000 VR15:1d 0000000000000000 0100 ; 2be TR15:1e 0000000000000000 VR15:1e 0000000000000000 0100 ; 2bf TR15:1f 0000000000000000 VR15:1f 0000000000000000 0100 ; 2c0 TR16:00 000000000000007f VR16:00 0000000000000000 0100 ; 2c1 TR16:01 0000000080000000 VR16:01 0000000000000000 0100 ; 2c2 TR16:02 0000000000000000 VR16:02 0000000000000000 0100 ; 2c3 TR16:03 0000000000000000 VR16:03 0000000000000000 0100 ; 2c4 TR16:04 0000000000000000 VR16:04 0000000000000000 0100 ; 2c5 TR16:05 0000000000000000 VR16:05 0000000000000000 0100 ; 2c6 TR16:06 0000000000000000 VR16:06 0000000000000000 0100 ; 2c7 TR16:07 0000000000000000 VR16:07 0000000000000000 0100 ; 2c8 TR16:08 0000000000000000 VR16:08 0000000000000000 0100 ; 2c9 TR16:09 0000000000000000 VR16:09 0000000000000000 0100 ; 2ca TR16:0a 0000000000000000 VR16:0a 0000000000000000 0100 ; 2cb TR16:0b 0000000000000000 VR16:0b 0000000000000000 0100 ; 2cc TR16:0c 0000000000000000 VR16:0c 0000000000000000 0100 ; 2cd TR16:0d 0000000000000000 VR16:0d 0000000000000000 0100 ; 2ce TR16:0e 0000000000000000 VR16:0e 0000000000000000 0100 ; 2cf TR16:0f 0000000000000000 VR16:0f 0000000000000000 0100 ; 2d0 TR16:10 0000000000000000 VR16:10 0000000000000000 0100 ; 2d1 TR16:11 0000000000000000 VR16:11 0000000000000000 0100 ; 2d2 TR16:12 0000000000000000 VR16:12 0000000000000000 0100 ; 2d3 TR16:13 0000000000000000 VR16:13 0000000000000000 0100 ; 2d4 TR16:14 0000000000000000 VR16:14 0000000000000000 0100 ; 2d5 TR16:15 0000000000000000 VR16:15 0000000000000000 0100 ; 2d6 TR16:16 0000000000000000 VR16:16 0000000000000000 0100 ; 2d7 TR16:17 0000000000000000 VR16:17 0000000000000000 0100 ; 2d8 TR16:18 0000000000000000 VR16:18 0000000000000000 0100 ; 2d9 TR16:19 0000000000000000 VR16:19 0000000000000000 0100 ; 2da TR16:1a 0000000000000000 VR16:1a 0000000000000000 0100 ; 2db TR16:1b 0000000000000000 VR16:1b 0000000000000000 0100 ; 2dc TR16:1c 0000000000000000 VR16:1c 0000000000000000 0100 ; 2dd TR16:1d 0000000000000000 VR16:1d 0000000000000000 0100 ; 2de TR16:1e 0000000000000000 VR16:1e 0000000000000000 0100 ; 2df TR16:1f 0000000000000000 VR16:1f 0000000000000000 0100 ; 2e0 TR17:00 0000000000000000 VR17:00 0000000000000000 0100 ; 2e1 TR17:01 0000000000000000 VR17:01 0000000000000000 0100 ; 2e2 TR17:02 0000000000000000 VR17:02 0000000000000000 0100 ; 2e3 TR17:03 0000000000000000 VR17:03 0000000000000000 0100 ; 2e4 TR17:04 0000000000000000 VR17:04 0000000000000000 0100 ; 2e5 TR17:05 0000000000000000 VR17:05 0000000000000000 0100 ; 2e6 TR17:06 0000000000000000 VR17:06 0000000000000000 0100 ; 2e7 TR17:07 0000000000000000 VR17:07 0000000000000000 0100 ; 2e8 TR17:08 0000000000000000 VR17:08 0000000000000000 0100 ; 2e9 TR17:09 0000000000000000 VR17:09 0000000000000000 0100 ; 2ea TR17:0a 0000000000000000 VR17:0a 0000000000000000 0100 ; 2eb TR17:0b 0000000000000000 VR17:0b 0000000000000000 0100 ; 2ec TR17:0c 0000000000000000 VR17:0c 0000000000000000 0100 ; 2ed TR17:0d 0000000000000000 VR17:0d 0000000000000000 0100 ; 2ee TR17:0e 0000000000000000 VR17:0e 0000000000000000 0100 ; 2ef TR17:0f 0000000000000000 VR17:0f 0000000000000000 0100 ; 2f0 TR17:10 0000000000000000 VR17:10 0000000000000000 0100 ; 2f1 TR17:11 0000000000000000 VR17:11 0000000000000000 0100 ; 2f2 TR17:12 0000000000000000 VR17:12 0000000000000000 0100 ; 2f3 TR17:13 0000000000000000 VR17:13 0000000000000000 0100 ; 2f4 TR17:14 ffffffffffff0000 VR17:14 0000000007fffd80 0100 ; 2f5 TR17:15 0000000000000600 VR17:15 000ffcf00000a000 0100 ; 2f6 TR17:16 0000000000000180 VR17:16 0000000000000180 0100 ; 2f7 TR17:17 0000000000000100 VR17:17 0000000000000600 0100 ; 2f8 TR17:18 0000000000000500 VR17:18 0000000649534e00 0100 ; 2f9 TR17:19 fd00000000000000 VR17:19 0000000000098969 0100 ; 2fa TR17:1a fe00000000000000 VR17:1a ffff000000000000 0100 ; 2fb TR17:1b 8f8f000000000000 VR17:1b 000000000000ff00 0100 ; 2fc TR17:1c 4f4f000000000000 VR17:1c 0003ffffffffffff 0100 ; 2fd TR17:1d 0000000000000000 VR17:1d 0000000000000000 0100 ; 2fe TR17:1e 0000000080000000 VR17:1e 0000000000000500 0100 ; 2ff TR17:1f 0000000000000000 VR17:1f 0000000000000000 0100 ; 300 TR18:00 0000000080000000 VR18:00 0000000000000000 0100 ; 301 TR18:01 0000000000000000 VR18:01 0000000000000000 0100 ; 302 TR18:02 0000000000000000 VR18:02 0000000000000000 0100 ; 303 TR18:03 0000000000000000 VR18:03 0000000000000000 0100 ; 304 TR18:04 0000000000000000 VR18:04 0000000000000000 0100 ; 305 TR18:05 0000000000000000 VR18:05 0000000000000000 0100 ; 306 TR18:06 0000000000000000 VR18:06 0000000000000000 0100 ; 307 TR18:07 0000000000000000 VR18:07 0000000000000000 0100 ; 308 TR18:08 0000000000000000 VR18:08 0000000000000000 0100 ; 309 TR18:09 0000000000000000 VR18:09 0000000000000000 0100 ; 30a TR18:0a 0000000000000000 VR18:0a 0000000000000000 0100 ; 30b TR18:0b 0000000000000000 VR18:0b 0000000000000000 0100 ; 30c TR18:0c 0000000000000000 VR18:0c 0000000000000000 0100 ; 30d TR18:0d 0000000000000000 VR18:0d 0000000000000000 0100 ; 30e TR18:0e 0000000000000000 VR18:0e 0000000000000000 0100 ; 30f TR18:0f 0000000000000000 VR18:0f 0000000000000000 0100 ; 310 TR18:10 0000000000000000 VR18:10 0000000000000000 0100 ; 311 TR18:11 0000000000000000 VR18:11 0000000000000000 0100 ; 312 TR18:12 0000000007ffe700 VR18:12 0000000000000000 0100 ; 313 TR18:13 0000000000000000 VR18:13 0000000000000000 0100 ; 314 TR18:14 0000000000000000 VR18:14 0000000000000000 0100 ; 315 TR18:15 0000000000000000 VR18:15 0000000000000000 0100 ; 316 TR18:16 0000000000000000 VR18:16 0000000000000000 0100 ; 317 TR18:17 0000000000000000 VR18:17 0000000000000000 0100 ; 318 TR18:18 0000000000000000 VR18:18 0000000000000000 0100 ; 319 TR18:19 0000000000000000 VR18:19 0000000000000000 0100 ; 31a TR18:1a 0000000000000000 VR18:1a 0000000000000000 0100 ; 31b TR18:1b 0000000000000000 VR18:1b 0000000000000000 0100 ; 31c TR18:1c 0000000000000000 VR18:1c 0000000000000000 0100 ; 31d TR18:1d 0000000000000000 VR18:1d 0000000000000000 0100 ; 31e TR18:1e 0000000000000000 VR18:1e 0000000000000000 0100 ; 31f TR18:1f 0000000000000000 VR18:1f 0000000000000000 0100 ; 320 TR19:00 0000000000000000 VR19:00 0000000000000000 0100 ; 321 TR19:01 0000000000000000 VR19:01 0000000000000000 0100 ; 322 TR19:02 0000000000000000 VR19:02 0000000000000000 0100 ; 323 TR19:03 0000000000000000 VR19:03 0000000000000000 0100 ; 324 TR19:04 0000000000000000 VR19:04 0000000000000000 0100 ; 325 TR19:05 0000000000000000 VR19:05 0000000000000000 0100 ; 326 TR19:06 0000000000000000 VR19:06 0000000000000000 0100 ; 327 TR19:07 0000000000000000 VR19:07 0000000000000000 0100 ; 328 TR19:08 0000000000000000 VR19:08 0000000000000008 0100 ; 329 TR19:09 0000000000000000 VR19:09 0000000000000000 0100 ; 32a TR19:0a 0000000000000000 VR19:0a 0000000000000000 0100 ; 32b TR19:0b 0000000000000000 VR19:0b 0000000000000000 0100 ; 32c TR19:0c 0000000000000000 VR19:0c 0000000000000000 0100 ; 32d TR19:0d 0000000000000000 VR19:0d 0000000000000000 0100 ; 32e TR19:0e 0000000000000000 VR19:0e 0000000000000000 0100 ; 32f TR19:0f 0000000000000000 VR19:0f 0000000000000000 0100 ; 330 TR19:10 0000000000000000 VR19:10 0000000000000000 0100 ; 331 TR19:11 0000000000000000 VR19:11 0000000000000000 0100 ; 332 TR19:12 0000000000000000 VR19:12 0000000000000000 0100 ; 333 TR19:13 0000000000000000 VR19:13 0000000000000000 0100 ; 334 TR19:14 0000000000000000 VR19:14 0000000000000000 0100 ; 335 TR19:15 0000000000000000 VR19:15 0000000000000000 0100 ; 336 TR19:16 0000000000000000 VR19:16 0000000000000000 0100 ; 337 TR19:17 0000000000000000 VR19:17 0000000000000000 0100 ; 338 TR19:18 0000000000000000 VR19:18 0000000000000000 0100 ; 339 TR19:19 0000000000000000 VR19:19 0000000000000000 0100 ; 33a TR19:1a 0000000000000000 VR19:1a 0000000000000000 0100 ; 33b TR19:1b 0000000000000000 VR19:1b 0000000000000000 0100 ; 33c TR19:1c 0000000000000000 VR19:1c 0000000000000000 0100 ; 33d TR19:1d 0000000000000000 VR19:1d 0000000000000000 0100 ; 33e TR19:1e 0000000000000000 VR19:1e 0000000000000000 0100 ; 33f TR19:1f 0000000000000000 VR19:1f 0000000000000000 0100 ; 340 TR1a:00 0000000000000000 VR1a:00 0000000000000000 0100 ; 341 TR1a:01 0000000000000000 VR1a:01 0000000000000000 0100 ; 342 TR1a:02 0000000000000000 VR1a:02 0000000000000000 0100 ; 343 TR1a:03 0000000000000000 VR1a:03 0000000000000000 0100 ; 344 TR1a:04 0000000000000000 VR1a:04 0000000000000000 0100 ; 345 TR1a:05 0000000000000000 VR1a:05 0000000000000000 0100 ; 346 TR1a:06 0000000000000000 VR1a:06 0000000000000000 0100 ; 347 TR1a:07 0000000000000000 VR1a:07 0000000000000000 0100 ; 348 TR1a:08 0000000000000000 VR1a:08 0000000000000000 0100 ; 349 TR1a:09 0000000000000000 VR1a:09 0000000000000000 0100 ; 34a TR1a:0a 0000000000000000 VR1a:0a 0000000000000000 0100 ; 34b TR1a:0b 0000000000000000 VR1a:0b 0000000000000000 0100 ; 34c TR1a:0c 0000000000000000 VR1a:0c 0000000000000000 0100 ; 34d TR1a:0d 0000000000000000 VR1a:0d 0000000000000000 0100 ; 34e TR1a:0e 0000000000000000 VR1a:0e 0000000000000000 0100 ; 34f TR1a:0f 0000000000000000 VR1a:0f 0000000000000000 0100 ; 350 TR1a:10 0000000000000000 VR1a:10 0000000000000000 0100 ; 351 TR1a:11 0000000000000000 VR1a:11 0000000000000000 0100 ; 352 TR1a:12 0000000000000000 VR1a:12 0000000000000000 0100 ; 353 TR1a:13 0000000000000000 VR1a:13 0000000000000000 0100 ; 354 TR1a:14 0000000000000000 VR1a:14 0000000000000000 0100 ; 355 TR1a:15 0000000000000000 VR1a:15 0000000000000000 0100 ; 356 TR1a:16 0000000000000000 VR1a:16 0000000000000000 0100 ; 357 TR1a:17 0000000000000000 VR1a:17 0000000000000000 0100 ; 358 TR1a:18 0000000000000000 VR1a:18 0000000000000000 0100 ; 359 TR1a:19 0000000000000000 VR1a:19 0000000000000000 0100 ; 35a TR1a:1a 0000000000000000 VR1a:1a 0000000000000000 0100 ; 35b TR1a:1b 0000000000000000 VR1a:1b 0000000000000000 0100 ; 35c TR1a:1c 0000000000000000 VR1a:1c 0000000000000000 0100 ; 35d TR1a:1d 0000000000000000 VR1a:1d 0000000000000000 0100 ; 35e TR1a:1e 0000000000000000 VR1a:1e 0000000000000000 0100 ; 35f TR1a:1f 0000000000000000 VR1a:1f 0000000000000000 0100 ; 360 TR1b:00 0000000000000000 VR1b:00 0000000000000000 0100 ; 361 TR1b:01 0000000000000000 VR1b:01 0000000000000000 0100 ; 362 TR1b:02 0000000000000000 VR1b:02 0000000000000000 0100 ; 363 TR1b:03 0000000000000000 VR1b:03 0000000000000000 0100 ; 364 TR1b:04 000000000000005d VR1b:04 000000000000005d 0100 ; 365 TR1b:05 0000000000000000 VR1b:05 0000000000000000 0100 ; 366 TR1b:06 0000000000000000 VR1b:06 0000000000000000 0100 ; 367 TR1b:07 0000000000000000 VR1b:07 0000000000000000 0100 ; 368 TR1b:08 0000000000000000 VR1b:08 0000000000000000 0100 ; 369 TR1b:09 0000000000000000 VR1b:09 0000000000000000 0100 ; 36a TR1b:0a 0000000000000000 VR1b:0a 0000000000000000 0100 ; 36b TR1b:0b 0000000000000000 VR1b:0b 0000000000000080 0100 ; 36c TR1b:0c 0000000000000000 VR1b:0c 0000000000000100 0100 ; 36d TR1b:0d 0000000000000080 VR1b:0d 000000000000001f 0100 ; 36e TR1b:0e ffff000040000000 VR1b:0e 0000000000000000 0100 ; 36f TR1b:0f 0000000000007f80 VR1b:0f ffffffffffff0000 0100 ; 370 TR1b:10 000000000000007f VR1b:10 0000000000000001 0100 ; 371 TR1b:11 000000008000003f VR1b:11 fffff00000000000 0100 ; 372 TR1b:12 000000000000003f VR1b:12 0000000000000000 0100 ; 373 TR1b:13 fffe000000000601 VR1b:13 0000000000000001 0100 ; 374 TR1b:14 fffe000040000601 VR1b:14 0000000000000000 0100 ; 375 TR1b:15 000000000000003f VR1b:15 0000000000000001 0100 ; 376 TR1b:16 0000000000000021 VR1b:16 0000000000000000 0100 ; 377 TR1b:17 0000000000000029 VR1b:17 0000000000000000 0100 ; 378 TR1b:18 0000000000000011 VR1b:18 0000000000000000 0100 ; 379 TR1b:19 0000000000000019 VR1b:19 0000000000000000 0100 ; 37a TR1b:1a 0000000000001fc1 VR1b:1a ffff000000000000 0100 ; 37b TR1b:1b 000000000000003f VR1b:1b 0000000000000000 0100 ; 37c TR1b:1c 0000000000000049 VR1b:1c 0000000000000000 0100 ; 37d TR1b:1d 0000000000000076 VR1b:1d 0000000000000000 0100 ; 37e TR1b:1e 0000000000000009 VR1b:1e 0000000000000000 0100 ; 37f TR1b:1f 0000000000000000 VR1b:1f 0000000000000000 0100 ; 380 TR1c:00 0000000080000000 VR1c:00 0000000000000000 0100 ; 381 TR1c:01 0000000000000000 VR1c:01 0000000000000000 0100 ; 382 TR1c:02 0000000000000000 VR1c:02 0000000000000000 0100 ; 383 TR1c:03 0000000000000000 VR1c:03 0000000000000000 0100 ; 384 TR1c:04 0000000000000000 VR1c:04 0000000000000000 0100 ; 385 TR1c:05 0000000000000000 VR1c:05 0000000000000000 0100 ; 386 TR1c:06 0000000000000000 VR1c:06 0000000000000000 0100 ; 387 TR1c:07 0000000000000000 VR1c:07 0000000000000000 0100 ; 388 TR1c:08 0000000000000000 VR1c:08 0000000000000000 0100 ; 389 TR1c:09 0000000000000000 VR1c:09 0000000000000000 0100 ; 38a TR1c:0a 0000000000000000 VR1c:0a 0000000000000000 0100 ; 38b TR1c:0b 0000000000000000 VR1c:0b 0000000000000000 0100 ; 38c TR1c:0c 0000000000000000 VR1c:0c 0000000000000000 0100 ; 38d TR1c:0d 0000000000000000 VR1c:0d 0000000000000000 0100 ; 38e TR1c:0e 0000000000000000 VR1c:0e 0000000000000000 0100 ; 38f TR1c:0f 0000000000000000 VR1c:0f 0000000000000000 0100 ; 390 TR1c:10 0000000000000000 VR1c:10 0000000000000000 0100 ; 391 TR1c:11 0000000000000000 VR1c:11 0000000000000000 0100 ; 392 TR1c:12 0000000000000000 VR1c:12 0000000000000000 0100 ; 393 TR1c:13 0000000000000000 VR1c:13 0000000000000000 0100 ; 394 TR1c:14 0000000000000000 VR1c:14 0000000000000000 0100 ; 395 TR1c:15 0000000000000000 VR1c:15 0000000000000000 0100 ; 396 TR1c:16 0000000000000000 VR1c:16 0000000000000000 0100 ; 397 TR1c:17 0000000000000000 VR1c:17 0000000000000000 0100 ; 398 TR1c:18 0000000000000000 VR1c:18 0000000000000000 0100 ; 399 TR1c:19 0000000000000000 VR1c:19 0000000000000000 0100 ; 39a TR1c:1a 0000000000000000 VR1c:1a 0000000000000000 0100 ; 39b TR1c:1b 0000000000000000 VR1c:1b 0000000000000000 0100 ; 39c TR1c:1c 0000000000000000 VR1c:1c 0000000000000000 0100 ; 39d TR1c:1d 0000000000000000 VR1c:1d 0000000000000000 0100 ; 39e TR1c:1e 0000000000000000 VR1c:1e 0000000000000000 0100 ; 39f TR1c:1f 0000000000000000 VR1c:1f 0000000000000000 0100 ; 3a0 TR1d:00 0000000000000001 VR1d:00 0000000000000000 0100 ; 3a1 TR1d:01 ffffffffffffffff VR1d:01 0000000000000000 0100 ; 3a2 TR1d:02 0000000000000000 VR1d:02 0000000000000000 0100 ; 3a3 TR1d:03 0000000000000000 VR1d:03 0000000000000000 0100 ; 3a4 TR1d:04 0000000000000000 VR1d:04 0000040000000000 0100 ; 3a5 TR1d:05 0000000000000000 VR1d:05 0000000000000000 0100 ; 3a6 TR1d:06 0000000000000000 VR1d:06 0000000000000000 0100 ; 3a7 TR1d:07 0000000000000000 VR1d:07 0000000000000000 0100 ; 3a8 TR1d:08 0000000000000000 VR1d:08 0000000000000000 0100 ; 3a9 TR1d:09 0000000000000000 VR1d:09 0000000000000000 0100 ; 3aa TR1d:0a 0000000000000000 VR1d:0a 0000000000000000 0100 ; 3ab TR1d:0b 0000000000000000 VR1d:0b 0000000000000000 0100 ; 3ac TR1d:0c 0000000000000000 VR1d:0c 000ffff00000bf80 0100 ; 3ad TR1d:0d 0000000000000068 VR1d:0d 0000000000000000 0100 ; 3ae TR1d:0e 0000000000000000 VR1d:0e 0000000000000000 0100 ; 3af TR1d:0f 0000000000000000 VR1d:0f 0000000000000000 0100 ; 3b0 TR1d:10 0000000000000000 VR1d:10 0000000000000000 0100 ; 3b1 TR1d:11 00000000000001f4 VR1d:11 0000000000000000 0100 ; 3b2 TR1d:12 0000000000000000 VR1d:12 fffffffffffffff0 0100 ; 3b3 TR1d:13 0000000000000000 VR1d:13 0000000000000000 0100 ; 3b4 TR1d:14 0000000000000000 VR1d:14 0000000000000000 0100 ; 3b5 TR1d:15 0000000000000000 VR1d:15 0000000000000000 0100 ; 3b6 TR1d:16 0000000000000000 VR1d:16 0000000000000000 0100 ; 3b7 TR1d:17 0000000000000000 VR1d:17 0000000000000000 0100 ; 3b8 TR1d:18 0000000000000000 VR1d:18 0000000000000000 0100 ; 3b9 TR1d:19 0000000000000000 VR1d:19 0000000000000000 0100 ; 3ba TR1d:1a 0000000000000000 VR1d:1a 0000000000000000 0100 ; 3bb TR1d:1b 0000000000000000 VR1d:1b 0000000000000000 0100 ; 3bc TR1d:1c 0000000000000000 VR1d:1c 0000000000000000 0100 ; 3bd TR1d:1d 0000000000000000 VR1d:1d 0000000000000000 0100 ; 3be TR1d:1e 0000000000000000 VR1d:1e 0000000000000000 0100 ; 3bf TR1d:1f 0000000000000000 VR1d:1f 0000000000000000 0100 ; 3c0 TR1e:00 0000000020000000 VR1e:00 0000000000000000 0100 ; 3c1 TR1e:01 0000000000000000 VR1e:01 0000000000000000 0100 ; 3c2 TR1e:02 0000000000000000 VR1e:02 0000000000000000 0100 ; 3c3 TR1e:03 0000000000000000 VR1e:03 0000000000000000 0100 ; 3c4 TR1e:04 0000000000000000 VR1e:04 0000000000000000 0100 ; 3c5 TR1e:05 0000000000000000 VR1e:05 0000000000000000 0100 ; 3c6 TR1e:06 0000000000000000 VR1e:06 0000000000000000 0100 ; 3c7 TR1e:07 0000000000000000 VR1e:07 0000000000000000 0100 ; 3c8 TR1e:08 0000000000000000 VR1e:08 0000000000000000 0100 ; 3c9 TR1e:09 0000000000000000 VR1e:09 0000000000000000 0100 ; 3ca TR1e:0a 0000000000000000 VR1e:0a 0000000000000000 0100 ; 3cb TR1e:0b 0000000000000000 VR1e:0b 0000000000000000 0100 ; 3cc TR1e:0c 0000000000000000 VR1e:0c 0000000000000000 0100 ; 3cd TR1e:0d 0000000000000000 VR1e:0d 0000000000000000 0100 ; 3ce TR1e:0e 0000000000000000 VR1e:0e 0000000000000000 0100 ; 3cf TR1e:0f 00000000c0000003 VR1e:0f 0000000000000000 0100 ; 3d0 TR1e:10 0000000000000030 VR1e:10 0000000000000000 0100 ; 3d1 TR1e:11 000000008000000d VR1e:11 0000000000000000 0100 ; 3d2 TR1e:12 0000000000000003 VR1e:12 0000000000000000 0100 ; 3d3 TR1e:13 0000000080000005 VR1e:13 0000000000000000 0100 ; 3d4 TR1e:14 00000000c0000002 VR1e:14 0000000000000000 0100 ; 3d5 TR1e:15 00000000c0000001 VR1e:15 0000000000000000 0100 ; 3d6 TR1e:16 00000000c0000000 VR1e:16 0000000000000000 0100 ; 3d7 TR1e:17 0000000000000002 VR1e:17 0000000000000000 0100 ; 3d8 TR1e:18 0000000000000020 VR1e:18 0000000000000000 0100 ; 3d9 TR1e:19 0000000000000010 VR1e:19 0000000000000000 0100 ; 3da TR1e:1a 0000000000000000 VR1e:1a 0000000000000000 0100 ; 3db TR1e:1b 0000000040000002 VR1e:1b 0000000000000000 0100 ; 3dc TR1e:1c 0000000080000009 VR1e:1c 0000000000000002 0100 ; 3dd TR1e:1d 0000000080000001 VR1e:1d 0000000000000001 0100 ; 3de TR1e:1e 0000000007ffff80 VR1e:1e 0000000000000000 0100 ; 3df TR1e:1f ffffffff07ffff80 VR1e:1f ffffffff07ffff80 0100 ; 3e0 TCSA0 00c80000b96581d0 VCSA0 00cf002d444a4c00 0100 ; 3e1 TCSA1 0000000000000000 VCSA1 0000000000000000 0100 ; 3e2 TCSA2 0000000000000000 VCSA2 0000000000000000 0100 ; 3e3 TCSA3 0000000000000000 VCSA3 0000000000000000 0100 ; 3e4 TCSA4 0000000000000000 VCSA4 0000000000000000 0100 ; 3e5 TCSA5 0000000000000000 VCSA5 0000000000000000 0100 ; 3e6 TCSA6 0000000000000000 VCSA6 0000000000000000 0100 ; 3e7 TCSA7 0000000000000000 VCSA7 0000000000000000 0100 ; 3e8 TCSA8 0000000000000000 VCSA8 0000000000000000 0100 ; 3e9 TCSA9 0000000000000000 VCSA9 0000000000000000 0100 ; 3ea TCSAa 0000000000000000 VCSAa 0000000000000000 0100 ; 3eb TCSAb 0000000000000000 VCSAb 0000000000000000 0100 ; 3ec TCSAc 0000000000000000 VCSAc 0000000000000000 0100 ; 3ed TCSAd 0000000000000000 VCSAd 0000000000000000 0100 ; 3ee TCSAe 0000000000000000 VCSAe 0000000000000000 0100 ; 3ef TCSAf 0000000000000000 VCSAf 0000000000000000 0100 ; 3f0 TGP0 0000000000000000 VGP0 0000000000000000 0100 ; 3f1 TGP1 0000000000000000 VGP1 0000000000000000 0100 ; 3f2 TGP2 0000000000000000 VGP2 0000000000000000 0100 ; 3f3 TGP3 0000000000000000 VGP3 0000000000000000 0100 ; 3f4 TGP4 0000000000000000 VGP4 0000000000000000 0100 ; 3f5 TGP5 0000000000000000 VGP5 0000000000000000 0100 ; 3f6 TGP6 0000000000000000 VGP6 0000000000000000 0100 ; 3f7 TGP7 0000000000000000 VGP7 0000000000000000 0100 ; 3f8 TGP8 0000000000000000 VGP8 0000000000000000 0100 ; 3f9 TGP9 0000000000000000 VGP9 0000000000000000 0100 ; 3fa TGPa 0000000000000000 VGPa 0000000000000000 0100 ; 3fb TGPb 0000000000000000 VGPb 0000000000000000 0100 ; 3fc TGPc 0000000000000000 VGPc 0000000000000000 0100 ; 3fd TGPd 0000000000000000 VGPd 0000000000000000 0100 ; 3fe TGPe 0000000000000000 VGPe 0000000000000000 0100 ; 3ff TGPf 0000000000000000 VGPf 0000000000000000 0100 ; 0100 ; Defaults not shown: 0100 ; =================== 0100 ; dispatch_csa_free 0 0100 ; dispatch_ibuff_fill 0 0100 ; dispatch_ignore 0 0100 ; dispatch_mem_strt 4 MEMORY NOT STARTED 0100 ; dispatch_uses_tos 0 0100 ; fiu_fill_mode_src 1 0100 ; fiu_len_fill_lit 7f zero-fill 0x3f 0100 ; fiu_len_fill_reg_ctl 3 len=unchanged, fill=unchanged 0100 ; fiu_length_src 1 length_literal 0100 ; fiu_load_mdr 0 load_mdr 0100 ; fiu_load_oreg 0 load_oreg 0100 ; fiu_load_tar 0 load_tar 0100 ; fiu_load_var 0 load_var 0100 ; fiu_mem_start 19 nop_0x19 0100 ; fiu_offs_lit 00 0100 ; fiu_offset_src 1 offset_literal 0100 ; fiu_op_sel 0 extract 0100 ; fiu_oreg_src 1 merge data register 0100 ; fiu_rdata_src 1 mdr 0100 ; fiu_tivi_src 0 tar_var 0100 ; fiu_vmux_sel 2 VI 0100 ; ioc_adrbs 0 fiu 0100 ; ioc_fiubs 3 seq 0100 ; ioc_load_wdr 1 0100 ; ioc_random 0 noop 0100 ; ioc_tvbs 0 typ+val 0100 ; seq_b_timing 2 Late Condition, Hint True (or unconditional branch) 0100 ; seq_br_type 6 Continue 0100 ; seq_branch_adr 0000 0100 ; seq_cond_sel 46 SEQ.previously_latched_cond 0100 ; seq_en_micro 1 0100 ; seq_int_reads 3 TOP OF THE MICRO STACK 0100 ; seq_latch 0 0100 ; seq_lex_adr 0 0100 ; seq_random 00 ? 0100 ; typ_a_adr 00 GP00 0100 ; typ_alu_func 1f ZEROS 0100 ; typ_b_adr 00 GP00 0100 ; typ_c_adr 29 WRITE_DISABLE 0100 ; typ_c_lit 3 0100 ; typ_c_mux_sel 1 WDR 0100 ; typ_c_source 1 MUX 0100 ; typ_csa_cntl 6 NOP 0100 ; typ_frame 0 0100 ; typ_mar_cntl 0 NOP 0100 ; typ_priv_check 7 NOP 0100 ; typ_rand f INC_DEC_128 0100 ; val_a_adr 00 GP00 0100 ; val_alu_func 1f ZEROS 0100 ; val_b_adr 00 GP00 0100 ; val_c_adr 29 WRITE_DISABLE 0100 ; val_c_mux_sel 3 WDR 0100 ; val_c_source 1 MUX 0100 ; val_frame 0 0100 ; val_m_a_src 3 Bits 48…63 0100 ; val_m_b_src 3 Bits 48…63 0100 ; val_rand 0 NO_OP 0100 ; 0100 ; Early macro event: ME_STOP_MACH 0100 ; -------------------------------------------------------------------------------------- 0100 ME_STOP_MACH: 0100 0100 <halt> ; Flow R 0101 0101 seq_en_micro 0 0102 0102 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0103 0103 <halt> ; Flow R 0104 0104 <halt> ; Flow R 0105 0105 <halt> ; Flow R 0106 0106 <halt> ; Flow R 0107 0107 <halt> ; Flow R 0108 ; -------------------------------------------------------------------------------------- 0108 ; Early macro event: ME_GP_TIME 0108 ; -------------------------------------------------------------------------------------- 0108 ME_GP_TIME: 0108 0108 seq_br_type 7 Unconditional Call; Flow C 0x5db seq_branch_adr 05db 0x05db seq_en_micro 0 0109 0109 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 010a 010a <halt> ; Flow R 010b 010b <halt> ; Flow R 010c 010c <halt> ; Flow R 010d 010d <halt> ; Flow R 010e 010e <halt> ; Flow R 010f 010f <halt> ; Flow R 0110 ; -------------------------------------------------------------------------------------- 0110 ; Early macro event: ME_SL_TIME 0110 ; -------------------------------------------------------------------------------------- 0110 ME_SL_TIME: 0110 0110 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x763 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0763 0x0763 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0111 0111 fiu_tivi_src 2 tar_fiu; Flow J cc=True 0x765 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0765 0x0765 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR13:0d typ_frame 13 val_a_adr 21 VR02:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0112 0112 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0113 0113 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x760 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_random 6 load slice timer seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0760 0x0760 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 val_a_adr 2f VR02:0f val_frame 2 0114 0114 fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0115 0115 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x73a seq_br_type 1 Branch True seq_branch_adr 073a 0x073a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0116 0116 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0117 0117 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x73c fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 073c 0x073c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0118 ; -------------------------------------------------------------------------------------- 0118 ; Early macro event: ME_SPARE1 0118 ; -------------------------------------------------------------------------------------- 0118 ME_SPARE1: 0118 0118 <halt> ; Flow R 0119 0119 <halt> ; Flow R 011a 011a <halt> ; Flow R 011b 011b <halt> ; Flow R 011c 011c <halt> ; Flow R 011d 011d <halt> ; Flow R 011e 011e <halt> ; Flow R 011f 011f <halt> ; Flow R 0120 ; -------------------------------------------------------------------------------------- 0120 ; Early macro event: ME_PACKET 0120 ; -------------------------------------------------------------------------------------- 0120 ME_PACKET: 0120 0120 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 5 read response fifo ioc_tvbs 4 ioc+ioc seq_en_micro 0 0121 0121 ioc_fiubs 0 fiu ioc_random 15 clear transfer parity error ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0122 0122 ioc_load_wdr 0 ; Flow C cc=False 0x20c ioc_random 13 set cpu running seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR03:13 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0b GP0b typ_frame 3 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0123 0123 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b val_m_a_src 2 Bits 32…47 0124 0124 ioc_random 1c read ioc memory and increment address seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0125 0125 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0b GP0b 0126 0126 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x819 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 3 Unconditional Branch seq_branch_adr 0819 0x0819 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0127 0127 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0128 ; -------------------------------------------------------------------------------------- 0128 ; Early macro event: ME_STATUS 0128 ; -------------------------------------------------------------------------------------- 0128 ME_STATUS: 0128 0128 <halt> ; Flow R 0129 0129 <halt> ; Flow R 012a 012a <halt> ; Flow R 012b 012b <halt> ; Flow R 012c 012c <halt> ; Flow R 012d 012d <halt> ; Flow R 012e 012e <halt> ; Flow R 012f 012f <halt> ; Flow R 0130 ; -------------------------------------------------------------------------------------- 0130 ; Early macro event: ME_SPARE0 0130 ; -------------------------------------------------------------------------------------- 0130 ME_SPARE0: 0130 0130 <halt> ; Flow R 0131 0131 <halt> ; Flow R 0132 0132 <halt> ; Flow R 0133 0133 <halt> ; Flow R 0134 0134 <halt> ; Flow R 0135 0135 <halt> ; Flow R 0136 0136 <halt> ; Flow R 0137 0137 <halt> ; Flow R 0138 ; -------------------------------------------------------------------------------------- 0138 ; Early macro event: ME_REFRESH 0138 ; -------------------------------------------------------------------------------------- 0138 ME_REFRESH: 0138 0138 fiu_mem_start d start_physical_rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 0139 0139 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x2a65 fiu_tivi_src c mar_0xc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2a65 0x2a65 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 34 VR0d:14 val_alu_func 1c DEC_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 013a 013a ioc_tvbs 3 fiu+fiu; Flow C 0xbab seq_br_type 7 Unconditional Call seq_branch_adr 0bab 0x0bab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR0d:11 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0e VR0d:11 val_c_mux_sel 2 ALU val_frame d 013b 013b fiu_load_tar 1 hold_tar; Flow J cc=True 0x13e fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 013e 0x013e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_b_adr 31 TR0d:11 typ_frame d val_a_adr 34 VR0d:14 val_alu_func 7 INC_A val_b_adr 31 VR0d:11 val_frame d 013c 013c fiu_len_fill_reg_ctl 2 ; Flow R cc=True fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 013d 0x013d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR1d:01 val_alu_func 0 PASS_A val_frame 1d 013d 013d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 013e 013e fiu_mem_start d start_physical_rd; Flow J 0x2a66 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a66 0x2a66 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_frame 1d 013f 013f <halt> ; Flow R 0140 ; -------------------------------------------------------------------------------------- 0140 ; Late macro event: ML_IBUF_empty 0140 ; -------------------------------------------------------------------------------------- 0140 ML_IBUF_empty: 0140 0140 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_cond_sel 55 SEQ.E_MACRO_PEND seq_int_reads 0 TYP VAL BUS seq_random 28 Load_ibuff+Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0141 0141 seq_br_type 7 Unconditional Call; Flow C 0x364b seq_branch_adr 364b 0x364b seq_en_micro 0 0142 0142 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0143 0143 seq_en_micro 0 0144 0144 seq_en_micro 0 0145 ; -------------------------------------------------------------------------------------- 0145 ; Micro event: UE_MACHINE_STARTUP 0145 ; -------------------------------------------------------------------------------------- 0145 UE_MACHINE_STARTUP: 0145 0145 seq_br_type 3 Unconditional Branch; Flow J 0x2abd seq_branch_adr 2abd 0x2abd seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 09 TR04:16 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 0 PASS_A val_c_adr 09 VR04:16 val_c_mux_sel 2 ALU val_frame 4 0146 0146 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0147 0147 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0148 ; -------------------------------------------------------------------------------------- 0148 ; Late macro event: ML_break_class 0148 ; -------------------------------------------------------------------------------------- 0148 ML_break_class: 0148 0148 fiu_load_tar 1 hold_tar; Flow C cc=True 0x2d55 fiu_load_var 1 hold_var fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2d55 0x2d55 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR00:10 val_a_adr 24 VR07:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 0149 0149 ioc_tvbs 5 seq+seq; Flow J cc=True 0x14a ; Flow J cc=#0x0 0x2d67 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2d67 0x2d67 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 30 TR00:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 014a 014a ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 014b 014b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2d54 seq_br_type 1 Branch True seq_branch_adr 2d54 0x2d54 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3c TR05:1c typ_frame 5 014c 014c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 014d 014d fiu_mem_start 4 continue; Flow J cc=True 0x170 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0170 ML_CSA_Underflow seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 2a TR06:0a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR05:09 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 014e 014e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 014f 014f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d3c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d3c 0x2d3c typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0150 ; -------------------------------------------------------------------------------------- 0150 ; Late macro event: ML_pullup 0150 ; -------------------------------------------------------------------------------------- 0150 ML_pullup: 0150 0150 <halt> ; Flow R 0151 0151 <halt> ; Flow R 0152 0152 <halt> ; Flow R 0153 0153 <halt> ; Flow R 0154 0154 <halt> ; Flow R 0155 0155 <halt> ; Flow R 0156 0156 <halt> ; Flow R 0157 0157 <halt> ; Flow R 0158 ; -------------------------------------------------------------------------------------- 0158 ; Late macro event: ML_TOS_INVLD 0158 ; -------------------------------------------------------------------------------------- 0158 ML_TOS_INVLD: 0158 0158 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0159 0159 <halt> ; Flow R 015a 015a <halt> ; Flow R 015b 015b <halt> ; Flow R 015c 015c <halt> ; Flow R 015d 015d <halt> ; Flow R 015e 015e <halt> ; Flow R 015f 015f <halt> ; Flow R 0160 ; -------------------------------------------------------------------------------------- 0160 ; Late macro event: ML_Resolve Reference 0160 ; -------------------------------------------------------------------------------------- 0160 ML_Resolve Reference: 0160 0160 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x165 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0165 0x0165 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR1d:13 val_frame 1d 0161 0161 fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_b_adr 2f TR02:0f typ_c_adr 10 TR02:0f typ_frame 2 val_a_adr 34 VR1d:14 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0b VR1d:14 val_c_source 0 FIU_BUS val_frame 1d 0162 0162 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0163 0x0163 seq_cond_sel 4a SEQ.ME_resolve_ref seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 19 TR02:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR1d:13 val_c_mux_sel 2 ALU val_frame 1d val_rand a PASS_B_HIGH 0163 0163 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? val_a_adr 33 VR1d:13 val_frame 1d 0164 0164 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a5e fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a5e 0x2a5e seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0165 0165 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a5e fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type c Dispatch True seq_branch_adr 2a5e 0x2a5e seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0166 0166 <halt> ; Flow R 0167 0167 <halt> ; Flow R 0168 ; -------------------------------------------------------------------------------------- 0168 ; Late macro event: ML_SEQ_STOP 0168 ; -------------------------------------------------------------------------------------- 0168 ML_SEQ_STOP: 0168 0168 <halt> ; Flow R 0169 0169 <halt> ; Flow R 016a 016a <halt> ; Flow R 016b 016b <halt> ; Flow R 016c 016c <halt> ; Flow R 016d 016d <halt> ; Flow R 016e 016e <halt> ; Flow R 016f 016f <halt> ; Flow R 0170 ; -------------------------------------------------------------------------------------- 0170 ; Late macro event: ML_CSA_Underflow 0170 ; -------------------------------------------------------------------------------------- 0170 ML_CSA_Underflow: 0170 0170 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0171 0171 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR05:05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0172 0172 fiu_mem_start 3 start-wr; Flow J cc=True 0x176 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0176 0x0176 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 0173 0173 fiu_mem_start 4 continue; Flow J cc=False 0x173 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0173 0x0173 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0174 0174 ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 0175 0175 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0176 0176 fiu_mem_start 4 continue; Flow J 0x173 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0173 0x0173 seq_lex_adr 2 seq_random 0b ? typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0177 0177 <halt> ; Flow R 0178 ; -------------------------------------------------------------------------------------- 0178 ; Late macro event: ML_CSA_overflow 0178 ; -------------------------------------------------------------------------------------- 0178 ML_CSA_overflow: 0178 0178 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0179 0179 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 3 017a 017a fiu_mem_start 2 start-rd; Flow J cc=True 0x17e fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 017e 0x017e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 017b 017b seq_b_timing 0 Early Condition; Flow J cc=True 0x17d seq_br_type 1 Branch True seq_branch_adr 017d 0x017d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 10 TOP 017c 017c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x17b fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 017b 0x017b typ_alu_func 0 PASS_A typ_c_adr 2b BOT - 1 typ_c_source 0 FIU_BUS typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 017d 017d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 017e 017e seq_br_type 3 Unconditional Branch; Flow J 0x17c seq_branch_adr 017c 0x017c seq_lex_adr 2 seq_random 0b ? typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 017f 017f <halt> ; Flow R 0180 ; -------------------------------------------------------------------------------------- 0180 ; Micro event: UE_MEM_EXP 0180 ; -------------------------------------------------------------------------------------- 0180 UE_MEM_EXP: 0180 0180 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xeef seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0eef 0x0eef seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0181 0181 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0182 0182 fiu_tivi_src 8 type_var; Flow J 0xeef ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0eef 0x0eef seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0183 0183 <halt> ; Flow R 0184 0184 <halt> ; Flow R 0185 0185 <halt> ; Flow R 0186 0186 <halt> ; Flow R 0187 0187 <halt> ; Flow R 0188 ; -------------------------------------------------------------------------------------- 0188 ; Micro event: UE_ECC 0188 ; -------------------------------------------------------------------------------------- 0188 UE_ECC: 0188 0188 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a96 seq_br_type 1 Branch True seq_branch_adr 2a96 0x2a96 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 0 PASS_A typ_c_adr 19 TR1d:06 typ_frame 1d val_c_adr 19 VR1d:06 val_frame 1d 0189 0189 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2ab9 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab9 0x2ab9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 13 TR1d:0c typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 018a 018a fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x2a8b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a8b 0x2a8b seq_cond_sel 63 CSA_HIT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1d typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR1d:0a val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR1d:05 val_c_mux_sel 2 ALU val_frame 1d 018b 018b fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x2a8d fiu_load_oreg 1 hold_oreg fiu_offs_lit 73 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 018c 018c fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0x2a8d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 018d 018d seq_br_type 7 Unconditional Call; Flow C 0x20e seq_branch_adr 020e 0x020e seq_en_micro 0 018e 018e ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3d VR12:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 018f 018f fiu_mem_start c start_if_incmplt; Flow R ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 6c INCOMPLETE_MEMORY_CYCLE seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 7 INC_A typ_b_adr 28 TR1d:08 typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 1 RESTORE_RDR val_b_adr 28 VR1d:08 val_frame 1d 0190 ; -------------------------------------------------------------------------------------- 0190 ; Micro event: UE_BKPT 0190 ; -------------------------------------------------------------------------------------- 0190 UE_BKPT: 0190 0190 <halt> ; Flow R 0191 0191 <halt> ; Flow R 0192 0192 <halt> ; Flow R 0193 0193 <halt> ; Flow R 0194 0194 <halt> ; Flow R 0195 0195 <halt> ; Flow R 0196 0196 <halt> ; Flow R 0197 0197 <halt> ; Flow R 0198 ; -------------------------------------------------------------------------------------- 0198 ; Micro event: UE_CHK_EXIT 0198 ; -------------------------------------------------------------------------------------- 0198 UE_CHK_EXIT: 0198 0198 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0199 0199 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 019a 019a seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 019b 019b <halt> ; Flow R 019c 019c <halt> ; Flow R 019d 019d <halt> ; Flow R 019e 019e <halt> ; Flow R 019f 019f <halt> ; Flow R 01a0 ; -------------------------------------------------------------------------------------- 01a0 ; Micro event: UE_FIELD_ERROR 01a0 ; -------------------------------------------------------------------------------------- 01a0 UE_FIELD_ERROR: 01a0 01a0 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 01a1 01a1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a2 01a2 fiu_tivi_src 8 type_var; Flow C 0x32b0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32b0 0x32b0 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01a3 01a3 <halt> ; Flow R 01a4 01a4 <halt> ; Flow R 01a5 01a5 <halt> ; Flow R 01a6 01a6 <halt> ; Flow R 01a7 01a7 <halt> ; Flow R 01a8 ; -------------------------------------------------------------------------------------- 01a8 ; Micro event: UE_CLASS 01a8 ; -------------------------------------------------------------------------------------- 01a8 UE_CLASS: 01a8 01a8 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a9 01a9 fiu_tivi_src 8 type_var; Flow C 0x32a7 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01aa 01aa <halt> ; Flow R 01ab 01ab <halt> ; Flow R 01ac 01ac <halt> ; Flow R 01ad 01ad <halt> ; Flow R 01ae 01ae <halt> ; Flow R 01af 01af <halt> ; Flow R 01b0 ; -------------------------------------------------------------------------------------- 01b0 ; Micro event: UE_BIN_EQ 01b0 ; -------------------------------------------------------------------------------------- 01b0 UE_BIN_EQ: 01b0 01b0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b1 01b1 <halt> ; Flow R 01b2 01b2 <halt> ; Flow R 01b3 01b3 <halt> ; Flow R 01b4 01b4 <halt> ; Flow R 01b5 01b5 <halt> ; Flow R 01b6 01b6 <halt> ; Flow R 01b7 01b7 <halt> ; Flow R 01b8 ; -------------------------------------------------------------------------------------- 01b8 ; Micro event: UE_BIN_OP 01b8 ; -------------------------------------------------------------------------------------- 01b8 UE_BIN_OP: 01b8 01b8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b9 01b9 <halt> ; Flow R 01ba 01ba <halt> ; Flow R 01bb 01bb <halt> ; Flow R 01bc 01bc <halt> ; Flow R 01bd 01bd <halt> ; Flow R 01be 01be <halt> ; Flow R 01bf 01bf <halt> ; Flow R 01c0 ; -------------------------------------------------------------------------------------- 01c0 ; Micro event: UE_TOS_OP 01c0 ; -------------------------------------------------------------------------------------- 01c0 UE_TOS_OP: 01c0 01c0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c1 01c1 <halt> ; Flow R 01c2 01c2 <halt> ; Flow R 01c3 01c3 <halt> ; Flow R 01c4 01c4 <halt> ; Flow R 01c5 01c5 <halt> ; Flow R 01c6 01c6 <halt> ; Flow R 01c7 01c7 <halt> ; Flow R 01c8 ; -------------------------------------------------------------------------------------- 01c8 ; Micro event: UE_TOSI_OP 01c8 ; -------------------------------------------------------------------------------------- 01c8 UE_TOSI_OP: 01c8 01c8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c9 01c9 <halt> ; Flow R 01ca 01ca <halt> ; Flow R 01cb 01cb <halt> ; Flow R 01cc 01cc <halt> ; Flow R 01cd 01cd <halt> ; Flow R 01ce 01ce <halt> ; Flow R 01cf 01cf <halt> ; Flow R 01d0 ; -------------------------------------------------------------------------------------- 01d0 ; Micro event: UE_PAGE_X 01d0 ; -------------------------------------------------------------------------------------- 01d0 UE_PAGE_X: 01d0 01d0 fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 27 VR07:07 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 7 01d1 01d1 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 01d2 01d2 fiu_mem_start c start_if_incmplt; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 6e INCOMPLETE_MEMORY_CYCLE_FOR_PAGE_CROSSING seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 01d3 01d3 <halt> ; Flow R 01d4 01d4 <halt> ; Flow R 01d5 01d5 <halt> ; Flow R 01d6 01d6 <halt> ; Flow R 01d7 01d7 <halt> ; Flow R 01d8 ; -------------------------------------------------------------------------------------- 01d8 ; Micro event: UE_CHK_SYS 01d8 ; -------------------------------------------------------------------------------------- 01d8 UE_CHK_SYS: 01d8 01d8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 01d9 01d9 <halt> ; Flow R 01da 01da <halt> ; Flow R 01db 01db <halt> ; Flow R 01dc 01dc <halt> ; Flow R 01dd 01dd <halt> ; Flow R 01de 01de <halt> ; Flow R 01df 01df <halt> ; Flow R 01e0 ; -------------------------------------------------------------------------------------- 01e0 ; Micro event: UE_NEW_PAK 01e0 ; -------------------------------------------------------------------------------------- 01e0 UE_NEW_PAK: 01e0 01e0 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01e1 01e1 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01e2 01e2 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 01e3 01e3 <halt> ; Flow R 01e4 01e4 <halt> ; Flow R 01e5 01e5 <halt> ; Flow R 01e6 01e6 <halt> ; Flow R 01e7 01e7 <halt> ; Flow R 01e8 ; -------------------------------------------------------------------------------------- 01e8 ; Micro event: UE_NEW_STS 01e8 ; -------------------------------------------------------------------------------------- 01e8 UE_NEW_STS: 01e8 01e8 <halt> ; Flow R 01e9 01e9 <halt> ; Flow R 01ea 01ea <halt> ; Flow R 01eb 01eb <halt> ; Flow R 01ec 01ec <halt> ; Flow R 01ed 01ed <halt> ; Flow R 01ee 01ee <halt> ; Flow R 01ef 01ef <halt> ; Flow R 01f0 ; -------------------------------------------------------------------------------------- 01f0 ; Micro event: UE_XFER_CP 01f0 ; -------------------------------------------------------------------------------------- 01f0 UE_XFER_CP: 01f0 01f0 <halt> ; Flow R 01f1 01f1 <halt> ; Flow R 01f2 01f2 <halt> ; Flow R 01f3 01f3 <halt> ; Flow R 01f4 01f4 <halt> ; Flow R 01f5 01f5 <halt> ; Flow R 01f6 01f6 <halt> ; Flow R 01f7 01f7 <halt> ; Flow R 01f8 ; -------------------------------------------------------------------------------------- 01f8 ; 0x0020-0x0030 Illegal - 01f8 ; 0x0037-0x0038 Illegal - 01f8 ; 0x003f-0x0040 Illegal - 01f8 ; 0x0047-0x0048 Illegal - 01f8 ; 0x004f-0x0050 Illegal - 01f8 ; 0x0057-0x0058 Illegal - 01f8 ; 0x005f-0x0067 Illegal - 01f8 ; 0x0077-0x007f Illegal - 01f8 ; 0x0083-0x0086 Illegal - 01f8 ; 0x0094 Illegal - 01f8 ; 0x00ae-0x00b2 Illegal - 01f8 ; 0x00c0-0x00c3 Illegal - 01f8 ; 0x00df Illegal - 01f8 ; 0x0102-0x0105 Illegal - 01f8 ; 0x0108 Illegal - 01f8 ; 0x0113 Illegal - 01f8 ; 0x0130-0x0131 Illegal - 01f8 ; 0x0134-0x0135 Illegal - 01f8 ; 0x0138-0x013b Illegal - 01f8 ; 0x0150-0x015a Illegal - 01f8 ; 0x0170-0x0176 Illegal - 01f8 ; 0x0180-0x0188 Illegal - 01f8 ; 0x018c Illegal - 01f8 ; 0x0190-0x019a Illegal - 01f8 ; 0x01a0-0x01a2 Illegal - 01f8 ; 0x01b0-0x01bd Illegal - 01f8 ; 0x01c8-0x01c9 Illegal - 01f8 ; 0x01e0-0x01ea Illegal - 01f8 ; 0x01f0-0x01f2 Illegal - 01f8 ; 0x0200-0x0204 Illegal - 01f8 ; 0x0207 Illegal - 01f8 ; 0x0280-0x0298 Illegal - 01f8 ; 0x02a1 Illegal - 01f8 ; 0x02a3 Illegal - 01f8 ; 0x02a6-0x02a7 Illegal - 01f8 ; 0x02ac-0x02bd Illegal - 01f8 ; 0x02c0-0x02c5 Illegal - 01f8 ; 0x02c8 Illegal - 01f8 ; 0x02ca Illegal - 01f8 ; 0x02cc-0x02cd Illegal - 01f8 ; 0x02d0-0x02fa Illegal - 01f8 ; 0x0300-0x0302 Illegal - 01f8 ; 0x0308-0x0310 Illegal - 01f8 ; 0x0313-0x0314 Illegal - 01f8 ; 0x0317 Illegal - 01f8 ; 0x031a Illegal - 01f8 ; 0x031f Illegal - 01f8 ; 0x0323 Illegal - 01f8 ; 0x0329 Illegal - 01f8 ; 0x032c Illegal - 01f8 ; 0x032f-0x0332 Illegal - 01f8 ; 0x0338-0x033f Illegal - 01f8 ; 0x0344-0x0345 Illegal - 01f8 ; 0x034a Illegal - 01f8 ; 0x034d Illegal - 01f8 ; 0x0352 Illegal - 01f8 ; 0x0357 Illegal - 01f8 ; 0x035a Illegal - 01f8 ; 0x035f-0x0369 Illegal - 01f8 ; 0x0370-0x0373 Illegal - 01f8 ; 0x0375-0x0376 Illegal - 01f8 ; 0x0379 Illegal - 01f8 ; 0x037c Illegal - 01f8 ; 0x037f-0x0383 Illegal - 01f8 ; 0x0388-0x038b Illegal - 01f8 ; 0x0390-0x0394 Illegal - 01f8 ; 0x03aa Illegal - 01f8 ; 0x03af-0x03b4 Illegal - 01f8 ; 0x03c0-0x03c3 Illegal - 01f8 ; 0x03c8-0x03cb Illegal - 01f8 ; 0x03d0 Illegal - 01f8 ; 0x03d7 Illegal - 01f8 ; 0x03e2 Illegal - 01f8 ; 0x03e7 Illegal - 01f8 ; 0x03f4 Illegal - 01f8 ; 0x03ff Illegal - 01f8 ; 0x1e00-0x1fff Illegal - 01f8 ; 0x3100-0x33ff Illegal - 01f8 ; 0x3500-0x35ff Illegal - 01f8 ; 0x3900-0x3bff Illegal - 01f8 ; 0x3d00-0x3dff Illegal - 01f8 ; 0x4000-0x40ff Illegal - 01f8 ; 0x0075-0x0076 QQUnknown InMicrocode 01f8 ; -------------------------------------------------------------------------------------- 01f8 MACRO_01f8_QQUnknown_InMicrocode: 01f8 MACRO_Illegal_-: 01f8 01f8 dispatch_brk_class 0 ; Flow C 0x32ad dispatch_csa_valid 0 dispatch_uadr 01f8 seq_br_type 7 Unconditional Call seq_branch_adr 32ad 0x32ad seq_random 05 ? 01f9 01f9 ioc_random 14 clear cpu running; Flow R seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 01 Halt+? 01fa 01fa <halt> ; Flow R 01fb 01fb <halt> ; Flow R 01fc 01fc <halt> ; Flow R 01fd 01fd <halt> ; Flow R 01fe 01fe <halt> ; Flow R 01ff 01ff <halt> ; Flow R 0200 0200 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 seq_random 01 Halt+? 0201 0201 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 seq_random 01 Halt+? 0202 0202 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 seq_random 01 Halt+? 0203 0203 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 seq_random 01 Halt+? 0204 0204 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 seq_random 01 Halt+? 0205 0205 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 seq_random 01 Halt+? 0206 0206 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 seq_random 01 Halt+? 0207 0207 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 seq_random 01 Halt+? 0208 0208 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 seq_random 01 Halt+? 0209 0209 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 seq_random 01 Halt+? 020a ; -------------------------------------------------------------------------------------- 020a ; Comes from: 020a ; 058e C False from color 0x058d 020a ; 0bc7 C False from color 0x0bab 020a ; 0bd3 C from color 0x0bab 020a ; 0bf9 C False from color 0x0bab 020a ; 0c05 C from color 0x0bab 020a ; 22ce C from color 0x0000 020a ; 2ac5 C False from color 0x2abf 020a ; 2ad5 C False from color 0x2abf 020a ; 2ad8 C False from color 0x2abf 020a ; 2ae0 C True from color 0x2add 020a ; 2ae6 C True from color 0x2add 020a ; 331b C from color 0x0000 020a ; 331e C from color 0x0000 020a ; 332d C from color 0x0000 020a ; 3337 C False from color 0x0000 020a ; 3339 C False from color 0x0000 020a ; 334e C from color MACRO_Action_Accept_Activation 020a ; 3351 C from color MACRO_Action_Accept_Activation 020a ; 3355 C from color MACRO_Action_Accept_Activation 020a ; 3362 C from color 0x2ee7 020a ; 3364 C from color 0x2ee7 020a ; 3694 C False from color 0x05a7 020a ; 36a0 C from color 0x36a0 020a ; 36a1 C from color 0x36a0 020a ; 36a8 C from color 0x05a7 020a ; 36ab C False from color 0x05a7 020a ; 36ae C False from color 0x05a7 020a ; 36b2 C False from color 0x05a7 020a ; 36b5 C True from color 0x05a7 020a ; 36bd C from color 0x05a7 020a ; 36cb C from color 0x05a7 020a ; -------------------------------------------------------------------------------------- 020a 020a ioc_random 14 clear cpu running; Flow J 0x200 seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 020b ; -------------------------------------------------------------------------------------- 020b ; Comes from: 020b ; 081b C False from color 0x0000 020b ; 083c C False from color 0x0000 020b ; 0854 C False from color 0x0820 020b ; -------------------------------------------------------------------------------------- 020b 020b ioc_random 14 clear cpu running; Flow J 0x201 seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 020c ; -------------------------------------------------------------------------------------- 020c ; Comes from: 020c ; 0122 C False from color 0x0000 020c ; 081e C from color 0x0000 020c ; 0827 C False from color 0x0000 020c ; 0847 C True from color 0x0820 020c ; 0848 C True from color 0x0820 020c ; 0849 C True from color 0x0820 020c ; 0872 C True from color 0x0821 020c ; -------------------------------------------------------------------------------------- 020c 020c ioc_random 14 clear cpu running; Flow J 0x202 seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 020d ; -------------------------------------------------------------------------------------- 020d ; Comes from: 020d ; 01b0 C from color UE_BIN_EQ 020d ; 01b8 C from color UE_BIN_OP 020d ; 01c0 C from color UE_TOS_OP 020d ; 01c8 C from color UE_TOSI_OP 020d ; 06bc C from color 0x062d 020d ; 06c4 C False from color 0x06c3 020d ; 06c9 C from color 0x06b6 020d ; 06cc C False from color 0x06cb 020d ; 06dc C False from color 0x0000 020d ; 08be C False from color 0x0127 020d ; 08d2 C True from color 0x0127 020d ; 08e6 C True from color 0x08e6 020d ; 08e7 C True from color 0x08e6 020d ; 08eb C True from color 0x08e6 020d ; 08ee C True from color 0x08e6 020d ; 08f1 C True from color 0x08e6 020d ; 08f4 C True from color 0x08e6 020d ; 098e C from color 0x098e 020d ; 09b0 C from color 0x09b0 020d ; 09c0 C from color 0x09c0 020d ; 0a7e C from color 0x0a7e 020d ; 0a92 C from color 0x0a92 020d ; 0aa6 C from color 0x0a35 020d ; 0d56 C False from color 0x0000 020d ; 0ef1 C True from color 0x0000 020d ; 0ef5 C True from color 0x0000 020d ; 0ef7 C from color 0x0000 020d ; 0ef8 C from color 0x0000 020d ; 0f0a C False from color 0x0000 020d ; 191d C from color 0x191d 020d ; 191e C from color 0x191d 020d ; 191f C from color 0x191d 020d ; 1920 C from color 0x191d 020d ; 1924 C from color 0x1924 020d ; 1928 C from color 0x1928 020d ; 192c C from color 0x0000 020d ; 2a72 C True from color 0x0000 020d ; 2a74 C True from color 0x0000 020d ; 2a76 C True from color 0x0000 020d ; 2a78 C True from color 0x0000 020d ; 2a7a C True from color 0x0000 020d ; 2a7d C True from color 0x0000 020d ; 2abc C from color 0x0127 020d ; 34a2 C from color 0x349d 020d ; 395b C False from color 0x0000 020d ; 39fd C False from color 0x39fb 020d ; 3a0c C False from color 0x0000 020d ; 3b64 C from color 0x3b5f 020d ; -------------------------------------------------------------------------------------- 020d 020d ioc_random 14 clear cpu running; Flow J 0x203 seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 020e ; -------------------------------------------------------------------------------------- 020e ; Comes from: 020e ; 018d C from color 0x0127 020e ; -------------------------------------------------------------------------------------- 020e 020e ioc_random 14 clear cpu running; Flow J 0x204 seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 020f 020f ioc_random 14 clear cpu running; Flow J 0x205 seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 0210 ; -------------------------------------------------------------------------------------- 0210 ; Comes from: 0210 ; 0116 C from color 0x0000 0210 ; 01d0 C from color UE_PAGE_X 0210 ; 01d8 C from color UE_CHK_SYS 0210 ; 026a C from color 0x026a 0210 ; 0299 C from color 0x0299 0210 ; 029d C from color 0x0000 0210 ; 02b6 C from color 0x0000 0210 ; 02d5 C from color 0x02ca 0210 ; 02ea C from color 0x0000 0210 ; 0311 C from color 0x0000 0210 ; 0315 C from color 0x0000 0210 ; 0316 C from color 0x0000 0210 ; 0326 C from color MACRO_Action_Set_Priority 0210 ; 0329 C from color MACRO_Action_Set_Priority 0210 ; 032a C from color 0x032a 0210 ; 032b C from color 0x032b 0210 ; 032e C from color 0x032c 0210 ; 0330 C from color 0x032f 0210 ; 0337 C from color 0x0000 0210 ; 0339 C from color 0x0338 0210 ; 033b C from color 0x033a 0210 ; 033c C from color 0x033c 0210 ; 033d C from color 0x033d 0210 ; 0382 C from color 0x0380 0210 ; 0385 C from color 0x0383 0210 ; 0393 C from color 0x0000 0210 ; 039a C from color 0x0398 0210 ; 03ac C from color 0x0398 0210 ; 03ad C from color 0x03ad 0210 ; 03b0 C from color 0x03ae 0210 ; 03be C from color 0x0000 0210 ; 03d3 C from color 0x03d1 0210 ; 03ef C from color 0x0000 0210 ; 03f8 C from color 0x03f8 0210 ; 0420 C from color 0x0000 0210 ; 0424 C from color 0x0421 0210 ; 042a C from color 0x0000 0210 ; 0447 C from color 0x0000 0210 ; 0468 C from color 0x0000 0210 ; 047f C from color 0x0000 0210 ; 0499 C from color 0x0000 0210 ; 049e C from color 0x0000 0210 ; 04af C from color 0x0000 0210 ; 04b2 C from color 0x04b2 0210 ; 04bc C from color 0x04bb 0210 ; 04bd C from color 0x04bd 0210 ; 04be C from color 0x04be 0210 ; 04c2 C from color 0x04c2 0210 ; 04c3 C from color 0x04c3 0210 ; 04c4 C from color 0x04c4 0210 ; 04f5 C from color 0x04f5 0210 ; 04f7 C from color 0x04f7 0210 ; 04f8 C from color 0x04f8 0210 ; 04f9 C from color 0x04f9 0210 ; 0516 C from color 0x0515 0210 ; 0518 C from color 0x0518 0210 ; 0519 C from color 0x0519 0210 ; 0556 C from color MACRO_Action_Pop_Auxiliary 0210 ; 0564 C from color 0x0564 0210 ; 0566 C from color 0x0565 0210 ; 0571 C from color 0x0000 0210 ; 0572 C from color 0x0572 0210 ; 0575 C from color 0x0573 0210 ; 0577 C from color 0x0576 0210 ; 057b C from color 0x0573 0210 ; 057e C from color 0x0573 0210 ; 0581 C from color 0x0573 0210 ; 0583 C from color 0x0582 0210 ; 0585 C from color 0x0584 0210 ; 0587 C from color 0x0586 0210 ; 058c C from color 0x0573 0210 ; 05a9 C from color 0x05a7 0210 ; 05ae C from color 0x05a7 0210 ; 05b2 C from color 0x05af 0210 ; 05b3 C from color 0x05b3 0210 ; 05b4 C from color 0x05b4 0210 ; 05c6 C from color 0x05a7 0210 ; 05d1 C from color 0x05d0 0210 ; 05d5 C from color 0x05a7 0210 ; 05d7 C from color 0x05d6 0210 ; 05e8 C from color 0x05db 0210 ; 05ea C from color 0x05e9 0210 ; 05eb C from color 0x05eb 0210 ; 05f8 C from color 0x05ec 0210 ; 05f9 C from color 0x05f9 0210 ; 05fa C from color 0x05fa 0210 ; 0605 C from color 0x05fb 0210 ; 060f C from color 0x0000 0210 ; 0616 C from color 0x0000 0210 ; 061a C from color 0x0000 0210 ; 061f C from color 0x0000 0210 ; 0624 C from color 0x05fb 0210 ; 062c C from color 0x062a 0210 ; 062e C from color 0x062e 0210 ; 0644 C from color 0x0000 0210 ; 0663 C from color 0x0000 0210 ; 0667 C from color 0x0664 0210 ; 0668 C from color 0x0668 0210 ; 0669 C from color 0x0669 0210 ; 0682 C from color 0x066a 0210 ; 0683 C from color 0x0683 0210 ; 0685 C from color 0x0684 0210 ; 0694 C from color 0x0693 0210 ; 06b5 C from color 0x0000 0210 ; 06b9 C from color 0x06b6 0210 ; 06be C from color 0x062d 0210 ; 06c2 C from color 0x06b6 0210 ; 06c6 C from color 0x06c3 0210 ; 06ca C from color 0x06b6 0210 ; 06d1 C from color 0x06ce 0210 ; 06da C from color 0x06d2 0210 ; 06db C from color 0x06db 0210 ; 06e3 C from color 0x06ce 0210 ; 06e7 C from color 0x06e6 0210 ; 06fb C from color 0x06d2 0210 ; 06fc C from color 0x06fc 0210 ; 0700 C from color 0x06fd 0210 ; 0716 C from color 0x0000 0210 ; 071b C from color 0x0717 0210 ; 071f C from color 0x071c 0210 ; 073a C from color 0x0000 0210 ; 073c C from color 0x0117 0210 ; 073d C from color 0x073d 0210 ; 0745 C from color 0x0000 0210 ; 0758 C from color 0x0203 0210 ; 0773 C from color 0x0773 0210 ; 079e C from color 0x0799 0210 ; 07a2 C from color 0x0799 0210 ; 07b3 C from color 0x07b1 0210 ; 07b8 C from color 0x07b5 0210 ; 07bf C from color 0x07b9 0210 ; 07c0 C from color 0x07c0 0210 ; 07c2 C from color 0x07c1 0210 ; 07c3 C from color 0x07c3 0210 ; 07d9 C from color 0x07c4 0210 ; 07ee C from color 0x07e8 0210 ; 0806 C from color 0x07ef 0210 ; 0807 C from color 0x0807 0210 ; 0984 C from color MACRO_Declare_Variable_Any 0210 ; 0994 C from color MACRO_Declare_Variable_Any,Visible 0210 ; 09a6 C from color MACRO_Execute_Any,Equal 0210 ; 09b6 C from color MACRO_Execute_Any,Not_Equal 0210 ; 09c8 C from color MACRO_Execute_Any,Address 0210 ; 0a2a C from color MACRO_Execute_Any,Convert 0210 ; 0a3c C from color MACRO_Execute_Any,Convert 0210 ; 0a54 C from color 0x0a54 0210 ; 0a55 C from color 0x0a55 0210 ; 0a56 C from color 0x0a56 0210 ; 0a65 C from color 0x0a65 0210 ; 0a66 C from color 0x0a66 0210 ; 0a67 C from color 0x0a67 0210 ; 0a74 C from color 0x0a50 0210 ; 0a88 C from color 0x0a50 0210 ; 0a9c C from color MACRO_Execute_Any,Convert 0210 ; 0abf C from color 0x0abf 0210 ; 0ac0 C from color 0x0ac0 0210 ; 0ac1 C from color 0x0ac1 0210 ; 0ac5 C from color 0x0ac5 0210 ; 0ac7 C from color 0x0ac7 0210 ; 0dbd C from color 0x0db3 0210 ; 0e07 C from color 0x0000 0210 ; 0e0e C from color 0x0000 0210 ; 0e1b C from color 0x0000 0210 ; 0eae C from color 0x0000 0210 ; 0eb9 C from color 0x0000 0210 ; 0ebd C from color 0x0000 0210 ; 0ed3 C from color 0x0000 0210 ; 0ed9 C from color 0x0ed8 0210 ; 0f03 C from color 0x0efa 0210 ; 0f06 C from color 0x0f04 0210 ; 0f11 C from color 0x0000 0210 ; 0f18 C from color 0x0f18 0210 ; 0f1c C from color 0x0efa 0210 ; 0f1d C from color 0x0f1d 0210 ; 0f27 C from color 0x0efa 0210 ; 0f2f C from color 0x0efa 0210 ; 0f30 C from color 0x0f30 0210 ; 0f39 C from color 0x0efa 0210 ; 0f3a C from color 0x0f3a 0210 ; 0f3d C from color 0x0f3d 0210 ; 0f42 C from color 0x0efa 0210 ; 0f43 C from color 0x0efa 0210 ; 0f5d C from color 0x0efa 0210 ; 0f69 C from color 0x0f66 0210 ; 0f6e C from color 0x0f64 0210 ; 0f7e C from color 0x0efa 0210 ; 0f89 C from color 0x0efa 0210 ; 0fb4 C from color 0x0efa 0210 ; 0fba C from color 0x0fba 0210 ; 0fbf C from color 0x0fbb 0210 ; 0fc1 C from color 0x0fc0 0210 ; 0fce C from color 0x0fce 0210 ; 0ff1 C from color 0x0fd2 0210 ; 1003 C from color 0x0fd2 0210 ; 1019 C from color 0x0fd2 0210 ; 1055 C from color 0x0fd2 0210 ; 1056 C from color 0x0fd2 0210 ; 105d C from color 0x105d 0210 ; 105e C from color 0x1057 0210 ; 106a C from color 0x1066 0210 ; 106c C from color 0x0fc9 0210 ; 1073 C from color 0x0efa 0210 ; 1076 C from color 0x0efa 0210 ; 107a C from color 0x0efa 0210 ; 10bc C from color 0x10bc 0210 ; 10bd C from color 0x10bd 0210 ; 10be C from color 0x10be 0210 ; 10c2 C from color 0x10c2 0210 ; 10c3 C from color 0x10c3 0210 ; 10c4 C from color 0x10c4 0210 ; 10d5 C from color 0x10d4 0210 ; 1102 C from color 0x1102 0210 ; 1106 C from color 0x1106 0210 ; 110a C from color 0x110a 0210 ; 110e C from color 0x110e 0210 ; 1113 C from color 0x1112 0210 ; 1114 C from color 0x1114 0210 ; 1115 C from color 0x1115 0210 ; 1119 C from color 0x1119 0210 ; 111a C from color 0x111a 0210 ; 111b C from color 0x111b 0210 ; 1148 C from color 0x110f 0210 ; 11f7 C from color 0x11f2 0210 ; 11f8 C from color 0x11f8 0210 ; 11f9 C from color 0x11f9 0210 ; 11fd C from color 0x11fd 0210 ; 11fe C from color 0x11fe 0210 ; 11ff C from color 0x11ff 0210 ; 1255 C from color 0x1250 0210 ; 1256 C from color 0x1256 0210 ; 1257 C from color 0x1257 0210 ; 125b C from color 0x125b 0210 ; 125c C from color 0x125c 0210 ; 125d C from color 0x125d 0210 ; 1629 C from color MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 0210 ; 163b C from color MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 0210 ; 164d C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 0210 ; 165f C from color MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 0210 ; 1788 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 178a C from color 0x1789 0210 ; 1791 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1795 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1b21 C from color MACRO_Execute_Access,Deallocate 0210 ; 1c97 C from color 0x0000 0210 ; 1c98 C from color 0x1c98 0210 ; 1ca9 C from color 0x1ca9 0210 ; 1caa C from color 0x1caa 0210 ; 1cab C from color 0x1cab 0210 ; 1d0f C from color 0x0000 0210 ; 1d30 C from color 0x1d2e 0210 ; 1d32 C from color 0x1d31 0210 ; 1d34 C from color 0x1d33 0210 ; 1d35 C from color 0x1d35 0210 ; 1d38 C from color 0x1d38 0210 ; 1d3a C from color 0x1d3a 0210 ; 1d3c C from color 0x1d3c 0210 ; 1d3d C from color 0x1d3d 0210 ; 1d3f C from color 0x1d3e 0210 ; 1d40 C from color 0x1d40 0210 ; 1d41 C from color 0x1d41 0210 ; 1d42 C from color 0x1d42 0210 ; 1d44 C from color 0x1d44 0210 ; 1d46 C from color 0x1d46 0210 ; 1d4d C from color 0x1d4c 0210 ; 1d4e C from color 0x1d4e 0210 ; 1d4f C from color 0x1d4f 0210 ; 1d53 C from color 0x1d53 0210 ; 1d54 C from color 0x1d54 0210 ; 1d55 C from color 0x1d55 0210 ; 1e92 C from color 0x1e91 0210 ; 1e93 C from color 0x1e93 0210 ; 1ec3 C from color 0x1ec3 0210 ; 1f66 C from color 0x1f66 0210 ; 1f68 C from color 0x1f68 0210 ; 1f69 C from color 0x1f69 0210 ; 1f6a C from color 0x1f6a 0210 ; 1fe4 C from color MACRO_Complete_Type_Array,By_Constraining 0210 ; 2033 C from color 0x2012 0210 ; 2073 C from color 0x2073 0210 ; 2074 C from color 0x2074 0210 ; 2075 C from color 0x2075 0210 ; 2079 C from color 0x2079 0210 ; 207a C from color 0x207a 0210 ; 207b C from color 0x207b 0210 ; 20ac C from color 0x20ac 0210 ; 20ad C from color 0x20ad 0210 ; 20ae C from color 0x20ae 0210 ; 20b2 C from color 0x20b2 0210 ; 20b3 C from color 0x20b3 0210 ; 20b4 C from color 0x20b4 0210 ; 2180 C from color MACRO_Declare_Type_Array,Constrained 0210 ; 21dc C from color 0x2005 0210 ; 21f3 C from color 0x21f3 0210 ; 21f5 C from color 0x21f5 0210 ; 21f6 C from color 0x21f6 0210 ; 21f7 C from color 0x21f7 0210 ; 2312 C from color 0x2312 0210 ; 2346 C from color 0x2344 0210 ; 2390 C from color 0x2390 0210 ; 244a C from color 0x240b 0210 ; 2493 C from color 0x248a 0210 ; 255d C from color MACRO_Complete_Type_Variant_Record,By_Defining 0210 ; 256a C from color 0x256a 0210 ; 256b C from color 0x256b 0210 ; 2590 C from color MACRO_Complete_Type_Variant_Record,By_Defining 0210 ; 266b C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 2689 C from color 0x2686 0210 ; 268a C from color 0x268a 0210 ; 268f C from color 0x268b 0210 ; 269e C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 26c3 C from color 0x26c3 0210 ; 26c4 C from color 0x26c4 0210 ; 26c5 C from color 0x26c5 0210 ; 26c9 C from color 0x26c9 0210 ; 26ca C from color 0x26ca 0210 ; 26cb C from color 0x26cb 0210 ; 26e4 C from color 0x26e2 0210 ; 26e6 C from color 0x26e6 0210 ; 26e7 C from color 0x26e7 0210 ; 26e8 C from color 0x26e8 0210 ; 27e3 C from color 0x0000 0210 ; 292e C from color 0x0000 0210 ; 2a64 C from color ML_Resolve Reference 0210 ; 2a93 C from color 0x0127 0210 ; 2a95 C from color 0x0127 0210 ; 2a96 C from color 0x0127 0210 ; 2a9b C from color 0x0127 0210 ; 2b08 C from color 0x2b08 0210 ; 2b09 C from color 0x2b09 0210 ; 2b0a C from color 0x2b0a 0210 ; 2b0b C from color 0x2b0b 0210 ; 2b0c C from color 0x2b0c 0210 ; 2b0f C from color 0x2b0f 0210 ; 2b10 C from color 0x2b10 0210 ; 2b11 C from color 0x2b11 0210 ; 2b1e C from color 0x2b1e 0210 ; 2b1f C from color 0x2b1f 0210 ; 2b20 C from color 0x2b20 0210 ; 2b24 C from color 0x2b24 0210 ; 2b25 C from color 0x2b25 0210 ; 2b26 C from color 0x2b26 0210 ; 2b66 C from color MACRO_Complete_Type_Task,By_Renaming 0210 ; 2b70 C from color 0x0000 0210 ; 2b73 C from color 0x2b73 0210 ; 2c28 C from color 0x0000 0210 ; 2c42 C from color 0x0000 0210 ; 2c4f C from color 0x2c4e 0210 ; 2c52 C from color 0x2c52 0210 ; 2c5a C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 0210 ; 2c81 C from color MACRO_Execute_Select,Member_Write,fieldnum 0210 ; 2c86 C from color 0x2c86 0210 ; 2c88 C from color 0x2c87 0210 ; 2cd7 C from color MACRO_Action_Elaborate_Subprogram 0210 ; 2cdd C from color MACRO_Action_Check_Subprogram_Elaborated 0210 ; 2d15 C from color 0x2d13 0210 ; 2d44 C from color ML_break_class 0210 ; 2d47 C from color 0x2d45 0210 ; 2d57 C from color 0x2d55 0210 ; 2df0 C from color 0x0000 0210 ; 2df6 C from color 0x0000 0210 ; 2e29 C from color 0x0000 0210 ; 2eb2 C from color 0x2eb2 0210 ; 2ec8 C from color 0x0000 0210 ; 2efa C from color 0x2ee7 0210 ; 2f15 C from color 0x2ec9 0210 ; 2f2a C from color 0x06b6 0210 ; 2f3e C from color 0x2ec9 0210 ; 2f64 C from color 0x0000 0210 ; 2f81 C from color 0x2f75 0210 ; 2f97 C from color 0x0000 0210 ; 3298 C from color 0x3298 0210 ; 32ca C from color 0x0000 0210 ; 32e0 C from color 0x0000 0210 ; 3379 C from color 0x0000 0210 ; 337e C from color 0x0000 0210 ; 3384 C from color 0x0000 0210 ; 3389 C from color 0x0000 0210 ; 338d C from color 0x0000 0210 ; 3395 C from color 0x0000 0210 ; 3396 C from color 0x3396 0210 ; 339b C from color 0x3397 0210 ; 339e C from color 0x3397 0210 ; 33a0 C from color 0x3397 0210 ; 33a3 C from color 0x3397 0210 ; 33a4 C from color 0x33a4 0210 ; 33ba C from color 0x3397 0210 ; 33bb C from color 0x33bb 0210 ; 33bc C from color 0x0000 0210 ; 33cb C from color 0x0f07 0210 ; 33cd C from color 0x33cc 0210 ; 33e8 C from color 0x0000 0210 ; 33f3 C from color 0x0000 0210 ; 33f6 C from color 0x0000 0210 ; 3410 C from color 0x22cd 0210 ; 3411 C from color 0x3411 0210 ; 3412 C from color 0x3412 0210 ; 3413 C from color 0x3413 0210 ; 3414 C from color 0x3414 0210 ; 341f C from color 0x0000 0210 ; 3452 C from color 0x02c9 0210 ; 3454 C from color 0x0fc9 0210 ; 346c C from color 0x0000 0210 ; 346d C from color 0x346d 0210 ; 3470 C from color 0x0000 0210 ; 3471 C from color 0x3471 0210 ; 3473 C from color 0x3472 0210 ; 3474 C from color 0x3474 0210 ; 3475 C from color 0x3475 0210 ; 347e C from color 0x347d 0210 ; 347f C from color 0x347f 0210 ; 3480 C from color 0x3480 0210 ; 3481 C from color 0x3481 0210 ; 3491 C from color 0x348f 0210 ; 3492 C from color 0x3492 0210 ; 3497 C from color 0x3495 0210 ; 34b6 C from color 0x0000 0210 ; 34c6 C from color 0x0000 0210 ; 34d1 C from color 0x0f07 0210 ; 34d3 C from color 0x34d2 0210 ; 34d6 C from color 0x34d4 0210 ; 34dc C from color 0x0000 0210 ; 34dd C from color 0x34dd 0210 ; 34df C from color 0x34de 0210 ; 34eb C from color 0x0000 0210 ; 34ee C from color 0x0000 0210 ; 34f1 C from color 0x0000 0210 ; 3530 C from color 0x0000 0210 ; 353c C from color 0x0000 0210 ; 3546 C from color 0x0000 0210 ; 3548 C from color 0x0000 0210 ; 3549 C from color 0x3549 0210 ; 3552 C from color 0x0000 0210 ; 3554 C from color 0x0000 0210 ; 3555 C from color 0x3555 0210 ; 3591 C from color 0x0000 0210 ; 35a0 C from color 0x0000 0210 ; 35a2 C from color 0x35a2 0210 ; 3619 C from color 0x0000 0210 ; 361c C from color 0x361a 0210 ; 363b C from color 0x362e 0210 ; 363c C from color 0x363c 0210 ; 365d C from color 0x3659 0210 ; 365f C from color 0x365e 0210 ; 3663 C from color 0x3660 0210 ; 36ed C from color 0x36eb 0210 ; 36ee C from color 0x36ee 0210 ; 36f3 C from color 0x0000 0210 ; 36fa C from color 0x36fa 0210 ; 36fb C from color 0x36fb 0210 ; 36fc C from color 0x36fc 0210 ; 3706 C from color 0x36f7 0210 ; 3718 C from color 0x0000 0210 ; 371c C from color 0x0000 0210 ; 3720 C from color 0x371d 0210 ; 3723 C from color 0x0000 0210 ; 3726 C from color 0x3726 0210 ; 3727 C from color 0x3727 0210 ; 3728 C from color 0x3728 0210 ; 3729 C from color 0x3729 0210 ; 372a C from color 0x372a 0210 ; 3730 C from color 0x0000 0210 ; 3739 C from color 0x3737 0210 ; 373d C from color 0x373a 0210 ; 3746 C from color 0x3742 0210 ; 3759 C from color 0x3742 0210 ; 3766 C from color 0x3766 0210 ; 3767 C from color 0x3767 0210 ; 3768 C from color 0x3768 0210 ; 376a C from color 0x376a 0210 ; 376e C from color 0x376e 0210 ; 376f C from color 0x3737 0210 ; 3775 C from color 0x0000 0210 ; 377d C from color 0x3769 0210 ; 377e C from color 0x377e 0210 ; 3787 C from color 0x3769 0210 ; 3789 C from color 0x0000 0210 ; 378f C from color 0x0000 0210 ; 3794 C from color 0x3790 0210 ; 3796 C from color 0x3795 0210 ; 379d C from color 0x3797 0210 ; 37ac C from color 0x0000 0210 ; 37c5 C from color 0x0000 0210 ; 37df C from color MACRO_Execute_Select,Rendezvous 0210 ; 37ff C from color 0x37e0 0210 ; 3805 C from color 0x3803 0210 ; 380e C from color 0x3802 0210 ; 381d C from color 0x3803 0210 ; 3826 C from color 0x3803 0210 ; 383d C from color 0x0000 0210 ; 3885 C from color 0x387e 0210 ; 389e C from color 0x2abf 0210 ; 38c3 C from color 0x38b7 0210 ; 38c6 C from color 0x38c4 0210 ; 38d9 C from color 0x38cc 0210 ; 391e C from color 0x0000 0210 ; 3924 C from color 0x0000 0210 ; 393e C from color 0x03fa 0210 ; 394e C from color 0x0913 0210 ; 3954 C from color 0x0000 0210 ; 395c C from color 0x0000 0210 ; 3972 C from color 0x03fa 0210 ; 3973 C from color 0x03fa 0210 ; 3974 C from color 0x3974 0210 ; 3975 C from color 0x3975 0210 ; 3984 C from color 0x3976 0210 ; 398d C from color 0x3978 0210 ; 39af C from color 0x0000 0210 ; 39b1 C from color 0x0000 0210 ; 39b5 C from color 0x39b2 0210 ; 39c2 C from color 0x0000 0210 ; 39ed C from color 0x0000 0210 ; 39f5 C from color 0x0000 0210 ; 39fa C from color 0x0000 0210 ; 39fe C from color 0x39fb 0210 ; 3a08 C from color 0x0000 0210 ; 3a0d C from color 0x0000 0210 ; 3a2b C from color 0x03fa 0210 ; 3a3a C from color 0x3a39 0210 ; 3a48 C from color 0x0000 0210 ; 3a51 C from color 0x0000 0210 ; 3a73 C from color 0x0000 0210 ; 3a85 C from color 0x3a85 0210 ; 3a86 C from color 0x3a86 0210 ; 3a89 C from color 0x3a89 0210 ; 3a8a C from color 0x3a8a 0210 ; 3a8c C from color 0x3a8c 0210 ; 3a8d C from color 0x3a8d 0210 ; 3a8e C from color 0x3a8e 0210 ; 3a8f C from color 0x3a8f 0210 ; 3a95 C from color 0x3a95 0210 ; 3a96 C from color 0x3a96 0210 ; 3a97 C from color 0x3a97 0210 ; 3ab1 C from color 0x0000 0210 ; 3ab5 C from color 0x0000 0210 ; 3ac1 C from color 0x0000 0210 ; 3ae3 C from color 0x0000 0210 ; 3aea C from color 0x0000 0210 ; 3aeb C from color 0x03fa 0210 ; 3b4f C from color 0x0000 0210 ; 3b53 C from color 0x3b52 0210 ; 3b58 C from color 0x0200 0210 ; 3b5a C from color 0x3b59 0210 ; 3b5e C from color 0x0efa 0210 ; 3b67 C from color 0x3b67 0210 ; 3b7f C from color 0x3b4d 0210 ; 3b81 C from color 0x3b4d 0210 ; 3b84 C from color 0x3b4d 0210 ; 3b8e C from color 0x3b8d 0210 ; 3b94 C from color 0x3b8f 0210 ; -------------------------------------------------------------------------------------- 0210 0210 ioc_random 14 clear cpu running; Flow J 0x206 seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 0211 ; -------------------------------------------------------------------------------------- 0211 ; Comes from: 0211 ; 03ae C True from color 0x03ae 0211 ; 06d6 C True from color 0x06d2 0211 ; 077c C False from color 0x0767 0211 ; 0783 C from color 0x0767 0211 ; 084b C False from color 0x0820 0211 ; 0878 C True from color 0x0821 0211 ; 0b72 C False from color 0x0b70 0211 ; 0b76 C False from color 0x0b74 0211 ; 0b7a C False from color 0x0b78 0211 ; 0ed4 C False from color 0x0203 0211 ; 0fc4 C from color 0x0fc0 0211 ; 108d C from color 0x0efa 0211 ; 361a C True from color 0x361a 0211 ; 371d C False from color 0x371d 0211 ; 371f C True from color 0x371d 0211 ; 3784 C True from color 0x3769 0211 ; 3785 C False from color 0x3769 0211 ; 3786 C False from color 0x3769 0211 ; 379c C False from color 0x3797 0211 ; 3b5d C True from color 0x0efa 0211 ; -------------------------------------------------------------------------------------- 0211 0211 ioc_random 14 clear cpu running; Flow J 0x207 seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 0212 ; -------------------------------------------------------------------------------------- 0212 ; Comes from: 0212 ; 0ed0 C from color 0x0000 0212 ; -------------------------------------------------------------------------------------- 0212 0212 ioc_random 14 clear cpu running; Flow J 0x208 seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 0213 ; -------------------------------------------------------------------------------------- 0213 ; Comes from: 0213 ; 0ecf C from color 0x0000 0213 ; -------------------------------------------------------------------------------------- 0213 0213 ioc_random 14 clear cpu running; Flow J 0x209 seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 0214 ; -------------------------------------------------------------------------------------- 0214 ; 0x00bf Action Accept_Activation 0214 ; -------------------------------------------------------------------------------------- 0214 MACRO_Action_Accept_Activation: 0214 0214 dispatch_brk_class 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0214 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0215 0215 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a4 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0216 0216 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x217 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0219 0x0219 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0217 0217 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0218 0218 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3919 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3919 0x3919 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0219 0219 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 021a 021a seq_br_type 2 Push (branch address); Flow J 0x21b seq_branch_adr 0228 0x0228 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 021b 021b fiu_mem_start 2 start-rd; Flow J cc=False 0x220 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0220 0x0220 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 021c 021c <default> 021d 021d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 021e 021e ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 021f 021f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x221 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0220 0220 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0221 0221 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0222 0222 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0223 0223 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 0224 0224 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3279 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0225 0225 ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 val_c_adr 3c GP03 0226 0226 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0227 0227 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 val_b_adr 03 GP03 0228 0228 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0229 0229 <halt> ; Flow R 022a ; -------------------------------------------------------------------------------------- 022a ; 0x00bc Action Signal_Activated 022a ; -------------------------------------------------------------------------------------- 022a MACRO_Action_Signal_Activated: 022a 022a dispatch_brk_class 3 ; Flow C 0x337f dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 022a seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f 022b 022b fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 022c 022c fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 022d 022d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 022e 022e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 022f 022f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x395d seq_br_type 5 Call True seq_branch_adr 395d 0x395d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0230 0230 seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0231 0231 <halt> ; Flow R 0232 ; -------------------------------------------------------------------------------------- 0232 ; 0x00be Action Activate_Tasks 0232 ; -------------------------------------------------------------------------------------- 0232 MACRO_Action_Activate_Tasks: 0232 0232 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0232 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0233 0233 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f 0234 0234 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR07:0f val_frame 7 0235 0235 ioc_load_wdr 0 ; Flow J cc=False 0x526 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0236 0236 fiu_mem_start 2 start-rd; Flow C 0x333f ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 333f 0x333f seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 0237 0237 seq_br_type 7 Unconditional Call; Flow C 0x23a seq_branch_adr 023a 0x023a seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0238 0238 seq_br_type 2 Push (branch address); Flow J 0x239 seq_branch_adr 0238 0x0238 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0239 0239 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x334a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 334a 0x334a typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 023a 023a fiu_load_var 1 hold_var; Flow C cc=True 0x245 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 023b 023b typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 023c 023c fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 023d 023d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x394f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 394f 0x394f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 03 GP03 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 023e 023e ioc_tvbs 2 fiu+val; Flow J cc=True 0x242 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 023f 023f seq_br_type 2 Push (branch address); Flow J 0x240 seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0240 0240 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3373 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0241 0241 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0242 0242 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x244 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0244 0x0244 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0243 0243 ioc_tvbs 2 fiu+val; Flow C 0x32a4 seq_br_type 7 Unconditional Call seq_branch_adr 32a4 0x32a4 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0244 0244 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0245 ; -------------------------------------------------------------------------------------- 0245 ; Comes from: 0245 ; 023a C True from color 0x0000 0245 ; 0253 C True from color 0x0000 0245 ; 02d1 C True from color 0x02ca 0245 ; -------------------------------------------------------------------------------------- 0245 0245 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 0246 0246 fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 0247 0247 <halt> ; Flow R 0248 ; -------------------------------------------------------------------------------------- 0248 ; 0x00bd Action Activate_Heap_Tasks 0248 ; -------------------------------------------------------------------------------------- 0248 MACRO_Action_Activate_Heap_Tasks: 0248 0248 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0248 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0249 0249 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f 024a 024a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR05:18 val_frame 5 024b 024b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x25f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 025f 0x025f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 024c 024c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 024d 024d ioc_load_wdr 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 024e 024e fiu_mem_start 2 start-rd; Flow C 0x3347 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3347 0x3347 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 024f 024f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x260 seq_br_type f Unconditional Case Call seq_branch_adr 0260 0x0260 seq_en_micro 0 0250 0250 seq_br_type 2 Push (branch address); Flow J 0x251 seq_branch_adr 0250 0x0250 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0251 0251 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x334a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 334a 0x334a seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 0252 0252 fiu_tivi_src c mar_0xc; Flow C cc=False 0x266 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0266 0x0266 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0253 0253 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0254 0254 ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0255 0255 fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0256 0256 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x394f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 394f 0x394f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 02 GP02 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0257 0257 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x258 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 025d 0x025d seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 0258 0258 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0259 0259 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 025a 025a seq_b_timing 1 Latch Condition; Flow J cc=True 0x25d seq_br_type 1 Branch True seq_branch_adr 025d 0x025d typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025b 025b fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3373 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 025c 025c seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 025d 025d typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025e 025e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a4 seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 23 TR02:03 typ_frame 2 025f 025f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0260 0260 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0261 0261 seq_br_type 3 Unconditional Branch; Flow J 0x252 seq_branch_adr 0252 0x0252 0262 0262 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0263 0263 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0264 0264 seq_b_timing 1 Latch Condition; Flow J cc=True 0x252 seq_br_type 1 Branch True seq_branch_adr 0252 0x0252 0265 0265 seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 0266 0266 seq_br_type 7 Unconditional Call; Flow C 0x359c seq_branch_adr 359c 0x359c 0267 0267 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 0268 0x0268 seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 0268 0268 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x269 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 026a 0x026a typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR05:02 val_frame 5 0269 0269 ioc_tvbs 2 fiu+val; Flow J 0x25b seq_br_type 3 Unconditional Branch seq_branch_adr 025b 0x025b typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 026a 026a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 026b 026b seq_br_type 3 Unconditional Branch; Flow J 0x268 seq_branch_adr 0268 0x0268 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 026c ; -------------------------------------------------------------------------------------- 026c ; Comes from: 026c ; 0232 C True from color 0x0000 026c ; 0248 C True from color 0x0000 026c ; -------------------------------------------------------------------------------------- 026c 026c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x333f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 333f 0x333f seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 026d 026d fiu_load_var 1 hold_var; Flow R cc=True fiu_mem_start 6 start_rd_if_false fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 026e 0x026e typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 026e 026e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x274 seq_br_type 5 Call True seq_branch_adr 0274 0x0274 seq_cond_sel 67 REFRESH_MACRO_EVENT 026f 026f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0270 0270 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x277 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0277 0x0277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0271 0271 seq_br_type 2 Push (branch address); Flow J 0x272 seq_branch_adr 026d 0x026d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0272 0272 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x334a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 334a 0x334a typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 0273 0273 seq_br_type a Unconditional Return; Flow R 0274 ; -------------------------------------------------------------------------------------- 0274 ; Comes from: 0274 ; 026e C True from color MACRO_Action_Accept_Activation 0274 ; -------------------------------------------------------------------------------------- 0274 0274 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 0275 0275 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0276 0276 seq_br_type a Unconditional Return; Flow R 0277 0277 ioc_fiubs 1 val ; Flow J 0x221 seq_br_type 3 Unconditional Branch seq_branch_adr 0221 0x0221 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 0278 ; -------------------------------------------------------------------------------------- 0278 ; 0x00bb Action Signal_Completion,>R 0278 ; -------------------------------------------------------------------------------------- 0278 MACRO_Action_Signal_Completion,>R: 0278 0278 dispatch_brk_class 3 ; Flow C 0x337f dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0278 seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0279 0279 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2ab fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ab 0x02ab seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 027a 027a ioc_tvbs 1 typ+fiu; Flow J cc=True 0x291 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0291 0x0291 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 027b 027b fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2a1 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 02a1 0x02a1 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027c 027c fiu_mem_start 2 start-rd; Flow C 0x347d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 347d 0x347d seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027d 027d fiu_mem_start 11 start_tag_query; Flow C cc=True 0x3495 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 3495 0x3495 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 20 VR02:00 val_frame 2 027e 027e seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 027f 027f fiu_mem_start 2 start-rd; Flow J 0x280 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0280 0280 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0281 0281 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x39a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 39a7 0x39a7 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0282 0282 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x2af fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 02af 0x02af seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 0283 0283 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0284 0284 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02c0 0x02c0 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0285 0285 fiu_mem_start 2 start-rd; Flow J cc=True 0x29e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 029e 0x029e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 0286 0286 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0287 0287 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28f seq_br_type 1 Branch True seq_branch_adr 028f 0x028f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_rand 6 CHECK_CLASS_A_??_B 0288 0288 seq_br_type 7 Unconditional Call; Flow C 0x3a21 seq_branch_adr 3a21 0x3a21 0289 0289 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 028a 028a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 028b 028b fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x28c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0299 0x0299 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 028c 028c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x28d fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 028d 028d ioc_tvbs 1 typ+fiu; Flow C 0x3373 seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 028e 028e ioc_adrbs 2 typ ; Flow J 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 028f 028f ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0290 0290 seq_br_type 3 Unconditional Branch; Flow J 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0291 0291 ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0292 0292 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0293 0293 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0294 0294 ioc_load_wdr 0 ; Flow J cc=True 0x296 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0296 0x0296 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_frame 8 0295 0295 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A 0296 0296 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 0297 0297 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x371 seq_br_type 1 Branch True seq_branch_adr 0371 0x0371 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0298 0298 seq_br_type 3 Unconditional Branch; Flow J 0x371 seq_branch_adr 0371 0x0371 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0299 0299 fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 029a 029a fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 029b 029b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x289 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0289 0x0289 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 029c 029c seq_br_type 1 Branch True; Flow J cc=True 0x27f seq_branch_adr 027f 0x027f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 029d 029d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 029e 029e fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x29f fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 029f 029f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2a0 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02a0 02a0 ioc_tvbs 2 fiu+val; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02a1 02a1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 02a2 02a2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 7 val_rand a PASS_B_HIGH 02a3 02a3 ioc_load_wdr 0 ; Flow C cc=True 0x2e1 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 02e1 0x02e1 typ_alu_func 1a PASS_B typ_b_adr 2d TR02:0d typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 02a4 02a4 seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 02a5 02a5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a6 02a6 ioc_load_wdr 0 typ_b_adr 2e TR07:0e typ_frame 7 val_b_adr 39 VR02:19 val_frame 2 02a7 02a7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2c0 seq_br_type 1 Branch True seq_branch_adr 02c0 0x02c0 typ_c_adr 1b TR02:04 typ_frame 2 02a8 02a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a9 02a9 seq_br_type 2 Push (branch address); Flow J 0x2aa seq_branch_adr 02af 0x02af 02aa 02aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x39a2 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39a2 0x39a2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02ab 02ab seq_br_type 7 Unconditional Call; Flow C 0x2ad seq_branch_adr 02ad 0x02ad typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02ac 02ac seq_br_type 3 Unconditional Branch; Flow J 0x278 seq_branch_adr 0278 MACRO_Action_Signal_Completion,>R 02ad 02ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 02ae 02ae fiu_mem_start 3 start-wr; Flow J 0x3b4e fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 02af 02af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ad seq_br_type 5 Call True seq_branch_adr 02ad 0x02ad seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02b0 02b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 02b1 02b1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 02b2 02b2 ioc_load_wdr 0 ; Flow J 0x2b3 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 02b3 02b3 fiu_mem_start 2 start-rd; Flow J 0x3466 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3466 0x3466 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02b4 02b4 ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02b5 02b5 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 02b6 02b6 ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_b_adr 16 CSA/VAL_BUS 02b7 02b7 fiu_mem_start 2 start-rd; Flow C 0x336b seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b 02b8 02b8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2bd seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02bd 0x02bd seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02b9 02b9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 02ba 02ba fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 02b4 0x02b4 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 02bb 02bb fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2bc fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02bc 02bc ioc_tvbs 1 typ+fiu; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 02bd 02bd typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 02be 02be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a5 seq_br_type 1 Branch True seq_branch_adr 02a5 0x02a5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02bf 02bf seq_br_type 3 Unconditional Branch; Flow J 0x27f seq_branch_adr 027f 0x027f 02c0 02c0 fiu_mem_start 2 start-rd; Flow C 0x3347 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3347 0x3347 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02c1 02c1 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c2 02c2 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c3 02c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2ce fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ce 0x02ce seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 02c4 02c4 fiu_load_oreg 1 hold_oreg; Flow C 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335c 0x335c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 02c5 02c5 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c6 02c6 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c7 02c7 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c8 02c8 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c9 02c9 fiu_mem_start 2 start-rd; Flow J 0x3457 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3457 0x3457 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 02ca 02ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d1 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 02d1 0x02d1 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 02cb 02cb seq_br_type 2 Push (branch address); Flow J 0x2cc seq_branch_adr 02c3 0x02c3 02cc 02cc fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 02cd 02cd ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02ce 02ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 02cf 02cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a8 seq_br_type 1 Branch True seq_branch_adr 02a8 0x02a8 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02d0 02d0 seq_br_type 3 Unconditional Branch; Flow J 0x2af seq_branch_adr 02af 0x02af 02d1 02d1 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d2 02d2 ioc_fiubs 2 typ typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02d3 02d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d4 02d4 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 02d5 0x02d5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 02d5 02d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 02d6 02d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2df seq_br_type 1 Branch True seq_branch_adr 02df 0x02df seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 02d7 02d7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 02d8 02d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2da seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 02da 0x02da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 02d9 02d9 fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02da 02da fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 02db 02db fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dc 02dc ioc_fiubs 2 typ ; Flow J 0x2dd seq_br_type 2 Push (branch address) seq_branch_adr 02d6 0x02d6 typ_a_adr 02 GP02 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dd 02dd fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 23 VR02:03 val_frame 2 02de 02de ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02df 02df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 02e0 02e0 seq_br_type 3 Unconditional Branch; Flow J 0x2c3 seq_branch_adr 02c3 0x02c3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02e1 02e1 ioc_tvbs 2 fiu+val; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 02e2 0x02e2 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 02e2 02e2 fiu_mem_start 2 start-rd; Flow J 0x2e3 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0309 0x0309 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 2 val_rand a PASS_B_HIGH 02e3 02e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_random 06 Pop_stack+? val_c_adr 3c GP03 val_c_source 0 FIU_BUS 02e4 02e4 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e5 02e5 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x302 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0302 0x0302 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 02e6 02e6 seq_br_type 0 Branch False; Flow J cc=False 0x304 seq_branch_adr 0304 0x0304 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 02e7 02e7 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e8 02e8 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2eb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 02eb 0x02eb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 02e9 02e9 ioc_fiubs 0 fiu ; Flow J cc=False 0x300 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 13 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 02ea 02ea seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 02eb 02eb fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 02ec 02ec fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02ed 02ed <default> 02ee 02ee fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x300 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0300 0x0300 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 02ef 02ef ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2f6 seq_br_type 1 Branch True seq_branch_adr 02f6 0x02f6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02f0 02f0 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 02f1 02f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f5 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 02f5 0x02f5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f2 02f2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 25 VR05:05 val_frame 5 02f3 02f3 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 02f4 02f4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 02f5 02f5 fiu_load_var 1 hold_var; Flow J 0x2eb fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02eb 0x02eb val_a_adr 05 GP05 02f6 02f6 ioc_fiubs 0 fiu ; Flow J cc=True 0x2fb ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02fb 0x02fb seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 25 VR05:05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 02f7 02f7 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f8 02f8 ioc_load_wdr 0 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 02f9 02f9 fiu_mem_start 3 start-wr; Flow J 0x2fa ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 02fa 02fa ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x6b4 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 06b4 0x06b4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 03 GP03 02fb 02fb fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 02fc 02fc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 02fd 02fd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x2f7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02f7 0x02f7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 02fe 02fe fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe 02ff 02ff seq_br_type 3 Unconditional Branch; Flow J 0x2f7 seq_branch_adr 02f7 0x02f7 0300 0300 ioc_adrbs 1 val typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0301 0301 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2e6 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02e6 0x02e6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0302 0302 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0303 0303 fiu_mem_start 2 start-rd; Flow J 0x2e6 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02e6 0x02e6 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 0 PASS_A 0304 0304 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0305 0305 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0306 0306 seq_br_type 1 Branch True; Flow J cc=True 0x308 seq_branch_adr 0308 0x0308 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0307 0307 seq_br_type 3 Unconditional Branch; Flow J 0x304 seq_branch_adr 0304 0x0304 seq_en_micro 0 seq_random 06 Pop_stack+? 0308 0308 fiu_mem_start 2 start-rd; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0309 0x0309 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0309 0309 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 030a ; -------------------------------------------------------------------------------------- 030a ; 0x00b7 Action Make_Self 030a ; -------------------------------------------------------------------------------------- 030a MACRO_Action_Make_Self: 030a 030a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030b 030b seq_br_type 3 Unconditional Branch; Flow J 0x314 seq_branch_adr 0314 0x0314 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 030c ; -------------------------------------------------------------------------------------- 030c ; 0x00b6 Action Make_Scope 030c ; -------------------------------------------------------------------------------------- 030c MACRO_Action_Make_Scope: 030c 030c dispatch_brk_class 8 ; Flow J 0x312 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0312 0x0312 seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030d 030d <halt> ; Flow R 030e ; -------------------------------------------------------------------------------------- 030e ; 0x00b5 Action Make_Parent 030e ; -------------------------------------------------------------------------------------- 030e MACRO_Action_Make_Parent: 030e 030e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR04:0e val_frame 4 030f 030f ioc_tvbs 2 fiu+val typ_a_adr 38 TR1b:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b 0310 0310 fiu_mem_start 2 start-rd; Flow J cc=True 0x312 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0312 0x0312 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 0311 0311 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0312 0312 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME 0313 0313 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0314 0314 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x316 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0316 0x0316 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_latch 1 typ_a_adr 27 TR12:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0315 0315 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR12:08 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0316 0316 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR02:0a typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0317 0317 <halt> ; Flow R 0318 ; -------------------------------------------------------------------------------------- 0318 ; 0x00b4 Action Name_Partner 0318 ; -------------------------------------------------------------------------------------- 0318 MACRO_Action_Name_Partner: 0318 0318 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0318 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM 0319 0319 ioc_fiubs 0 fiu ; Flow J cc=False 0x320 seq_br_type 0 Branch False seq_branch_adr 0320 0x0320 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 031a 031a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_frame 7 031b 031b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031c 031c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 031d 031d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x321 seq_br_type 1 Branch True seq_branch_adr 0321 0x0321 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 031e 031e fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x31a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 031a 0x031a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031f 031f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0320 0320 fiu_mem_start 2 start-rd; Flow J 0x31d ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 031d 0x031d typ_a_adr 39 TR02:19 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0321 0321 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0322 ; -------------------------------------------------------------------------------------- 0322 ; 0x00b8 Action Set_Priority 0322 ; -------------------------------------------------------------------------------------- 0322 MACRO_Action_Set_Priority: 0322 0322 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0322 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR06:01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0323 0323 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x327 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0327 0x0327 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_frame 5 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 0324 0324 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0325 0325 seq_en_micro 0 0326 0326 fiu_len_fill_lit 42 zero-fill 0x2; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0327 0327 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_b_adr 01 GP01 0328 0328 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x326e fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_frame 5 0329 0329 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_b_adr 16 CSA/VAL_BUS 032a 032a ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 032b 032b seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 032c 032c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 032d 032d fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 032e 032e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 032f 032f ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0330 0330 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0331 0331 seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 0332 0332 ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0333 0333 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0334 0334 ioc_fiubs 1 val ; Flow J cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR06:01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 0335 0335 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0336 0336 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0337 0337 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0338 0338 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0339 0339 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1b A_OR_B val_b_adr 20 VR02:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 033a 033a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 033b 033b fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 033c 033c ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 033d 033d seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 033e 033e seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 033f 033f ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0340 0340 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0341 0341 <halt> ; Flow R 0342 ; -------------------------------------------------------------------------------------- 0342 ; 0x00b3 Action Increase_Priority 0342 ; -------------------------------------------------------------------------------------- 0342 MACRO_Action_Increase_Priority: 0342 0342 dispatch_brk_class 4 ; Flow C 0x326c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0342 seq_br_type 7 Unconditional Call seq_branch_adr 326c 0x326c 0343 0343 <halt> ; Flow R 0344 ; -------------------------------------------------------------------------------------- 0344 ; 0x00b9 Action Get_Priority 0344 ; -------------------------------------------------------------------------------------- 0344 MACRO_Action_Get_Priority: 0344 0344 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0344 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0345 0345 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0346 0346 fiu_load_tar 1 hold_tar; Flow J 0x347 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 32c5 0x32c5 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0347 0347 ioc_load_wdr 0 ; Flow J cc=True 0x526 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_frame 8 0348 0348 fiu_mem_start 3 start-wr; Flow J 0x32fe ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0349 0349 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 034a 034a fiu_load_tar 1 hold_tar; Flow J cc=True 0x32c5 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32c5 0x32c5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 034b 034b ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 2e VR04:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 034c 034c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 034d 034d ioc_fiubs 2 typ ; Flow J cc=True 0x526 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 3b TR02:1b typ_frame 2 val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 8 034e 034e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3a3e ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3a3e 0x3a3e seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 034f 034f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0350 0350 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0351 0351 ioc_tvbs 5 seq+seq; Flow J cc=False 0x366 seq_br_type 0 Branch False seq_branch_adr 0366 0x0366 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0352 0352 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x354 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0354 0x0354 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 0353 0353 seq_br_type 1 Branch True; Flow J cc=True 0x359 seq_branch_adr 0359 0x0359 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 val_c_adr 3d GP02 0354 0354 seq_b_timing 0 Early Condition; Flow J cc=True 0x367 seq_br_type 1 Branch True seq_branch_adr 0367 0x0367 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0355 0355 fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_rand a PASS_B_HIGH 0356 0356 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0357 0x0357 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0357 0357 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0358 0358 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x359 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0359 0x0359 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0359 0359 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x365 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0365 0x0365 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 23 TR01:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 typ_frame 1 val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 035a 035a fiu_load_tar 1 hold_tar; Flow C cc=True 0x35d fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 035d 0x035d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 035b 035b fiu_mem_start 3 start-wr; Flow J 0x35c ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 035c 035c ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 035d 035d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x363 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0363 0x0363 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 035e 035e seq_br_type 0 Branch False; Flow J cc=False 0x367 seq_branch_adr 0367 0x0367 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 035f 035f seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 seq_en_micro 0 0360 0360 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0361 0361 seq_b_timing 1 Latch Condition; Flow J cc=False 0x352 seq_br_type 0 Branch False seq_branch_adr 0352 0x0352 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0362 0362 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0363 0363 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 31 TR12:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0364 0364 ioc_load_wdr 0 ; Flow J 0x365 seq_br_type 3 Unconditional Branch seq_branch_adr 0365 0x0365 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 0365 0365 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0366 0366 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36b fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 036b 0x036b typ_a_adr 20 TR05:00 typ_b_adr 03 GP03 typ_frame 5 0367 0367 seq_br_type 2 Push (branch address); Flow J 0x368 seq_branch_adr 069b 0x069b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0368 0368 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 2e TR12:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 24 VR04:04 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0369 0369 fiu_mem_start 2 start-rd; Flow J 0x3713 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 036a 036a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 20 TR02:00 typ_frame 2 036b 036b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 036c 036c seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 036d 036d seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 036e 036e fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 11 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A 036f 036f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x372 seq_br_type 1 Branch True seq_branch_adr 0372 0x0372 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 31 TR12:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0370 0370 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0371 0371 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 2e TR02:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0372 0372 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x374 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0374 0x0374 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR06:01 val_frame 6 0373 0373 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3373 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0374 0374 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_frame 2 0375 0375 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3373 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0376 0376 ioc_tvbs 5 seq+seq; Flow J 0x56b seq_br_type 3 Unconditional Branch seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0377 0377 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR02:18 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0378 0378 fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0379 0379 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x37e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 037e 0x037e typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 037a 037a <default> 037b 037b fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 037c 037c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 037d 037d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 037e 037e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 037f 037f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x37e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 037e 0x037e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 0380 ; -------------------------------------------------------------------------------------- 0380 ; Comes from: 0380 ; 36fd C from color 0x0000 0380 ; 36ff C from color 0x0000 0380 ; 3701 C from color 0x36f7 0380 ; -------------------------------------------------------------------------------------- 0380 0380 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_frame 4 val_rand a PASS_B_HIGH 0381 0381 ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0382 0382 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 0383 0383 ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 0384 0384 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0385 0385 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0386 0386 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0387 0387 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x393 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0393 0x0393 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0388 0388 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 0389 0389 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 038a 038a fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x38e fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 038e 0x038e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 038b 038b seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 038c 038c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 038d 038d ioc_fiubs 0 fiu seq_en_micro 0 038e 038e fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x396 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0396 0x0396 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 038f 038f fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x395 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0395 0x0395 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0390 0390 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x38a seq_br_type 1 Branch True seq_branch_adr 038a 0x038a seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0391 0391 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0392 0392 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0393 0393 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0394 0394 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0395 0395 seq_br_type 3 Unconditional Branch; Flow J 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0396 ; -------------------------------------------------------------------------------------- 0396 ; Comes from: 0396 ; 038e C #0x0 from color 0x0000 0396 ; -------------------------------------------------------------------------------------- 0396 0396 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 0397 0397 fiu_load_tar 1 hold_tar; Flow J 0x39b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 039b 0x039b typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 0398 0398 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 0399 0399 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3a2 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 03a2 0x03a2 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 039a 039a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 039b 039b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 039c 039c fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 039d 0x039d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 039d 039d fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 039e 039e <default> 039f 039f fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a0 03a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03a1 03a1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03a2 03a2 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 03a3 0x03a3 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03a3 03a3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x3ab fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 03ab 0x03ab seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS 03a4 03a4 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x3aa fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 03aa 0x03aa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 03a5 03a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 06 Pop_stack+? typ_a_adr 02 GP02 typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 02 GP02 03a6 03a6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03a7 03a7 <default> 03a8 03a8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a9 03a9 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03aa 03aa fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR06:11 val_frame 6 03ab 03ab ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32b2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b2 0x32b2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e 03ac 03ac seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03ad ; -------------------------------------------------------------------------------------- 03ad ; Comes from: 03ad ; 372b C from color 0x0000 03ad ; 372d C from color 0x0000 03ad ; -------------------------------------------------------------------------------------- 03ad 03ad fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 03ae 03ae ioc_fiubs 1 val ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 03af 03af ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 03b0 03b0 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03b1 03b1 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03b2 03b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3be fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 03be 0x03be seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03b3 03b3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 03b4 03b4 seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03b5 03b5 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03b9 0x03b9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03b6 03b6 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 03b7 03b7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 03b8 03b8 ioc_fiubs 0 fiu seq_en_micro 0 03b9 03b9 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x3c0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 03c0 0x03c0 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 03ba 03ba fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x470 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0470 0x0470 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 03bb 03bb ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x3b5 seq_br_type 1 Branch True seq_branch_adr 03b5 0x03b5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03bc 03bc fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bd 03bd seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03be 03be fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bf 03bf seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03c0 ; -------------------------------------------------------------------------------------- 03c0 ; Comes from: 03c0 ; 03b9 C #0x0 from color 0x0000 03c0 ; -------------------------------------------------------------------------------------- 03c0 03c0 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 03c1 03c1 fiu_load_tar 1 hold_tar; Flow J 0x3c4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 03c4 0x03c4 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 03c2 03c2 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c3 03c3 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c4 03c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 03c5 03c5 fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 03c6 0x03c6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 03c6 03c6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03c7 03c7 <default> 03c8 03c8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03c9 03c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03ca 03ca fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03cb 03cb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3a GP05 03cc 03cc seq_b_timing 1 Latch Condition; Flow C cc=True 0x3cf seq_br_type 5 Call True seq_branch_adr 03cf 0x03cf typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03cd 03cd fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x3d1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 03d1 0x03d1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03ce 03ce ioc_fiubs 2 typ ; Flow J 0x3d8 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03cf 03cf ioc_fiubs 2 typ typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03d0 03d0 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 03d1 ; -------------------------------------------------------------------------------------- 03d1 ; Comes from: 03d1 ; 03cd C False from color 0x0000 03d1 ; -------------------------------------------------------------------------------------- 03d1 03d1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d2 03d2 ioc_load_wdr 0 typ_b_adr 03 GP03 03d3 03d3 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 03d4 03d4 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03d5 03d5 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d6 03d6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 03d7 0x03d7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 03d7 03d7 seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 03d8 03d8 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d9 03d9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 03da 03da fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 03db 03db fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x409 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0409 0x0409 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 03dc 03dc fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x408 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0408 0x0408 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03dd 03dd ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 03de 03de fiu_load_tar 1 hold_tar; Flow J cc=False 0x3e1 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03e1 0x03e1 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 03df 03df seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 03e0 03e0 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 03e1 03e1 ioc_tvbs 2 fiu+val; Flow J cc=True 0x40c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 040c 0x040c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03e2 03e2 fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 03e3 03e3 seq_b_timing 0 Early Condition; Flow J cc=False 0x3de seq_br_type 0 Branch False seq_branch_adr 03de 0x03de seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 03e4 03e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 02 GP02 03e5 03e5 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 03e6 03e6 seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 val_a_adr 2f VR02:0f val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03e7 03e7 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 03e8 03e8 fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03e9 03e9 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3ec seq_br_type 0 Branch False seq_branch_adr 03ec 0x03ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ea 03ea seq_br_type 7 Unconditional Call; Flow C 0x33bc seq_branch_adr 33bc 0x33bc 03eb 03eb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ec 03ec fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 03ed 03ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 03ee 03ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 03ef 03ef fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP seq_random 3e ? typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03f0 03f0 seq_br_type 7 Unconditional Call; Flow C 0x410 seq_branch_adr 0410 0x0410 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 03f1 03f1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_random 39 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 03f2 03f2 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3fe fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 0 Branch False seq_branch_adr 03fe 0x03fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 03f3 03f3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x400 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 03f4 03f4 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 03f5 03f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x40a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 040a 0x040a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03f6 03f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x3f8 seq_br_type f Unconditional Case Call seq_branch_adr 03f8 0x03f8 seq_en_micro 0 03f7 03f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 03f8 ; -------------------------------------------------------------------------------------- 03f8 ; Comes from: 03f8 ; 03f6 C #0x0 from color 0x03f0 03f8 ; -------------------------------------------------------------------------------------- 03f8 03f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03f9 03f9 seq_br_type 3 Unconditional Branch; Flow J 0x3fc seq_branch_adr 03fc 0x03fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 03fa 03fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a21 0x3a21 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fb 03fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3a21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3a21 0x3a21 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fc 03fc seq_br_type 1 Branch True; Flow J cc=True 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03fd 03fd seq_br_type 3 Unconditional Branch; Flow J 0x32ae seq_branch_adr 32ae 0x32ae 03fe 03fe fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3ff fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 03f4 0x03f4 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 03ff 03ff ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2f TR12:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 0400 0400 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0401 0401 ioc_load_wdr 0 ; Flow J 0x405 seq_br_type 3 Unconditional Branch seq_branch_adr 0405 0x0405 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0402 0402 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0403 0403 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x405 seq_br_type 0 Branch False seq_branch_adr 0405 0x0405 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0404 0404 fiu_load_tar 1 hold_tar; Flow R cc=False ; Flow J cc=True 0x3f5 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0405 0405 ioc_adrbs 3 seq ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0406 0406 ioc_fiubs 2 typ ; Flow J cc=True 0x402 seq_br_type 1 Branch True seq_branch_adr 0402 0x0402 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0407 0407 seq_br_type 3 Unconditional Branch; Flow J 0x402 seq_branch_adr 0402 0x0402 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 0408 0408 ioc_tvbs 2 fiu+val; Flow J 0x3e4 seq_br_type 3 Unconditional Branch seq_branch_adr 03e4 0x03e4 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0409 ; -------------------------------------------------------------------------------------- 0409 ; Comes from: 0409 ; 03db C True from color 0x0000 0409 ; -------------------------------------------------------------------------------------- 0409 0409 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 040a ; -------------------------------------------------------------------------------------- 040a ; Comes from: 040a ; 03f5 C True from color 0x03f0 040a ; -------------------------------------------------------------------------------------- 040a 040a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 040b 0x040b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 040b 040b seq_br_type a Unconditional Return; Flow R typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 040c 040c fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 1 INC_LOOP_COUNTER 040d 040d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 040e 040e fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x40d ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 040d 0x040d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 040f 040f seq_br_type 3 Unconditional Branch; Flow J 0x3e6 seq_branch_adr 03e6 0x03e6 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0410 ; -------------------------------------------------------------------------------------- 0410 ; Comes from: 0410 ; 03f0 C from color 0x03f0 0410 ; -------------------------------------------------------------------------------------- 0410 0410 ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0411 0411 seq_br_type a Unconditional Return; Flow R typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0412 0412 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_b_adr 08 GP08 0413 0413 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x414 fiu_mem_start 3 start-wr fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0417 0x0417 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR08:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0414 0414 ioc_load_wdr 0 ; Flow J cc=True 0x416 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0416 0x0416 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 0415 0415 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0416 0416 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0417 0417 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42c fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 042c 0x042c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 0418 0418 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0419 0419 seq_br_type 3 Unconditional Branch; Flow J 0x41b seq_branch_adr 041b 0x041b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 041a 041a seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 041b 041b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 13 LOOP_REG typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 13 LOOP_REG 041c 041c ioc_tvbs 2 fiu+val; Flow J cc=True 0x41a seq_br_type 1 Branch True seq_branch_adr 041a 0x041a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 041d 041d seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 05 GP05 val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 041e 041e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 041f 041f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0420 0420 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR12:18 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0421 0421 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 0422 0422 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 02 GP02 0423 0423 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 05 GP05 val_b_adr 08 GP08 0424 0424 fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 0425 0425 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 08 GP08 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0426 0426 seq_br_type 2 Push (branch address); Flow J 0x427 seq_branch_adr 042d 0x042d val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0427 0427 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6b4 seq_br_type 0 Branch False seq_branch_adr 06b4 0x06b4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0428 0428 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0429 0429 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 042a 042a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR11:0f typ_frame 11 042b 042b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a21 0x3a21 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 042c 042c ioc_tvbs 2 fiu+val; Flow J 0x41d seq_br_type 3 Unconditional Branch seq_branch_adr 041d 0x041d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 042d 042d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 042e 042e seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 042f 042f fiu_mem_start 2 start-rd; Flow C cc=False 0x49e ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 049e 0x049e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0430 0430 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x46a seq_br_type 1 Branch True seq_branch_adr 046a 0x046a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 08 GP08 0431 0431 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x432 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 044b 0x044b seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0432 0432 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 1e A_AND_B typ_b_adr 21 TR07:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0433 0433 fiu_tivi_src c mar_0xc; Flow J cc=True 0x436 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0436 0x0436 0434 0434 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame e val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0435 0435 fiu_mem_start 2 start-rd; Flow J 0x43c ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 043c 0x043c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 0436 0436 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 0437 0437 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0438 0438 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x49c fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 049c 0x049c seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0439 0439 fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 043a 043a fiu_mem_start 2 start-rd; Flow J cc=False 0x43c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 043c 0x043c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 043b 043b seq_br_type 3 Unconditional Branch; Flow J 0x49c seq_branch_adr 049c 0x049c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 043c 043c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x46e fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 046e 0x046e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 20 VR02:00 val_frame 2 043d 043d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 043e 043e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 043f 043f fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0440 0440 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22c7 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22c7 0x22c7 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0441 0441 ioc_fiubs 1 val ; Flow C 0x22c7 seq_br_type 7 Unconditional Call seq_branch_adr 22c7 0x22c7 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 0442 0442 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0443 0443 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 0444 0444 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 0445 0445 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 0446 0446 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0447 0447 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0448 0448 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0449 0449 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 044a 044a seq_br_type 3 Unconditional Branch; Flow J 0x450 seq_branch_adr 0450 0x0450 044b 044b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 044c 044c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 044d 044d fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 044e 044e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 044f 044f ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0450 0450 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x456 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0456 0x0456 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0451 0451 <default> 0452 0452 ioc_load_wdr 0 ; Flow J cc=True 0x4a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04a7 0x04a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 0453 0453 fiu_mem_start 3 start-wr; Flow C cc=True 0x460 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0460 0x0460 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP 0454 0454 <default> 0455 0455 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x451 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0451 0x0451 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0456 0456 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 0457 0457 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 02 GP02 typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN 0458 0458 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 0459 0459 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 02 GP02 val_a_adr 01 GP01 val_b_adr 02 GP02 045a 045a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR01:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 045b 045b ioc_load_wdr 0 ; Flow J 0x45c seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 05 GP05 045c 045c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 3e VR11:1e val_frame 11 045d 045d fiu_mem_start 3 start-wr; Flow J cc=True 0x461 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0461 0x0461 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 045e 045e ioc_load_wdr 0 ; Flow C 0x3373 seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 045f 045f fiu_mem_start 2 start-rd; Flow J 0x4a0 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0460 0460 seq_br_type 3 Unconditional Branch; Flow J 0x2a84 seq_branch_adr 2a84 0x2a84 0461 0461 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 0462 0462 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 2a TR02:0a typ_b_adr 20 TR02:00 typ_frame 2 0463 0463 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3373 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0464 0464 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR02:04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0465 0465 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A 0466 0466 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x469 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0469 0x0469 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 07 GP07 typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 0467 0467 ioc_fiubs 1 val ; Flow C 0x56b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b typ_a_adr 3e TR17:1e typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0468 0468 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 0469 ; -------------------------------------------------------------------------------------- 0469 ; Comes from: 0469 ; 0466 C True from color 0x0000 0469 ; -------------------------------------------------------------------------------------- 0469 0469 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 3e TR17:1e typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 046a 046a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_random 02 ? typ_a_adr 20 TR05:00 typ_csa_cntl 1 START_POP_DOWN typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 046b 046b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 046c 046c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 046d 046d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 046e 046e fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 046f 046f seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0470 0470 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0471 0471 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x472 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0483 0x0483 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0472 0472 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 0473 0473 fiu_mem_start 2 start-rd; Flow J cc=False 0x4a6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 0474 0474 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0475 0475 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0476 0476 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 0477 0477 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0478 0478 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22c7 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22c7 0x22c7 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0479 0479 ioc_fiubs 1 val ; Flow C 0x22c7 seq_br_type 7 Unconditional Call seq_branch_adr 22c7 0x22c7 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 047a 047a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 047b 047b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_b_adr 39 VR02:19 val_frame 2 047c 047c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 047d 047d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 047e 047e fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x4a6 fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 047f 047f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0480 0480 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0481 0481 ioc_fiubs 1 val ; Flow J cc=False 0x489 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0489 0x0489 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 0482 0482 seq_br_type 3 Unconditional Branch; Flow J 0x48d seq_branch_adr 048d 0x048d 0483 0483 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0484 0484 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 0485 0485 seq_en_micro 0 0486 0486 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 0487 0487 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 0488 0488 ioc_fiubs 0 fiu ; Flow J cc=True 0x48d ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 048d 0x048d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0489 0489 seq_br_type 3 Unconditional Branch; Flow J 0x48b seq_branch_adr 048b 0x048b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 048a 048a <default> 048b 048b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 13 LOOP_REG typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame f typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_b_adr 13 LOOP_REG 048c 048c seq_br_type 1 Branch True; Flow J cc=True 0x48a seq_branch_adr 048a 0x048a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 048d 048d fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 048e 048e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 02 GP02 val_a_adr 20 VR02:00 val_b_adr 02 GP02 val_frame 2 048f 048f fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 0490 0490 ioc_load_wdr 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0491 0491 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0492 0x0492 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0492 0492 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0493 0493 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0494 0494 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0495 0495 seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_frame e 0496 0496 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 0497 0497 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 7 0498 0498 seq_br_type 5 Call True; Flow C cc=True 0x32ae seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 09 GP09 0499 0499 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 049a 049a fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049b 049b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049c 049c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049d 049d seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049e 049e fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 049f 049f ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 04a0 04a0 <default> 04a1 04a1 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 04a2 04a2 fiu_mem_start 3 start-wr typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 04a3 04a3 ioc_load_wdr 0 04a4 04a4 fiu_tivi_src c mar_0xc; Flow C 0x3b75 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 04a5 04a5 seq_br_type a Unconditional Return; Flow R 04a6 04a6 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 04a7 04a7 seq_br_type 7 Unconditional Call; Flow C 0x49a seq_branch_adr 049a 0x049a 04a8 ; -------------------------------------------------------------------------------------- 04a8 ; 0x03c7 Complete_Type Access,By_Defining 04a8 ; -------------------------------------------------------------------------------------- 04a8 MACRO_Complete_Type_Access,By_Defining: 04a8 04a8 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04a8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04a9 04a9 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04aa 04aa fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 3d TR07:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 04ab 04ab fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x4ac fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32a9 0x32a9 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 2a TR09:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ac 04ac fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x3279 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ad 04ad fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a7 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 04ae 04ae fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x4af ; Flow J cc=#0x0 0x4af fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 04af 0x04af seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 04af 04af seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b0 04b0 fiu_load_tar 1 hold_tar; Flow J 0x4b3 fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04b3 0x04b3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b1 04b1 fiu_load_var 1 hold_var; Flow J 0x4cc fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04cc 0x04cc typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b2 04b2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b3 04b3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x4b4 ; Flow J cc=#0x0 0x4b8 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 04b8 0x04b8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04b4 04b4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04b5 04b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_random 02 ? typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04b6 04b6 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04b7 04b7 ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 04b8 04b8 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04b9 04b9 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04ba 04ba ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04bb 04bb seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 04bc 04bc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bd 04bd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04be 04be seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bf 04bf seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 04c0 04c0 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c1 04c1 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c2 04c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c3 04c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c4 04c4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c5 04c5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c6 04c6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c7 04c7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c8 04c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 0 PASS_A 04c9 04c9 fiu_fill_mode_src 0 ; Flow C 0x34fd fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 04ca 04ca ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cb 04cb ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04cc 04cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x4cf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 04cf 0x04cf seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 04cd 04cd fiu_fill_mode_src 0 ; Flow C 0x34fd fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04ce 04ce ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cf ; -------------------------------------------------------------------------------------- 04cf ; Comes from: 04cf ; 04cc C True from color 0x0000 04cf ; -------------------------------------------------------------------------------------- 04cf 04cf seq_br_type a Unconditional Return; Flow R typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 04d0 04d0 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x4d4 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 04d4 0x04d4 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04d1 04d1 fiu_mem_start a start_continue_if_false; Flow C cc=True 0x32a7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04d2 04d2 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 04d3 04d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 04d4 04d4 seq_br_type 3 Unconditional Branch; Flow J 0x4d0 seq_branch_adr 04d0 0x04d0 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 04d5 04d5 <halt> ; Flow R 04d6 ; -------------------------------------------------------------------------------------- 04d6 ; 0x03c6 Complete_Type Access,By_Renaming 04d6 ; -------------------------------------------------------------------------------------- 04d6 MACRO_Complete_Type_Access,By_Renaming: 04d6 04d6 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 04d6 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04d7 04d7 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04d8 04d8 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04d9 04d9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04da 04da fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 04db 04db fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04dc 04dc fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04dd 04dd fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04de 04de fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04df 04df fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 04e0 04e0 fiu_mem_start 3 start-wr; Flow C cc=True 0x32a9 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 04e1 04e1 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04e2 04e2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04e3 04e3 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 04e4 ; -------------------------------------------------------------------------------------- 04e4 ; 0x03c5 Complete_Type Access,By_Constraining 04e4 ; -------------------------------------------------------------------------------------- 04e4 MACRO_Complete_Type_Access,By_Constraining: 04e4 04e4 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04e4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04e5 04e5 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e6 04e6 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04e7 04e7 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04e8 04e8 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e9 04e9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04ea 04ea fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04eb 04eb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04ec 04ec fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04ed 04ed fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 04ee 04ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 val_c_adr 3e GP01 04ef 04ef fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 04f0 04f0 ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x4f5 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 04f5 0x04f5 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 04f1 04f1 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 04f2 04f2 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04f3 04f3 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 04f4 04f4 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 04f5 ; -------------------------------------------------------------------------------------- 04f5 ; Comes from: 04f5 ; 04f0 C #0x0 from color 0x0000 04f5 ; -------------------------------------------------------------------------------------- 04f5 04f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f6 04f6 fiu_mem_start 2 start-rd; Flow J 0x4fd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 04fd 0x04fd typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 04f7 04f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f8 04f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f9 04f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04fa 04fa seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fb 04fb seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fc 04fc fiu_mem_start 2 start-rd; Flow J 0x509 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0509 0x0509 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 04fd 04fd <default> 04fe 04fe fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 04ff 04ff ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0500 0500 fiu_mem_start 2 start-rd; Flow J 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3244 0x3244 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0501 0501 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 0502 0502 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0503 0x0503 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 01 GP01 0503 0503 fiu_mem_start 2 start-rd; Flow C 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3244 0x3244 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0504 0504 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 0505 0505 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 0506 0506 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0507 0507 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0508 0x0508 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 0508 0508 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 0509 0509 <default> 050a 050a fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x501 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0501 0x0501 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 050b 050b fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 050c 050c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ab seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 050d 050d seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 050e ; -------------------------------------------------------------------------------------- 050e ; 0x03c4 Complete_Type Access,By_Component_Completion 050e ; -------------------------------------------------------------------------------------- 050e MACRO_Complete_Type_Access,By_Component_Completion: 050e 050e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 050e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 050f 050f fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0510 0510 fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0511 0511 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x4d3 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04d3 0x04d3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0512 0512 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 39 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0513 0513 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3279 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0514 0514 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x516 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0516 0x0516 seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0515 0515 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0516 ; -------------------------------------------------------------------------------------- 0516 ; Comes from: 0516 ; 0514 C #0x0 from color 0x0000 0516 ; -------------------------------------------------------------------------------------- 0516 0516 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0517 0517 ioc_tvbs 1 typ+fiu; Flow J 0x51a seq_br_type 3 Unconditional Branch seq_branch_adr 051a 0x051a val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0518 0518 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0519 0519 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 051a 051a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x51f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 051f 0x051f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 02 GP02 typ_b_adr 10 TOP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 051b 051b fiu_fill_mode_src 0 ; Flow C 0x34fd fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 051c 051c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x526 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_a_adr 02 GP02 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA 051d 051d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 051e 051e ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle val_b_adr 02 GP02 051f 051f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0520 0520 fiu_mem_start 3 start-wr; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0521 0521 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 0522 ; -------------------------------------------------------------------------------------- 0522 ; 0x0000 Action Illegal,>R 0522 ; -------------------------------------------------------------------------------------- 0522 MACRO_Action_Illegal,>R: 0522 0522 dispatch_brk_class 0 ; Flow C cc=True 0x68d dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0522 seq_br_type 5 Call True seq_branch_adr 068d 0x068d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0523 0523 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32ad seq_br_type 1 Branch True seq_branch_adr 32ad 0x32ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0524 0524 seq_br_type 3 Unconditional Branch; Flow J 0x526 seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0525 0525 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_csa_cntl 2 PUSH_CSA 0526 ; -------------------------------------------------------------------------------------- 0526 ; 0x0008 Action Idle 0526 ; -------------------------------------------------------------------------------------- 0526 MACRO_Action_Idle: 0526 0526 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0526 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0527 0527 <halt> ; Flow R 0528 ; -------------------------------------------------------------------------------------- 0528 ; 0x00c4 Action Make_Default 0528 ; -------------------------------------------------------------------------------------- 0528 MACRO_Action_Make_Default: 0528 0528 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0528 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 37 TR07:17 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0529 ; -------------------------------------------------------------------------------------- 0529 ; Comes from: 0529 ; 052d C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 052f C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0531 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0533 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0535 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0537 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 053a C from color MACRO_Pop_Control_Pop_Count_7 0529 ; -------------------------------------------------------------------------------------- 0529 0529 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 052a 0x052a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 052a 052a seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 052b 0x052b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 10 052b 052b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x525 seq_br_type 9 Return False seq_branch_adr 0525 0x0525 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 18 052c ; -------------------------------------------------------------------------------------- 052c ; 0x00d7 Pop_Control Pop_Count_7 052c ; -------------------------------------------------------------------------------------- 052c MACRO_Pop_Control_Pop_Count_7: 052c 052c dispatch_brk_class 3 ; Flow J cc=False 0x52e dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 052c seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 052e MACRO_Pop_Control_Pop_Count_6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052d 052d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 052e ; -------------------------------------------------------------------------------------- 052e ; 0x00d6 Pop_Control Pop_Count_6 052e ; -------------------------------------------------------------------------------------- 052e MACRO_Pop_Control_Pop_Count_6: 052e 052e dispatch_brk_class 3 ; Flow J cc=False 0x530 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 052e seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0530 MACRO_Pop_Control_Pop_Count_5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052f 052f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0530 ; -------------------------------------------------------------------------------------- 0530 ; 0x00d5 Pop_Control Pop_Count_5 0530 ; -------------------------------------------------------------------------------------- 0530 MACRO_Pop_Control_Pop_Count_5: 0530 0530 dispatch_brk_class 3 ; Flow J cc=False 0x532 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 0530 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0532 MACRO_Pop_Control_Pop_Count_4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0531 0531 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0532 ; -------------------------------------------------------------------------------------- 0532 ; 0x00d4 Pop_Control Pop_Count_4 0532 ; -------------------------------------------------------------------------------------- 0532 MACRO_Pop_Control_Pop_Count_4: 0532 0532 dispatch_brk_class 3 ; Flow J cc=False 0x534 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 0532 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0534 MACRO_Pop_Control_Pop_Count_3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0533 0533 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0534 ; -------------------------------------------------------------------------------------- 0534 ; 0x00d3 Pop_Control Pop_Count_3 0534 ; -------------------------------------------------------------------------------------- 0534 MACRO_Pop_Control_Pop_Count_3: 0534 0534 dispatch_brk_class 3 ; Flow J cc=False 0x536 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0534 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0536 MACRO_Pop_Control_Pop_Count_2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0535 0535 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0536 ; -------------------------------------------------------------------------------------- 0536 ; 0x00d2 Pop_Control Pop_Count_2 0536 ; -------------------------------------------------------------------------------------- 0536 MACRO_Pop_Control_Pop_Count_2: 0536 0536 dispatch_brk_class 3 ; Flow J cc=False 0x538 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0536 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0538 MACRO_Pop_Control_Pop_Count_1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0537 0537 seq_br_type 5 Call True; Flow C cc=True 0x529 seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0538 ; -------------------------------------------------------------------------------------- 0538 ; 0x00d1 Pop_Control Pop_Count_1 0538 ; -------------------------------------------------------------------------------------- 0538 MACRO_Pop_Control_Pop_Count_1: 0538 0538 dispatch_brk_class 3 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0538 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0539 0x0539 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0539 0539 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053a 0x053a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 11 TOP + 1 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 053a 053a seq_br_type 7 Unconditional Call; Flow C 0x529 seq_branch_adr 0529 0x0529 053b 053b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 053c ; -------------------------------------------------------------------------------------- 053c ; 0x00d0 Action Swap_Control 053c ; -------------------------------------------------------------------------------------- 053c MACRO_Action_Swap_Control: 053c 053c dispatch_brk_class 3 ; Flow J cc=True 0x53f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 053c ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 053f 0x053f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 053d 053d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053e 0x053e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 053e 053e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 053f 053f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_c_adr 2f TOP val_c_adr 2f TOP 0540 ; -------------------------------------------------------------------------------------- 0540 ; 0x00cd Action Spare6_Action 0540 ; -------------------------------------------------------------------------------------- 0540 MACRO_Action_Spare6_Action: 0540 0540 dispatch_brk_class 3 ; Flow J cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0540 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 val_b_adr 10 TOP 0541 0541 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0542 0x0542 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0542 0542 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0543 0543 <halt> ; Flow R 0544 ; -------------------------------------------------------------------------------------- 0544 ; 0x00cf Action Mark_Auxiliary 0544 ; -------------------------------------------------------------------------------------- 0544 MACRO_Action_Mark_Auxiliary: 0544 0544 dispatch_brk_class 3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0544 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR02:16 val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0545 0545 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_alu_func 1b A_OR_B typ_b_adr 21 TR02:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0546 0546 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x54c fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 054c 0x054c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0547 0547 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 19 X_XOR_B typ_b_adr 31 TR11:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0548 0548 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0549 0x0549 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_frame 2 0549 0549 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 22 TR02:02 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 054a 054a fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 054b 054b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 054c 054c seq_br_type 3 Unconditional Branch; Flow J 0x548 seq_branch_adr 0548 0x0548 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR07:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 054d 054d <halt> ; Flow R 054e ; -------------------------------------------------------------------------------------- 054e ; 0x00ce Action Pop_Auxiliary 054e ; -------------------------------------------------------------------------------------- 054e MACRO_Action_Pop_Auxiliary: 054e 054e dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 054e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 054f 054f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 2 0550 0550 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x555 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0555 0x0555 typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0551 0551 ioc_load_wdr 0 ; Flow J cc=True 0x552 ; Flow J cc=#0x0 0x552 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0552 0x0552 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0552 0552 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0553 0553 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0554 0554 ioc_load_wdr 0 ; Flow J 0x552 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0552 0x0552 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 0555 0555 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0556 0x0556 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0556 0556 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0557 0557 <halt> ; Flow R 0558 ; -------------------------------------------------------------------------------------- 0558 ; 0x00c9 Action Pop_Auxiliary_Loop 0558 ; -------------------------------------------------------------------------------------- 0558 MACRO_Action_Pop_Auxiliary_Loop: 0558 0558 dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0558 fiu_len_fill_lit 64 zero-fill 0x24 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 10 TOP typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 0559 0559 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055a ; -------------------------------------------------------------------------------------- 055a ; 0x00c8 Action Pop_Auxiliary_Range 055a ; -------------------------------------------------------------------------------------- 055a MACRO_Action_Pop_Auxiliary_Range: 055a 055a dispatch_brk_class 3 ; Flow C cc=False 0x32a7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 055a fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 34 VR06:14 val_frame 6 055b 055b fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 055c 0x055c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 1f TOP - 1 typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055c 055c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU 055d 055d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 055e ; -------------------------------------------------------------------------------------- 055e ; 0x00ba Action Initiate_Delay 055e ; -------------------------------------------------------------------------------------- 055e MACRO_Action_Initiate_Delay: 055e 055e dispatch_brk_class 3 ; Flow J cc=False 0x563 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 055e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type 0 Branch False seq_branch_adr 0563 0x0563 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 1d ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 055f 055f seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f seq_random 05 ? 0560 0560 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0561 0561 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x562 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 28 VR05:08 val_frame 5 0562 0562 ioc_tvbs 2 fiu+val; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0563 0563 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0564 ; -------------------------------------------------------------------------------------- 0564 ; Comes from: 0564 ; 0591 C from color 0x058d 0564 ; 05c2 C from color 0x05a7 0564 ; 05e7 C True from color 0x05db 0564 ; -------------------------------------------------------------------------------------- 0564 0564 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0565 0565 seq_en_micro 0 0566 0566 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0567 0567 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x3653 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3653 0x3653 seq_en_micro 0 val_c_adr 00 VR17:1f val_c_source 0 FIU_BUS val_frame 17 0568 0568 fiu_load_var 1 hold_var; Flow C cc=True 0x2a84 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 0569 0569 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 056a 0x056a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056a 056a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056b 056b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x599 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0599 0x0599 seq_en_micro 0 typ_c_adr 18 TR17:07 typ_c_source 0 FIU_BUS typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR17:07 val_c_mux_sel 2 ALU val_frame 17 056c 056c fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 056d 056d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 056e 056e fiu_len_fill_lit 71 zero-fill 0x31 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 07 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 23 VR17:03 val_frame 17 056f 056f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 07 fiu_rdata_src 0 rotator seq_en_micro 0 0570 0570 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x62e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0571 0571 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 0572 0572 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0573 0573 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR17:02 typ_frame 17 val_b_adr 22 VR17:02 val_frame 17 0574 0574 seq_br_type 0 Branch False; Flow J cc=False 0x58c seq_branch_adr 058c 0x058c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 0575 0575 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0576 0576 seq_en_micro 0 0577 0577 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0578 0578 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x58c seq_br_type 0 Branch False seq_branch_adr 058c 0x058c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0579 0579 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 057a 057a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 057b 057b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 057c 057c fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x581 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 057d 057d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x596 seq_br_type 1 Branch True seq_branch_adr 0596 0x0596 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 057e 057e fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 057f 057f fiu_mem_start 2 start-rd; Flow J cc=False 0x581 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0580 0580 fiu_load_tar 1 hold_tar; Flow J 0x57b fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 057b 0x057b seq_en_micro 0 typ_b_adr 24 TR17:04 typ_frame 17 0581 0581 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0582 0582 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_frame 17 0583 0583 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0584 0584 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0585 0585 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0586 0586 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_frame 17 0587 0587 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0588 0588 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0589 0589 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 058a 058a fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 058b ; -------------------------------------------------------------------------------------- 058b ; Comes from: 058b ; 368f C from color 0x0200 058b ; -------------------------------------------------------------------------------------- 058b 058b seq_br_type 1 Branch True; Flow J cc=True 0x575 seq_branch_adr 0575 0x0575 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 058c 058c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 058d 058d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 058e 058e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 058f 058f ioc_fiubs 2 typ ; Flow C cc=True 0x2a84 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR17:01 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 0590 0590 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 0591 0591 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 0592 0592 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 0593 0593 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 0594 ; -------------------------------------------------------------------------------------- 0594 ; Comes from: 0594 ; 0589 C False from color 0x0588 0594 ; 0590 C False from color 0x058d 0594 ; -------------------------------------------------------------------------------------- 0594 0594 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 0595 0595 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0596 0596 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0597 0597 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 0 PASS_A typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 0598 0598 seq_br_type 3 Unconditional Branch; Flow J 0x57e seq_branch_adr 057e 0x057e seq_en_micro 0 0599 ; -------------------------------------------------------------------------------------- 0599 ; Comes from: 0599 ; 056b C from color 0x0000 0599 ; -------------------------------------------------------------------------------------- 0599 0599 ioc_fiubs 1 val ; Flow C cc=True 0x5a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 05a4 0x05a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 21 VR17:01 val_alu_func 1e A_AND_B val_b_adr 3a VR17:1a val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 059a 059a seq_en_micro 0 val_a_adr 23 VR17:03 val_b_adr 39 VR17:19 val_frame 17 val_rand c START_MULTIPLY 059b 059b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 1 ALU >> 16 val_frame 17 val_m_b_src 2 Bits 32…47 059c 059c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 059d 059d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 059e 059e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 059f 059f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 05a0 05a0 seq_br_type 7 Unconditional Call; Flow C 0x3653 seq_branch_adr 3653 0x3653 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_rand e PRODUCT_LEFT_32 05a1 05a1 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 05a2 05a2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a3 05a3 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x5a6 seq_branch_adr 05a6 0x05a6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1d A_AND_NOT_B val_b_adr 3c VR17:1c val_frame 17 05a4 05a4 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 05a5 0x05a5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 21 VR17:01 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 05a5 05a5 seq_en_micro 0 seq_random 06 Pop_stack+? 05a6 05a6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3c VR17:1c val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a7 ; -------------------------------------------------------------------------------------- 05a7 ; Comes from: 05a7 ; 02f0 C from color 0x0000 05a7 ; 035f C from color 0x0000 05a7 ; 3703 C from color 0x36f7 05a7 ; 372e C from color 0x0000 05a7 ; 38b8 C from color 0x38b7 05a7 ; 3aa3 C from color 0x0000 05a7 ; 3acd C from color 0x0000 05a7 ; 3ad1 C from color 0x0000 05a7 ; -------------------------------------------------------------------------------------- 05a7 05a7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 05a8 05a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 05a9 05a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 05aa 05aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x5bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 05bb 0x05bb seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 05ab 05ab fiu_mem_start 3 start-wr; Flow C 0x3b52 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b52 0x3b52 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 05ac 05ac seq_br_type 2 Push (branch address); Flow J 0x5ad seq_branch_adr 05b8 0x05b8 seq_en_micro 0 05ad 05ad seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 05ae 05ae seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 27 VR04:07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 05af 05af ioc_fiubs 2 typ ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 05b0 05b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 05b1 05b1 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b2 05b2 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 39 TR09:19 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b3 05b3 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 05b4 05b4 ioc_adrbs 2 typ ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 05b5 05b5 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 05b6 05b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 05b7 05b7 fiu_mem_start 2 start-rd; Flow J 0x3713 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 05b8 05b8 ioc_adrbs 1 val ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05b9 05b9 fiu_mem_start 2 start-rd; Flow J cc=False 0x5da ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05ba 05ba ioc_fiubs 1 val ; Flow J 0x5a9 seq_br_type 3 Unconditional Branch seq_branch_adr 05a9 0x05a9 seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 val_a_adr 06 GP06 05bb 05bb seq_br_type 0 Branch False; Flow J cc=False 0x5da seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05bc 05bc fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05bd 05bd seq_en_micro 0 05be 05be fiu_tivi_src 3 tar_frame; Flow C cc=False 0x62e ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05bf 05bf fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05c0 05c0 seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 20 TR17:00 typ_b_adr 23 TR17:03 typ_frame 17 05c1 05c1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x5c5 seq_br_type 0 Branch False seq_branch_adr 05c5 0x05c5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c2 05c2 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 05c3 05c3 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 05c4 05c4 seq_br_type 3 Unconditional Branch; Flow J 0x5d2 seq_branch_adr 05d2 0x05d2 seq_en_micro 0 05c5 05c5 seq_br_type 1 Branch True; Flow J cc=True 0x5d2 seq_branch_adr 05d2 0x05d2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05c6 05c6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 05c7 05c7 fiu_mem_start 11 start_tag_query; Flow J 0x5bd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 05bd 0x05bd seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 23 VR04:03 val_frame 4 05c8 05c8 ioc_load_wdr 0 ; Flow C cc=True 0x2a84 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 36 TR17:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c9 05c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x5da fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 24 TR17:04 typ_frame 17 val_a_adr 26 VR17:06 val_frame 17 05ca 05ca fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05cb 05cb fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05cc 05cc seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 24 TR17:04 typ_frame 17 05cd 05cd fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 1a TR17:05 typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1a VR17:05 val_frame 17 05ce 05ce fiu_mem_start e start_physical_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED 05cf 05cf ioc_load_wdr 0 ; Flow J 0x5d2 seq_br_type 3 Unconditional Branch seq_branch_adr 05d2 0x05d2 seq_en_micro 0 typ_b_adr 25 TR17:05 typ_frame 17 val_b_adr 25 VR17:05 val_frame 17 05d0 ; -------------------------------------------------------------------------------------- 05d0 ; Comes from: 05d0 ; 05ca C from color 0x05a7 05d0 ; 05d2 C from color 0x05a7 05d0 ; -------------------------------------------------------------------------------------- 05d0 05d0 seq_en_micro 0 05d1 05d1 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d2 05d2 fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05d3 05d3 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 3e VR17:1e val_frame 17 05d4 05d4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 23 TR17:03 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 37 VR17:17 val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d5 05d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 05d6 05d6 fiu_len_fill_lit 71 zero-fill 0x31 fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_source 0 FIU_BUS val_frame 17 05d7 05d7 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 21 TR17:01 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05d8 05d8 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 05d9 05d9 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 05da 05da fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? typ_b_adr 04 GP04 val_b_adr 04 GP04 05db ; -------------------------------------------------------------------------------------- 05db ; Comes from: 05db ; 0108 C from color ME_GP_TIME 05db ; -------------------------------------------------------------------------------------- 05db 05db seq_br_type 0 Branch False; Flow J cc=False 0x5e4 seq_branch_adr 05e4 0x05e4 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05dc 05dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5e5 seq_br_type 1 Branch True seq_branch_adr 05e5 0x05e5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 0 PASS_A val_frame 17 05dd ; -------------------------------------------------------------------------------------- 05dd ; Comes from: 05dd ; 0592 C from color 0x058d 05dd ; 05c3 C from color 0x05a7 05dd ; -------------------------------------------------------------------------------------- 05dd 05dd seq_br_type 1 Branch True; Flow J cc=True 0x5df seq_branch_adr 05df 0x05df seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR17:1b val_frame 17 05de 05de fiu_load_var 1 hold_var; Flow J 0x5e0 fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 05e0 0x05e0 seq_en_micro 0 val_b_adr 3f VR17:1f val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05df 05df fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 3b VR17:1b val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05e0 05e0 ioc_random e enable delay timer; Flow J cc=True 0x5e2 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 05e2 0x05e2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 05e1 05e1 fiu_load_var 1 hold_var; Flow J 0x364d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 364d 0x364d seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e2 05e2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05e3 05e3 fiu_load_var 1 hold_var; Flow J 0x364d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 364d 0x364d seq_en_micro 0 val_b_adr 23 VR17:03 val_frame 17 05e4 05e4 fiu_load_var 1 hold_var; Flow J 0x364d fiu_tivi_src 1 tar_val ioc_random f disable delay timer seq_br_type 3 Unconditional Branch seq_branch_adr 364d 0x364d seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e5 05e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_c_adr 1c TR17:03 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e6 05e6 seq_en_micro 0 05e7 05e7 ioc_fiubs 2 typ ; Flow C cc=True 0x564 ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 0564 0x0564 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 05e8 05e8 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e9 05e9 seq_en_micro 0 05ea 05ea ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 05eb 05eb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ec 05ec fiu_len_fill_lit 60 zero-fill 0x20 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ed 05ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 05ee 05ee fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 37 TR17:17 typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05ef 05ef seq_en_micro 0 05f0 05f0 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x62e ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f1 05f1 ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 05f2 05f2 seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05f3 05f3 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05f4 05f4 seq_b_timing 1 Latch Condition; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05f5 05f5 seq_br_type 3 Unconditional Branch; Flow J 0x5ee seq_branch_adr 05ee 0x05ee seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 05f6 05f6 fiu_mem_start 2 start-rd; Flow J 0x5f7 ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 05ff 0x05ff seq_en_micro 0 seq_random 02 ? typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 37 TR17:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05f7 05f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 05f8 05f8 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f9 05f9 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 05fa 05fa ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 03 GP03 typ_frame 1 val_b_adr 03 GP03 05fb 05fb fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05fc 05fc ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 0f GP0f 05fd 05fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x69b seq_br_type 4 Call False seq_branch_adr 069b 0x069b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05fe 05fe seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05ff 05ff fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0600 0600 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0601 0601 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x62e fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0602 0602 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0603 0603 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0604 0604 fiu_mem_start 3 start-wr; Flow J cc=True 0x623 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0623 0x0623 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0605 0605 ioc_fiubs 2 typ ; Flow C 0x210 ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0606 0606 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x621 seq_br_type 1 Branch True seq_branch_adr 0621 0x0621 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 35 VR02:15 val_frame 2 0607 0607 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0608 0608 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 0609 0609 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 060a 060a fiu_mem_start 2 start-rd; Flow J 0x60b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 060b 0x060b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 060b 060b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 060c 060c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x611 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0611 0x0611 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 060d 060d fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x613 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0613 0x0613 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 060e 060e ioc_tvbs 2 fiu+val; Flow J cc=True 0x617 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0617 0x0617 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 060f 060f fiu_mem_start 3 start-wr; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0610 0610 ioc_load_wdr 0 ; Flow J 0x61b seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 0611 0611 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0612 0612 ioc_load_wdr 0 ; Flow J 0x61b ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0613 0613 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0614 0614 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 0615 0615 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0616 0616 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0617 0617 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0618 0618 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 0619 0619 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 061a 061a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 061b 061b fiu_mem_start 2 start-rd; Flow C 0x2abf ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2abf 0x2abf seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 061c 061c fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 061d 061d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x627 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0627 0x0627 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 061e 061e fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 061f 061f ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0620 0620 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0621 0621 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x622 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 0622 0622 ioc_tvbs 2 fiu+val; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0623 0623 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 0624 0624 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0625 0625 fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0626 0626 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x603 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0603 0x0603 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0627 ; -------------------------------------------------------------------------------------- 0627 ; Comes from: 0627 ; 061d C True from color 0x0000 0627 ; -------------------------------------------------------------------------------------- 0627 0627 ioc_adrbs 1 val ; Flow C 0x3b75 seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0628 0628 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0629 0629 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 062a ; -------------------------------------------------------------------------------------- 062a ; Comes from: 062a ; 05f1 C from color 0x05ec 062a ; 05fc C from color 0x05fb 062a ; -------------------------------------------------------------------------------------- 062a 062a fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 062b 062b seq_en_micro 0 062c 062c seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062d 062d seq_br_type 3 Unconditional Branch; Flow J 0x6bd seq_branch_adr 06bd 0x06bd seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 062e ; -------------------------------------------------------------------------------------- 062e ; Comes from: 062e ; 0570 C False from color 0x0000 062e ; 05be C False from color 0x05a7 062e ; 05f0 C False from color 0x05ec 062e ; 0601 C False from color 0x05fb 062e ; -------------------------------------------------------------------------------------- 062e 062e seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062f 062f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x632 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 0632 0x0632 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0630 0630 ioc_fiubs 0 fiu typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0631 0631 seq_br_type 3 Unconditional Branch; Flow J 0x632 seq_branch_adr 0632 0x0632 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0632 0632 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 0633 0633 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x634 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0637 0x0637 seq_int_reads 6 CONTROL TOP 0634 0634 fiu_mem_start 2 start-rd; Flow C 0x3342 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3342 0x3342 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0635 0635 fiu_load_var 1 hold_var; Flow J cc=True 0x636 ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0636 0636 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0652 0x0652 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? 0637 0637 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 0638 0638 seq_br_type 2 Push (branch address); Flow J 0x639 seq_branch_adr 0637 0x0637 0639 0639 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0652 0x0652 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 063a 063a fiu_load_oreg 1 hold_oreg; Flow C 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335c 0x335c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 063b 063b fiu_load_var 1 hold_var; Flow J cc=True 0x63c ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063c 063c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063d 063d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063e 063e ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 063f 063f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x640 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0640 0x0640 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0640 0640 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0641 0641 ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0642 0642 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0643 0643 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0644 0x0644 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR08:0c typ_frame 8 val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0644 0644 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 42 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 0645 0645 ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0646 0646 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 0647 0647 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 0648 0648 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA 0649 0649 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x64b fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 064b 0x064b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064a 064a fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064b 064b fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 064c 064c fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064d 064d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x64e fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0646 0x0646 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064e 064e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 064f 064f ioc_fiubs 0 fiu ; Flow C 0x3a42 seq_br_type 7 Unconditional Call seq_branch_adr 3a42 0x3a42 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0650 0650 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 0651 0651 ioc_fiubs 0 fiu ; Flow J 0x3a42 seq_br_type 3 Unconditional Branch seq_branch_adr 3a42 0x3a42 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0652 0652 ioc_tvbs 1 typ+fiu val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0653 0653 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 0654 0654 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x656 seq_br_type 1 Branch True seq_branch_adr 0656 0x0656 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_frame 2 0655 0655 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x632 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0632 0x0632 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0656 0656 ioc_fiubs 2 typ ; Flow J cc=False 0x661 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 24 TR02:04 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0657 0657 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x3add seq_br_type 4 Call False seq_branch_adr 3add 0x3add seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 24 TR02:04 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A 0658 0658 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x65c fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 065c 0x065c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 25 VR05:05 val_frame 5 0659 0659 ioc_tvbs 2 fiu+val; Flow J 0x65a seq_br_type 2 Push (branch address) seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065a 065a fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3373 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 065b 065b seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 065c 065c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 065d 065d ioc_tvbs 1 typ+fiu; Flow J cc=False 0x661 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 065e 065e seq_br_type 2 Push (branch address); Flow J 0x65f seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065f 065f fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3373 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0660 0660 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0661 0661 seq_br_type 7 Unconditional Call; Flow C 0x32b3 seq_branch_adr 32b3 0x32b3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0662 0662 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0663 0663 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0664 0664 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 29 TR09:09 typ_frame 9 val_b_adr 39 VR02:19 val_frame 2 0665 0665 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 0666 0666 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0667 0667 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0668 0668 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_b_adr 0f GP0f 0669 0669 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 066a 066a fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x68a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 066b 066b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 066c 066c fiu_load_tar 1 hold_tar; Flow J cc=False 0x68a fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 066d 066d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x68a fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 066e 066e seq_br_type 0 Branch False; Flow J cc=False 0x68a seq_branch_adr 068a 0x068a seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 066f 066f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x674 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0674 0x0674 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 0670 0670 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x676 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0676 0x0676 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0671 0671 ioc_tvbs 2 fiu+val; Flow J cc=True 0x67a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 067a 0x067a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 0672 0672 fiu_mem_start 3 start-wr; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0673 0673 ioc_load_wdr 0 ; Flow J 0x67e seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e seq_random 02 ? 0674 0674 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val val_b_adr 39 VR02:19 val_frame 2 0675 0675 ioc_load_wdr 0 ; Flow J 0x67e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e val_b_adr 39 VR02:19 val_frame 2 0676 0676 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 0677 0677 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val 0678 0678 ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0679 0679 seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067a 067a fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 067b 067b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 067c 067c ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 067d 067d seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067e 067e fiu_mem_start 2 start-rd; Flow C 0x2abf ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2abf 0x2abf typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 067f 067f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 0680 0680 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x687 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0687 0x0687 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0681 0681 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0682 0682 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0683 0683 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0684 0684 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x685 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 2 Push (branch address) seq_branch_adr 0662 0x0662 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 0685 0685 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0686 0686 fiu_mem_start 3 start-wr; Flow J 0x3b4e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0687 ; -------------------------------------------------------------------------------------- 0687 ; Comes from: 0687 ; 0680 C True from color 0x066a 0687 ; -------------------------------------------------------------------------------------- 0687 0687 ioc_adrbs 1 val ; Flow C 0x3b75 seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0688 0688 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0689 0689 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 068a 068a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 068b 068b fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 068c 068c seq_br_type 3 Unconditional Branch; Flow J 0x680 seq_branch_adr 0680 0x0680 068d ; -------------------------------------------------------------------------------------- 068d ; Comes from: 068d ; 0340 C from color 0x033e 068d ; 05f3 C from color 0x05ec 068d ; 05fe C from color 0x05fb 068d ; 39b2 C False from color 0x39b2 068d ; 39b4 C False from color 0x39b2 068d ; 3b6f C from color 0x0bab 068d ; -------------------------------------------------------------------------------------- 068d 068d seq_br_type 7 Unconditional Call; Flow C 0x6a3 seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 068e 068e seq_b_timing 1 Latch Condition; Flow C cc=True 0x722 seq_br_type 5 Call True seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 068f 068f ioc_adrbs 2 typ ioc_random 14 clear cpu running seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0690 0690 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0691 0691 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0692 0692 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0693 0693 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0694 0694 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0695 0695 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0696 0696 ioc_fiubs 1 val seq_en_micro 0 0697 0697 ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0698 0698 seq_b_timing 1 Latch Condition; Flow C cc=False 0x72b seq_br_type 4 Call False seq_branch_adr 072b 0x072b seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0699 0699 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 069a 069a seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 069b ; -------------------------------------------------------------------------------------- 069b ; Comes from: 069b ; 042d C True from color 0x0000 069b ; 05f2 C True from color 0x05ec 069b ; 05fd C False from color 0x05fb 069b ; 391d C True from color 0x0000 069b ; 394d C True from color 0x0913 069b ; 3ae6 C from color 0x0000 069b ; -------------------------------------------------------------------------------------- 069b 069b seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f seq_en_micro 0 069c 069c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069d 069d fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x69e fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 06a1 0x06a1 seq_en_micro 0 069e 069e ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069f 069f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3373 seq_br_type 1 Branch True seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 06a0 06a0 seq_br_type 3 Unconditional Branch; Flow J 0x72e seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 06a1 06a1 ioc_adrbs 3 seq ; Flow C 0x6b7 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 06a2 06a2 seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 06a3 ; -------------------------------------------------------------------------------------- 06a3 ; Comes from: 06a3 ; 068d C from color 0x0000 06a3 ; 0697 C #0x0 from color 0x0695 06a3 ; 069e C #0x0 from color 0x0698 06a3 ; -------------------------------------------------------------------------------------- 06a3 06a3 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a4 0x06a4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a4 06a4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a5 0x06a5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a5 06a5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a6 0x06a6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a6 06a6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a7 0x06a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a7 06a7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a8 0x06a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a8 06a8 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a9 0x06a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a9 06a9 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06aa 0x06aa seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06aa 06aa seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ab 0x06ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ab 06ab seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ac 0x06ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ac 06ac seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ad 0x06ad seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ad 06ad seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ae 0x06ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ae 06ae seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06af 0x06af seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06af 06af seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b0 0x06b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b0 06b0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b1 0x06b1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b1 06b1 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b2 0x06b2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b2 06b2 seq_br_type a Unconditional Return; Flow R seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b3 06b3 seq_br_type a Unconditional Return; Flow R seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 seq_latch 1 06b4 ; -------------------------------------------------------------------------------------- 06b4 ; Comes from: 06b4 ; 3664 C from color 0x3660 06b4 ; 3680 C from color 0x0200 06b4 ; 397f C from color 0x3976 06b4 ; 3998 C from color 0x398f 06b4 ; 3a2c C from color 0x3a2c 06b4 ; -------------------------------------------------------------------------------------- 06b4 06b4 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b5 06b5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 06b6 06b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06b7 ; -------------------------------------------------------------------------------------- 06b7 ; Comes from: 06b7 ; 0699 C from color 0x0698 06b7 ; 06a1 C from color 0x06a1 06b7 ; 374e C from color 0x0000 06b7 ; 375e C from color 0x0000 06b7 ; 378b C from color 0x0000 06b7 ; 397c C from color 0x3976 06b7 ; 3b86 C from color 0x3b4d 06b7 ; -------------------------------------------------------------------------------------- 06b7 06b7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b8 06b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 13 LOOP_REG typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06b9 06b9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06ba 06ba ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06bb 06bb fiu_tivi_src c mar_0xc; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 06bc 0x06bc seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 06bc 06bc seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06bd ; -------------------------------------------------------------------------------------- 06bd ; Comes from: 06bd ; 2efd C from color 0x2ee7 06bd ; 2f01 C from color 0x2ee7 06bd ; 3a1b C from color 0x0000 06bd ; -------------------------------------------------------------------------------------- 06bd 06bd fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06be 06be fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06bf 06bf seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 06c0 ; -------------------------------------------------------------------------------------- 06c0 ; Comes from: 06c0 ; 0332 C from color 0x0000 06c0 ; 033f C from color 0x033e 06c0 ; 074d C from color 0x0203 06c0 ; 075e C from color 0x0000 06c0 ; -------------------------------------------------------------------------------------- 06c0 06c0 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06c1 06c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 13 LOOP_REG val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06c2 06c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c3 06c3 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06c4 06c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 13 LOOP_REG val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 06c5 06c5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06c6 06c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c7 06c7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 06c8 06c8 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06c9 0x06c9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06c9 06c9 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06ca 06ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 06cb 06cb ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 06cc 06cc fiu_tivi_src c mar_0xc; Flow C cc=False 0x20d ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06cd 06cd seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06ce 06ce seq_en_micro 0 06cf ; -------------------------------------------------------------------------------------- 06cf ; Comes from: 06cf ; 370b C from color 0x0000 06cf ; 38c0 C from color 0x38b7 06cf ; 38cf C from color 0x38b7 06cf ; 3aa0 C from color 0x0000 06cf ; 3acb C from color 0x0000 06cf ; -------------------------------------------------------------------------------------- 06cf 06cf fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06d0 06d0 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR04:05 typ_frame 4 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 06d1 06d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 06d2 06d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x6e8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 06e8 0x06e8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06d3 06d3 fiu_mem_start 3 start-wr; Flow C 0x3b52 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b52 0x3b52 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 06d4 06d4 seq_br_type 2 Push (branch address); Flow J 0x6d5 seq_branch_adr 06e0 0x06e0 seq_en_micro 0 06d5 06d5 seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 06d6 06d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 28 VR04:08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 06d7 06d7 ioc_fiubs 2 typ ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06d8 06d8 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 06d9 06d9 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06da 06da fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR09:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06db 06db ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 06dc 06dc ioc_adrbs 2 typ ; Flow C cc=False 0x20d seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 06dd 06dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 06de 06de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 06df 06df fiu_mem_start 2 start-rd; Flow J 0x3713 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 06e0 06e0 ioc_adrbs 1 val ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand a PASS_B_HIGH 06e1 06e1 fiu_mem_start 2 start-rd; Flow J cc=False 0x6e5 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 06e5 0x06e5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 06e2 06e2 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 06 GP06 06e3 06e3 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06e4 06e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x6d1 seq_br_type 1 Branch True seq_branch_adr 06d1 0x06d1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06e5 06e5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? 06e6 ; -------------------------------------------------------------------------------------- 06e6 ; Comes from: 06e6 ; 06e8 C from color 0x06d2 06e6 ; 06ed C from color 0x06d2 06e6 ; 0702 C from color 0x0000 06e6 ; -------------------------------------------------------------------------------------- 06e6 06e6 seq_en_micro 0 06e7 06e7 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 06e8 06e8 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 06e9 06e9 fiu_mem_start d start_physical_rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 06ea 06ea fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 06eb 06eb seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06ec ; -------------------------------------------------------------------------------------- 06ec ; Comes from: 06ec ; 3698 C from color 0x05a7 06ec ; -------------------------------------------------------------------------------------- 06ec 06ec seq_br_type 0 Branch False; Flow J cc=False 0x6f8 seq_branch_adr 06f8 0x06f8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 32 TR02:12 typ_frame 2 06ed 06ed fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 06ee 06ee fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 06ef 06ef ioc_fiubs 2 typ ; Flow J cc=False 0x6f5 seq_br_type 0 Branch False seq_branch_adr 06f5 0x06f5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 25 TR04:05 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 06f0 06f0 seq_br_type 7 Unconditional Call; Flow C 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 06f1 06f1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x6f8 seq_br_type 0 Branch False seq_branch_adr 06f8 0x06f8 seq_en_micro 0 06f2 06f2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06f3 0x06f3 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 2c TR04:0c typ_frame 4 val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f3 06f3 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f4 06f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06f5 06f5 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 06f6 0x06f6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f6 06f6 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f7 06f7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 06f8 06f8 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 typ_b_adr 25 TR04:05 typ_frame 4 06f9 06f9 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06fa 0x06fa seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06fa 06fa fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 val_a_adr 3d VR04:1d val_frame 4 06fb 06fb seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_en_micro 0 06fc ; -------------------------------------------------------------------------------------- 06fc ; Comes from: 06fc ; 06f8 C from color 0x06d2 06fc ; 06fa C from color 0x06d2 06fc ; -------------------------------------------------------------------------------------- 06fc 06fc seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fd 06fd fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fe 06fe fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06ff 06ff seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0700 0700 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 0701 0701 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0702 0x0702 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0702 0702 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 26 TR04:06 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0703 0703 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0704 0704 seq_br_type 0 Branch False; Flow J cc=False 0x706 seq_branch_adr 0706 0x0706 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_b_adr 25 TR04:05 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 0705 0705 seq_br_type 3 Unconditional Branch; Flow J 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0706 0706 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0707 0707 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 0708 0708 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 0 PASS_A val_b_adr 3a VR04:1a val_frame 4 0709 0709 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 070a 070a seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 070b ; -------------------------------------------------------------------------------------- 070b ; Comes from: 070b ; 06f0 C from color 0x06d2 070b ; -------------------------------------------------------------------------------------- 070b 070b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 070c 070c fiu_load_var 1 hold_var; Flow J cc=False 0x710 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0710 0x0710 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 19 TR04:06 typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_b_adr 29 VR04:09 val_frame 4 070d 070d seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 070e 070e fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 070f 070f seq_en_micro 0 0710 0710 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x716 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0716 0x0716 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 0711 0711 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0712 0712 ioc_fiubs 0 fiu ; Flow J cc=True 0x70b seq_br_type 1 Branch True seq_branch_adr 070b 0x070b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 25 TR04:05 typ_b_adr 26 TR04:06 typ_c_adr 1b TR04:04 typ_c_source 0 FIU_BUS typ_frame 4 0713 0713 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_c_adr 13 VR04:0c val_frame 4 0714 0714 fiu_mem_start e start_physical_wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR04:04 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR04:0d typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED 0715 0715 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 2c TR04:0c typ_frame 4 val_b_adr 2c VR04:0c val_frame 4 0716 0716 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0717 0717 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0718 0718 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 04 GP04 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0719 0719 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 071a 071a seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 071b 071b fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 30 GP0f val_c_source 0 FIU_BUS 071c 071c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 071d 071d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 071e 071e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 071f 071f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 14 ZEROS 0720 0720 seq_br_type 7 Unconditional Call; Flow C 0x707 seq_branch_adr 0707 0x0707 seq_en_micro 0 0721 0721 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0722 ; -------------------------------------------------------------------------------------- 0722 ; Comes from: 0722 ; 069a C from color 0x0698 0722 ; 06a2 C from color 0x06a1 0722 ; 074e C from color 0x0203 0722 ; -------------------------------------------------------------------------------------- 0722 0722 fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 2 typ ioc_random 13 set cpu running seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0723 0723 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x727 seq_br_type 1 Branch True seq_branch_adr 0727 0x0727 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 0724 0724 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0725 0725 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 0726 0726 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0727 0727 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0728 0728 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 0729 0729 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 072a 072a fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072b ; -------------------------------------------------------------------------------------- 072b ; Comes from: 072b ; 0698 C False from color 0x0698 072b ; -------------------------------------------------------------------------------------- 072b 072b fiu_mem_start 2 start-rd; Flow C 0x3394 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_random 14 clear cpu running ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 072c 072c seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 072d 072d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072e 072e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072f ; -------------------------------------------------------------------------------------- 072f ; Comes from: 072f ; 0725 C from color 0x0000 072f ; 0729 C from color 0x0000 072f ; -------------------------------------------------------------------------------------- 072f 072f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 25 TR08:05 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 0730 0730 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0731 0731 fiu_fill_mode_src 0 ; Flow J cc=True 0x733 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0733 0x0733 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 0732 0732 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 0733 0733 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 0734 0734 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x736 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0736 0x0736 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 23 VR02:03 val_frame 2 0735 0735 seq_b_timing 0 Early Condition; Flow J cc=True 0x736 ; Flow J cc=#0x0 0x0 seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0736 0736 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 0737 0737 seq_br_type 3 Unconditional Branch; Flow J 0x734 seq_branch_adr 0734 0x0734 seq_en_micro 0 0738 ; -------------------------------------------------------------------------------------- 0738 ; Comes from: 0738 ; 0724 C True from color 0x0000 0738 ; 0728 C True from color 0x0000 0738 ; 072c C True from color 0x0000 0738 ; -------------------------------------------------------------------------------------- 0738 0738 seq_br_type 7 Unconditional Call; Flow C 0x33bc seq_branch_adr 33bc 0x33bc seq_en_micro 0 seq_random 02 ? 0739 0739 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 073a 073a fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR06:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 073b 073b fiu_mem_start 3 start-wr; Flow J 0x74f seq_br_type 3 Unconditional Branch seq_branch_adr 074f 0x074f seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 28 VR08:08 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 073c 073c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 073d 073d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 073e 073e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 073f 073f seq_br_type 1 Branch True; Flow J cc=True 0x742 seq_branch_adr 0742 0x0742 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 5 DEC_A_MINUS_B val_b_adr 26 VR05:06 val_frame 5 0740 0740 seq_b_timing 0 Early Condition; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0741 0741 fiu_mem_start 2 start-rd; Flow J 0x744 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0744 0x0744 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0742 0742 seq_b_timing 0 Early Condition; Flow J cc=False 0x749 seq_br_type 0 Branch False seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0743 0743 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1 A_PLUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0744 0744 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 0745 0745 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0746 0746 ioc_load_wdr 0 ; Flow J 0x747 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 075d 0x075d seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0747 0747 seq_br_type 0 Branch False; Flow J cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0748 0748 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x756 seq_br_type 8 Return True seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0749 0749 seq_b_timing 1 Latch Condition; Flow C cc=False 0x756 seq_br_type 4 Call False seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 074a 074a seq_br_type 2 Push (branch address); Flow J 0x74b seq_branch_adr 074d 0x074d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 074b 074b fiu_load_tar 1 hold_tar; Flow J cc=True 0x3390 fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3390 0x3390 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 074c 074c ioc_random c enable slice timer; Flow J 0x72e seq_br_type 3 Unconditional Branch seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 074d 074d ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 074e 074e seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 074f 074f ioc_load_wdr 0 ; Flow J 0x750 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 074a 0x074a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f 0750 0750 seq_br_type 4 Call False; Flow C cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0751 0751 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x731 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 0752 0752 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x731 seq_br_type 0 Branch False seq_branch_adr 0731 0x0731 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 34 TR08:14 typ_frame 8 0753 0753 fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP 0754 0754 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0755 0755 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x731 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0756 ; -------------------------------------------------------------------------------------- 0756 ; Comes from: 0756 ; 0749 C False from color 0x0000 0756 ; -------------------------------------------------------------------------------------- 0756 0756 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f seq_en_micro 0 0757 0757 fiu_mem_start 2 start-rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 0758 0758 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0759 0759 ioc_tvbs 2 fiu+val; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 075a 0x075a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 075a 075a seq_en_micro 0 seq_random 06 Pop_stack+? 075b 075b fiu_load_tar 1 hold_tar; Flow J 0x75c fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 0717 0x0717 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 075c 075c ioc_adrbs 3 seq ; Flow J 0x3390 ioc_random a clear slice event seq_br_type 3 Unconditional Branch seq_branch_adr 3390 0x3390 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 075d 075d fiu_load_tar 1 hold_tar; Flow C 0x3390 fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_br_type 7 Unconditional Call seq_branch_adr 3390 0x3390 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL 075e 075e ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 075f 075f seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0760 0760 seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0761 0761 seq_br_type 2 Push (branch address); Flow J 0x762 seq_branch_adr 074d 0x074d seq_en_micro 0 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0762 0762 seq_br_type 3 Unconditional Branch; Flow J 0x74b seq_branch_adr 074b 0x074b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 0763 0763 fiu_load_tar 1 hold_tar; Flow C 0x3651 fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 3651 0x3651 seq_en_micro 0 typ_b_adr 3b TR12:1b typ_frame 12 0764 0764 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0765 0765 ioc_random c enable slice timer seq_en_micro 0 val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0766 0766 seq_br_type 3 Unconditional Branch; Flow J 0x32a1 seq_branch_adr 32a1 0x32a1 seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0767 0767 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 19 VR04:06 val_c_source 0 FIU_BUS val_frame 4 0768 0768 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0769 0769 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 076a 076a fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR04:02 val_c_mux_sel 2 ALU val_frame 4 076b 076b seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 4 076c 076c ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_frame d val_c_adr 3c GP03 val_c_source 0 FIU_BUS 076d 076d seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 076e 076e seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 076f 076f seq_b_timing 0 Early Condition; Flow J cc=False 0x76d seq_br_type 0 Branch False seq_branch_adr 076d 0x076d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0770 0770 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 11 TR0d:0e typ_c_source 0 FIU_BUS typ_frame d val_a_adr 22 VR04:02 val_frame 4 0771 0771 seq_en_micro 0 typ_a_adr 26 TR0d:06 typ_alu_func 0 PASS_A typ_c_adr 17 TR0d:08 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 27 VR0d:07 val_alu_func 0 PASS_A val_c_adr 17 VR0d:08 val_c_mux_sel 2 ALU val_frame d 0772 0772 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 2b TR0d:0b typ_alu_func 0 PASS_A typ_c_adr 10 TR0d:0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2b VR0d:0b val_alu_func 0 PASS_A val_c_adr 10 VR0d:0f val_c_mux_sel 2 ALU val_frame d 0773 0773 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0774 0774 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 27 VR04:07 val_alu_func 0 PASS_A val_c_adr 18 VR04:07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0775 0775 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 28 VR04:08 val_alu_func 0 PASS_A val_c_adr 17 VR04:08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0776 0776 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0777 0777 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_random 02 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 25 VR04:05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0778 0778 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 26 VR04:06 val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 0779 0779 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x77c seq_br_type 1 Branch True seq_branch_adr 077c 0x077c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3b TR05:1b typ_frame 5 077a 077a fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 077b 077b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 077c 077c fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 077d 077d fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 077e 077e fiu_fill_mode_src 0 ; Flow J 0x77f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0782 0x0782 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 077f 077f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x791 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0780 0780 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 06 Pop_stack+? typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0781 0781 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 0782 0782 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0783 0783 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0784 0784 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 0785 0785 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0786 0786 <default> 0787 0787 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x78b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 078b 0x078b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0788 0788 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 0789 0789 <default> 078a 078a ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 078b 078b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 078c 078c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1a PASS_B 078d 078d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 078e 078e fiu_fill_mode_src 0 ; Flow J cc=False 0x791 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 078f 078f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0790 0790 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0791 0791 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0792 0792 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0793 0793 fiu_load_var 1 hold_var; Flow J 0x790 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0790 0x0790 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0794 0794 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 2b VR04:0b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 0795 0795 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 0796 0796 ioc_fiubs 2 typ typ_a_adr 2b TR04:0b typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0797 0797 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0798 0x0798 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 0798 0798 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0799 0799 seq_br_type 3 Unconditional Branch; Flow J 0x79b seq_branch_adr 079b 0x079b seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3d VR02:1d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 079a 079a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7a2 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07a2 0x07a2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 14 ZEROS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 079b 079b seq_br_type 1 Branch True; Flow J cc=True 0x79a seq_branch_adr 079a 0x079a seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 26 VR06:06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 079c 079c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x79a fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 079a 0x079a seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 079d 079d fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x79e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 079c 0x079c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 25 TR08:05 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 079e 079e fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 079f 079f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x7a1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 07a1 0x07a1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 07a0 07a0 ioc_tvbs 3 fiu+fiu; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 07a1 07a1 ioc_tvbs 3 fiu+fiu; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 07a2 07a2 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07a3 07a3 fiu_load_var 1 hold_var; Flow C 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 07ab 0x07ab seq_en_micro 0 typ_a_adr 37 TR04:17 typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07a4 07a4 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_frame 5 val_alu_func 1a PASS_B val_b_adr 37 VR04:17 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a5 07a5 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 0 PASS_A typ_frame 4 val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 07a6 07a6 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_frame 6 val_alu_func 1a PASS_B val_b_adr 38 VR04:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a7 07a7 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 08 TR04:17 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 14 ZEROS val_c_adr 08 VR04:17 val_c_source 0 FIU_BUS val_frame 4 07a8 07a8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR05:1e val_frame 5 07a9 07a9 fiu_fill_mode_src 0 ; Flow C 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 07b1 0x07b1 seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 07aa 07aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 07 TR04:18 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_c_adr 07 VR04:18 val_c_source 0 FIU_BUS val_frame 4 07ab ; -------------------------------------------------------------------------------------- 07ab ; Comes from: 07ab ; 07a3 C from color 0x07a3 07ab ; 07a4 C True from color 0x07a3 07ab ; 07a5 C True from color 0x07a3 07ab ; 07a6 C True from color 0x07a3 07ab ; -------------------------------------------------------------------------------------- 07ab 07ab fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 07ac 0x07ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 07ac 07ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07ad 07ad fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 07ae 07ae fiu_fill_mode_src 0 ; Flow C cc=True 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 07b1 0x07b1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 07af 07af fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 07b0 07b0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x7ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 07ab 0x07ab seq_en_micro 0 val_a_adr 03 GP03 val_b_adr 39 VR02:19 val_frame 2 07b1 ; -------------------------------------------------------------------------------------- 07b1 ; Comes from: 07b1 ; 07a9 C from color 0x07a3 07b1 ; 07ae C True from color 0x07ab 07b1 ; -------------------------------------------------------------------------------------- 07b1 07b1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 07b2 07b2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07b3 07b3 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07b4 ; -------------------------------------------------------------------------------------- 07b4 ; Comes from: 07b4 ; 0693 C from color 0x0693 07b4 ; 06b4 C from color 0x0000 07b4 ; 06bd C from color 0x062d 07b4 ; 06e9 C from color 0x06d2 07b4 ; 0757 C from color 0x0203 07b4 ; -------------------------------------------------------------------------------------- 07b4 07b4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 07b5 07b5 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 07b6 ; -------------------------------------------------------------------------------------- 07b6 ; Comes from: 07b6 ; 05ad C from color 0x05a7 07b6 ; 06d5 C from color 0x06d2 07b6 ; 361e C from color 0x0000 07b6 ; 3b6d C from color 0x0bab 07b6 ; -------------------------------------------------------------------------------------- 07b6 07b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7b5 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07b5 0x07b5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07b7 07b7 seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 07b8 07b8 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 15 ? typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS 07b9 07b9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 21 TR02:01 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 07ba 07ba fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x7dd fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 07dd 0x07dd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_c_adr 34 GP0b val_frame 2 07bb 07bb seq_en_micro 0 typ_c_adr 32 GP0d val_c_adr 32 GP0d 07bc 07bc fiu_len_fill_lit 6f zero-fill 0x2f; Flow J cc=False 0x7bf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07bf 0x07bf seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c 07bd 07bd fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3651 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3651 0x3651 seq_en_micro 0 val_a_adr 0c GP0c val_b_adr 3c VR12:1c val_frame 12 07be 07be fiu_mem_start 3 start-wr seq_en_micro 0 07bf 07bf fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07c0 07c0 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0e GP0e val_b_adr 0e GP0e 07c1 07c1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_random 06 Pop_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07c2 07c2 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07c3 07c3 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 22 VR02:02 val_frame 2 07c4 07c4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR 07c5 07c5 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 07c6 07c6 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 07c7 07c7 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 07c8 07c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 07c9 07c9 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 05 GP05 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 05 GP05 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07ca 07ca fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 07cb 07cb fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 07cc 07cc fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 07cd 07cd fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 09 GP09 07ce 07ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x7d0 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d0 0x07d0 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 5b ? typ_a_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 07cf 07cf fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d0 07d0 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=False 0x7d2 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d2 0x07d2 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 21 VR0d:01 val_frame d 07d1 07d1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d2 07d2 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 0a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 17 LOOP_COUNTER val_b_adr 20 VR0d:00 val_frame d 07d3 07d3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0b GP0b val_b_adr 22 VR0d:02 val_frame d 07d4 07d4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR0d:03 val_frame d 07d5 07d5 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 07d6 07d6 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 24 TR02:04 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR02:04 val_frame 2 07d7 07d7 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07d8 07d8 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0b GP0b 07d9 07d9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR12:14 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 07da 07da fiu_mem_start a start_continue_if_false; Flow J cc=True 0x7dc ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07dc 0x07dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 14 BOT - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 07db 07db fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7db ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07db 0x07db seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 15 BOT typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 15 BOT val_rand 2 DEC_LOOP_COUNTER 07dc 07dc seq_br_type a Unconditional Return; Flow R seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 07dd 07dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 39 VR02:19 val_frame 2 07de 07de fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07df 07df fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e0 07e0 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e1 07e1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e2 07e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 07e3 07e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e4 07e4 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e5 07e5 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e6 07e6 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION 07e7 07e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x7bc fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 07bc 0x07bc seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07e8 07e8 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 07e9 07e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7e8 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07e8 0x07e8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ea 07ea fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7ed seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07ed 0x07ed seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_frame 3 typ_mar_cntl 6 INCREMENT_MAR 07eb 07eb ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ec 07ec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x80f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 080f 0x080f seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ed 07ed fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 07ee 07ee fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ef 07ef fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 25 TR02:05 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07f0 07f0 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 6 INCREMENT_MAR 07f1 07f1 fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 07f2 07f2 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 07f3 07f3 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07f4 07f4 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 07f5 07f5 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 07f6 07f6 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 07f7 07f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 07f8 07f8 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 07f9 07f9 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 07fa 07fa fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 07fb 07fb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 55 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 07fc 07fc fiu_len_fill_lit 4a zero-fill 0xa fiu_mem_start 4 continue fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07fd 07fd fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 07fe 07fe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 07ff 07ff fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0800 0800 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_mux_sel 2 ALU val_frame d 0801 0801 ioc_adrbs 1 val ; Flow J cc=True 0x802 ; Flow J cc=#0x0 0x802 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0802 0x0802 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_lex_adr 2 seq_random 14 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0802 0802 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0803 0803 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0804 0804 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0805 0805 seq_br_type 3 Unconditional Branch; Flow J 0x804 seq_branch_adr 0804 0x0804 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? 0806 0806 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 22 TR02:02 typ_b_adr 21 TR02:01 typ_c_adr 1b TR02:04 typ_frame 2 val_b_adr 25 VR02:05 val_c_adr 1b VR02:04 val_frame 2 0807 0807 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR11:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 11 val_rand a PASS_B_HIGH 0808 0808 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80c ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080c 0x080c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0e GP0e 0809 0809 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80b ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080b 0x080b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080a 080a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x80a ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 080a 0x080a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080b 080b fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080c 080c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080d 080d fiu_len_fill_lit 59 zero-fill 0x19 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 0d GP0d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 080e 080e fiu_len_fill_lit 49 zero-fill 0x9; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 1 ALU >> 16 080f ; -------------------------------------------------------------------------------------- 080f ; Comes from: 080f ; 07ec C from color 0x07e8 080f ; -------------------------------------------------------------------------------------- 080f 080f fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0810 0810 seq_en_micro 0 0811 0811 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x816 seq_br_type 1 Branch True seq_branch_adr 0816 0x0816 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0812 0812 fiu_mem_start 3 start-wr; Flow C 0x3653 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3653 0x3653 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0813 0813 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl b LOAD_MAR_DATA 0814 0814 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0815 0815 fiu_tivi_src 4 fiu_var; Flow R cc=True ; Flow J cc=False 0x211 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_b_adr 39 VR03:19 val_frame 3 0816 0816 fiu_mem_start 5 start_rd_if_true; Flow R cc=False ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0817 0x0817 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0817 0817 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0818 0x0818 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0818 0818 fiu_tivi_src 2 tar_fiu; Flow J 0x812 ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0812 0x0812 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0819 0819 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 081a 081a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 16 stage data register ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 081b 081b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20b fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b val_b_adr 0b GP0b 081c 081c fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 34 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 081d 081d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x81e ; Flow J cc=#0x0 0x81f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 081f 0x081f seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR00:05 val_a_adr 0b GP0b 081e 081e seq_br_type 7 Unconditional Call; Flow C 0x20c seq_branch_adr 020c 0x020c seq_en_micro 0 081f 081f seq_br_type 3 Unconditional Branch; Flow J 0x825 seq_branch_adr 0825 0x0825 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0820 0820 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x846 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0846 0x0846 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0821 0821 fiu_len_fill_lit 57 zero-fill 0x17; Flow J 0x871 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0871 0x0871 seq_en_micro 0 0822 0822 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x85d fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 085d 0x085d seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0823 0823 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x865 fiu_load_mdr 1 hold_mdr fiu_mem_start f start_physical_tag_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0865 0x0865 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0824 0824 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x86c fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 086c 0x086c seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0825 0825 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 1e TR19:01 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0826 0826 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 1e VR19:01 val_c_source 0 FIU_BUS val_frame 19 0827 0827 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x20c fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0828 0828 fiu_len_fill_lit 7c zero-fill 0x3c fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 1c TR19:03 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1c VR19:03 val_c_source 0 FIU_BUS val_frame 19 0829 0829 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 34 GP0b val_c_source 0 FIU_BUS 082a 082a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 1d TR19:02 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 23 VR19:03 val_alu_func 6 A_MINUS_B val_b_adr 0b GP0b val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 082b 082b fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 082c 082c seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 082d 082d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 082e 082e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x211 fiu_mem_start 4 continue fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_c_adr 3f GP00 082f 082f ioc_load_wdr 0 ; Flow J cc=True 0x830 ; Flow J cc=#0x0 0x830 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0830 0x0830 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0830 0830 fiu_vmux_sel 1 fill value; Flow J 0x834 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0834 0x0834 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 23 VR19:03 val_c_adr 1d VR19:02 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 0831 0831 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0832 0832 fiu_mem_start 11 start_tag_query; Flow J 0x836 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0836 0x0836 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR19:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame 19 0833 0833 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0834 0834 seq_en_micro 0 val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0835 0835 ioc_fiubs 2 typ ; Flow J 0x83e seq_br_type 3 Unconditional Branch seq_branch_adr 083e 0x083e seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0836 0836 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x834 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0834 0x0834 seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0837 0837 seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0838 0838 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x211 ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0839 0839 ioc_adrbs 1 val ; Flow C cc=True 0x2a84 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 083a 083a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 083b 083b fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 083c 083c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083d 083d ioc_fiubs 2 typ ; Flow J cc=True 0x839 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0839 0x0839 seq_en_micro 0 typ_a_adr 21 TR05:01 typ_b_adr 05 GP05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083e 083e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 083f 083f fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0840 0840 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0841 0841 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3713 seq_br_type 1 Branch True seq_branch_adr 3713 0x3713 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 2 0842 0842 seq_br_type 4 Call False; Flow C cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0843 0843 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3713 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3713 0x3713 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0844 0844 seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3e VR04:1e val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0845 0845 fiu_mem_start 2 start-rd; Flow J 0x3713 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0846 0846 fiu_load_oreg 1 hold_oreg fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 12 0847 0847 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x20c fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0848 0848 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20c fiu_mem_start 13 start_available_query fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 0849 0849 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20c fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR10:01 typ_frame 10 084a 084a seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 084b 084b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 084c 084c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 084d 084d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_frame 6 084e 084e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 31 VR02:11 val_frame 2 084f 084f fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0850 0850 fiu_tivi_src 2 tar_fiu; Flow C 0x8a5 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 08a5 0x08a5 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0851 0851 ioc_adrbs 1 val ; Flow C cc=True 0x2a84 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 0852 0852 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0853 0853 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0854 0854 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0855 0855 ioc_load_wdr 0 ; Flow J cc=False 0x851 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0851 0x0851 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 0856 0856 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0b GP0b val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0857 0857 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0858 0858 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b 0859 0859 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 32 VR02:12 val_frame 2 085a 085a fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 14 clear cpu running seq_en_micro 0 val_a_adr 14 ZEROS 085b 085b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 085c 085c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 085d 085d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_rand e CHECK_CLASS_SYSTEM_B 085e 085e ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 3a TR02:1a typ_frame 2 085f 085f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 13 LOOP_REG val_rand 1 INC_LOOP_COUNTER 0860 0860 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x85d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 085d 0x085d seq_en_micro 0 typ_a_adr 0b GP0b 0861 0861 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 typ_c_adr 34 GP0b 0862 0862 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0863 0863 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_b_adr 0b GP0b typ_frame 10 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0864 0864 fiu_tivi_src 4 fiu_var; Flow J 0x859 ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0859 0x0859 seq_en_micro 0 val_a_adr 0b GP0b val_c_adr 34 GP0b 0865 0865 fiu_mem_start 15 setup_tag_read fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0866 0866 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x868 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 0868 0x0868 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0867 0867 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x861 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs a fiu+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0868 0868 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x867 fiu_load_tar 1 hold_tar fiu_mem_start 15 setup_tag_read fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0867 0x0867 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 0869 0869 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 086a 086a fiu_mem_start f start_physical_tag_rd seq_en_micro 0 086b 086b fiu_mem_start 15 setup_tag_read; Flow J 0x867 seq_br_type 3 Unconditional Branch seq_branch_adr 0867 0x0867 seq_en_micro 0 086c 086c seq_br_type 3 Unconditional Branch; Flow J 0x86f seq_branch_adr 086f 0x086f seq_en_micro 0 086d 086d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 7 INC_A typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 0b GP0b 086e 086e ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x861 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 086f 086f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0870 0870 fiu_tivi_src c mar_0xc; Flow J 0x86d ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address seq_br_type 3 Unconditional Branch seq_branch_adr 086d 0x086d seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_rand d SET_PASS_PRIVACY_BIT 0871 0871 fiu_len_fill_lit 57 zero-fill 0x17 fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 32 TR02:12 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0872 0872 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20c seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_frame 3 0873 0873 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0874 0874 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 0875 0875 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0876 0876 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0877 0877 fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0878 0878 seq_b_timing 1 Latch Condition; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 05 VR03:1a val_c_mux_sel 2 ALU val_frame 3 0879 0879 ioc_fiubs 1 val ; Flow C 0xb92 seq_br_type 7 Unconditional Call seq_branch_adr 0b92 0x0b92 seq_en_micro 0 typ_c_adr 1b TR1b:04 typ_c_mux_sel 0 ALU typ_frame 1b typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR1b:04 val_c_mux_sel 2 ALU val_frame 1b val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 087a 087a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 087b 087b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 087c 087c ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 087d 087d typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 087e 087e typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 087f 087f typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 0880 0880 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0881 0881 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0882 0882 fiu_mem_start 2 start-rd; Flow J 0x3713 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0883 0883 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 14 ZEROS typ_b_adr 1e TOP - 2 typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 20 VR06:00 val_frame 6 0884 0884 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x888 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0888 0x0888 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0885 0885 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0886 0886 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x88c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 088c 0x088c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0887 0887 fiu_fill_mode_src 0 ; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0888 0888 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0889 0889 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 088a 088a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 088b 088b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088c 088c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 088d 088d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088e 088e fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 33 VR03:13 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 3 088f 088f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR05:01 val_frame 5 0890 0890 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3e TR03:1e typ_alu_func 7 INC_A typ_c_adr 01 TR03:1e typ_c_mux_sel 0 ALU typ_frame 3 0891 0891 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 0892 0892 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR05:1b val_frame 5 0893 0893 ioc_load_wdr 0 ; Flow J cc=True 0x89c ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 089c 0x089c typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0894 0894 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0895 0895 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x211 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 0896 0896 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 0897 0897 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 05 GP05 0898 0898 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0899 0899 ioc_random 1e write ioc memory and increment address seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 06 GP06 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 089a 089a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 06 GP06 089b 089b ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x898 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0898 0x0898 seq_en_micro 0 089c 089c fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3f GP00 val_frame 3 val_rand c START_MULTIPLY 089d 089d seq_en_micro 0 typ_c_adr 3f GP00 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 089e 089e fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 089f 089f fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 05 GP05 08a0 08a0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address seq_en_micro 0 08a1 08a1 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a2 08a2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a3 08a3 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a4 08a4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 08a5 ; -------------------------------------------------------------------------------------- 08a5 ; Comes from: 08a5 ; 0850 C from color 0x0820 08a5 ; -------------------------------------------------------------------------------------- 08a5 08a5 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 08a6 08a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 08a7 08a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34cd fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 08a8 08a8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 08 GP08 val_b_adr 08 GP08 08a9 08a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 08aa 08aa fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_frame 2 08ab 08ab fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 val_a_adr 3a VR08:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 08ac 08ac seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 08ad 08ad fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3f VR02:1f val_frame 2 08ae 08ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 33 TR09:13 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 9 typ_rand c WRITE_OUTER_FRAME 08af 08af fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_c_adr 13 VR0d:0c val_c_mux_sel 2 ALU val_frame d 08b0 08b0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 12 VR0d:0d val_c_source 0 FIU_BUS val_frame d 08b1 08b1 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 2d VR0d:0d val_alu_func 7 INC_A val_c_adr 12 VR0d:0d val_c_mux_sel 2 ALU val_frame d 08b2 08b2 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_mux_sel 2 ALU 08b3 08b3 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 08b4 08b4 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08b5 08b5 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08b6 08b6 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08b7 08b7 seq_br_type 0 Branch False; Flow J cc=False 0x8c4 seq_branch_adr 08c4 0x08c4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 08b8 08b8 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08b9 08b9 fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ba 08ba fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08bb 08bb fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08bc 08bc fiu_mem_start f start_physical_tag_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08bd 08bd fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08be 08be fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08bf 08bf fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 13 VR0d:0c val_c_source 0 FIU_BUS val_frame d 08c0 08c0 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08c1 08c1 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c0 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08c0 0x08c0 seq_en_micro 0 08c2 08c2 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 08c3 08c3 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c4 08c4 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8b5 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08b5 0x08b5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08c5 08c5 seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08c6 08c6 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR08:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 2c VR0d:0c val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame d 08c7 08c7 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c8 08c8 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08c9 08c9 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08ca 08ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 12 TR0d:0d typ_c_source 0 FIU_BUS typ_frame d 08cb 08cb seq_br_type 0 Branch False; Flow J cc=False 0x8d9 seq_branch_adr 08d9 0x08d9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08cc 08cc fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08cd 08cd fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ce 08ce fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08cf 08cf fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08d0 08d0 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08d1 08d1 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08d2 08d2 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x20d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08d3 08d3 fiu_mem_start e start_physical_wr fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 2c VR0d:0c val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame d 08d4 08d4 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 08d5 08d5 fiu_mem_start e start_physical_wr; Flow J cc=True 0x8d4 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08d4 0x08d4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08d6 08d6 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x8d3 fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08d3 0x08d3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 39 VR08:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 08d7 08d7 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 08d8 08d8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08d9 08d9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c9 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08c9 0x08c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08da 08da seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08db 08db fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2c VR0d:0c val_frame d 08dc 08dc fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 11 VR0d:0e val_c_source 0 FIU_BUS val_frame d 08dd 08dd seq_en_micro 0 val_a_adr 23 VR08:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 08de 08de fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_frame d val_a_adr 33 VR05:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 08df 08df fiu_mem_start 13 start_available_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 08e0 08e0 seq_en_micro 0 08e1 08e1 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 08e2 08e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 08e3 08e3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 04 GP04 08e4 08e4 ioc_load_wdr 0 ; Flow J cc=False 0x8df ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08df 0x08df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 08e5 08e5 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 08e6 ; -------------------------------------------------------------------------------------- 08e6 ; Comes from: 08e6 ; 08c5 C from color 0x0127 08e6 ; 08da C from color 0x0127 08e6 ; -------------------------------------------------------------------------------------- 08e6 08e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 08e7 08e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 08e8 08e8 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 08e9 08e9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ea 08ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ec seq_br_type 1 Branch True seq_branch_adr 08ec 0x08ec seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08eb 08eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ec 08ec fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ed 08ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ef seq_br_type 1 Branch True seq_branch_adr 08ef 0x08ef seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08ee 08ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ef 08ef fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f0 08f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f2 seq_br_type 1 Branch True seq_branch_adr 08f2 0x08f2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f1 08f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f2 08f2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f3 08f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f5 seq_br_type 1 Branch True seq_branch_adr 08f5 0x08f5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f4 08f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f5 08f5 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 08f6 08f6 fiu_mem_start 18 acknowledge_refresh; Flow C 0x364b fiu_tivi_src c mar_0xc ioc_random 1 load transfer address seq_br_type 7 Unconditional Call seq_branch_adr 364b 0x364b seq_en_micro 0 seq_random 0a ? typ_b_adr 33 TR02:13 typ_frame 2 08f7 08f7 ioc_random 1c read ioc memory and increment address seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 30 VR02:10 val_frame 2 08f8 08f8 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08f9 08f9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 seq_random 55 ? typ_c_adr 0c TR03:13 typ_c_source 0 FIU_BUS typ_frame 3 val_c_adr 0c VR03:13 val_c_source 0 FIU_BUS val_frame 3 08fa 08fa fiu_mem_start 13 start_available_query ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08fb 08fb seq_en_micro 0 08fc 08fc fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3a VR11:1a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 08fd 08fd fiu_mem_start 17 scavenger_write; Flow J cc=False 0x8fc fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fc 0x08fc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_b_adr 22 VR07:02 val_frame 7 val_rand 2 DEC_LOOP_COUNTER 08fe 08fe fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x8fb ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fb 0x08fb seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08ff 08ff fiu_tivi_src 8 type_var; Flow C 0x2a84 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a84 0x2a84 seq_en_micro 0 typ_b_adr 33 TR09:13 typ_frame 9 typ_mar_cntl 4 RESTORE_MAR 0900 0900 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0b VR03:14 val_c_source 0 FIU_BUS val_frame 3 0901 0901 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0a VR03:15 val_c_source 0 FIU_BUS val_frame 3 0902 0902 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 09 VR03:16 val_c_source 0 FIU_BUS val_frame 3 0903 0903 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb53 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b53 0x0b53 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0904 0904 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0905 0905 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_b_adr 1f TOP - 1 0906 0906 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0907 0907 ioc_fiubs 1 val ; Flow C cc=False 0x32ac ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2f VR12:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 12 0908 0908 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0909 0909 ioc_fiubs 0 fiu typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 090a 090a fiu_mem_start 2 start-rd; Flow C cc=True 0x326e ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 090b 090b typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 090c 090c fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a7 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 090d 090d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 090e 090e fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x90b ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 090b 0x090b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 090f 090f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 03 GP03 val_rand a PASS_B_HIGH 0910 0910 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 0f Load_control_top+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 1 START_POP_DOWN typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0911 0911 fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 04 GP04 0912 0912 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0913 0913 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0914 0914 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0915 0915 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x916 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32ae 0x32ae typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0916 0916 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x3941 fiu_offs_lit 45 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 3941 0x3941 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 0917 0917 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0918 0918 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0919 0919 ioc_adrbs 1 val ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 091a 091a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x91e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 091e 0x091e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 091b 091b <default> 091c 091c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 091d 091d ioc_load_wdr 0 ; Flow J 0x94d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 094d 0x094d 091e 091e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 091f 091f <halt> ; Flow R 0920 ; -------------------------------------------------------------------------------------- 0920 ; 0x020d Execute Module,Elaborate 0920 ; -------------------------------------------------------------------------------------- 0920 MACRO_Execute_Module,Elaborate: 0920 0920 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0920 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0921 0921 fiu_mem_start 4 continue; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 0922 0922 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0923 0923 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0924 0924 fiu_mem_start 3 start-wr; Flow C cc=True 0x32ab ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0925 0925 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 0926 0926 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0927 0927 <halt> ; Flow R 0928 ; -------------------------------------------------------------------------------------- 0928 ; 0x0206 Execute Module,Check_Elaborated 0928 ; -------------------------------------------------------------------------------------- 0928 MACRO_Execute_Module,Check_Elaborated: 0928 0928 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0928 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 0929 0929 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 092a 0x092a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 092a 092a fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x3279 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 092b 092b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092c 092c fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092d 092d ioc_load_wdr 0 ; Flow J 0x926 seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 typ_b_adr 01 GP01 val_b_adr 01 GP01 092e ; -------------------------------------------------------------------------------------- 092e ; 0x020f Execute Module,Activate 092e ; -------------------------------------------------------------------------------------- 092e MACRO_Execute_Module,Activate: 092e 092e dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 092e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 092f 092f fiu_tivi_src c mar_0xc; Flow C cc=False 0x3279 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 0930 0930 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0931 0931 seq_br_type 7 Unconditional Call; Flow C 0x3941 seq_branch_adr 3941 0x3941 seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 0932 ; -------------------------------------------------------------------------------------- 0932 ; 0x020e Execute Module,Augment_Imports 0932 ; -------------------------------------------------------------------------------------- 0932 MACRO_Execute_Module,Augment_Imports: 0932 0932 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0932 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0933 0933 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0934 0934 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0935 0935 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x936 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 093a 0x093a typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0936 0936 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x943 fiu_load_tar 1 hold_tar fiu_offs_lit 2c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0943 0x0943 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0937 0937 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0938 0938 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0939 0939 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 093a 093a ioc_fiubs 1 val ; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1d A_AND_NOT_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 093b 093b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x940 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0940 0x0940 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 093c 093c typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093d 093d fiu_mem_start 3 start-wr; Flow J cc=True 0x949 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0949 0x0949 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 093e 093e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093f 093f fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x93c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 093c 0x093c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0940 0940 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_csa_cntl 1 START_POP_DOWN val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0941 0941 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE 0942 0942 ioc_load_wdr 0 ; Flow J 0x926 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 val_b_adr 01 GP01 0943 0943 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0944 0944 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0945 0945 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0946 0946 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0xb53 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b53 0x0b53 typ_a_adr 10 TOP 0947 0947 fiu_tivi_src c mar_0xc; Flow J 0x3309 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3309 0x3309 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_rand c WRITE_OUTER_FRAME val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0948 0948 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0949 0949 fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 094a 094a seq_br_type 3 Unconditional Branch; Flow J 0x32a7 seq_branch_adr 32a7 0x32a7 094b 094b <halt> ; Flow R 094c ; -------------------------------------------------------------------------------------- 094c ; 0x0209 Execute Task,Abort 094c ; -------------------------------------------------------------------------------------- 094c MACRO_Execute_Task,Abort: 094c 094c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094c typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU 094d 094d seq_br_type 7 Unconditional Call; Flow C 0x3a3e seq_branch_adr 3a3e 0x3a3e val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 094e ; -------------------------------------------------------------------------------------- 094e ; 0x0208 Execute Task,Abort_Multiple 094e ; -------------------------------------------------------------------------------------- 094e MACRO_Execute_Task,Abort_Multiple: 094e 094e dispatch_brk_class 8 ; Flow J 0x326c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094e seq_br_type 3 Unconditional Branch seq_branch_adr 326c 0x326c typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 094f 094f <halt> ; Flow R 0950 ; -------------------------------------------------------------------------------------- 0950 ; 0x020c Execute Module,Is_Callable 0950 ; -------------------------------------------------------------------------------------- 0950 MACRO_Execute_Module,Is_Callable: 0950 0950 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0950 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0951 0951 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x958 seq_br_type 1 Branch True seq_branch_adr 0958 0x0958 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_frame 2 0952 0952 fiu_load_tar 1 hold_tar; Flow J cc=False 0x959 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0959 0x0959 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0953 0953 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_rand 2 DEC_LOOP_COUNTER 0954 0954 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x956 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0956 0x0956 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0955 0955 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x957 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0956 0956 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0957 0957 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0958 0958 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0959 0959 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 095a 095a fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 095b 095b fiu_load_tar 1 hold_tar; Flow J 0x953 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0953 0x0953 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 095c 095c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 095d 095d ioc_tvbs 1 typ+fiu; Flow J 0x950 seq_br_type 3 Unconditional Branch seq_branch_adr 0950 MACRO_Execute_Module,Is_Callable typ_a_adr 24 TR00:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 095e ; -------------------------------------------------------------------------------------- 095e ; 0x020b Execute Module,Is_Terminated 095e ; -------------------------------------------------------------------------------------- 095e MACRO_Execute_Module,Is_Terminated: 095e 095e dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 095e fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 095f 095f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x963 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0963 0x0963 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0960 0960 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0961 0x0961 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0961 0961 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 0962 0962 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x958 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0958 0x0958 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0963 0963 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0964 0964 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x958 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0958 0x0958 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0965 0965 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x960 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0960 0x0960 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0966 ; -------------------------------------------------------------------------------------- 0966 ; 0x0205 QQUnknown InMicrocode 0966 ; -------------------------------------------------------------------------------------- 0966 MACRO_0966_QQUnknown_InMicrocode: 0966 0966 dispatch_brk_class 0 ; Flow J cc=False 0x96b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0966 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 096b 0x096b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0967 0967 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x969 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0969 0x0969 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0968 0968 fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0969 0969 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 096a 096a fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 096b 096b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x96f seq_br_type 0 Branch False seq_branch_adr 096f 0x096f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU 096c 096c seq_br_type 1 Branch True; Flow J cc=True 0x96e seq_branch_adr 096e 0x096e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame a 096d 096d seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 096e 096e fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 096f 096f fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0970 ; -------------------------------------------------------------------------------------- 0970 ; 0x020a Execute Module,Get_Name 0970 ; -------------------------------------------------------------------------------------- 0970 MACRO_Execute_Module,Get_Name: 0970 0970 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0970 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0971 0x0971 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL 0971 0971 typ_c_adr 2f TOP 0972 0972 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0973 0973 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x975 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0975 0x0975 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0974 0974 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0975 0975 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0976 0976 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0977 0977 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0978 0978 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x97a fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 097a 0x097a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0979 0979 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 097a 097a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 097b 097b seq_br_type 1 Branch True; Flow J cc=True 0x97d seq_branch_adr 097d 0x097d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 29 VR0c:09 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_frame c 097c 097c seq_br_type 7 Unconditional Call; Flow C 0x32c5 seq_branch_adr 32c5 0x32c5 seq_en_micro 0 097d 097d seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_en_micro 0 097e 097e fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 097f 097f seq_br_type 3 Unconditional Branch; Flow J 0x978 seq_branch_adr 0978 0x0978 0980 ; -------------------------------------------------------------------------------------- 0980 ; 0x02c7 Declare_Variable Any 0980 ; -------------------------------------------------------------------------------------- 0980 MACRO_Declare_Variable_Any: 0980 0980 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0980 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0981 0981 fiu_fill_mode_src 0 ; Flow J cc=True 0x3164 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3164 MACRO_Declare_Variable_Discrete seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0982 0982 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x983 ; Flow J cc=#0x0 0x983 seq_br_type b Case False seq_branch_adr 0983 0x0983 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0983 0983 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0984 0984 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0985 0985 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0986 0986 seq_br_type 3 Unconditional Branch; Flow J 0xaee seq_branch_adr 0aee MACRO_Declare_Variable_Package 0987 0987 seq_br_type 3 Unconditional Branch; Flow J 0xaf2 seq_branch_adr 0af2 MACRO_Declare_Variable_Task 0988 0988 seq_br_type 3 Unconditional Branch; Flow J 0x132a seq_branch_adr 132a MACRO_Declare_Variable_Array 0989 0989 seq_br_type 3 Unconditional Branch; Flow J 0x132a seq_branch_adr 132a MACRO_Declare_Variable_Array 098a 098a seq_br_type 3 Unconditional Branch; Flow J 0x132a seq_branch_adr 132a MACRO_Declare_Variable_Array 098b 098b seq_br_type 3 Unconditional Branch; Flow J 0x1ee4 seq_branch_adr 1ee4 MACRO_Declare_Variable_Record 098c 098c seq_br_type 3 Unconditional Branch; Flow J 0x12d4 seq_branch_adr 12d4 MACRO_Declare_Variable_Variant_Record 098d 098d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 098e 098e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 098f 098f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0990 ; -------------------------------------------------------------------------------------- 0990 ; 0x02c6 Declare_Variable Any,Visible 0990 ; -------------------------------------------------------------------------------------- 0990 MACRO_Declare_Variable_Any,Visible: 0990 0990 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0990 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0991 0991 fiu_fill_mode_src 0 ; Flow J cc=True 0x3162 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3162 MACRO_Declare_Variable_Discrete,Visible seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0992 0992 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x993 ; Flow J cc=#0x0 0x993 seq_br_type b Case False seq_branch_adr 0993 0x0993 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0993 0993 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0994 0994 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0995 0995 seq_br_type 3 Unconditional Branch; Flow J 0x30cc seq_branch_adr 30cc MACRO_Declare_Variable_Float,Visible 0996 0996 seq_br_type 3 Unconditional Branch; Flow J 0xaf8 seq_branch_adr 0af8 MACRO_Declare_Variable_Package,Visible 0997 0997 seq_br_type 3 Unconditional Branch; Flow J 0xafe seq_branch_adr 0afe MACRO_Declare_Variable_Task,Visible 0998 0998 seq_br_type 3 Unconditional Branch; Flow J 0x133c seq_branch_adr 133c MACRO_Declare_Variable_Array,Visible 0999 0999 seq_br_type 3 Unconditional Branch; Flow J 0x133c seq_branch_adr 133c MACRO_Declare_Variable_Array,Visible 099a 099a seq_br_type 3 Unconditional Branch; Flow J 0x133c seq_branch_adr 133c MACRO_Declare_Variable_Array,Visible 099b 099b seq_br_type 3 Unconditional Branch; Flow J 0x1ed6 seq_branch_adr 1ed6 MACRO_Declare_Variable_Record,Visible 099c 099c seq_br_type 3 Unconditional Branch; Flow J 0x12c8 seq_branch_adr 12c8 MACRO_Declare_Variable_Variant_Record,Visible 099d 099d seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 099e 099e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 099f 099f seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 09a0 09a0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 09a1 09a1 <halt> ; Flow R 09a2 ; -------------------------------------------------------------------------------------- 09a2 ; 0x012f Execute Any,Equal 09a2 ; -------------------------------------------------------------------------------------- 09a2 MACRO_Execute_Any,Equal: 09a2 09a2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09a2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09a3 09a3 fiu_fill_mode_src 0 ; Flow J cc=True 0x2f9c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2f9c MACRO_Execute_Discrete,Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09a4 09a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9a5 ; Flow J cc=#0x0 0x9a5 seq_br_type b Case False seq_branch_adr 09a5 0x09a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09a5 09a5 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09a6 09a6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09a7 09a7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09a8 09a8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09a9 09a9 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09aa 09aa seq_br_type 3 Unconditional Branch; Flow J 0x1b44 seq_branch_adr 1b44 MACRO_Execute_Array,Equal 09ab 09ab seq_br_type 3 Unconditional Branch; Flow J 0x181a seq_branch_adr 181a MACRO_Execute_Vector,Equal 09ac 09ac seq_br_type 3 Unconditional Branch; Flow J 0x1438 seq_branch_adr 1438 MACRO_Execute_Matrix,Equal 09ad 09ad seq_br_type 3 Unconditional Branch; Flow J 0x17f0 seq_branch_adr 17f0 MACRO_Execute_Record,Equal 09ae 09ae seq_br_type 3 Unconditional Branch; Flow J 0x1744 seq_branch_adr 1744 MACRO_Execute_Variant_Record,Equal 09af 09af fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b0 09b0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09b1 09b1 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b2 ; -------------------------------------------------------------------------------------- 09b2 ; 0x012e Execute Any,Not_Equal 09b2 ; -------------------------------------------------------------------------------------- 09b2 MACRO_Execute_Any,Not_Equal: 09b2 09b2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09b2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09b3 09b3 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fa0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fa0 MACRO_Execute_Discrete,Not_Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09b4 09b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9b5 ; Flow J cc=#0x0 0x9b5 seq_br_type b Case False seq_branch_adr 09b5 0x09b5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09b5 09b5 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09b6 09b6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09b7 09b7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b8 09b8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09b9 09b9 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 09ba 09ba seq_br_type 3 Unconditional Branch; Flow J 0x1b44 seq_branch_adr 1b44 MACRO_Execute_Array,Equal 09bb 09bb seq_br_type 3 Unconditional Branch; Flow J 0x181a seq_branch_adr 181a MACRO_Execute_Vector,Equal 09bc 09bc seq_br_type 3 Unconditional Branch; Flow J 0x1438 seq_branch_adr 1438 MACRO_Execute_Matrix,Equal 09bd 09bd seq_br_type 3 Unconditional Branch; Flow J 0x17f0 seq_branch_adr 17f0 MACRO_Execute_Record,Equal 09be 09be seq_br_type 3 Unconditional Branch; Flow J 0x1744 seq_branch_adr 1744 MACRO_Execute_Variant_Record,Equal 09bf 09bf fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09c0 09c0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09c1 09c1 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09c2 ; -------------------------------------------------------------------------------------- 09c2 ; 0x012d Execute Any,Address 09c2 ; -------------------------------------------------------------------------------------- 09c2 MACRO_Execute_Any,Address: 09c2 09c2 dispatch_brk_class 8 ; Flow J cc=False 0x9c6 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09c2 seq_br_type 0 Branch False seq_branch_adr 09c6 0x09c6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 09c3 09c3 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c7 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 09c7 0x09c7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 09c4 09c4 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c8 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 09c8 0x09c8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 09c5 09c5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09c6 09c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09c7 09c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c8 09c8 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c9 09c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 09ca ; -------------------------------------------------------------------------------------- 09ca ; 0x0116 Execute Any,Address_Of_Type 09ca ; -------------------------------------------------------------------------------------- 09ca MACRO_Execute_Any,Address_Of_Type: 09ca 09ca dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09ca ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09cb 09cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09cc ; -------------------------------------------------------------------------------------- 09cc ; 0x012c Execute Any,Size 09cc ; -------------------------------------------------------------------------------------- 09cc MACRO_Execute_Any,Size: 09cc 09cc dispatch_brk_class 8 ; Flow J cc=False 0x9d1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09cc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 09d1 0x09d1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 09cd 09cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 09ce 09ce fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09cf 0x09cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09cf 09cf fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09d0 0x09d0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL 09d0 09d0 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 seq_en_micro 0 seq_random 02 ? 09d1 09d1 ioc_fiubs 0 fiu ; Flow J cc=True 0x9f4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 09f4 0x09f4 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 09d2 09d2 fiu_load_tar 1 hold_tar; Flow J cc=False 0x9d5 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09d5 0x09d5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 09d3 09d3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09d4 0x09d4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09d4 09d4 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 seq_en_micro 0 seq_random 02 ? 09d5 09d5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 09d6 09d6 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x9e5 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 09e5 0x09e5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 09d7 09d7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9da ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09da 0x09da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 09d8 09d8 fiu_fill_mode_src 0 ; Flow C cc=False 0x9e1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09e1 0x09e1 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09d9 09d9 seq_br_type 3 Unconditional Branch; Flow J 0x9dd seq_branch_adr 09dd 0x09dd seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09da 09da fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09db 09db fiu_fill_mode_src 0 ; Flow C cc=False 0x9e1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09e1 0x09e1 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09dc 09dc seq_br_type 3 Unconditional Branch; Flow J 0x9dd seq_branch_adr 09dd 0x09dd seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09dd 09dd seq_b_timing 1 Latch Condition; Flow J cc=True 0x9e0 seq_br_type 1 Branch True seq_branch_adr 09e0 0x09e0 seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 09de 09de seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 09df 09df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 09e0 09e0 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x9ec ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 09ec 0x09ec seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B 09e1 ; -------------------------------------------------------------------------------------- 09e1 ; Comes from: 09e1 ; 09d8 C False from color MACRO_Execute_Any,Size 09e1 ; 09db C False from color MACRO_Execute_Any,Size 09e1 ; -------------------------------------------------------------------------------------- 09e1 09e1 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9e3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09e3 0x09e3 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 09e2 09e2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e3 09e3 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09e4 09e4 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e5 09e5 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 09e6 09e6 fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09e7 09e7 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x9ea seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09ea 0x09ea seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 09e8 09e8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09e9 09e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09ea 09ea fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 09eb 0x09eb seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09eb 09eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 38 VR13:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 13 09ec 09ec fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 09ed 09ed fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x9f2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09f2 0x09f2 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09ee 09ee fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9f0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09f0 0x09f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 09ef 09ef fiu_fill_mode_src 0 ; Flow J 0x9ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ec 0x09ec typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 09f0 09f0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09f1 09f1 fiu_fill_mode_src 0 ; Flow J 0x9ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ec 0x09ec typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 09f2 09f2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 09f3 09f3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f4 09f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9ce seq_br_type 1 Branch True seq_branch_adr 09ce 0x09ce seq_cond_sel 00 VAL.ALU_ZERO(late) val_b_adr 10 TOP val_rand a PASS_B_HIGH 09f5 09f5 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 09f6 09f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f7 09f7 <halt> ; Flow R 09f8 ; -------------------------------------------------------------------------------------- 09f8 ; 0x012a Execute Any,Change_Utility 09f8 ; -------------------------------------------------------------------------------------- 09f8 MACRO_Execute_Any,Change_Utility: 09f8 09f8 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09f8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09f9 09f9 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 09fa 09fa fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 09fb 09fb ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 09fc 09fc fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 09fd 09fd ioc_load_wdr 0 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 1f TOP - 1 09fe 09fe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 09ff 09ff <halt> ; Flow R 0a00 ; -------------------------------------------------------------------------------------- 0a00 ; 0x0129 Execute Any,Make_Visible 0a00 ; -------------------------------------------------------------------------------------- 0a00 MACRO_Execute_Any,Make_Visible: 0a00 0a00 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a00 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0a01 0a01 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a02 0x0a02 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a02 0a02 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a03 0x0a03 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a03 0a03 ioc_tvbs 2 fiu+val; Flow C 0x32a7 seq_br_type 7 Unconditional Call seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 0a04 ; -------------------------------------------------------------------------------------- 0a04 ; 0x0128 QQUnknown InMicrocode 0a04 ; -------------------------------------------------------------------------------------- 0a04 MACRO_0a04_QQUnknown_InMicrocode: 0a04 0a04 dispatch_brk_class 0 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a05 0x0a05 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a05 0a05 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a06 ; -------------------------------------------------------------------------------------- 0a06 ; 0x0124 Execute Any,Is_Constrained 0a06 ; -------------------------------------------------------------------------------------- 0a06 MACRO_Execute_Any,Is_Constrained: 0a06 0a06 dispatch_brk_class 8 ; Flow J cc=True 0xa09 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a06 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0a09 0x0a09 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame b 0a07 0a07 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0a08 0x0a08 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0a08 0a08 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a09 0a09 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a0a 0x0a0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a0a 0a0a seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a0b 0a0b <halt> ; Flow R 0a0c ; -------------------------------------------------------------------------------------- 0a0c ; 0x0112 Execute Any,Make_Constrained 0a0c ; -------------------------------------------------------------------------------------- 0a0c MACRO_Execute_Any,Make_Constrained: 0a0c 0a0c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0a0d 0x0a0d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL 0a0d 0a0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0a0e ; -------------------------------------------------------------------------------------- 0a0e ; 0x0123 Execute Any,Make_Aligned 0a0e ; -------------------------------------------------------------------------------------- 0a0e MACRO_Execute_Any,Make_Aligned: 0a0e 0a0e dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0a0f 0a0f ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS 0a10 0a10 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x32a7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a11 0a11 ioc_load_wdr 0 ; Flow J cc=False 0x9c9 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 09c9 0x09c9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 0a12 0a12 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a13 0a13 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 0a14 0a14 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 0a15 0a15 <halt> ; Flow R 0a16 ; -------------------------------------------------------------------------------------- 0a16 ; 0x0122 Execute Any,Make_Root_Type 0a16 ; -------------------------------------------------------------------------------------- 0a16 MACRO_Execute_Any,Make_Root_Type: 0a16 0a16 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a16 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR09:00 val_frame 9 0a17 0a17 seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 39 VR02:19 val_frame 2 0a18 0a18 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x3279 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a19 0a19 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0a1a 0x0a1a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS 0a1a 0a1a fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0xa1c ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0a1c 0x0a1c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0a1b 0a1b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a1c 0a1c <default> 0a1d 0a1d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 0a1e 0a1e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 0a1f 0a1f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a20 ; -------------------------------------------------------------------------------------- 0a20 ; 0x0121 Execute Any,Is_Default 0a20 ; -------------------------------------------------------------------------------------- 0a20 MACRO_Execute_Any,Is_Default: 0a20 0a20 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a20 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a21 0x0a21 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0a21 0a21 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xa1f ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 0a1f 0x0a1f seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a22 ; -------------------------------------------------------------------------------------- 0a22 ; 0x0120 Execute Any,Is_Value 0a22 ; -------------------------------------------------------------------------------------- 0a22 MACRO_Execute_Any,Is_Value: 0a22 0a22 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a22 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a23 0a23 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a24 ; -------------------------------------------------------------------------------------- 0a24 ; 0x011f Execute Any,Is_Scalar 0a24 ; -------------------------------------------------------------------------------------- 0a24 MACRO_Execute_Any,Is_Scalar: 0a24 0a24 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a24 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a25 0a25 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 34 VR05:14 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0a26 ; -------------------------------------------------------------------------------------- 0a26 ; 0x011e Execute Any,Convert 0a26 ; -------------------------------------------------------------------------------------- 0a26 MACRO_Execute_Any,Convert: 0a26 0a26 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a26 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a27 0a27 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fee fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fee MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a28 0a28 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa29 ; Flow J cc=#0x0 0xa29 seq_br_type b Case False seq_branch_adr 0a29 0x0a29 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a29 0a29 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a2a 0a2a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a2b 0a2b seq_br_type 3 Unconditional Branch; Flow J 0x28d0 seq_branch_adr 28d0 MACRO_Execute_Float,Convert 0a2c 0a2c seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a2d 0a2d seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a2e 0a2e seq_br_type 3 Unconditional Branch; Flow J 0x1bd6 seq_branch_adr 1bd6 MACRO_Execute_Array,Convert 0a2f 0a2f seq_br_type 3 Unconditional Branch; Flow J 0x1a58 seq_branch_adr 1a58 MACRO_Execute_Vector,Convert 0a30 0a30 seq_br_type 3 Unconditional Branch; Flow J 0x1552 seq_branch_adr 1552 MACRO_Execute_Matrix,Convert 0a31 0a31 seq_br_type 3 Unconditional Branch; Flow J 0x1804 seq_branch_adr 1804 MACRO_Execute_Record,Convert 0a32 0a32 seq_br_type 3 Unconditional Branch; Flow J 0x179e seq_branch_adr 179e MACRO_Execute_Variant_Record,Convert 0a33 0a33 seq_br_type 0 Branch False; Flow J cc=False 0x1af3 seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a34 0a34 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b0b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b0b 0x1b0b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a35 0a35 seq_br_type 0 Branch False; Flow J cc=False 0xc33 seq_branch_adr 0c33 0x0c33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a36 0a36 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a37 0a37 <halt> ; Flow R 0a38 ; -------------------------------------------------------------------------------------- 0a38 ; 0x011d Execute Any,Convert_To_Formal 0a38 ; -------------------------------------------------------------------------------------- 0a38 MACRO_Execute_Any,Convert_To_Formal: 0a38 0a38 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a38 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a39 0a39 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fee fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fee MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a3a 0a3a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa3b ; Flow J cc=#0x0 0xa3b seq_br_type b Case False seq_branch_adr 0a3b 0x0a3b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a3b 0a3b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a3c 0a3c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a3d 0a3d seq_br_type 3 Unconditional Branch; Flow J 0x28d0 seq_branch_adr 28d0 MACRO_Execute_Float,Convert 0a3e 0a3e seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a3f 0a3f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a40 0a40 seq_br_type 3 Unconditional Branch; Flow J 0x1c3c seq_branch_adr 1c3c MACRO_Execute_Array,Convert_To_Formal 0a41 0a41 seq_br_type 3 Unconditional Branch; Flow J 0x1a98 seq_branch_adr 1a98 MACRO_Execute_Vector,Convert_To_Formal 0a42 0a42 seq_br_type 3 Unconditional Branch; Flow J 0x15c8 seq_branch_adr 15c8 MACRO_Execute_Matrix,Convert_To_Formal 0a43 0a43 seq_br_type 3 Unconditional Branch; Flow J 0x1804 seq_branch_adr 1804 MACRO_Execute_Record,Convert 0a44 0a44 seq_br_type 3 Unconditional Branch; Flow J 0x179e seq_branch_adr 179e MACRO_Execute_Variant_Record,Convert 0a45 0a45 seq_br_type 0 Branch False; Flow J cc=False 0x1af3 seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a46 0a46 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b0b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b0b 0x1b0b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a47 0a47 seq_br_type 0 Branch False; Flow J cc=False 0xc33 seq_branch_adr 0c33 0x0c33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a48 0a48 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a49 0a49 <halt> ; Flow R 0a4a ; -------------------------------------------------------------------------------------- 0a4a ; 0x011c Execute Any,Convert_Unchecked 0a4a ; -------------------------------------------------------------------------------------- 0a4a MACRO_Execute_Any,Convert_Unchecked: 0a4a 0a4a dispatch_brk_class 4 ; Flow C cc=False 0xa4f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0a4a fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0a4f 0x0a4f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a4b 0a4b fiu_load_tar 1 hold_tar; Flow J cc=True 0xa4d fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0a4d 0x0a4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 3 0a4c 0a4c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a4d 0x0a4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 11 TOP + 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 0a4d 0a4d ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 0a4e 0a4e seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 0a4f 0a4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0xa52 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0a52 0x0a52 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0a50 0a50 fiu_tivi_src 4 fiu_var; Flow J cc=True 0xa51 ; Flow J cc=#0x0 0xa63 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0a63 0x0a63 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 7 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a51 0a51 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a52 ; -------------------------------------------------------------------------------------- 0a52 ; Comes from: 0a52 ; 0a4f C #0x0 from color MACRO_Execute_Any,Convert_Unchecked 0a52 ; -------------------------------------------------------------------------------------- 0a52 0a52 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a53 0a53 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5a 0x0a5a typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a54 0a54 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a55 0a55 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a56 0a56 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a57 0a57 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5c fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5c 0x0a5c typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a58 0a58 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5d fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5d 0x0a5d typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a59 0a59 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5e fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5e 0x0a5e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5a 0a5a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0a5b 0a5b fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=True ; Flow J cc=False 0xa6f fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0a6f 0x0a6f seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5c 0a5c fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0a5d 0a5d fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 34 VR07:14 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 0a5e 0a5e fiu_mem_start 2 start-rd; Flow C cc=True 0x32a7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5f 0a5f fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a60 0a60 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0a61 0a61 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 06 Pop_stack+? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 0a62 0a62 seq_b_timing 0 Early Condition; Flow J cc=True 0xa63 ; Flow J cc=#0x0 0xa63 seq_br_type b Case False seq_branch_adr 0a63 0x0a63 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0a63 0a63 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa6d seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a6d 0x0a6d seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a64 0a64 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa6b seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a6b 0x0a6b seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a65 0a65 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a66 0a66 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a67 0a67 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a68 0a68 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a69 0a69 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a6a 0a6a seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a6b 0a6b fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xa6d ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a6d 0x0a6d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 0a6c 0a6c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32ab seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a6d 0a6d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 0a6e 0x0a6e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 28 TR09:08 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0a6e 0a6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0a6f 0a6f seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 0a70 ; -------------------------------------------------------------------------------------- 0a70 ; 0x011b Execute Any,In_Type 0a70 ; -------------------------------------------------------------------------------------- 0a70 MACRO_Execute_Any,In_Type: 0a70 0a70 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a70 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a71 0a71 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fea fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fea MACRO_Execute_Discrete,In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a72 0a72 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa73 ; Flow J cc=#0x0 0xa73 seq_br_type b Case False seq_branch_adr 0a73 0x0a73 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a73 0a73 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a74 0a74 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a75 0a75 seq_br_type 3 Unconditional Branch; Flow J 0x28f4 seq_branch_adr 28f4 MACRO_Execute_Float,In_Type 0a76 0a76 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a77 0a77 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a78 0a78 seq_br_type 3 Unconditional Branch; Flow J 0x1ba6 seq_branch_adr 1ba6 MACRO_Execute_Array,In_Type 0a79 0a79 seq_br_type 3 Unconditional Branch; Flow J 0x1aa0 seq_branch_adr 1aa0 MACRO_Execute_Vector,In_Type 0a7a 0a7a seq_br_type 3 Unconditional Branch; Flow J 0x14b0 seq_branch_adr 14b0 MACRO_Execute_Matrix,In_Type 0a7b 0a7b fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7c 0a7c seq_br_type 3 Unconditional Branch; Flow J 0x17b0 seq_branch_adr 17b0 MACRO_Execute_Variant_Record,In_Type 0a7d 0a7d fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1afd fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1afd 0x1afd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7e 0a7e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a7f 0a7f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc3d fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3d 0x0c3d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a80 0a80 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a81 0a81 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a82 0a82 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a83 0a83 <halt> ; Flow R 0a84 ; -------------------------------------------------------------------------------------- 0a84 ; 0x011a Execute Any,Not_In_Type 0a84 ; -------------------------------------------------------------------------------------- 0a84 MACRO_Execute_Any,Not_In_Type: 0a84 0a84 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a84 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a85 0a85 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fec MACRO_Execute_Discrete,Not_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a86 0a86 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa87 ; Flow J cc=#0x0 0xa87 seq_br_type b Case False seq_branch_adr 0a87 0x0a87 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a87 0a87 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a88 0a88 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a89 0a89 seq_br_type 3 Unconditional Branch; Flow J 0x28f6 seq_branch_adr 28f6 MACRO_Execute_Float,Not_In_Type 0a8a 0a8a fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8b 0a8b fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8c 0a8c seq_br_type 3 Unconditional Branch; Flow J 0x1bb4 seq_branch_adr 1bb4 MACRO_Execute_Array,Not_In_Type 0a8d 0a8d seq_br_type 3 Unconditional Branch; Flow J 0x1aae seq_branch_adr 1aae MACRO_Execute_Vector,Not_In_Type 0a8e 0a8e seq_br_type 3 Unconditional Branch; Flow J 0x14b4 seq_branch_adr 14b4 MACRO_Execute_Matrix,Not_In_Type 0a8f 0a8f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a90 0a90 seq_br_type 3 Unconditional Branch; Flow J 0x17b4 seq_branch_adr 17b4 MACRO_Execute_Variant_Record,Not_In_Type 0a91 0a91 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1b03 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b03 0x1b03 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a92 0a92 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a93 0a93 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc43 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c43 0x0c43 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a94 0a94 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a95 0a95 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a96 0a96 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a97 0a97 <halt> ; Flow R 0a98 ; -------------------------------------------------------------------------------------- 0a98 ; 0x0119 Execute Any,Check_In_Formal_Type 0a98 ; -------------------------------------------------------------------------------------- 0a98 MACRO_Execute_Any,Check_In_Formal_Type: 0a98 0a98 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a98 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a99 0a99 fiu_fill_mode_src 0 ; Flow J cc=True 0x2ffa fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2ffa MACRO_Execute_Discrete,Check_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a9a 0a9a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa9b ; Flow J cc=#0x0 0xa9b seq_br_type b Case False seq_branch_adr 0a9b 0x0a9b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a9b 0a9b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0a9c 0a9c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a9d 0a9d seq_br_type 3 Unconditional Branch; Flow J 0x28fa seq_branch_adr 28fa MACRO_Execute_Float,Check_In_Type 0a9e 0a9e fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0a9f 0a9f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa0 0aa0 seq_br_type 3 Unconditional Branch; Flow J 0x1bc2 seq_branch_adr 1bc2 MACRO_Execute_Array,Check_In_Type 0aa1 0aa1 seq_br_type 3 Unconditional Branch; Flow J 0x1ab6 seq_branch_adr 1ab6 MACRO_Execute_Vector,Check_In_Type 0aa2 0aa2 seq_br_type 3 Unconditional Branch; Flow J 0x14b8 seq_branch_adr 14b8 MACRO_Execute_Matrix,Check_In_Type 0aa3 0aa3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa4 0aa4 seq_br_type 3 Unconditional Branch; Flow J 0x17be seq_branch_adr 17be MACRO_Execute_Variant_Record,Check_In_Formal_Type 0aa5 0aa5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b09 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa6 0aa6 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0aa7 0aa7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc49 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa8 0aa8 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aa9 0aa9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0aaa ; -------------------------------------------------------------------------------------- 0aaa ; 0x0118 Execute Any,Write_Unchecked 0aaa ; -------------------------------------------------------------------------------------- 0aaa MACRO_Execute_Any,Write_Unchecked: 0aaa 0aaa dispatch_brk_class 2 ; Flow J cc=False 0x1d48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0aaa fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0aab 0aab fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aac 0aac seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xaaf seq_br_type 0 Branch False seq_branch_adr 0aaf 0x0aaf seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 1f TOP - 1 typ_frame 4 0aad 0aad fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE 0aae 0aae seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0aaf 0aaf fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR05:01 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0ab0 0ab0 fiu_fill_mode_src 0 ; Flow J cc=False 0xab2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ab2 0x0ab2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 0ab1 0ab1 fiu_fill_mode_src 0 ; Flow J 0xab5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ab5 0x0ab5 typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 0ab2 0ab2 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ab3 0ab3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ab4 0ab4 fiu_load_var 1 hold_var; Flow J 0xab5 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ab5 0x0ab5 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ab5 0ab5 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ab6 0ab6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0ab7 0ab7 <halt> ; Flow R 0ab8 ; -------------------------------------------------------------------------------------- 0ab8 ; 0x0117 Execute Any,Structure_Query 0ab8 ; -------------------------------------------------------------------------------------- 0ab8 MACRO_Execute_Any,Structure_Query: 0ab8 0ab8 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ab8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ab9 0ab9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0xabb fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0abb 0x0abb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl 6 INCREMENT_MAR 0aba 0aba seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 0abb ; -------------------------------------------------------------------------------------- 0abb ; Comes from: 0abb ; 0ab9 C #0x0 from color MACRO_Execute_Any,Structure_Query 0abb ; -------------------------------------------------------------------------------------- 0abb 0abb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abc 0abc fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abd 0abd fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abe 0abe fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0abf 0abf seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_rand b CARRY IN = Q BIT FROM VAL 0ac0 0ac0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 0ac1 0ac1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac2 0ac2 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0ac3 0ac3 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0xacd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acd 0x0acd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac4 0ac4 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xace seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0ace 0x0ace seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0ac5 0ac5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac6 0ac6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3279 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0ac7 0ac7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac8 0ac8 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xacb ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac9 0ac9 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xacb ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aca 0aca fiu_mem_start 4 continue; Flow R cc=True ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0acb 0acb typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0acc 0acc fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0acd 0acd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR05:09 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0ace 0ace fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0acf 0acf fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ad0 0ad0 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0xadf fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0adf 0x0adf seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR05:04 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0ad1 0ad1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0ad2 0ad2 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xad7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ad7 0x0ad7 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ad3 0ad3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad4 0ad4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad5 0ad5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad6 0ad6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR05:0a val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0ad7 0ad7 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0xad3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ad3 0x0ad3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0ad8 0ad8 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ad9 0ad9 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xad3 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ad3 0x0ad3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0ada 0ada typ_rand e CHECK_CLASS_SYSTEM_B val_rand 2 DEC_LOOP_COUNTER 0adb 0adb fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2a84 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0adc 0adc seq_br_type 1 Branch True; Flow J cc=True 0xad9 seq_branch_adr 0ad9 0x0ad9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 0add 0add fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ade 0ade ioc_tvbs 1 typ+fiu; Flow J 0xad5 seq_br_type 3 Unconditional Branch seq_branch_adr 0ad5 0x0ad5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0adf ; -------------------------------------------------------------------------------------- 0adf ; Comes from: 0adf ; 0ad0 C True from color 0x0ac4 0adf ; -------------------------------------------------------------------------------------- 0adf 0adf ioc_tvbs 3 fiu+fiu; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ae0 0ae0 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 0ae1 0ae1 <halt> ; Flow R 0ae2 ; -------------------------------------------------------------------------------------- 0ae2 ; 0x0126 Execute Any,Has_Default_Initialization 0ae2 ; -------------------------------------------------------------------------------------- 0ae2 MACRO_Execute_Any,Has_Default_Initialization: 0ae2 0ae2 dispatch_brk_class 8 ; Flow J cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae3 0ae3 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d 0ae4 0ae4 fiu_fill_mode_src 0 ; Flow J cc=False 0x32a7 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 0ae5 0ae5 ioc_load_wdr 0 ; Flow J 0x9c9 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 09c9 0x09c9 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 ; 0x0111 Execute Any,Has_Repeated_Initialization 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 MACRO_Execute_Any,Has_Repeated_Initialization: 0ae6 0ae6 dispatch_brk_class 8 ; Flow J cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae7 0ae7 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xae4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d seq_br_type 3 Unconditional Branch seq_branch_adr 0ae4 0x0ae4 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 ; 0x0110 Execute Any,Is_Initialization_Repeated 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 MACRO_Execute_Any,Is_Initialization_Repeated: 0ae8 0ae8 dispatch_brk_class 8 ; Flow J cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ae9 0ae9 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True ; Flow J cc=False 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aea ; -------------------------------------------------------------------------------------- 0aea ; 0x012b Execute Any,Spare14 0aea ; -------------------------------------------------------------------------------------- 0aea MACRO_Execute_Any,Spare14: 0aea 0aea dispatch_brk_class 8 ; Flow J cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0aea fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aeb 0aeb fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x32a7 fiu_offs_lit 3b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aec 0aec fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0aed 0aed <halt> ; Flow R 0aee ; -------------------------------------------------------------------------------------- 0aee ; 0x0387 Declare_Variable Package 0aee ; -------------------------------------------------------------------------------------- 0aee MACRO_Declare_Variable_Package: 0aee 0aee dispatch_brk_class 4 ; Flow J 0xaef dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0aee fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0aef 0aef fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af0 0af0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3279 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af1 0af1 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 0af2 ; -------------------------------------------------------------------------------------- 0af2 ; 0x036f Declare_Variable Task 0af2 ; -------------------------------------------------------------------------------------- 0af2 MACRO_Declare_Variable_Task: 0af2 0af2 dispatch_brk_class 4 ; Flow J 0xaf3 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af3 0af3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af4 0af4 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af5 0af5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0af6 0af6 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0af7 0af7 <halt> ; Flow R 0af8 ; -------------------------------------------------------------------------------------- 0af8 ; 0x0386 Declare_Variable Package,Visible 0af8 ; -------------------------------------------------------------------------------------- 0af8 MACRO_Declare_Variable_Package,Visible: 0af8 0af8 dispatch_brk_class 4 ; Flow J 0xaf9 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af9 0af9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR18:00 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0afa 0afa ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3279 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0afb 0afb fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0afc 0afc seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 0afd 0afd <halt> ; Flow R 0afe ; -------------------------------------------------------------------------------------- 0afe ; 0x036e Declare_Variable Task,Visible 0afe ; -------------------------------------------------------------------------------------- 0afe MACRO_Declare_Variable_Task,Visible: 0afe 0afe dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0afe fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0aff 0aff fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb00 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b00 0b00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x32aa fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0b01 0b01 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 0b02 0b02 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0b03 0b03 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b04 ; -------------------------------------------------------------------------------------- 0b04 ; 0x036d Declare_Variable Task,On_Processor 0b04 ; -------------------------------------------------------------------------------------- 0b04 MACRO_Declare_Variable_Task,On_Processor: 0b04 0b04 dispatch_brk_class 4 ; Flow C cc=True 0x326e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b04 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b05 0b05 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b06 0b06 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b07 0b07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb08 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b08 0b08 fiu_load_var 1 hold_var; Flow J 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0b5f 0x0b5f typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b09 0b09 <halt> ; Flow R 0b0a ; -------------------------------------------------------------------------------------- 0b0a ; 0x036c Declare_Variable Task,Visible,On_Processor 0b0a ; -------------------------------------------------------------------------------------- 0b0a MACRO_Declare_Variable_Task,Visible,On_Processor: 0b0a 0b0a dispatch_brk_class 4 ; Flow C cc=True 0x326e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b0a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b0b 0b0b fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b0c 0b0c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b0d 0b0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb0e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b0e 0b0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b0f 0b0f seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa typ_csa_cntl 3 POP_CSA 0b10 ; -------------------------------------------------------------------------------------- 0b10 ; 0x036b Declare_Variable Task,As_Component 0b10 ; -------------------------------------------------------------------------------------- 0b10 MACRO_Declare_Variable_Task,As_Component: 0b10 0b10 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b10 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0b11 0b11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb12 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b12 0b12 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b13 0b13 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x32ab fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame c 0b14 0b14 fiu_load_var 1 hold_var; Flow C 0xb1f fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b1f 0x0b1f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b15 0b15 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 08 GP08 val_alu_func 1a PASS_B 0b16 0b16 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 0b17 0b17 <halt> ; Flow R 0b18 ; -------------------------------------------------------------------------------------- 0b18 ; 0x036a Declare_Variable Task,On_Processor,As_Component 0b18 ; -------------------------------------------------------------------------------------- 0b18 MACRO_Declare_Variable_Task,On_Processor,As_Component: 0b18 0b18 dispatch_brk_class 4 ; Flow C cc=True 0x326e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b18 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b19 0b19 ioc_fiubs 1 val ; Flow J cc=True 0x32ab ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame c 0b1a 0b1a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b1b 0b1b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb1c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b1c 0b1c fiu_load_var 1 hold_var; Flow C 0xb1f fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 0b1f 0x0b1f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b1d 0b1d fiu_load_var 1 hold_var; Flow J cc=True 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 1a PASS_B 0b1e 0b1e seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 0b1f 0b1f fiu_mem_start a start_continue_if_false; Flow J cc=False 0xb21 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0b21 0x0b21 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b20 0b20 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b21 0b21 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0b22 0b22 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b23 0b23 <halt> ; Flow R 0b24 ; -------------------------------------------------------------------------------------- 0b24 ; 0x0385 Declare_Variable Package,On_Processor 0b24 ; -------------------------------------------------------------------------------------- 0b24 MACRO_Declare_Variable_Package,On_Processor: 0b24 0b24 dispatch_brk_class 4 ; Flow C cc=True 0x326e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b24 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b25 0b25 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b26 0b26 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb27 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b27 0b27 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b28 0b28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b29 0b29 seq_br_type 3 Unconditional Branch; Flow J 0x3279 seq_branch_adr 3279 0x3279 0b2a ; -------------------------------------------------------------------------------------- 0b2a ; 0x0384 Declare_Variable Package,Visible,On_Processor 0b2a ; -------------------------------------------------------------------------------------- 0b2a MACRO_Declare_Variable_Package,Visible,On_Processor: 0b2a 0b2a dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b2a seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0b2b 0b2b fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x326e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b2c 0b2c ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b2d 0b2d fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb2e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b2e 0b2e fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b2f 0b2f fiu_load_var 1 hold_var; Flow J cc=True 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b30 0b30 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 0b31 0b31 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 10 TOP 0b32 0b32 ioc_adrbs 1 val ; Flow C 0xb6b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b6b 0x0b6b typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b33 0b33 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0b34 0b34 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b35 0b35 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 0b36 0b36 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0xb37 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 0b37 0b37 ioc_adrbs 1 val ; Flow R cc=False ; Flow J cc=True 0xb4b ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0b4b 0x0b4b typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0b38 0b38 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_frame 2 0b39 0b39 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b3a 0b3a fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b3b 0b3b fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0b3c 0b3c fiu_mem_start 4 continue; Flow C cc=False 0x326e ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0b3d 0b3d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0b3e 0b3e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 25 VR11:05 val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 11 0b3f 0b3f ioc_load_wdr 0 ; Flow C cc=True 0x32a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1d val_b_adr 16 CSA/VAL_BUS 0b40 0b40 ioc_fiubs 0 fiu ; Flow C cc=True 0xb4a seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b4a 0x0b4a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 10 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 0b41 0b41 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 0b42 0b42 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b43 0b43 fiu_load_var 1 hold_var; Flow C 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b5f 0x0b5f typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_a_adr 02 GP02 val_c_adr 2e TOP + 1 0b44 0b44 fiu_tivi_src c mar_0xc; Flow J cc=True 0xb48 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b48 0x0b48 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 16 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b45 0b45 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 0b46 0b46 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 16 CSA/VAL_BUS typ_frame 1b val_a_adr 24 VR11:04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 11 0b47 0b47 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0b48 0b48 seq_br_type 1 Branch True; Flow J cc=True 0x38e6 seq_branch_adr 38e6 0x38e6 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 0b49 0b49 seq_br_type 3 Unconditional Branch; Flow J 0x38e6 seq_branch_adr 38e6 0x38e6 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 0b4a 0b4a seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 16 0b4b 0b4b fiu_tivi_src c mar_0xc; Flow C 0x3301 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3301 0x3301 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4c 0b4c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x38e6 seq_br_type 0 Branch False seq_branch_adr 38e6 0x38e6 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b4d 0b4d fiu_mem_start 2 start-rd; Flow J 0xb51 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b51 0x0b51 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b4e 0b4e fiu_tivi_src c mar_0xc; Flow C 0x3300 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3300 0x3300 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4f 0b4f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x38e6 seq_br_type 0 Branch False seq_branch_adr 38e6 0x38e6 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b50 0b50 fiu_mem_start 2 start-rd; Flow J 0xb51 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b51 0x0b51 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b51 0b51 seq_br_type 2 Push (branch address); Flow J 0xb52 seq_branch_adr 0b49 0x0b49 0b52 0b52 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x38e6 seq_br_type 9 Return False seq_branch_adr 38e6 0x38e6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 0b53 ; -------------------------------------------------------------------------------------- 0b53 ; Comes from: 0b53 ; 0903 C from color 0x0903 0b53 ; -------------------------------------------------------------------------------------- 0b53 0b53 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b54 0b54 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb5b fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b5b 0x0b5b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b55 0b55 ioc_fiubs 1 val ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b56 0b56 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b57 0b57 fiu_tivi_src c mar_0xc; Flow C 0xb7d ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7d 0x0b7d seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b58 0b58 fiu_load_var 1 hold_var; Flow J cc=True 0xb56 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b56 0x0b56 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b59 0b59 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5c fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b5c 0x0b5c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl a LOAD_MAR_IMPORT 0b5a 0b5a seq_br_type 3 Unconditional Branch; Flow J 0xb53 seq_branch_adr 0b53 0x0b53 seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b5b 0b5b fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x32a3 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b5c 0b5c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b5d 0b5d fiu_load_var 1 hold_var; Flow C 0xb78 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b78 0x0b78 seq_en_micro 0 0b5e 0b5e ioc_adrbs 1 val ; Flow J 0x3419 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3419 0x3419 seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b5f 0b5f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b60 0b60 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb67 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b67 0x0b67 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b61 0b61 ioc_fiubs 1 val ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b62 0b62 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b63 0b63 fiu_tivi_src c mar_0xc; Flow C 0xb7d ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7d 0x0b7d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b64 0b64 fiu_load_var 1 hold_var; Flow J cc=True 0xb62 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b62 0x0b62 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b65 0b65 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb68 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b68 0x0b68 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0b66 0b66 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b67 0b67 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x32a3 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a3 0x32a3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b68 0b68 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b69 0b69 fiu_load_var 1 hold_var; Flow C 0xb78 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b78 0x0b78 seq_en_micro 0 0b6a 0b6a ioc_adrbs 1 val ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b6b 0b6b fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b6c 0b6c fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b6d 0b6d ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0b6e 0b6e ioc_adrbs 1 val ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 0 PASS_A 0b6f 0b6f seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a3 seq_br_type 9 Return False seq_branch_adr 32a3 0x32a3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0b70 0b70 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0b71 0b71 fiu_len_fill_lit 55 zero-fill 0x15; Flow C cc=False 0x32c5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 19 X_XOR_B val_b_adr 10 TOP 0b72 0b72 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b73 0b73 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR08:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 8 0b74 ; -------------------------------------------------------------------------------------- 0b74 ; Comes from: 0b74 ; 0b53 C from color 0x0000 0b74 ; 0b5f C from color 0x0000 0b74 ; 0b6c C from color 0x0000 0b74 ; -------------------------------------------------------------------------------------- 0b74 0b74 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM 0b75 0b75 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0b76 0b76 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 35 VR09:15 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 0b77 0b77 fiu_len_fill_lit 55 zero-fill 0x15; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0f GP0f 0b78 ; -------------------------------------------------------------------------------------- 0b78 ; Comes from: 0b78 ; 0b5d C from color 0x0000 0b78 ; 0b69 C from color 0x0000 0b78 ; -------------------------------------------------------------------------------------- 0b78 0b78 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0b79 0b79 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 0b7a 0b7a fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b7b 0b7b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0b7c 0b7c fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0e GP0e 0b7d ; -------------------------------------------------------------------------------------- 0b7d ; Comes from: 0b7d ; 0b57 C from color 0x0000 0b7d ; 0b63 C from color 0x0000 0b7d ; -------------------------------------------------------------------------------------- 0b7d 0b7d seq_br_type 7 Unconditional Call; Flow C 0xb85 seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b7e 0b7e fiu_tivi_src c mar_0xc; Flow J cc=True 0xb82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b82 0x0b82 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 5 0b7f 0b7f fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b80 0b80 fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b81 0b81 fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0b82 0b82 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 0b83 0x0b83 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_a_adr 0b GP0b val_alu_func 19 X_XOR_B val_b_adr 0c GP0c 0b83 0b83 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0b84 0x0b84 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 6 A_MINUS_B typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 0b GP0b 0b84 0b84 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0b85 ; -------------------------------------------------------------------------------------- 0b85 ; Comes from: 0b85 ; 0b7d C from color 0x0b7d 0b85 ; 0b7f C from color 0x0b7d 0b85 ; 0b80 C from color 0x0b7d 0b85 ; 0b81 C from color 0x0b7d 0b85 ; -------------------------------------------------------------------------------------- 0b85 0b85 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 0b86 0b86 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0b87 0b87 seq_b_timing 0 Early Condition; Flow J cc=True 0xb8b seq_br_type 1 Branch True seq_branch_adr 0b8b 0x0b8b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b88 0b88 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b89 0b89 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 12 start_lru_query fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 val_rand 2 DEC_LOOP_COUNTER 0b8a 0b8a seq_b_timing 0 Early Condition; Flow J cc=False 0xb88 seq_br_type 0 Branch False seq_branch_adr 0b88 0x0b88 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b8b 0b8b fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b8c 0b8c fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0b8d 0b8d fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 0b8e 0b8e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b8f 0b8f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0c GP0c 0b90 0b90 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 0f GP0f typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0f GP0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b91 0b91 <halt> ; Flow R 0b92 ; -------------------------------------------------------------------------------------- 0b92 ; Comes from: 0b92 ; 0879 C from color 0x0821 0b92 ; -------------------------------------------------------------------------------------- 0b92 0b92 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2d TR1d:0d typ_frame 1d val_c_adr 04 VR0d:1b val_c_source 0 FIU_BUS val_frame d 0b93 0b93 fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 09 TR0d:16 typ_c_mux_sel 0 ALU typ_frame d 0b94 0b94 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 34 VR02:14 val_frame 2 0b95 0b95 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xba4 seq_br_type 1 Branch True seq_branch_adr 0ba4 0x0ba4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0b96 0b96 ioc_fiubs 1 val ; Flow C 0x2a84 seq_br_type 7 Unconditional Call seq_branch_adr 2a84 0x2a84 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 3b VR0d:1b val_frame d 0b97 0b97 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b98 0b98 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 26 TR05:06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0b99 0b99 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b9a 0b9a fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_c_adr 02 TR0d:1d typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b9b 0b9b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 0a TR0d:15 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 01 GP01 val_b_adr 01 GP01 0b9c 0b9c fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xba3 fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ba3 0x0ba3 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b9d 0b9d fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 12 TR1d:0d typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_frame 5 0b9e 0b9e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR08:1a val_frame 8 0b9f 0b9f fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d 0ba0 0ba0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 0ba1 0ba1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 0a VR0d:15 val_c_source 0 FIU_BUS val_frame d 0ba2 0ba2 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 35 VR0d:15 val_alu_func 1c DEC_A val_c_adr 0a VR0d:15 val_c_mux_sel 2 ALU val_frame d 0ba3 0ba3 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0xbaa seq_br_type 8 Return True seq_branch_adr 0baa 0x0baa seq_en_micro 0 val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 0ba4 0ba4 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 12 TR1d:0d typ_c_source 0 FIU_BUS typ_frame 1d val_a_adr 3b VR0d:1b val_frame d 0ba5 0ba5 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 3e VR05:1e val_frame 5 0ba6 0ba6 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ba7 0ba7 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl 6 INCREMENT_MAR 0ba8 0ba8 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 3d TR0d:1d typ_frame d val_b_adr 39 VR02:19 val_frame 2 0ba9 0ba9 fiu_tivi_src 8 type_var; Flow C 0x2a84 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a84 0x2a84 seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d typ_mar_cntl 5 RESTORE_MAR_REFRESH 0baa 0baa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0bab ; -------------------------------------------------------------------------------------- 0bab ; Comes from: 0bab ; 013a C from color 0x0000 0bab ; 361d C True from color 0x0000 0bab ; -------------------------------------------------------------------------------------- 0bab 0bab fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xbad fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bad 0x0bad seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 14 ZEROS typ_c_adr 0d TR0d:12 typ_frame d val_a_adr 24 VR09:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 9 0bac 0bac fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR12:10 typ_frame 12 0bad 0bad fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 38 TR0d:18 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0bae 0bae fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xbaf ; Flow J cc=#0x0 0xbb2 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0bb2 0x0bb2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 34 TR0d:14 typ_c_adr 0f TR0d:10 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 0f VR0d:10 val_c_mux_sel 2 ALU val_frame d 0baf 0baf ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 0a TR0d:15 typ_c_mux_sel 0 ALU typ_frame d val_b_adr 0f GP0f val_c_adr 0d VR0d:12 val_frame d 0bb0 0bb0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xbb6 seq_br_type 0 Branch False seq_branch_adr 0bb6 0x0bb6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d 0bb1 0bb1 fiu_len_fill_lit 4a zero-fill 0xa; Flow J 0xbd4 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bd4 0x0bd4 seq_en_micro 0 typ_c_adr 04 TR0d:1b typ_c_source 0 FIU_BUS typ_frame d 0bb2 0bb2 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb3 0bb3 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb4 0bb4 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bb5 0bb5 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bb6 0bb6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbd2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bb7 0bb7 fiu_tivi_src 1 tar_val; Flow J cc=False 0xbbe ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0bbe 0x0bbe seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bb8 0bb8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bb9 0bb9 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xbd2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bba 0bba fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc5 0x0bc5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d 0bbb 0bbb fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xbbf fiu_mem_start 3 start-wr fiu_offs_lit 40 seq_br_type 1 Branch True seq_branch_adr 0bbf 0x0bbf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR0d:13 typ_alu_func 1c DEC_A typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 33 VR0d:13 val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbc 0bbc fiu_mem_start 8 start_wr_if_false; Flow J 0xbbd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbd 0x0bbd seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbd 0bbd ioc_load_wdr 0 ; Flow J 0xbd2 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd2 0x0bd2 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bbe 0bbe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbf 0bbf fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xbd2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bc0 0bc0 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc5 0x0bc5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame d 0bc1 0bc1 fiu_mem_start 3 start-wr; Flow J cc=True 0xbc3 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0bc3 0x0bc3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bc2 0bc2 fiu_mem_start 8 start_wr_if_false; Flow J 0xbbd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbd 0x0bbd seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_b_adr 34 TR0d:14 typ_frame d val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bc3 0bc3 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bc4 0bc4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbb7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bb7 0x0bb7 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bc5 0bc5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xbd2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bc6 0bc6 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS 0bc7 0bc7 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bc8 0bc8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bc9 0bc9 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bca 0bca fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bcb 0bcb fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bcc 0bcc seq_b_timing 0 Early Condition; Flow J cc=True 0xbcd ; Flow J cc=#0x0 0xbcd seq_br_type b Case False seq_branch_adr 0bcd 0x0bcd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bcd 0bcd fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bce 0bce fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bcf 0bcf fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bd0 0bd0 fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bd1 0bd1 ioc_load_wdr 0 ; Flow J 0xbd2 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd2 0x0bd2 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0bd2 0bd2 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0bd3 0x0bd3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bd3 0bd3 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0bd4 0bd4 fiu_tivi_src 1 tar_val; Flow C 0xbea ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0bea 0x0bea seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bd5 0bd5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0bd6 0bd6 seq_en_micro 0 0bd7 0bd7 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xbe7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0bd8 0bd8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbdf fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bdf 0x0bdf seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 03 VR0d:1c val_c_source 0 FIU_BUS val_frame d 0bd9 0bd9 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xc04 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0c04 0x0c04 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR0d:1d val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame d 0bda 0bda seq_en_micro 0 0bdb 0bdb fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xbe7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0bdc 0bdc fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 03 VR0d:1c val_c_mux_sel 2 ALU val_frame d 0bdd 0bdd fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0xbe7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bde 0bde fiu_mem_start 2 start-rd; Flow J cc=False 0xbe7 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bdf 0bdf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe7 seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR0d:1b typ_alu_func 1c DEC_A typ_c_adr 04 TR0d:1b typ_c_mux_sel 0 ALU typ_frame d 0be0 0be0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xbe7 seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0be1 0be1 fiu_tivi_src c mar_0xc; Flow C 0xbea ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0bea 0x0bea seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be2 0be2 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR0d:1a val_alu_func 1 A_PLUS_B val_b_adr 3d VR0d:1d val_frame d 0be3 0be3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe7 seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 3d VR0d:1d val_alu_func 6 A_MINUS_B val_b_adr 3a VR0d:1a val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be4 0be4 seq_br_type 0 Branch False; Flow J cc=False 0xbe7 seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0be5 0be5 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0xbd9 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd9 0x0bd9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 0be6 0be6 fiu_mem_start 2 start-rd; Flow J cc=True 0xbdf ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 0bdf 0x0bdf seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0be7 0be7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0be8 0be8 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0be9 0be9 seq_br_type 3 Unconditional Branch; Flow J 0xc04 seq_branch_adr 0c04 0x0c04 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 3d TR0d:1d typ_alu_func 7 INC_A typ_c_adr 02 TR0d:1d typ_c_mux_sel 0 ALU typ_frame d 0bea 0bea fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 0beb 0beb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbee fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0bee 0x0bee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bec 0bec fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bed 0bed ioc_load_wdr 0 ; Flow J 0xc04 seq_br_type 3 Unconditional Branch seq_branch_adr 0c04 0x0c04 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bee 0bee seq_b_timing 0 Early Condition; Flow J cc=False 0xbf3 seq_br_type 0 Branch False seq_branch_adr 0bf3 0x0bf3 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 0bef 0bef fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0bf0 0x0bf0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bf0 0bf0 fiu_mem_start 3 start-wr ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bf1 0bf1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xc03 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c03 0x0c03 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 01 TR0d:1e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0bf2 0bf2 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False ; Flow J cc=True 0xbf7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf7 0x0bf7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 3e TR0d:1e typ_frame d 0bf3 0bf3 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0bf4 0x0bf4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bf4 0bf4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bf5 0bf5 ioc_tvbs 2 fiu+val; Flow J cc=True 0xc03 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c03 0x0c03 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 01 VR0d:1e val_c_mux_sel 2 ALU val_frame d 0bf6 0bf6 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf7 0x0bf7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 3e VR0d:1e val_frame d 0bf7 0bf7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bf8 0bf8 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_b_adr 0f GP0f 0bf9 0bf9 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bfa 0bfa fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bfb 0bfb fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bfc 0bfc fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bfd 0bfd fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bfe 0bfe seq_b_timing 0 Early Condition; Flow J cc=True 0xbff ; Flow J cc=#0x0 0xbff seq_br_type b Case False seq_branch_adr 0bff 0x0bff seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bff 0bff fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0c00 0c00 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0c01 0c01 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0c02 0c02 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0c03 0c03 ioc_load_wdr 0 ; Flow J 0xc04 seq_br_type 3 Unconditional Branch seq_branch_adr 0c04 0x0c04 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0f GP0f val_b_adr 0f GP0f 0c04 0c04 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0c05 0x0c05 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0c05 0c05 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0c06 ; -------------------------------------------------------------------------------------- 0c06 ; 0x021f Execute Heap_Access,Equal 0c06 ; -------------------------------------------------------------------------------------- 0c06 MACRO_Execute_Heap_Access,Equal: 0c06 0c06 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c06 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c07 0c07 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0c08 ; -------------------------------------------------------------------------------------- 0c08 ; 0x021e Execute Heap_Access,Maximum 0c08 ; -------------------------------------------------------------------------------------- 0c08 MACRO_Execute_Heap_Access,Maximum: 0c08 0c08 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c08 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c09 0c09 <halt> ; Flow R 0c0a ; -------------------------------------------------------------------------------------- 0c0a ; 0x021d Execute Heap_Access,Is_Null 0c0a ; -------------------------------------------------------------------------------------- 0c0a MACRO_Execute_Heap_Access,Is_Null: 0c0a 0c0a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c0b 0c0b <halt> ; Flow R 0c0c ; -------------------------------------------------------------------------------------- 0c0c ; 0x021c Execute Heap_Access,Not_Null 0c0c ; -------------------------------------------------------------------------------------- 0c0c MACRO_Execute_Heap_Access,Not_Null: 0c0c 0c0c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c0d 0c0d <halt> ; Flow R 0c0e ; -------------------------------------------------------------------------------------- 0c0e ; 0x021b Execute Heap_Access,Set_Null 0c0e ; -------------------------------------------------------------------------------------- 0c0e MACRO_Execute_Heap_Access,Set_Null: 0c0e 0c0e dispatch_brk_class 8 ; Flow J cc=True 0xc12 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0e fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c12 0x0c12 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_lit 2 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c0f 0c0f fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c10 0c10 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 0c11 0c11 ioc_load_wdr 0 ; Flow J 0xc07 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0c07 0x0c07 val_b_adr 39 VR02:19 val_frame 2 0c12 0c12 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3279 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 0c13 0c13 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0xc15 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c15 0x0c15 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 0c14 0c14 fiu_fill_mode_src 0 ; Flow J 0xc18 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c18 0x0c18 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0c15 0c15 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c16 0c16 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c17 0c17 fiu_load_var 1 hold_var; Flow J 0xc18 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c18 0x0c18 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c18 0c18 ioc_load_wdr 0 ; Flow J 0xc07 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c07 0x0c07 0c19 0c19 <halt> ; Flow R 0c1a ; -------------------------------------------------------------------------------------- 0c1a ; 0x021a Execute Heap_Access,Element_Type 0c1a ; -------------------------------------------------------------------------------------- 0c1a MACRO_Execute_Heap_Access,Element_Type: 0c1a 0c1a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c1a dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 0c1b 0c1b fiu_load_tar 1 hold_tar; Flow J cc=False 0xc1e fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c1e 0x0c1e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 0c1c 0c1c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 0c1d 0c1d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 0c1e 0c1e fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c1f 0x0c1f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c1f 0c1f seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 0c20 ; -------------------------------------------------------------------------------------- 0c20 ; 0x0219 Execute Heap_Access,All_Read 0c20 ; -------------------------------------------------------------------------------------- 0c20 MACRO_Execute_Heap_Access,All_Read: 0c20 0c20 dispatch_brk_class 8 ; Flow C cc=True 0x3271 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c20 dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 0c21 0c21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc27 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c27 0x0c27 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c22 0c22 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c23 0c23 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc25 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c25 0x0c25 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0c24 0c24 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc28 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c28 0x0c28 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c25 0c25 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c26 0c26 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc28 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c28 0x0c28 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c27 0c27 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c28 0c28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0c29 0x0c29 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c29 0c29 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c2a ; -------------------------------------------------------------------------------------- 0c2a ; 0x0218 Execute Heap_Access,All_Write 0c2a ; -------------------------------------------------------------------------------------- 0c2a MACRO_Execute_Heap_Access,All_Write: 0c2a 0c2a dispatch_brk_class 2 ; Flow C cc=True 0x3271 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c2a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c2b 0c2b fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0c2c 0c2c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c2d 0c2d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 0c2e 0c2e fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 0c2f 0c2f <halt> ; Flow R 0c30 ; -------------------------------------------------------------------------------------- 0c30 ; 0x0217 Execute Heap_Access,All_Reference 0c30 ; -------------------------------------------------------------------------------------- 0c30 MACRO_Execute_Heap_Access,All_Reference: 0c30 0c30 dispatch_brk_class 8 ; Flow C cc=True 0x3271 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c30 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c31 0c31 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 0c32 ; -------------------------------------------------------------------------------------- 0c32 ; 0x0216 Execute Heap_Access,Convert 0c32 ; -------------------------------------------------------------------------------------- 0c32 MACRO_Execute_Heap_Access,Convert: 0c32 0c32 dispatch_brk_class 4 ; Flow J cc=True 0xc34 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c32 seq_br_type 1 Branch True seq_branch_adr 0c34 0x0c34 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0c33 0c33 seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c34 0c34 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c35 0c35 <halt> ; Flow R 0c36 ; -------------------------------------------------------------------------------------- 0c36 ; 0x0211 Execute Heap_Access,Convert_Reference 0c36 ; -------------------------------------------------------------------------------------- 0c36 MACRO_Execute_Heap_Access,Convert_Reference: 0c36 0c36 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c36 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c37 0c37 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 0c38 0c38 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0c39 0c39 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 0c3a 0c3a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0c3b 0x0c3b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c3b 0c3b seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_csa_cntl 3 POP_CSA 0c3c ; -------------------------------------------------------------------------------------- 0c3c ; 0x0215 Execute Heap_Access,In_Type 0c3c ; -------------------------------------------------------------------------------------- 0c3c MACRO_Execute_Heap_Access,In_Type: 0c3c 0c3c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c3c fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3d 0x0c3d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c3d 0c3d ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c3e 0c3e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c3f 0c3f seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c40 0c40 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c41 0c41 <halt> ; Flow R 0c42 ; -------------------------------------------------------------------------------------- 0c42 ; 0x0214 Execute Heap_Access,Not_In_Type 0c42 ; -------------------------------------------------------------------------------------- 0c42 MACRO_Execute_Heap_Access,Not_In_Type: 0c42 0c42 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c42 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c43 0x0c43 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c43 0c43 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c44 0c44 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c45 0c45 seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c46 0c46 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c47 0c47 <halt> ; Flow R 0c48 ; -------------------------------------------------------------------------------------- 0c48 ; 0x0213 Execute Heap_Access,Check_In_Type 0c48 ; -------------------------------------------------------------------------------------- 0c48 MACRO_Execute_Heap_Access,Check_In_Type: 0c48 0c48 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c48 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0c49 0c49 seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c4a 0c4a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c4b 0c4b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0c4c 0c4c <default> 0c4d 0c4d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 0c4e 0c4e seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 0c4f 0c4f <halt> ; Flow R 0c50 ; -------------------------------------------------------------------------------------- 0c50 ; 0x0212 Execute Heap_Access,Address 0c50 ; -------------------------------------------------------------------------------------- 0c50 MACRO_Execute_Heap_Access,Address: 0c50 0c50 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c50 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 0c51 0c51 <halt> ; Flow R 0c52 ; -------------------------------------------------------------------------------------- 0c52 ; 0x0210 Execute Heap_Access,Get_Segment 0c52 ; -------------------------------------------------------------------------------------- 0c52 MACRO_Execute_Heap_Access,Get_Segment: 0c52 0c52 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c52 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0c53 0c53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c54 ; -------------------------------------------------------------------------------------- 0c54 ; 0x0144 Execute Heap_Access,Get_Name 0c54 ; -------------------------------------------------------------------------------------- 0c54 MACRO_Execute_Heap_Access,Get_Name: 0c54 0c54 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c54 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0c55 0c55 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c56 ; -------------------------------------------------------------------------------------- 0c56 ; 0x0148 Execute Heap_Access,Get_Offset 0c56 ; -------------------------------------------------------------------------------------- 0c56 MACRO_Execute_Heap_Access,Get_Offset: 0c56 0c56 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c56 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0c57 0c57 <halt> ; Flow R 0c58 ; -------------------------------------------------------------------------------------- 0c58 ; 0x0147 Execute Heap_Access,Construct_Segment 0c58 ; -------------------------------------------------------------------------------------- 0c58 MACRO_Execute_Heap_Access,Construct_Segment: 0c58 0c58 dispatch_brk_class 8 ; Flow C cc=True 0x32b1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c58 fiu_len_fill_lit 55 zero-fill 0x15 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b1 0x32b1 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR08:01 val_frame 8 0c59 0c59 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32b1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b1 0x32b1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 0c5a 0c5a fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 30 TR0b:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c5b 0c5b <halt> ; Flow R 0c5c ; -------------------------------------------------------------------------------------- 0c5c ; 0x0146 Execute Heap_Access,Hash 0c5c ; -------------------------------------------------------------------------------------- 0c5c MACRO_Execute_Heap_Access,Hash: 0c5c 0c5c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c5c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0c5d 0c5d ioc_tvbs 1 typ+fiu typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c5e 0c5e fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c5f 0x0c5f seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0c5f 0c5f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c60 ; -------------------------------------------------------------------------------------- 0c60 ; 0x0070-0x0074 QQUnknown InMicrocode 0c60 ; 0x0145 Execute Heap_Access,Diana_Tree_Kind 0c60 ; -------------------------------------------------------------------------------------- 0c60 MACRO_0c60_QQUnknown_InMicrocode: 0c60 MACRO_Execute_Heap_Access,Diana_Tree_Kind: 0c60 0c60 dispatch_brk_class 8 ; Flow J cc=True 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c60 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c65 0x0c65 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c61 0c61 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc63 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c63 0x0c63 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 0c62 0c62 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c63 0c63 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c64 0c64 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c65 0c65 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0c66 0c66 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a9 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c67 ; -------------------------------------------------------------------------------------- 0c67 ; Comes from: 0c67 ; 0c72 C from color MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci 0c67 ; 0c76 C from color MACRO_Execute_Discrete,Diana_Arity_For_Kind 0c67 ; 0c78 C from color MACRO_Execute_Discrete,Diana_Spare0 0c67 ; 0c7a C from color MACRO_Execute_Discrete,Diana_Spare2 0c67 ; -------------------------------------------------------------------------------------- 0c67 0c67 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x326e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326e 0x326e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2b TR09:0b typ_frame 9 val_a_adr 05 GP05 0c68 0c68 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0xc69 ; Flow J cc=#0x0 0xc69 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0c69 0x0c69 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR06:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 35 VR06:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0c69 0c69 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6a 0c6a fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6b 0c6b fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6c 0c6c fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6d 0c6d fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6e 0c6e fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6f 0c6f fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c70 0c70 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c71 0c71 <halt> ; Flow R 0c72 ; -------------------------------------------------------------------------------------- 0c72 ; 0x008f Execute Discrete,Diana_Map_Kind_To_Vci 0c72 ; -------------------------------------------------------------------------------------- 0c72 MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci: 0c72 0c72 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c72 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c73 0c73 fiu_len_fill_lit 46 zero-fill 0x6; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0c74 0x0c74 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0c74 0c74 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0c75 0c75 <halt> ; Flow R 0c76 ; -------------------------------------------------------------------------------------- 0c76 ; 0x008e Execute Discrete,Diana_Arity_For_Kind 0c76 ; -------------------------------------------------------------------------------------- 0c76 MACRO_Execute_Discrete,Diana_Arity_For_Kind: 0c76 0c76 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c76 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c77 0c77 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c78 ; -------------------------------------------------------------------------------------- 0c78 ; 0x008a Execute Discrete,Diana_Spare0 0c78 ; -------------------------------------------------------------------------------------- 0c78 MACRO_Execute_Discrete,Diana_Spare0: 0c78 0c78 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c78 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c79 0c79 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c7a ; -------------------------------------------------------------------------------------- 0c7a ; 0x0087 Execute Discrete,Diana_Spare2 0c7a ; -------------------------------------------------------------------------------------- 0c7a MACRO_Execute_Discrete,Diana_Spare2: 0c7a 0c7a dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c7a fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c7b 0c7b fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c7c ; -------------------------------------------------------------------------------------- 0c7c ; 0x008d Execute Heap_Access,Diana_Allocate_Tree_Node 0c7c ; -------------------------------------------------------------------------------------- 0c7c MACRO_Execute_Heap_Access,Diana_Allocate_Tree_Node: 0c7c 0c7c dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c7c fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c7d 0c7d ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 12 0c7e 0c7e fiu_tivi_src c mar_0xc; Flow J 0xc7f ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0c87 0x0c87 typ_a_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 0c7f 0c7f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xc84 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c84 0x0c84 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR12:1e typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 0c80 0c80 seq_b_timing 1 Latch Condition; Flow J cc=True 0xc83 seq_br_type 1 Branch True seq_branch_adr 0c83 0x0c83 seq_random 05 ? typ_a_adr 20 TR13:00 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c81 0c81 fiu_mem_start 2 start-rd; Flow J cc=True 0x3596 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3596 0x3596 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR09:1f val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 9 0c82 0c82 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0c83 0c83 fiu_mem_start 2 start-rd; Flow J 0x3596 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3596 0x3596 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 33 VR05:13 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 0c84 0c84 fiu_len_fill_lit 4e zero-fill 0xe fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c85 0c85 fiu_fill_mode_src 0 ; Flow J cc=False 0x3596 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 0c86 0c86 seq_br_type 7 Unconditional Call; Flow C 0x3596 seq_branch_adr 3596 0x3596 val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 13 0c87 0c87 seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3f TR12:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c88 0c88 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 val_b_adr 10 TOP 0c89 0c89 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0xc8b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c8b 0x0c8b typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c8a 0c8a fiu_len_fill_lit 50 zero-fill 0x10 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0c8b 0c8b fiu_fill_mode_src 0 ; Flow J cc=False 0xc8f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c8f 0x0c8f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0c8c 0c8c fiu_fill_mode_src 0 ; Flow J 0xc8d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c8d 0x0c8d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c8d 0c8d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c8e 0c8e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0c8f 0c8f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 0c90 0c90 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c91 0c91 fiu_load_var 1 hold_var; Flow J 0xc8d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8d 0x0c8d seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c92 ; -------------------------------------------------------------------------------------- 0c92 ; 0x008c Execute Heap_Access,Diana_Put_Node_On_Seq_Type 0c92 ; -------------------------------------------------------------------------------------- 0c92 MACRO_Execute_Heap_Access,Diana_Put_Node_On_Seq_Type: 0c92 0c92 dispatch_brk_class 8 ; Flow J cc=True 0x3271 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c92 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3271 0x3271 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c93 0c93 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc95 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c95 0x0c95 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0c94 0c94 fiu_fill_mode_src 0 ; Flow J 0xc97 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c97 0x0c97 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c95 0c95 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c96 0c96 fiu_fill_mode_src 0 ; Flow J 0xc97 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c97 0x0c97 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c97 0c97 fiu_len_fill_lit 7c zero-fill 0x3c; Flow C 0xc67 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c98 0c98 ioc_fiubs 2 typ ; Flow J cc=True 0xca0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ca0 0x0ca0 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR13:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 12 0c99 0c99 fiu_len_fill_lit 5a zero-fill 0x1a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0c9a 0c9a fiu_fill_mode_src 0 ; Flow J cc=False 0xc9d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c9d 0x0c9d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 0c9b 0c9b fiu_fill_mode_src 0 ; Flow J 0xc9c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c9c 0x0c9c typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c9c 0c9c ioc_load_wdr 0 ; Flow J 0xc8e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8e 0x0c8e typ_a_adr 2e TR0b:0e typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c9d 0c9d fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c9e 0c9e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c9f 0c9f fiu_load_var 1 hold_var; Flow J 0xc9c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c9c 0x0c9c seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ca0 0ca0 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0ca1 0ca1 fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca2 0ca2 fiu_fill_mode_src 0 ; Flow J cc=False 0xca6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ca6 0x0ca6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 0ca3 0ca3 fiu_fill_mode_src 0 ; Flow J 0xca4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ca4 0x0ca4 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0ca4 0ca4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 2a VR13:0a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0ca5 0ca5 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0xc9a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0c9a 0x0c9a typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca6 0ca6 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ca7 0ca7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ca8 0ca8 fiu_load_var 1 hold_var; Flow J 0xca4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ca4 0x0ca4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ca9 0ca9 <halt> ; Flow R 0caa ; -------------------------------------------------------------------------------------- 0caa ; 0x008b Execute Heap_Access,Diana_Seq_Type_Get_Head 0caa ; -------------------------------------------------------------------------------------- 0caa MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head: 0caa 0caa dispatch_brk_class 8 ; Flow J cc=True 0xcb3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0caa fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb3 0x0cb3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0cab 0cab val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0cac 0cac fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cad 0cad fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0cae 0x0cae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0cae 0cae fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0caf 0caf fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcb1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cb1 0x0cb1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cb0 0cb0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb1 0cb1 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cb2 0cb2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb3 0cb3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cb4 ; -------------------------------------------------------------------------------------- 0cb4 ; 0x0089 Execute Discrete,Diana_Spare1 0cb4 ; -------------------------------------------------------------------------------------- 0cb4 MACRO_Execute_Discrete,Diana_Spare1: 0cb4 0cb4 dispatch_brk_class 8 ; Flow J cc=True 0xcb9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cb4 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 1e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb9 0x0cb9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0cb5 0cb5 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xcb8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb8 0x0cb8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1e A_AND_B typ_b_adr 27 TR13:07 typ_frame 13 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand 9 PASS_A_HIGH 0cb6 0cb6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_b_adr 38 TR11:18 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0cb7 0cb7 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb8 0cb8 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32ae ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32ae 0x32ae seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cb9 0cb9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0cba ; -------------------------------------------------------------------------------------- 0cba ; 0x0088 Execute Heap_Access,Diana_Spare2 0cba ; -------------------------------------------------------------------------------------- 0cba MACRO_Execute_Heap_Access,Diana_Spare2: 0cba 0cba dispatch_brk_class 8 ; Flow J cc=True 0xcd3 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0cba fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd3 0x0cd3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 0cbb 0cbb fiu_mem_start 2 start-rd; Flow J cc=True 0xcd4 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd4 0x0cd4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0cbc 0cbc typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0cbd 0cbd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cbe 0cbe fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcc2 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0cc2 0x0cc2 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cbf 0cbf fiu_load_tar 1 hold_tar; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cc0 0cc0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cc1 0cc1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc2 0cc2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc3 0cc3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc4 0cc4 ioc_load_wdr 0 ; Flow J cc=True 0xcc7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_rand 1 INC_LOOP_COUNTER 0cc5 0cc5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xcd5 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0cd5 0x0cd5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 0cc6 0cc6 seq_br_type 3 Unconditional Branch; Flow J 0xcbf seq_branch_adr 0cbf 0x0cbf 0cc7 0cc7 ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0cc8 0cc8 fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xcca fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cca 0x0cca seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0cc9 0cc9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0cca 0cca ioc_fiubs 1 val ; Flow J cc=True 0xccc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ccc 0x0ccc typ_c_adr 20 TOP - 0x1 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0ccb 0ccb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ccc 0ccc fiu_mem_start 2 start-rd; Flow J cc=True 0xccd ; Flow J cc=#0x0 0xccd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ccd 0x0ccd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0ccd 0ccd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cce 0cce fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0ccf 0ccf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cd0 0cd0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cd1 0cd1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 0cd2 0cd2 ioc_load_wdr 0 ; Flow J 0xc8e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8e 0x0c8e 0cd3 0cd3 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0cd4 0cd4 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1c DEC_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd5 0cd5 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd6 0cd6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cd7 0cd7 <halt> ; Flow R 0cd8 ; -------------------------------------------------------------------------------------- 0cd8 ; 0x0142 Execute Heap_Access,Diana_Find_Permanent_Attribute 0cd8 ; -------------------------------------------------------------------------------------- 0cd8 MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute: 0cd8 0cd8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cd8 fiu_len_fill_lit 65 zero-fill 0x25 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 0cd9 0cd9 fiu_len_fill_lit 59 zero-fill 0x19; Flow J cc=True 0xce8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ce8 0x0ce8 typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2b VR13:0b val_frame 13 val_rand 9 PASS_A_HIGH 0cda 0cda fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcdc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cdc 0x0cdc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cdb 0cdb fiu_fill_mode_src 0 ; Flow J 0xcde fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cde 0x0cde typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cdc 0cdc fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cdd 0cdd fiu_fill_mode_src 0 ; Flow J 0xcde fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cde 0x0cde typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cde 0cde ioc_fiubs 2 typ ; Flow J cc=True 0xce6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce6 0x0ce6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 0cdf 0cdf fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xce9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce9 0x0ce9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR06:17 typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA 0ce0 0ce0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xce3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ce3 0x0ce3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0ce1 0ce1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce2 0ce2 seq_br_type 3 Unconditional Branch; Flow J 0xcde seq_branch_adr 0cde 0x0cde typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce3 0ce3 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ce4 0ce4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce5 0ce5 seq_br_type 3 Unconditional Branch; Flow J 0xcde seq_branch_adr 0cde 0x0cde typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce6 0ce6 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0ce7 0x0ce7 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ce7 0ce7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce8 0ce8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce9 0ce9 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0cea 0cea seq_br_type 1 Branch True; Flow J cc=True 0xcdf seq_branch_adr 0cdf 0x0cdf seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 29 TR06:09 typ_frame 6 0ceb 0ceb seq_br_type 7 Unconditional Call; Flow C 0x32c5 seq_branch_adr 32c5 0x32c5 0cec ; -------------------------------------------------------------------------------------- 0cec ; 0x0143 Execute Heap_Access,Adaptive_Balanced_Tree_Lookup 0cec ; -------------------------------------------------------------------------------------- 0cec MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup: 0cec 0cec dispatch_brk_class 8 ; Flow C 0x32fe dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cec fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0ced 0ced fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 0cee 0cee fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 0cef 0cef fiu_mem_start 4 continue; Flow J 0xcf0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0d03 0x0d03 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0cf0 0cf0 fiu_mem_start 4 continue; Flow J cc=True 0xd02 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d02 0x0d02 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0cf1 0cf1 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0cf2 0cf2 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_frame 5 0cf3 0cf3 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf4 0cf4 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0xcf6 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cf6 0x0cf6 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0cf5 0cf5 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xd02 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d02 0x0d02 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf6 0cf6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd00 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d00 0x0d00 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cf7 0cf7 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0cf8 0cf8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcfc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cfc 0x0cfc seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR 0cf9 0cf9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfa 0cfa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfb 0cfb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0cfc 0cfc fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cfd 0cfd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfe 0cfe fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cff 0cff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d00 0d00 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d01 0d01 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0xcf8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d02 0d02 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d03 0d03 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0d04 0d04 seq_br_type 2 Push (branch address); Flow J 0xd05 seq_branch_adr 0d03 0x0d03 0d05 0d05 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xcf8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d06 0d06 seq_br_type 7 Unconditional Call; Flow C 0x32c5 seq_branch_adr 32c5 0x32c5 0d07 0d07 <halt> ; Flow R 0d08 ; -------------------------------------------------------------------------------------- 0d08 ; 0x01be Execute Vector,Hash 0d08 ; -------------------------------------------------------------------------------------- 0d08 MACRO_Execute_Vector,Hash: 0d08 0d08 dispatch_brk_class 8 ; Flow J cc=False 0xd0e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0d08 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 0d0e 0x0d0e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0d09 0d09 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd0b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d0b 0x0d0b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d0a 0d0a fiu_fill_mode_src 0 ; Flow J 0xd0d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0d 0x0d0d 0d0b 0d0b fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d0c 0d0c fiu_fill_mode_src 0 ; Flow J 0xd0d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0d 0x0d0d 0d0d 0d0d fiu_len_fill_lit 7c zero-fill 0x3c; Flow J 0xd10 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d10 0x0d10 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d0e 0d0e fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0d0f 0d0f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xd10 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d10 0x0d10 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d10 0d10 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xd21 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d21 0x0d21 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 0d11 0d11 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0d12 0d12 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1d 0x0d1d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d13 0d13 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d14 0d14 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1f 0x0d1f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d15 0d15 fiu_fill_mode_src 0 ; Flow J 0xd16 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d16 0x0d16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d16 0d16 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d17 0d17 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d18 0d18 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d19 0d19 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 14 ZEROS val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d1a 0d1a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 0d1b 0x0d1b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0d1b 0d1b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0d1c 0x0d1c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0d1c 0d1c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d1d 0d1d fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d1e 0d1e fiu_fill_mode_src 0 ; Flow J 0xd14 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d14 0x0d14 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d1f 0d1f fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d20 0d20 fiu_fill_mode_src 0 ; Flow J 0xd16 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d16 0x0d16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d21 0d21 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA 0d22 0d22 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd26 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d26 0x0d26 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0d23 0d23 fiu_fill_mode_src 0 ; Flow J 0xd24 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d24 0x0d24 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d24 0d24 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d25 0d25 ioc_tvbs 1 typ+fiu; Flow J 0xd17 seq_br_type 3 Unconditional Branch seq_branch_adr 0d17 0x0d17 val_a_adr 3f VR05:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d26 0d26 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d27 0d27 fiu_fill_mode_src 0 ; Flow J 0xd24 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d24 0x0d24 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d28 0d28 ioc_load_wdr 0 ; Flow J 0xe20 seq_br_type 3 Unconditional Branch seq_branch_adr 0e20 0x0e20 seq_en_micro 0 0d29 0d29 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0d2a ; -------------------------------------------------------------------------------------- 0d2a ; Comes from: 0d2a ; 0d30 C from color 0x0000 0d2a ; 0d7f C from color 0x0000 0d2a ; 0d86 C from color 0x0000 0d2a ; 0dde C from color 0x0000 0d2a ; 0de4 C from color 0x0000 0d2a ; 0dea C from color 0x0de8 0d2a ; 0e50 C from color 0x0e4c 0d2a ; 0e6a C from color 0x0d36 0d2a ; 0e82 C from color 0x0e81 0d2a ; 0e85 C from color 0x0e84 0d2a ; 0ea1 C from color 0x0000 0d2a ; 0ebf C from color 0x0000 0d2a ; 0ede C from color 0x0000 0d2a ; -------------------------------------------------------------------------------------- 0d2a 0d2a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0d2b ; -------------------------------------------------------------------------------------- 0d2b ; Comes from: 0d2b ; 0767 C from color 0x0767 0d2b ; 0769 C from color 0x0767 0d2b ; 0776 C from color 0x0767 0d2b ; 0d66 C from color 0x0d36 0d2b ; 0d68 C from color 0x0d36 0d2b ; 0da1 C from color 0x0da1 0d2b ; 0da6 C from color 0x0da1 0d2b ; 0db5 C from color 0x0db3 0d2b ; 0db7 C from color 0x0db3 0d2b ; 0dbc C from color 0x0db3 0d2b ; 0dda C from color 0x0dda 0d2b ; 0de8 C from color 0x0de8 0d2b ; 0dfa C from color 0x0dfa 0d2b ; 0e21 C from color 0x0e21 0d2b ; 0e24 C from color 0x0e24 0d2b ; 0e39 C from color 0x0e39 0d2b ; 0e4c C from color 0x0e4c 0d2b ; 0e55 C from color 0x0e55 0d2b ; 0e56 C from color 0x0e55 0d2b ; 0e59 C from color 0x0e59 0d2b ; 0e7a C from color 0x0e7a 0d2b ; 0e81 C from color 0x0e81 0d2b ; 0e84 C from color 0x0e84 0d2b ; 0e9d C from color 0x0e9d 0d2b ; 3b71 C from color 0x0bab 0d2b ; 3b79 C from color 0x3b79 0d2b ; -------------------------------------------------------------------------------------- 0d2b 0d2b fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd2d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d2d 0x0d2d seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0d2c 0d2c fiu_fill_mode_src 0 ; Flow J 0xd2f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d2f 0x0d2f typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d2d 0d2d fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d2e 0d2e fiu_fill_mode_src 0 ; Flow J 0xd2f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d2f 0x0d2f typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d2f 0d2f fiu_len_fill_lit 75 zero-fill 0x35; Flow J 0xd30 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d30 0x0d30 seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 0d30 0d30 fiu_load_oreg 1 hold_oreg; Flow C 0xd2a fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d31 0d31 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd34 fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d34 0x0d34 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d32 0d32 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d33 0d33 fiu_mem_start 15 setup_tag_read; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d34 0d34 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d35 0d35 fiu_mem_start 15 setup_tag_read; Flow R cc=True ; Flow J cc=False 0xe20 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0e20 0x0e20 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d36 0d36 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd38 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d38 0x0d38 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d37 0d37 fiu_fill_mode_src 0 ; Flow J 0xd3b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d3b 0x0d3b typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0d38 0d38 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d39 0d39 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0d3a 0d3a fiu_load_var 1 hold_var; Flow J 0xd3b fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d3b 0x0d3b seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0d3b 0d3b ioc_load_wdr 0 ; Flow J 0xd75 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d75 0x0d75 0d3c 0d3c fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d3d 0d3d fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_a_adr 3e VR09:1e val_b_adr 1f TOP - 1 val_frame 9 0d3e 0d3e ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0d3f 0d3f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd29 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0d40 0d40 seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 0d41 0d41 seq_b_timing 1 Latch Condition; Flow J cc=False 0xd43 seq_br_type 0 Branch False seq_branch_adr 0d43 0x0d43 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d42 0d42 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d43 0d43 fiu_mem_start 11 start_tag_query seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 1e A_AND_B typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0d44 0d44 seq_b_timing 0 Early Condition; Flow J cc=True 0xd49 seq_br_type 1 Branch True seq_branch_adr 0d49 0x0d49 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0d45 0d45 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 0d46 0d46 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d47 0d47 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d48 0d48 ioc_load_wdr 0 seq_en_micro 0 0d49 0d49 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start e start_physical_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d4a 0d4a fiu_mem_start 4 continue; Flow J cc=False 0xd4a ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d4a 0x0d4a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0d4b 0d4b seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d4c 0d4c fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d4d 0d4d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 0d4e 0d4e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d4f 0d4f ioc_load_wdr 0 ; Flow J 0xd29 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 0d50 0d50 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d51 0d51 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 2c VR12:0c val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 0d52 0d52 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xd55 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d55 0x0d55 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_b_adr 10 TOP 0d53 0d53 seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0d54 0d54 seq_b_timing 1 Latch Condition; Flow J cc=True 0xd29 seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d55 0d55 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34f3 fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d56 0d56 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20d fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0d57 0d57 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xd58 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d28 0x0d28 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0d58 0d58 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0xd29 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0d29 0x0d29 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0d59 0d59 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xe02 fiu_load_tar 1 hold_tar fiu_mem_start 10 start_physical_tag_wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0e02 0x0e02 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 4 0d5a 0d5a ioc_load_wdr 0 seq_en_micro 0 0d5b 0d5b fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0d5c 0d5c fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d5d 0d5d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 02 GP02 0d5e 0d5e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d5f 0d5f ioc_load_wdr 0 ; Flow J 0xe20 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e20 0x0e20 seq_en_micro 0 0d60 0d60 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0d61 0d61 fiu_load_var 1 hold_var; Flow J cc=True 0xd64 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d64 0x0d64 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0d62 0d62 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd63 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0e20 0x0e20 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d63 0d63 ioc_load_wdr 0 ; Flow J 0x34da seq_br_type 3 Unconditional Branch seq_branch_adr 34da 0x34da seq_en_micro 0 0d64 0d64 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xd62 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d62 0x0d62 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0d65 0d65 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd28 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d66 0d66 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0d67 0d67 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d68 0d68 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0d69 0d69 fiu_mem_start 2 start-rd; Flow J 0xd6b fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d6b 0x0d6b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0d6a 0d6a fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0d6b 0d6b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0d6c 0d6c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl 6 INCREMENT_MAR 0d6d 0d6d fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0d6e 0d6e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0d6f 0d6f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0d70 0d70 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 0 PASS_A 0d71 0d71 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d72 0d72 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 0d73 0d73 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0d74 0d74 ioc_load_wdr 0 ; Flow J cc=False 0xd6a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d6a 0x0d6a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 val_b_adr 04 GP04 0d75 0d75 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0d76 0d76 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d77 0d77 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd7d ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0d7d 0x0d7d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0d78 0d78 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd7d ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d7d 0x0d7d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0d79 0d79 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd7b fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0d7b 0x0d7b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0d7a 0d7a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 21 TR10:01 typ_frame 10 0d7b 0d7b fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 15 setup_tag_read fiu_offs_lit 38 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d7c 0d7c fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0xd7e fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d7e 0x0d7e seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0d7d 0d7d fiu_len_fill_lit 4c zero-fill 0xc fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0d7e 0d7e fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 15 setup_tag_read fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0d7f 0d7f fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd2a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d80 0d80 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 0d81 0d81 ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 0d82 0d82 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0d83 0d83 fiu_len_fill_lit 4c zero-fill 0xc fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 5 0d84 0d84 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d85 0d85 seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 18 NOT_A_AND_B val_b_adr 25 VR05:05 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0d86 0d86 fiu_mem_start 11 start_tag_query; Flow C 0xd2a ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 0d87 0d87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xd9f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0d9f 0x0d9f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0d88 0d88 ioc_tvbs 2 fiu+val; Flow J cc=True 0xd29 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0d89 0d89 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 0d8a 0d8a ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d8b 0d8b fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0d8c 0d8c ioc_load_wdr 0 seq_en_micro 0 val_b_adr 01 GP01 0d8d 0d8d fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0d8e 0d8e fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d8f 0d8f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 06 GP06 0d90 0d90 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d91 0d91 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0d92 0d92 fiu_mem_start d start_physical_rd; Flow C 0xd95 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d95 0x0d95 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0d93 0d93 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d94 0d94 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0d95 ; -------------------------------------------------------------------------------------- 0d95 ; Comes from: 0d95 ; 0d92 C from color 0x0000 0d95 ; 0dae C from color 0x0da1 0d95 ; 0dc2 C from color 0x0db3 0d95 ; -------------------------------------------------------------------------------------- 0d95 0d95 fiu_mem_start 4 continue seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 0d96 0d96 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0d97 0d97 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0d98 0d98 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0d99 0d99 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0d9a 0d9a fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 0 PASS_A 0d9b 0d9b fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 0d9c 0d9c fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0d9d 0d9d fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 0d9e 0d9e ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0xd94 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 0d94 0x0d94 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0d9f 0d9f seq_b_timing 1 Latch Condition; Flow C cc=False 0x3495 seq_br_type 4 Call False seq_branch_adr 3495 0x3495 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0da0 0da0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0da1 0da1 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0da2 0da2 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xdaa fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0daa 0x0daa seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0da3 0da3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdaa seq_br_type 1 Branch True seq_branch_adr 0daa 0x0daa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 val_rand 1 INC_LOOP_COUNTER 0da4 0da4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdaa seq_br_type 1 Branch True seq_branch_adr 0daa 0x0daa seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0da5 0da5 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 0da6 0da6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0da7 0da7 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xdab fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dab 0x0dab seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0da8 0da8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdaa seq_br_type 1 Branch True seq_branch_adr 0daa 0x0daa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 0da9 0da9 seq_br_type 1 Branch True; Flow J cc=True 0xdb1 seq_branch_adr 0db1 0x0db1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0daa 0daa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0dab 0dab seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 13 0dac 0dac fiu_load_var 1 hold_var; Flow J cc=True 0xdaa fiu_tivi_src 3 tar_frame seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0daa 0x0daa seq_en_micro 0 val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0dad 0dad ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0dae 0dae fiu_mem_start d start_physical_rd; Flow C 0xd95 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0d95 0x0d95 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0daf 0daf fiu_mem_start 11 start_tag_query; Flow C 0x3495 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 3495 0x3495 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR 0db0 0db0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0db1 0db1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0db2 0db2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xdad fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0dad 0x0dad seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 22 VR13:02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0db3 0db3 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_en_micro 0 0db4 0db4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xdc3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 0 Branch False seq_branch_adr 0dc3 0x0dc3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0db5 0db5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0db6 0db6 seq_b_timing 1 Latch Condition; Flow J cc=False 0xdb3 seq_br_type 0 Branch False seq_branch_adr 0db3 0x0db3 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand 1 INC_LOOP_COUNTER 0db7 0db7 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0db8 0db8 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xdbe fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0dbe 0x0dbe seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0db9 0db9 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0dba 0dba seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 0dbb 0dbb seq_b_timing 1 Latch Condition; Flow J cc=True 0xdb5 seq_br_type 1 Branch True seq_branch_adr 0db5 0x0db5 seq_en_micro 0 0dbc 0dbc fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0dbd 0dbd fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0dbe 0dbe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xdc1 seq_br_type 5 Call True seq_branch_adr 0dc1 0x0dc1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0dbf 0dbf fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0dc0 0dc0 ioc_load_wdr 0 ; Flow J 0xdc2 seq_br_type 3 Unconditional Branch seq_branch_adr 0dc2 0x0dc2 seq_en_micro 0 val_b_adr 01 GP01 0dc1 ; -------------------------------------------------------------------------------------- 0dc1 ; Comes from: 0dc1 ; 0dbe C True from color 0x0db3 0dc1 ; -------------------------------------------------------------------------------------- 0dc1 0dc1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0dc2 0dc2 fiu_mem_start d start_physical_rd; Flow C 0xd95 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d95 0x0d95 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0dc3 0dc3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 17 LOOP_COUNTER typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0dc4 0dc4 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0dc5 0dc5 fiu_tivi_src 3 tar_frame; Flow J cc=False 0xdcb ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dcb 0x0dcb seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0dc6 0dc6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dc7 0dc7 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A 0dc8 0dc8 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd29 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame d 0dc9 0dc9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32c5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c5 0x32c5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dca 0dca fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xd28 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d28 0x0d28 seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0dcb 0dcb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dcc 0dcc fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dcd 0dcd fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xd29 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0dce 0dce fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0dcf 0dcf fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0xd28 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d28 0x0d28 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0dd0 0dd0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe20 fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_frame 2 0dd1 0dd1 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xdd2 ; Flow J cc=#0x0 0xdd2 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0dd2 0x0dd2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0dd2 0dd2 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xdd4 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0dd4 0x0dd4 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0dd3 0dd3 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xdd4 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0dd4 0x0dd4 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0dd4 0dd4 ioc_load_wdr 0 ; Flow C 0x34d9 seq_br_type 7 Unconditional Call seq_branch_adr 34d9 0x34d9 seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dd5 0dd5 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34ce fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34ce 0x34ce seq_en_micro 0 0dd6 0dd6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0dd7 0dd7 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dd8 0dd8 fiu_load_var 1 hold_var; Flow J cc=True 0xe20 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0dd9 0dd9 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd28 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0dda 0dda fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ddb 0ddb fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0ddc 0ddc fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ddd 0ddd fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0dde 0dde fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd2a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 0ddf 0ddf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0de0 0de0 fiu_fill_mode_src 0 ; Flow J cc=True 0xe20 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0de1 0de1 ioc_load_wdr 0 ; Flow J 0xe20 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e20 0x0e20 seq_en_micro 0 0de2 0de2 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0de3 0de3 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0de4 0de4 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd2a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_frame 2 0de5 0de5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0de6 0de6 fiu_fill_mode_src 0 ; Flow J cc=True 0xe20 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0de7 0de7 ioc_load_wdr 0 ; Flow J 0xe20 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e20 0x0e20 seq_en_micro 0 0de8 0de8 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0de9 0de9 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0dea 0dea fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd2a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0deb 0deb fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0dec 0dec fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ded 0ded fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0dee 0dee ioc_load_wdr 0 ; Flow J 0xd29 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 0def 0def fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR05:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0df0 0df0 fiu_load_var 1 hold_var; Flow J cc=True 0xd29 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0df1 0df1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xdf4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0df4 0x0df4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 33 VR13:13 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0df2 0df2 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR13:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0df3 0df3 ioc_fiubs 2 typ ; Flow J 0xd29 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0df4 0df4 ioc_fiubs 2 typ ; Flow J cc=True 0xd29 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0df5 0df5 ioc_fiubs 2 typ ; Flow J cc=True 0xd29 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0df6 0df6 ioc_fiubs 2 typ ; Flow J 0xd29 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0df7 0df7 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0df8 0df8 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0df9 0df9 ioc_load_wdr 0 ; Flow J 0xd29 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 0dfa 0dfa fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0dfb 0dfb fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0dfc 0dfc fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dfd 0dfd fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0dfe 0dfe fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xe20 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0dff 0dff fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0e00 0e00 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xe01 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d28 0x0d28 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0e01 0e01 fiu_mem_start 10 start_physical_tag_wr; Flow R cc=False ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0e02 0x0e02 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e02 0e02 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e03 0e03 fiu_mem_start 11 start_tag_query; Flow C 0x34f3 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0e04 0e04 ioc_tvbs 8 typ+mem; Flow J cc=True 0xe10 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e10 0x0e10 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0e05 0e05 fiu_mem_start d start_physical_rd; Flow J cc=False 0xe10 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e10 0x0e10 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0e06 0e06 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0e07 0e07 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e08 0e08 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe0b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e0b 0x0e0b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A 0e09 0e09 fiu_fill_mode_src 0 ; Flow J cc=False 0xe10 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e10 0x0e10 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0e0a 0e0a fiu_fill_mode_src 0 ; Flow J cc=True 0xe0b ; Flow J cc=#0x0 0xe0c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e0c 0x0e0c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_frame d val_b_adr 28 VR0d:08 val_frame d 0e0b 0e0b fiu_fill_mode_src 0 ; Flow J cc=False 0xe10 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e10 0x0e10 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_frame d val_b_adr 2f VR0d:0f val_frame d 0e0c 0e0c seq_b_timing 0 Early Condition; Flow J cc=True 0xe0d ; Flow J cc=#0x0 0xe0e seq_br_type b Case False seq_branch_adr 0e0e 0x0e0e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0e0d 0e0d seq_br_type 3 Unconditional Branch; Flow J 0xe10 seq_branch_adr 0e10 0x0e10 seq_en_micro 0 0e0e 0e0e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0e0f 0e0f ioc_fiubs 1 val ; Flow C 0x3691 seq_br_type 7 Unconditional Call seq_branch_adr 3691 0x3691 seq_en_micro 0 val_a_adr 23 VR04:03 val_alu_func 1a PASS_B val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0e10 0e10 fiu_load_var 1 hold_var; Flow C 0x34fc fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0e11 0e11 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e12 0e12 fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e13 0e13 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e14 0e14 fiu_load_var 1 hold_var; Flow J cc=True 0xe20 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e15 0e15 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xe20 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0e16 0e16 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e17 0e17 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xe18 ; Flow J cc=#0x0 0xe18 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e18 0x0e18 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e18 0e18 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe1a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e1a 0x0e1a seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0e19 0e19 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe1a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e1a 0x0e1a seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0e1a 0e1a fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3e GP01 typ_frame 12 0e1b 0e1b fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start f start_physical_tag_rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0e1c 0e1c fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e1d 0e1d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e1e 0e1e fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x34da fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 34da 0x34da seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_frame 12 0e1f 0e1f ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 0e20 0e20 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0e21 0e21 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e22 0e22 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e23 0e23 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e24 0e24 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e25 0e25 fiu_mem_start 15 setup_tag_read; Flow C 0xe27 seq_br_type 7 Unconditional Call seq_branch_adr 0e27 0x0e27 seq_en_micro 0 0e26 0e26 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e27 ; -------------------------------------------------------------------------------------- 0e27 ; Comes from: 0e27 ; 0e25 C from color 0x0e24 0e27 ; 0e2b C from color 0x0000 0e27 ; -------------------------------------------------------------------------------------- 0e27 0e27 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe29 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e29 0x0e29 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0e28 0e28 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 8 Return True seq_branch_adr 0e29 0x0e29 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e29 0e29 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 14 ZEROS val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e2a 0e2a fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e2b 0e2b fiu_mem_start 15 setup_tag_read; Flow C 0xe27 seq_br_type 7 Unconditional Call seq_branch_adr 0e27 0x0e27 seq_en_micro 0 0e2c 0e2c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd29 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_frame 2 0e2d 0e2d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 0e2e 0e2e ioc_load_wdr 0 ; Flow J 0xd29 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 0e2f 0e2f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e30 0e30 fiu_load_var 1 hold_var; Flow J cc=True 0xe20 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e31 0e31 ioc_fiubs 0 fiu ; Flow J cc=True 0xe33 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e33 0x0e33 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e32 0e32 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e33 0e33 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd28 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e34 0e34 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e35 0e35 fiu_load_var 1 hold_var; Flow J cc=True 0xe20 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e20 0x0e20 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e36 0e36 ioc_fiubs 0 fiu ; Flow J cc=True 0xe38 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e38 0x0e38 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e37 0e37 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e38 0e38 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd28 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 18 NOT_A_AND_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e39 0e39 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e3a 0e3a fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e3b 0e3b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32c5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c5 0x32c5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3e VR03:1e val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 3 0e3c 0e3c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e3d 0x0e3d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0e3d 0e3d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e3e 0x0e3e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL 0e3e 0e3e seq_br_type 3 Unconditional Branch; Flow J 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0e3f 0e3f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e40 0e40 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32c5 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 32c5 0x32c5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e41 0e41 fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e42 0e42 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 10 TOP 0e43 0e43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x326e fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2c VR0d:0c val_frame d 0e44 0e44 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0e45 0e45 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x326e fiu_load_mdr 1 hold_mdr fiu_offs_lit 27 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2d VR0d:0d val_frame d 0e46 0e46 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_op_sel 3 insert seq_en_micro 0 0e47 0e47 fiu_mem_start f start_physical_tag_rd; Flow C cc=False 0x32a7 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0e48 0e48 fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 15 setup_tag_read fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 0e49 0e49 fiu_len_fill_lit 75 zero-fill 0x35 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e4a 0e4a fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e4b 0e4b fiu_fill_mode_src 0 ; Flow J 0xd36 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d36 0x0d36 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0e4c 0e4c fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e4d 0e4d fiu_mem_start 12 start_lru_query fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e4e 0e4e seq_br_type 3 Unconditional Branch; Flow J 0xe50 seq_branch_adr 0e50 0x0e50 seq_en_micro 0 0e4f 0e4f fiu_tivi_src 8 type_var; Flow C 0xfd2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e50 0e50 fiu_mem_start 13 start_available_query; Flow C 0xd2a fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e51 0e51 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xe4f ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e52 0e52 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR0d:0d val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame d 0e53 0e53 seq_en_micro 0 val_a_adr 2c VR0d:0c val_b_adr 2d VR0d:0d val_frame d val_rand c START_MULTIPLY 0e54 0e54 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0e55 0e55 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP 0e56 0e56 fiu_load_oreg 1 hold_oreg; Flow C 0xd2b fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e57 0e57 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 7 fiu_frame ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_frame d val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0e58 0e58 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0e59 0e59 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 22 TR08:02 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP 0e5a 0e5a fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src b type_frame fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e5b 0e5b ioc_fiubs 1 val ; Flow C cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 0e5c 0e5c ioc_adrbs 1 val ioc_fiubs 1 val typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_rand a PASS_B_HIGH 0e5d 0e5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0xe5f seq_br_type f Unconditional Case Call seq_branch_adr 0e5f 0x0e5f seq_en_micro 0 typ_csa_cntl 3 POP_CSA 0e5e 0e5e seq_br_type 3 Unconditional Branch; Flow J 0xd29 seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0e5f ; -------------------------------------------------------------------------------------- 0e5f ; Comes from: 0e5f ; 0e5d C #0x0 from color 0x0e5b 0e5f ; -------------------------------------------------------------------------------------- 0e5f 0e5f fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0xe62 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e62 0x0e62 seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e60 0e60 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0e61 0e61 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xe65 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e65 0x0e65 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0e62 0e62 seq_en_micro 0 0e63 0e63 fiu_fill_mode_src 0 ; Flow J cc=False 0xe6f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0e6f 0x0e6f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0e64 0e64 fiu_load_oreg 1 hold_oreg; Flow J 0x3426 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3426 0x3426 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 0e65 0e65 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR07:12 val_frame 7 0e66 0e66 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0xe69 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0e69 0x0e69 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0e67 0e67 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xe6f seq_br_type 0 Branch False seq_branch_adr 0e6f 0x0e6f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0e68 0e68 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xe62 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e62 0x0e62 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e69 0e69 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xe6e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e6e 0x0e6e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 0e6a 0e6a fiu_mem_start 2 start-rd; Flow C 0xd2a ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 0e6b 0e6b fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0e6c 0e6c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 02 GP02 typ_frame d 0e6d 0e6d ioc_load_wdr 0 ; Flow J 0xe6e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e6e 0x0e6e seq_en_micro 0 0e6e 0e6e fiu_mem_start 2 start-rd; Flow J 0x345b ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 345b 0x345b seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 0e6f 0e6f fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A 0e70 0e70 fiu_len_fill_lit 7c zero-fill 0x3c; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0e71 0e71 fiu_fill_mode_src 0 ; Flow J 0xd36 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d36 0x0d36 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0e72 0e72 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e73 0e73 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e74 0e74 ioc_load_wdr 0 ; Flow C cc=False 0x32c5 seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 2e VR12:0e val_alu_func 1d A_AND_NOT_B val_frame 12 0e75 0e75 fiu_mem_start d start_physical_rd; Flow C cc=True 0x32c5 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c5 0x32c5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_frame 11 0e76 0e76 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xe78 seq_br_type 1 Branch True seq_branch_adr 0e78 0x0e78 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0e77 0e77 fiu_mem_start d start_physical_rd; Flow C cc=False 0x32c5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0e78 0e78 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0e79 0e79 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0xd29 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e7a 0e7a fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e7b 0e7b fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e7c 0e7c ioc_fiubs 1 val ; Flow C cc=False 0x32c5 seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 0e7d 0e7d fiu_mem_start d start_physical_rd; Flow C cc=True 0x32c5 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c5 0x32c5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 33 TR12:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2c VR11:0c val_alu_func 1e A_AND_B val_frame 11 0e7e 0e7e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xe80 seq_br_type 1 Branch True seq_branch_adr 0e80 0x0e80 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0e7f 0e7f fiu_mem_start d start_physical_rd; Flow C cc=False 0x32c5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0e80 0e80 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e81 0e81 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e82 0e82 fiu_mem_start 2 start-rd; Flow C 0xd2a seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0e83 0e83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e84 0e84 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e85 0e85 fiu_mem_start 3 start-wr; Flow C 0xd2a ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 seq_random 02 ? typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0e86 0e86 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e87 0e87 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0e88 0e88 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0e89 0e89 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0e8a 0e8a fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e8b 0e8b fiu_mem_start 4 continue seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0e8c 0e8c fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0e8d 0e8d fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0e8e 0e8e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0e8f 0e8f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0e90 0e90 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e91 0e91 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0e92 0e92 fiu_mem_start 4 continue; Flow J cc=True 0xd29 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e93 0e93 fiu_mem_start 4 continue; Flow J cc=True 0xd29 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e94 0e94 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd29 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e95 0e95 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd29 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e96 0e96 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0xe8b ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e8b 0x0e8b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0e97 0e97 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0e98 0e98 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e99 0e99 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xd29 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0d29 0x0d29 seq_en_micro 0 val_a_adr 2d VR0d:0d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame d 0e9a 0e9a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 17 LOOP_COUNTER val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0e9b 0e9b fiu_mem_start 12 start_lru_query; Flow J cc=True 0xe9a seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0e9a 0x0e9a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0e9c 0e9c seq_br_type 3 Unconditional Branch; Flow J 0xd29 seq_branch_adr 0d29 0x0d29 seq_en_micro 0 0e9d 0e9d fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e9e 0e9e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0e9f 0e9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd29 seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0ea0 0ea0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd29 seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 29 TR04:09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0ea1 0ea1 fiu_mem_start 2 start-rd; Flow C 0xd2a ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0ea2 0ea2 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ea3 0ea3 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xec2 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ec2 0x0ec2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_mar_cntl f LOAD_MAR_RESERVED 0ea4 0ea4 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xec6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ec6 0x0ec6 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0ea5 0ea5 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xec4 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 0ec4 0x0ec4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR06:1f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0ea6 0ea6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xea3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0ea3 0x0ea3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_frame 12 0ea7 0ea7 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xea3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ea3 0x0ea3 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 0ea8 0ea8 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xeb5 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0eb5 0x0eb5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 0ea9 0ea9 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xeb5 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0eb5 0x0eb5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 30 VR11:10 val_frame 11 0eaa 0eaa fiu_mem_start 11 start_tag_query; Flow C 0x34f3 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0eab 0eab ioc_tvbs 8 typ+mem; Flow J cc=True 0xeb5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0eb5 0x0eb5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0eac 0eac fiu_mem_start d start_physical_rd; Flow J cc=False 0xeb4 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0eb4 0x0eb4 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0ead 0ead fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0eae 0eae fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 1 0eaf 0eaf ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 0eb0 0eb0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0xeb5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0eb5 0x0eb5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 15 NOT_B typ_b_adr 05 GP05 0eb1 0eb1 fiu_fill_mode_src 0 ; Flow J cc=True 0xea3 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0eb2 0eb2 seq_b_timing 0 Early Condition; Flow J cc=True 0xeb3 ; Flow J cc=#0x0 0xeb3 seq_br_type b Case False seq_branch_adr 0eb3 0x0eb3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0eb3 0eb3 seq_br_type 3 Unconditional Branch; Flow J 0xea3 seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 0eb4 0eb4 seq_en_micro 0 0eb5 0eb5 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1b A_OR_B val_b_adr 3f VR08:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 0eb6 0eb6 ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 01 GP01 0eb7 0eb7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0eb8 0eb8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 0eb9 0eb9 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0eba 0eba fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 02 GP02 val_frame 2 0ebb 0ebb seq_b_timing 1 Latch Condition; Flow J cc=True 0xea3 seq_br_type 1 Branch True seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 0ebc 0ebc fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0ebd 0ebd fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 0ebe 0ebe seq_br_type 1 Branch True; Flow J cc=True 0xea3 seq_branch_adr 0ea3 0x0ea3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 val_c_adr 3c GP03 0ebf 0ebf fiu_mem_start 3 start-wr; Flow C 0xd2a ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 0ec0 0ec0 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ec1 0ec1 ioc_load_wdr 0 ; Flow J 0xea3 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR07:06 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 0ec2 0ec2 ioc_load_wdr 0 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 16 TR04:09 typ_c_mux_sel 0 ALU typ_frame 4 val_b_adr 04 GP04 0ec3 0ec3 fiu_mem_start 3 start-wr; Flow J cc=True 0xd29 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d29 0x0d29 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0ec4 0ec4 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR07:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 0ec5 0ec5 seq_br_type 3 Unconditional Branch; Flow J 0xea3 seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 31 TR05:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 0ec6 0ec6 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 0ec7 0ec7 seq_br_type 3 Unconditional Branch; Flow J 0xea3 seq_branch_adr 0ea3 0x0ea3 seq_en_micro 0 0ec8 0ec8 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ec9 0ec9 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 0e VR03:11 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0eca 0eca fiu_mem_start 3 start-wr; Flow C cc=False 0x211 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 37 TR08:17 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0ecb 0ecb fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 0ecc 0ecc seq_br_type 3 Unconditional Branch; Flow J 0xd29 seq_branch_adr 0d29 0x0d29 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 0ecd 0ecd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR03:10 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 3 0ece 0ece seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0ecf 0ecf seq_br_type 7 Unconditional Call; Flow C 0x213 seq_branch_adr 0213 0x0213 seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 08 VR03:17 val_c_mux_sel 2 ALU val_frame 3 0ed0 0ed0 seq_br_type 7 Unconditional Call; Flow C 0x212 seq_branch_adr 0212 0x0212 seq_en_micro 0 0ed1 0ed1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 0d TR03:12 typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed2 0ed2 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 2a VR0c:0a val_frame c 0ed3 0ed3 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed4 0ed4 ioc_load_wdr 0 ; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0ed5 0ed5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20d ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0ed6 0ed6 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR04:04 val_alu_func 0 PASS_A val_c_adr 1b VR04:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed7 0ed7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR04:1e val_alu_func 0 PASS_A val_c_adr 01 VR04:1e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed8 0ed8 fiu_mem_start 11 start_tag_query; Flow C 0x34f3 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0ed9 0ed9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_mem_start 2 start-rd fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0eda 0eda fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 0edb 0edb fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=False ; Flow J cc=True 0x326e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR12:0e val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0edc 0edc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR1b:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 1b 0edd 0edd fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ede 0ede fiu_mem_start 2 start-rd; Flow C 0xd2a ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2a 0x0d2a seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 38 VR06:18 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 6 0edf 0edf fiu_mem_start 3 start-wr seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 34 VR11:14 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0ee0 0ee0 fiu_mem_start 4 continue ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 2a TR1d:0a typ_frame 1d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0ee1 0ee1 fiu_mem_start 4 continue; Flow J cc=False 0xee1 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0ee1 0x0ee1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 13 LOOP_REG typ_mar_cntl 6 INCREMENT_MAR typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_b_adr 13 LOOP_REG val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 0ee2 0ee2 ioc_load_wdr 0 ; Flow J 0xd29 seq_br_type 3 Unconditional Branch seq_branch_adr 0d29 0x0d29 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 0ee3 0ee3 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 36 VR04:16 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0ee4 0ee4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 36 TR04:16 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ee5 0ee5 ioc_fiubs 1 val ; Flow C cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 0ee6 0ee6 seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0ee7 0ee7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 13 LOOP_REG typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ee8 0ee8 seq_br_type 7 Unconditional Call; Flow C 0x3653 seq_branch_adr 3653 0x3653 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 34 VR04:14 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0ee9 0ee9 typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR03:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0eea 0eea fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2c VR06:0c val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 6 0eeb 0eeb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0eec 0eec fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0eed 0eed fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 00 TR04:1f typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 00 VR04:1f val_c_source 0 FIU_BUS val_frame 4 0eee 0eee seq_br_type 3 Unconditional Branch; Flow J 0x326c seq_branch_adr 326c 0x326c 0eef 0eef fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2a TR12:0a typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 0ef0 0ef0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xef5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ef5 0x0ef5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 0ef1 0ef1 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20d fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 0ef2 0ef2 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 0ef3 0ef3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xef4 ; Flow J cc=#0x0 0xf11 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0f11 0x0f11 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0ef4 0ef4 fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0xef5 ; Flow J cc=#0x0 0xef7 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ef7 0x0ef7 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0ef5 0ef5 seq_b_timing 0 Early Condition; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0ef6 0ef6 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 0ef7 0ef7 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0ef8 0ef8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0ef9 0ef9 fiu_load_var 1 hold_var; Flow J 0xf0a fiu_tivi_src b type_frame ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f0a 0x0f0a seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0efa 0efa ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf62 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f62 0x0f62 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0efb 0efb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xefc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 2 Push (branch address) seq_branch_adr 0fcb 0x0fcb seq_en_micro 0 val_c_adr 30 GP0f 0efc ; -------------------------------------------------------------------------------------- 0efc ; Comes from: 0efc ; 34a5 C from color 0x349d 0efc ; -------------------------------------------------------------------------------------- 0efc 0efc fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xf08 fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f08 0x0f08 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 2 0efd 0efd fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xefe ; Flow J cc=#0x0 0xefe fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0efe 0x0efe seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR02:1d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0efe 0efe fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xf00 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f00 0x0f00 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0eff 0eff fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xf00 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f00 0x0f00 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 0f00 0f00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_b_adr 0f GP0f val_frame 3 0f01 0f01 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xf03 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0f03 0x0f03 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 21 VR11:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 0f02 0f02 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 0f03 0f03 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 0f04 0f04 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f05 0f05 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0f06 0x0f06 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0f06 0f06 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f07 0f07 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34ce fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34ce 0x34ce seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_b_adr 0d GP0d typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 0f GP0f val_b_adr 0d GP0d 0f08 0f08 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0f09 0f09 fiu_mem_start 3 start-wr; Flow J 0x3b5d ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b5d 0x3b5d seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 0f0a 0f0a fiu_load_tar 1 hold_tar; Flow C cc=False 0x20d fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0f0b 0f0b ioc_tvbs 2 fiu+val; Flow C cc=True 0x32c2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c2 0x32c2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_c_adr 30 GP0f 0f0c 0f0c seq_br_type 0 Branch False; Flow J cc=False 0x32c2 seq_branch_adr 32c2 0x32c2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 0f0d 0f0d fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f0e 0f0e ioc_tvbs 8 typ+mem; Flow C cc=True 0x32c2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c2 0x32c2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f0f 0f0f fiu_mem_start 10 start_physical_tag_wr; Flow J 0xf10 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0fcb 0x0fcb seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f10 0f10 ioc_load_wdr 0 ; Flow J 0x34da seq_br_type 3 Unconditional Branch seq_branch_adr 34da 0x34da seq_en_micro 0 val_b_adr 0f GP0f 0f11 0f11 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f12 0f12 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf19 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f19 0x0f19 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f13 0f13 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf2c fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f2c 0x0f2c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f14 0f14 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf35 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f35 0x0f35 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f15 0f15 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf3f fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f3f 0x0f3f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f16 0f16 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf57 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f57 0x0f57 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f17 0f17 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0xf5f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f5f 0x0f5f seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_frame d 0f18 0f18 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f19 0f19 fiu_load_var 1 hold_var; Flow C cc=False 0xf64 fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f64 0x0f64 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f1a 0f1a fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f1b 0f1b fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0xf25 fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f25 0x0f25 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f1c 0f1c ioc_fiubs 0 fiu ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0f1d 0f1d fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f1e 0f1e fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf23 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f23 0x0f23 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f1f 0f1f fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xfa2 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa2 0x0fa2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f20 0f20 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfa2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa2 0x0fa2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 0e GP0e typ_frame 12 val_a_adr 31 VR04:11 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 4 0f21 0f21 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf7c fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7c 0x0f7c seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 0f22 0f22 seq_br_type 3 Unconditional Branch; Flow J 0xfa2 seq_branch_adr 0fa2 0x0fa2 seq_en_micro 0 0f23 0f23 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x327c fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 327c 0x327c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 29 VR12:09 val_frame 12 0f24 0f24 fiu_mem_start 11 start_tag_query; Flow J 0xf7c ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7c 0x0f7c seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_c_adr 34 GP0b 0f25 0f25 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfa2 seq_br_type 1 Branch True seq_branch_adr 0fa2 0x0fa2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 0f26 0f26 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfaf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0faf 0x0faf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f27 0f27 ioc_tvbs 3 fiu+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f28 0f28 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf23 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f23 0x0f23 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f29 0f29 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 0f2a 0f2a fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf7c seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7c 0x0f7c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f2b 0f2b seq_br_type 3 Unconditional Branch; Flow J 0xf9e seq_branch_adr 0f9e 0x0f9e seq_en_micro 0 0f2c 0f2c fiu_load_var 1 hold_var; Flow C cc=False 0xf6d fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f6d 0x0f6d seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f2d 0f2d fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f2e 0f2e ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfa2 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fa2 0x0fa2 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f2f 0f2f seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 2c TR12:0c typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 0f30 0f30 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f31 0f31 fiu_len_fill_lit 14 sign-fill 0x14; Flow J cc=False 0xf33 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f33 0x0f33 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f32 0f32 seq_br_type 3 Unconditional Branch; Flow J 0xf9e seq_branch_adr 0f9e 0x0f9e seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f33 0f33 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x329b fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329b 0x329b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f34 0f34 fiu_mem_start 11 start_tag_query; Flow J 0xf7c ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7c 0x0f7c seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 0f35 0f35 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f36 0f36 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d 0f37 0f37 fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 7 INC_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f38 0f38 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xfaf seq_br_type 0 Branch False seq_branch_adr 0faf 0x0faf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2d TR12:0d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0f39 0f39 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f3a 0f3a fiu_tivi_src 2 tar_fiu; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR01:02 typ_frame 1 val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0f3b 0f3b ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfa2 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa2 0x0fa2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f3c 0f3c ioc_fiubs 0 fiu ; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f3d 0f3d fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A val_a_adr 0b GP0b val_b_adr 0f GP0f 0f3e 0f3e fiu_mem_start 11 start_tag_query; Flow J 0xf7c ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0f7c 0x0f7c seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0f3f 0f3f fiu_load_var 1 hold_var; Flow C cc=False 0xf6d fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f6d 0x0f6d seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f40 0f40 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f41 0f41 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xf48 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f48 0x0f48 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0f42 0f42 fiu_vmux_sel 1 fill value; Flow C 0x210 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f43 0f43 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 0f44 0f44 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf46 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f46 0x0f46 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b 0f45 0f45 seq_br_type 3 Unconditional Branch; Flow J 0xf9e seq_branch_adr 0f9e 0x0f9e seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f46 0f46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329c seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 0f47 0f47 fiu_mem_start 11 start_tag_query; Flow J 0xf7c seq_br_type 3 Unconditional Branch seq_branch_adr 0f7c 0x0f7c seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0f48 0f48 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf43 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 0f43 0x0f43 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f49 0f49 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfaf seq_br_type 0 Branch False seq_branch_adr 0faf 0x0faf seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f4a 0f4a ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfb5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fb5 0x0fb5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3a VR05:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f4b 0f4b fiu_mem_start 2 start-rd; Flow C 0xfd1 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0fd1 0x0fd1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0f4c 0f4c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_en_micro 0 0f4d 0f4d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xfaf fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0faf 0x0faf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0f4e 0f4e fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0f4f 0f4f fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0xfd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0fd1 0x0fd1 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0c GP0c 0f50 0f50 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR0d:00 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 0f51 0f51 seq_en_micro 0 val_a_adr 3f VR06:1f val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 0f52 0f52 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f53 0f53 ioc_load_wdr 0 ; Flow J cc=True 0xf9e ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0f9e 0x0f9e seq_en_micro 0 typ_b_adr 0c GP0c typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f54 0f54 seq_en_micro 0 typ_c_adr 33 GP0c val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 33 VR02:13 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f55 0f55 fiu_mem_start 11 start_tag_query; Flow J cc=True 0xf7c seq_br_type 1 Branch True seq_branch_adr 0f7c 0x0f7c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 0f56 0f56 seq_br_type 7 Unconditional Call; Flow C 0x32b6 seq_branch_adr 32b6 0x32b6 seq_en_micro 0 0f57 0f57 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f58 0f58 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 20 VR0d:00 val_frame d val_rand a PASS_B_HIGH 0f59 0f59 ioc_fiubs 0 fiu ; Flow J cc=True 0xfa3 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0fa3 0x0fa3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0f5a 0f5a fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfaf fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0faf 0x0faf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 0f5b 0f5b fiu_tivi_src c mar_0xc; Flow J cc=True 0xf5e ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f5e 0x0f5e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 25 TR00:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f5c 0f5c ioc_tvbs 2 fiu+val; Flow J cc=False 0xfb6 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fb6 0x0fb6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 0e GP0e val_alu_func 1e A_AND_B val_b_adr 32 VR06:12 val_frame 6 0f5d 0f5d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f5e 0f5e fiu_mem_start 11 start_tag_query; Flow J 0xf7c ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0f7c 0x0f7c seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f5f 0f5f ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xfb6 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fb6 0x0fb6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0f60 0f60 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xf62 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f62 0x0f62 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 3e VR09:1e val_frame 9 0f61 0f61 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfb6 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fb6 0x0fb6 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame d 0f62 0f62 fiu_mem_start 2 start-rd; Flow C 0xfd1 seq_br_type 7 Unconditional Call seq_branch_adr 0fd1 0x0fd1 seq_en_micro 0 0f63 0f63 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0f64 ; -------------------------------------------------------------------------------------- 0f64 ; Comes from: 0f64 ; 0f19 C False from color 0x0efa 0f64 ; -------------------------------------------------------------------------------------- 0f64 0f64 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf6e fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0f6e 0x0f6e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f65 0f65 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f66 0f66 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0f67 0f67 fiu_mem_start 2 start-rd ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f68 0f68 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf66 seq_br_type 1 Branch True seq_branch_adr 0f66 0x0f66 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f69 0f69 fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame c val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f6a 0f6a ioc_fiubs 2 typ ; Flow C cc=True 0x32a1 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 0f6b 0f6b seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c 0f6c 0f6c ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x32a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a1 0x32a1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f6d ; -------------------------------------------------------------------------------------- 0f6d ; Comes from: 0f6d ; 0f2c C False from color 0x0efa 0f6d ; 0f3f C False from color 0x0efa 0f6d ; -------------------------------------------------------------------------------------- 0f6d 0f6d fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf65 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f65 0x0f65 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f6e 0f6e fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c val_rand 9 PASS_A_HIGH 0f6f 0f6f ioc_fiubs 0 fiu ; Flow J cc=True 0xf71 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f71 0x0f71 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f70 0f70 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xf65 seq_br_type 0 Branch False seq_branch_adr 0f65 0x0f65 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR0c:04 typ_frame c 0f71 0f71 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf65 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f65 0x0f65 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR13:0e typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_c_adr 32 GP0d typ_frame 13 val_a_adr 20 VR0d:00 val_frame d 0f72 0f72 ioc_fiubs 0 fiu ; Flow J cc=True 0xf7a seq_br_type 1 Branch True seq_branch_adr 0f7a 0x0f7a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1e A_AND_B typ_b_adr 26 TR0c:06 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame c 0f73 0f73 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf65 seq_br_type 1 Branch True seq_branch_adr 0f65 0x0f65 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_c_adr 1a VR0c:05 val_frame c 0f74 0f74 fiu_load_var 1 hold_var; Flow J cc=True 0xf65 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f65 0x0f65 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 2 0f75 0f75 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf65 seq_br_type 1 Branch True seq_branch_adr 0f65 0x0f65 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_frame 2 val_a_adr 2d VR0c:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f76 0f76 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 26 TR0c:06 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame c 0f77 0f77 ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 2d TR13:0d typ_b_adr 0d GP0d typ_frame 13 val_b_adr 25 VR0c:05 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame c 0f78 0f78 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3651 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random d disable slice timer seq_br_type 7 Unconditional Call seq_branch_adr 3651 0x3651 seq_en_micro 0 typ_a_adr 3c TR12:1c typ_frame 12 val_a_adr 21 VR02:01 val_alu_func 1b A_OR_B val_b_adr 0b GP0b val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0f79 0f79 ioc_random c enable slice timer; Flow J 0xf65 seq_br_type 3 Unconditional Branch seq_branch_adr 0f65 0x0f65 seq_en_micro 0 0f7a 0f7a fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 30 TR07:10 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 1a VR0c:05 val_frame c 0f7b 0f7b ioc_load_wdr 0 ; Flow J 0xf65 seq_br_type 3 Unconditional Branch seq_branch_adr 0f65 0x0f65 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 25 VR0c:05 val_frame c 0f7c 0f7c fiu_len_fill_lit 4c zero-fill 0xc; Flow C 0x34f4 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_frame d val_b_adr 20 VR0d:00 val_frame d 0f7d 0f7d ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0f7e 0f7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame d 0f7f 0f7f fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32c2 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32c2 0x32c2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A val_a_adr 25 VR05:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 5 0f80 0f80 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 0f81 0f81 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xf99 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f99 0x0f99 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0f82 0f82 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 0f83 0f83 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 0f84 0f84 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 72 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0f85 0f85 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 0f86 0f86 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0f87 0f87 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0f88 0f88 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 0f89 0f89 fiu_mem_start 15 setup_tag_read; Flow C 0x210 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame d val_a_adr 0c GP0c 0f8a 0f8a ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0f8b 0f8b fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f8c 0f8c fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34cd fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 val_b_adr 0e GP0e 0f8d 0f8d fiu_load_var 1 hold_var; Flow J cc=True 0xf94 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0f8e 0f8e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e 0f8f 0f8f fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 0f90 0f90 fiu_load_tar 1 hold_tar; Flow J cc=True 0xfcb fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fcb 0x0fcb seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0b GP0b val_b_adr 0b GP0b 0f91 0f91 fiu_mem_start e start_physical_wr; Flow J cc=False 0xf96 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f96 0x0f96 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0f92 0f92 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 0f93 0f93 fiu_mem_start e start_physical_wr; Flow J 0xf96 seq_br_type 3 Unconditional Branch seq_branch_adr 0f96 0x0f96 seq_en_micro 0 0f94 0f94 fiu_load_tar 1 hold_tar; Flow J cc=True 0xfcb fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0fcb 0x0fcb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e val_b_adr 0e GP0e 0f95 0f95 fiu_mem_start e start_physical_wr; Flow J cc=True 0xf92 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f92 0x0f92 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 0f96 0f96 fiu_mem_start 4 continue; Flow J cc=False 0xf96 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f96 0x0f96 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 0f97 0f97 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfcb fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fcb 0x0fcb seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 0f98 0f98 fiu_mem_start e start_physical_wr; Flow J 0xf96 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0f96 0x0f96 seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f99 0f99 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 0f9a 0f9a seq_br_type 7 Unconditional Call; Flow C 0xfd2 seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 0f9b 0f9b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfcb fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fcb 0x0fcb seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame d val_a_adr 25 VR0d:05 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame d 0f9c 0f9c fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xfcb fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 0 Branch False seq_branch_adr 0fcb 0x0fcb seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR0d:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 0f9d 0f9d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xf7f fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7f 0x0f7f seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0f9e 0f9e fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f9f 0f9f ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0fa0 0fa0 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 0f GP0f 0fa1 0fa1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfa3 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fa3 0x0fa3 seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 0fa2 0fa2 fiu_mem_start 2 start-rd; Flow J 0xfa3 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fa3 0x0fa3 seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0fa3 0fa3 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ae ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fa4 0fa4 seq_br_type 0 Branch False; Flow J cc=False 0xfb6 seq_branch_adr 0fb6 0x0fb6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fa5 0fa5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x34f5 seq_br_type 7 Unconditional Call seq_branch_adr 34f5 0x34f5 seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 0fa6 0fa6 ioc_load_wdr 0 ; Flow J cc=True 0xefb ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0efb 0x0efb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fa7 0fa7 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xfb6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fb6 0x0fb6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0fa8 0fa8 seq_br_type 3 Unconditional Branch; Flow J 0xfa9 seq_branch_adr 0fa9 0x0fa9 seq_en_micro 0 0fa9 0fa9 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x32b6 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32b6 0x32b6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl 4 RESTORE_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 20 VR0d:00 val_frame d 0faa 0faa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfad fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fad 0x0fad seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d 0fab 0fab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xf7f fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7f 0x0f7f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0fac 0fac seq_br_type 3 Unconditional Branch; Flow J 0xfcb seq_branch_adr 0fcb 0x0fcb seq_en_micro 0 0fad 0fad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfcb seq_br_type 1 Branch True seq_branch_adr 0fcb 0x0fcb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_a_adr 3c TR07:1c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 33 VR02:13 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 2 0fae 0fae seq_br_type 7 Unconditional Call; Flow C 0x32b6 seq_branch_adr 32b6 0x32b6 seq_en_micro 0 0faf 0faf fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 11 start_tag_query fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME 0fb0 0fb0 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ae ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fb1 0fb1 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 0fb2 0fb2 fiu_load_var 1 hold_var; Flow J cc=False 0xfb7 fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fb7 0x0fb7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 0fb3 0fb3 ioc_load_wdr 0 ; Flow J cc=True 0xefb ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0efb 0x0efb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fb4 0fb4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0fb5 0fb5 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ae ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fb6 0fb6 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0fb7 0fb7 seq_br_type 7 Unconditional Call; Flow C 0xfba seq_branch_adr 0fba 0x0fba seq_en_micro 0 0fb8 0fb8 seq_b_timing 1 Latch Condition; Flow J cc=False 0xfcb seq_br_type 0 Branch False seq_branch_adr 0fcb 0x0fcb seq_en_micro 0 0fb9 0fb9 seq_br_type 3 Unconditional Branch; Flow J 0xfa9 seq_branch_adr 0fa9 0x0fa9 seq_en_micro 0 0fba ; -------------------------------------------------------------------------------------- 0fba ; Comes from: 0fba ; 0fb7 C from color 0x0efa 0fba ; 34a9 C False from color 0x349d 0fba ; -------------------------------------------------------------------------------------- 0fba 0fba fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fbb 0fbb seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0fbc 0x0fbc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0fbc 0fbc seq_br_type 7 Unconditional Call; Flow C 0x3624 seq_branch_adr 3624 0x3624 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fbd 0fbd fiu_mem_start 2 start-rd; Flow C 0xfd1 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0fd1 0x0fd1 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fbe 0fbe ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0fbf 0fbf fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fc0 0fc0 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0xfc3 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fc3 0x0fc3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 5 0fc1 0fc1 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 0fc2 0fc2 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 0fc3 0fc3 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfc4 ; Flow J cc=#0x0 0xfc5 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0fc5 0x0fc5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0fc4 0fc4 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0fc5 0fc5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0fc6 0fc6 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc7 0fc7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc8 0fc8 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc9 0fc9 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362c 0x362c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_mar_cntl 1 RESTORE_RDR val_b_adr 0c GP0c 0fca 0fca seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 0fcb 0fcb fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xfca fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_offs_lit 27 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fca 0x0fca seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0fcc 0fcc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfcd ; Flow J cc=#0x0 0xfcd fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start b start_last_cmd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0fcd 0x0fcd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 23 VR0d:03 val_frame d 0fcd 0fcd fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fce 0fce seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0fcf 0fcf fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fd0 0fd0 fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fd1 ; -------------------------------------------------------------------------------------- 0fd1 ; Comes from: 0fd1 ; 0f4b C from color 0x0efa 0fd1 ; 0f4f C from color 0x0efa 0fd1 ; 0f62 C from color 0x0efa 0fd1 ; 0fbd C from color 0x0fbb 0fd1 ; -------------------------------------------------------------------------------------- 0fd1 0fd1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0fd2 ; -------------------------------------------------------------------------------------- 0fd2 ; Comes from: 0fd2 ; 0e4f C from color 0x0e4c 0fd2 ; 0f9a C from color 0x0efa 0fd2 ; 33d9 C from color 0x0f07 0fd2 ; 3644 C from color 0x3637 0fd2 ; -------------------------------------------------------------------------------------- 0fd2 0fd2 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 0fd3 0fd3 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0fd4 0fd4 fiu_vmux_sel 1 fill value; Flow C cc=True 0x2a84 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0fd5 0fd5 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0fd6 0fd6 fiu_fill_mode_src 0 ; Flow J cc=False 0xfdd fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fdd 0x0fdd seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 0fd7 0fd7 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fd8 0fd8 fiu_mem_start 15 setup_tag_read seq_en_micro 0 0fd9 0fd9 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0fda 0fda fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xfe1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0fe1 0x0fe1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 5 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0fdb 0fdb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0fdc 0fdc fiu_mem_start 12 start_lru_query; Flow J 0xfd6 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fd6 0x0fd6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0fdd 0fdd fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0xfd8 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fd8 0x0fd8 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fde 0fde fiu_mem_start 15 setup_tag_read seq_en_micro 0 0fdf 0fdf fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0fe0 0fe0 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0xfdb fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fdb 0x0fdb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0fe1 0fe1 fiu_tivi_src 4 fiu_var; Flow J cc=True 0xfe3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0fe3 0x0fe3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 0fe2 0fe2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfe4 seq_br_type 1 Branch True seq_branch_adr 0fe4 0x0fe4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 0fe3 0fe3 fiu_fill_mode_src 0 ; Flow J 0xfe4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 3 Unconditional Branch seq_branch_adr 0fe4 0x0fe4 seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0fe4 0fe4 fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 4 0fe5 0fe5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame d val_alu_func 13 ONES val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 0fe6 0fe6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 2d VR12:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 0fe7 0fe7 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 06 TR03:19 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl f LOAD_MAR_RESERVED 0fe8 0fe8 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x1042 fiu_load_var 1 hold_var fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1042 0x1042 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR typ_rand d SET_PASS_PRIVACY_BIT 0fe9 0fe9 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0xfee fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fee 0x0fee seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 3 SPARE_0x03 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fea 0fea fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xfeb ; Flow J cc=#0x0 0x1003 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1003 0x1003 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_c_adr 32 GP0d 0feb 0feb seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 0fec 0fec fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0xfea fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fea 0x0fea seq_en_micro 0 val_b_adr 0d GP0d 0fed 0fed fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xfea fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fea 0x0fea seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fee 0fee fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0xff4 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ff4 0x0ff4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 0fef 0fef fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0ff0 0ff0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0ff1 0ff1 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 28 LOOP_COUNTER typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 0ff2 0ff2 seq_br_type 7 Unconditional Call; Flow C 0x34da seq_branch_adr 34da 0x34da seq_en_micro 0 0ff3 0ff3 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0ff4 0ff4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xff6 seq_br_type 1 Branch True seq_branch_adr 0ff6 0x0ff6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_b_adr 0c GP0c val_rand a PASS_B_HIGH 0ff5 0ff5 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x104e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 104e 0x104e seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_a_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 0b GP0b val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0ff6 0ff6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0ff7 0ff7 seq_b_timing 0 Early Condition; Flow J cc=True 0xffe seq_br_type 1 Branch True seq_branch_adr 0ffe 0x0ffe seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 0ff8 0ff8 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0ff9 0ff9 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0ffa 0ffa fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0ffb 0ffb fiu_mem_start 12 start_lru_query; Flow J cc=False 0xff7 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0ff7 0x0ff7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 0ffc 0ffc seq_b_timing 0 Early Condition; Flow J cc=True 0x1002 seq_br_type 1 Branch True seq_branch_adr 1002 0x1002 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 0ffd 0ffd fiu_mem_start 12 start_lru_query; Flow J 0xffc seq_br_type 3 Unconditional Branch seq_branch_adr 0ffc 0x0ffc seq_en_micro 0 0ffe 0ffe fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fff 0fff fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1000 1000 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1001 1001 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xff5 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ff5 0x0ff5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 1002 1002 fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 1003 1003 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1004 1004 fiu_tivi_src 4 fiu_var; Flow J 0x100b ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 100b 0x100b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d val_alu_func 18 NOT_A_AND_B val_b_adr 30 VR11:10 val_frame 11 1005 1005 fiu_mem_start 11 start_tag_query; Flow J 0x1032 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1032 0x1032 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1006 1006 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1007 1007 fiu_mem_start 11 start_tag_query; Flow J 0x103a ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 103a 0x103a seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1008 1008 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1009 1009 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 100a 100a fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 100b 100b fiu_mem_start 11 start_tag_query; Flow C 0x34f3 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 100c 100c fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1006 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 100d 100d ioc_adrbs 2 typ ; Flow J cc=True 0x1006 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 100e 100e fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1015 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1015 0x1015 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 3b TR02:1b typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0d GP0d 100f 100f fiu_mem_start d start_physical_rd; Flow J cc=False 0x1013 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1013 0x1013 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 1010 1010 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1011 1011 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1006 seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 1012 1012 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1006 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1013 1013 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1006 seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1014 1014 fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1015 1015 seq_br_type 1 Branch True; Flow J cc=True 0x1017 seq_branch_adr 1017 0x1017 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 3c VR06:1c val_frame 6 1016 1016 seq_br_type 3 Unconditional Branch; Flow J 0x1014 seq_branch_adr 1014 0x1014 seq_en_micro 0 typ_c_adr 32 GP0d 1017 1017 fiu_mem_start d start_physical_rd; Flow J cc=True 0x1029 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1029 0x1029 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 1018 1018 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1027 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1027 0x1027 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1019 1019 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 1 101a 101a fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_alu_func 13 ONES val_rand 9 PASS_A_HIGH 101b 101b fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1025 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1025 0x1025 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 15 NOT_B typ_b_adr 0d GP0d 101c 101c fiu_fill_mode_src 0 ; Flow J cc=False 0x101f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 101f 0x101f seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 101d 101d fiu_fill_mode_src 0 ; Flow J cc=True 0x101e ; Flow J cc=#0x0 0x101e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 101e 0x101e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 101e 101e seq_b_timing 0 Early Condition; Flow J cc=True 0x101f ; Flow J cc=#0x0 0x1027 seq_br_type b Case False seq_branch_adr 1027 0x1027 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 101f 101f fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 1020 1020 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x1006 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1021 1021 seq_br_type 0 Branch False; Flow J cc=False 0x1006 seq_branch_adr 1006 0x1006 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 1022 1022 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1023 1023 ioc_load_wdr 0 ; Flow C 0x34da seq_br_type 7 Unconditional Call seq_branch_adr 34da 0x34da seq_en_micro 0 typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 1024 1024 ioc_load_wdr 0 ; Flow J 0x1006 seq_br_type 3 Unconditional Branch seq_branch_adr 1006 0x1006 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1025 1025 fiu_fill_mode_src 0 ; Flow J cc=False 0x1006 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_c_adr 32 GP0d typ_frame d val_b_adr 2f VR0d:0f val_c_adr 32 GP0d val_frame d 1026 1026 seq_b_timing 0 Early Condition; Flow J cc=True 0x1027 ; Flow J cc=#0x0 0x1027 seq_br_type b Case False seq_branch_adr 1027 0x1027 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1027 1027 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe8 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1028 1028 ioc_load_wdr 0 ; Flow J 0x1006 seq_br_type 3 Unconditional Branch seq_branch_adr 1006 0x1006 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1029 1029 fiu_mem_start d start_physical_rd seq_en_micro 0 102a 102a fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1027 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1027 0x1027 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 102b 102b fiu_len_fill_lit 07 sign-fill 0x7 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 102c 102c fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS 102d 102d fiu_fill_mode_src 0 ; Flow J cc=True 0x1025 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1025 0x1025 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 102e 102e fiu_fill_mode_src 0 ; Flow J cc=True 0x102f ; Flow J cc=#0x0 0x1030 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1030 0x1030 seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 102f 102f fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1030 1030 seq_b_timing 0 Early Condition; Flow J cc=True 0x1031 ; Flow J cc=#0x0 0x1027 seq_br_type b Case False seq_branch_adr 1027 0x1027 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1031 1031 fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1032 1032 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1006 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d 1033 1033 seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 1034 1034 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1006 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 1035 1035 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 1036 1036 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1006 seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_en_micro 0 1037 1037 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 2a TR09:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 1038 1038 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1006 seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1039 1039 fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 103a 103a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1006 seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 11 103b 103b seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 103c 103c fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1006 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1006 0x1006 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 103d 103d fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 103e 103e seq_b_timing 1 Latch Condition; Flow J cc=True 0x1006 seq_br_type 1 Branch True seq_branch_adr 1006 0x1006 seq_en_micro 0 103f 103f ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 1040 1040 seq_br_type 1 Branch True; Flow J cc=True 0x1006 seq_branch_adr 1006 0x1006 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 1041 1041 fiu_mem_start f start_physical_tag_rd; Flow J 0xfef ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fef 0x0fef seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1042 1042 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1043 1043 fiu_len_fill_lit 46 zero-fill 0x6 fiu_mem_start 2 start-rd fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR03:19 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA 1044 1044 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x104b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 104b 0x104b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_frame 12 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR04:02 val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 1045 1045 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1046 1046 fiu_mem_start 2 start-rd; Flow C 0x107c ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 107c 0x107c seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_frame 4 1047 1047 fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1048 1048 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 1049 1049 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 104a 104a seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 104b 104b fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0xfed ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0fed 0x0fed seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 39 VR03:19 val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_frame 3 104c 104c fiu_mem_start 15 setup_tag_read seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 104d 104d fiu_mem_start 15 setup_tag_read; Flow J 0xfed seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_c_adr 30 GP0f val_c_adr 30 GP0f 104e ; -------------------------------------------------------------------------------------- 104e ; Comes from: 104e ; 33db C True from color 0x0f07 104e ; 33fe C from color 0x0000 104e ; -------------------------------------------------------------------------------------- 104e 104e fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x106f fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 106f 0x106f seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 104f 104f fiu_mem_start 15 setup_tag_read; Flow J 0x1050 seq_br_type 2 Push (branch address) seq_branch_adr 1066 0x1066 seq_en_micro 0 1050 1050 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1054 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1054 0x1054 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1051 1051 fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x106f fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 106f 0x106f seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1052 1052 fiu_mem_start 15 setup_tag_read; Flow J 0x1053 seq_br_type 2 Push (branch address) seq_branch_adr 1067 0x1067 seq_en_micro 0 1053 1053 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1054 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1054 0x1054 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1054 1054 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1055 ; Flow J cc=#0x0 0x1056 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1056 0x1056 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_frame 12 1055 1055 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1056 1056 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1057 1057 fiu_mem_start 11 start_tag_query; Flow J 0x105e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105e 0x105e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1058 1058 fiu_mem_start 11 start_tag_query; Flow J 0x105e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105e 0x105e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1059 1059 fiu_mem_start 11 start_tag_query; Flow J 0x105e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105e 0x105e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 105a 105a fiu_mem_start 11 start_tag_query; Flow J 0x105e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105e 0x105e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 105b 105b fiu_mem_start 11 start_tag_query; Flow J 0x105e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105e 0x105e seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 105c 105c ioc_adrbs 1 val ; Flow J 0x3628 seq_br_type 3 Unconditional Branch seq_branch_adr 3628 0x3628 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 105d 105d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 105e 105e fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 105f 105f fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1065 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1065 0x1065 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 1060 1060 fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 1061 1061 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1 A_PLUS_B val_b_adr 0b GP0b 1062 1062 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x1065 seq_br_type 0 Branch False seq_branch_adr 1065 0x1065 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 1063 1063 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1065 seq_br_type 1 Branch True seq_branch_adr 1065 0x1065 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1064 1064 ioc_adrbs 1 val ; Flow J 0x3629 seq_br_type 3 Unconditional Branch seq_branch_adr 3629 0x3629 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1065 1065 ioc_adrbs 1 val ; Flow J 0x3628 seq_br_type 3 Unconditional Branch seq_branch_adr 3628 0x3628 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1066 1066 fiu_mem_start 2 start-rd; Flow J 0x1068 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1068 0x1068 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR02:11 val_frame 2 1067 1067 fiu_mem_start 2 start-rd; Flow J 0x1068 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1068 0x1068 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR02:19 val_frame 2 1068 1068 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 1069 1069 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 106a 106a fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 106b 106b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x106e seq_br_type 1 Branch True seq_branch_adr 106e 0x106e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0b GP0b val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 106c 106c fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 106d 106d ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_b_adr 0c GP0c 106e 106e fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362c 0x362c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 106f ; -------------------------------------------------------------------------------------- 106f ; Comes from: 106f ; 104e C True from color 0x0fd2 106f ; 1051 C True from color 0x0fd2 106f ; -------------------------------------------------------------------------------------- 106f 106f fiu_mem_start 15 setup_tag_read; Flow J cc=True 0x107d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 107d 0x107d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 10 NOT_A typ_c_adr 34 GP0b val_c_adr 34 GP0b 1070 1070 ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 1071 1071 ioc_fiubs 1 val ; Flow C 0x3691 seq_br_type 7 Unconditional Call seq_branch_adr 3691 0x3691 seq_en_micro 0 val_a_adr 23 VR04:03 val_c_adr 1c VR04:03 val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1072 1072 seq_br_type 0 Branch False; Flow J cc=False 0x1074 seq_branch_adr 1074 0x1074 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 1073 1073 fiu_mem_start f start_physical_tag_rd; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 1074 1074 fiu_mem_start 11 start_tag_query; Flow J cc=True 0x1078 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1078 0x1078 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 1075 1075 seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 1076 1076 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 1077 1077 fiu_mem_start f start_physical_tag_rd; Flow R cc=True ; Flow J cc=False 0x1079 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 1079 0x1079 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1078 1078 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED 1079 1079 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 107a 107a ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 2 107b 107b seq_br_type 7 Unconditional Call; Flow C 0x34da seq_branch_adr 34da 0x34da seq_en_micro 0 107c ; -------------------------------------------------------------------------------------- 107c ; Comes from: 107c ; 1046 C from color 0x0fd2 107c ; -------------------------------------------------------------------------------------- 107c 107c seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 107d 107d fiu_tivi_src 8 type_var; Flow C cc=True 0x2a84 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 0b GP0b 107e 107e fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 107f 107f seq_en_micro 0 1080 1080 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 1081 1081 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fc fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1082 1082 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1083 1083 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1087 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1087 0x1087 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 1084 1084 fiu_mem_start 12 start_lru_query; Flow J cc=True 0x1080 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1080 0x1080 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 1085 1085 seq_br_type 1 Branch True; Flow J cc=True 0x1080 seq_branch_adr 1080 0x1080 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 1086 1086 ioc_tvbs 2 fiu+val; Flow J 0x1080 seq_br_type 3 Unconditional Branch seq_branch_adr 1080 0x1080 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1087 1087 fiu_load_var 1 hold_var; Flow J cc=True 0x108a fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 108a 0x108a seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 1088 1088 seq_br_type 1 Branch True; Flow J cc=True 0x108a seq_branch_adr 108a 0x108a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 1089 1089 ioc_tvbs 2 fiu+val; Flow J 0x108a seq_br_type 3 Unconditional Branch seq_branch_adr 108a 0x108a seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 108a 108a fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f 108b 108b fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x108d fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 108d 0x108d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS 108c 108c fiu_mem_start 3 start-wr; Flow J 0x3b5d ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b5d 0x3b5d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 108d 108d fiu_mem_start 3 start-wr; Flow C 0x211 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0211 0x0211 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 0b GP0b 108e ; -------------------------------------------------------------------------------------- 108e ; 0x03bf Declare_Variable Access 108e ; -------------------------------------------------------------------------------------- 108e MACRO_Declare_Variable_Access: 108e 108e dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 108e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR10:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 108f 108f <halt> ; Flow R 1090 ; -------------------------------------------------------------------------------------- 1090 ; 0x03be Declare_Variable Access,Visible 1090 ; -------------------------------------------------------------------------------------- 1090 MACRO_Declare_Variable_Access,Visible: 1090 1090 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1090 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 1091 1091 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR07:1e typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1092 ; -------------------------------------------------------------------------------------- 1092 ; 0x03bd Declare_Variable Access,Duplicate 1092 ; -------------------------------------------------------------------------------------- 1092 MACRO_Declare_Variable_Access,Duplicate: 1092 1092 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1092 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1093 1093 <halt> ; Flow R 1094 ; -------------------------------------------------------------------------------------- 1094 ; 0x039f Declare_Variable Heap_Access 1094 ; -------------------------------------------------------------------------------------- 1094 MACRO_Declare_Variable_Heap_Access: 1094 1094 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1094 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR18:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1095 1095 <halt> ; Flow R 1096 ; -------------------------------------------------------------------------------------- 1096 ; 0x039e Declare_Variable Heap_Access,Visible 1096 ; -------------------------------------------------------------------------------------- 1096 MACRO_Declare_Variable_Heap_Access,Visible: 1096 1096 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1096 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 1097 1097 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR11:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1098 ; -------------------------------------------------------------------------------------- 1098 ; 0x039d Declare_Variable Heap_Access,Duplicate 1098 ; -------------------------------------------------------------------------------------- 1098 MACRO_Declare_Variable_Heap_Access,Duplicate: 1098 1098 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1098 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1099 ; -------------------------------------------------------------------------------------- 1099 ; Comes from: 1099 ; 10a8 C from color MACRO_Declare_Variable_Access,By_Allocation 1099 ; 1100 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 1099 ; 11e4 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 1099 ; 1242 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 1099 ; -------------------------------------------------------------------------------------- 1099 1099 <default> 109a 109a fiu_load_tar 1 hold_tar; Flow J 0x109d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 109d 0x109d typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 109b ; -------------------------------------------------------------------------------------- 109b ; Comes from: 109b ; 10b0 C from color 0x10aa 109b ; 1108 C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 109b ; 11ec C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 109b ; 124a C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 109b ; -------------------------------------------------------------------------------------- 109b 109b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 109c 109c fiu_load_tar 1 hold_tar; Flow J 0x109d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 109d 0x109d typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 109d 109d ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 01 GP01 109e 109e fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 109f 0x109f seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 109f 109f seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 10a0 ; -------------------------------------------------------------------------------------- 10a0 ; Comes from: 10a0 ; 10ac C from color 0x10aa 10a0 ; 1104 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 10a0 ; 11e8 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 10a0 ; 1246 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 10a0 ; -------------------------------------------------------------------------------------- 10a0 10a0 <default> 10a1 10a1 fiu_load_tar 1 hold_tar; Flow J 0x10a4 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10a4 0x10a4 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10a2 ; -------------------------------------------------------------------------------------- 10a2 ; Comes from: 10a2 ; 10b4 C from color 0x10aa 10a2 ; 110c C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 10a2 ; 11f0 C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 10a2 ; 124e C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 10a2 ; -------------------------------------------------------------------------------------- 10a2 10a2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 10a3 10a3 fiu_load_tar 1 hold_tar; Flow J 0x10a4 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10a4 0x10a4 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10a4 10a4 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 10a5 10a5 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 10a6 0x10a6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10a6 10a6 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 10a7 10a7 <halt> ; Flow R 10a8 ; -------------------------------------------------------------------------------------- 10a8 ; 0x03bc Declare_Variable Access,By_Allocation 10a8 ; -------------------------------------------------------------------------------------- 10a8 MACRO_Declare_Variable_Access,By_Allocation: 10a8 10a8 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10a9 10a9 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b8 0x10b8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10aa 10aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d3 0x10d3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10ab 10ab seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 10ac ; -------------------------------------------------------------------------------------- 10ac ; 0x039c Declare_Variable Heap_Access,By_Allocation 10ac ; -------------------------------------------------------------------------------------- 10ac MACRO_Declare_Variable_Heap_Access,By_Allocation: 10ac 10ac dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10ac fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10ad 10ad fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b8 0x10b8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10ae 10ae fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d3 0x10d3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10af 10af seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 10b0 ; -------------------------------------------------------------------------------------- 10b0 ; 0x03bb Declare_Variable Access,Visible,By_Allocation 10b0 ; -------------------------------------------------------------------------------------- 10b0 MACRO_Declare_Variable_Access,Visible,By_Allocation: 10b0 10b0 dispatch_brk_class 4 ; Flow C 0x109b dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10b0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109b 0x109b typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10b1 10b1 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b8 0x10b8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10b2 10b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d3 0x10d3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10b3 10b3 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 10b4 ; -------------------------------------------------------------------------------------- 10b4 ; 0x039b Declare_Variable Heap_Access,Visible,By_Allocation 10b4 ; -------------------------------------------------------------------------------------- 10b4 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation: 10b4 10b4 dispatch_brk_class 4 ; Flow C 0x10a2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10b4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a2 0x10a2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10b5 10b5 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b8 0x10b8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10b6 10b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d3 0x10d3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10b7 10b7 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 10b8 ; -------------------------------------------------------------------------------------- 10b8 ; Comes from: 10b8 ; 10a9 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation 10b8 ; -------------------------------------------------------------------------------------- 10b8 10b8 seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10b9 10b9 seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10ba 10ba seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10bb 10bb seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10bc 10bc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10bd 10bd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10be 10be seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10bf 10bf seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c0 10c0 seq_br_type 3 Unconditional Branch; Flow J 0x10c8 seq_branch_adr 10c8 0x10c8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c1 10c1 seq_br_type 3 Unconditional Branch; Flow J 0x10cc seq_branch_adr 10cc 0x10cc val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c2 10c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c3 10c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c4 10c4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c5 10c5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10c8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c8 0x10c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR05:00 typ_b_adr 01 GP01 typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c6 10c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10c8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c8 0x10c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2f TR11:0f typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c7 10c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c8 0x10c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2e TR11:0e typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c8 10c8 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10c9 10c9 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 10ca 0x10ca seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 10ca 10ca seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 10cb 10cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10cc 10cc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 10cd 10cd fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10ce 10ce seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 10cf 10cf typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 10d0 10d0 ioc_fiubs 2 typ typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_source 0 FIU_BUS 10d1 10d1 seq_br_type 7 Unconditional Call; Flow C 0x29b5 seq_branch_adr 29b5 0x29b5 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10d2 10d2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10d3 10d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x10d5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10d5 0x10d5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 10d4 10d4 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 10d5 ; -------------------------------------------------------------------------------------- 10d5 ; Comes from: 10d5 ; 10d3 C #0x0 from color 0x10aa 10d5 ; -------------------------------------------------------------------------------------- 10d5 10d5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10d6 10d6 ioc_fiubs 0 fiu ; Flow R cc=False ; Flow J cc=True 0x10dd seq_br_type 9 Return False seq_branch_adr 10dd 0x10dd seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 10d7 10d7 ioc_fiubs 2 typ ; Flow J 0x10f1 seq_br_type 3 Unconditional Branch seq_branch_adr 10f1 0x10f1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 27 TR09:07 typ_frame 9 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 10d8 10d8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 10d9 10d9 <default> 10da 10da fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10db 10db seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 10dc 10dc seq_br_type 3 Unconditional Branch; Flow J 0x10f2 seq_branch_adr 10f2 0x10f2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 10dd 10dd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x10e2 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 10e2 0x10e2 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10de 10de fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10df 10df val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 10e0 10e0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10e1 10e1 seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 10e2 10e2 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10e3 10e3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 10e4 10e4 fiu_fill_mode_src 0 ; Flow J cc=False 0x10ee fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 10ee 0x10ee seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 10e5 10e5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 10e6 10e6 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 10e7 10e7 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 10e8 0x10e8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 10e8 10e8 seq_b_timing 1 Latch Condition; Flow J cc=True 0x10eb seq_br_type 1 Branch True seq_branch_adr 10eb 0x10eb 10e9 10e9 seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 10ea 10ea fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10eb 10eb fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x118c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 118c 0x118c typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 10ec 10ec ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 10ed 10ed fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10ee 10ee fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 10ef 10ef fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10f0 10f0 fiu_load_var 1 hold_var; Flow J 0x10e6 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 10e6 0x10e6 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 10f1 10f1 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 10f2 10f2 ioc_fiubs 0 fiu ; Flow J cc=False 0x10f5 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 10f5 0x10f5 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10f3 10f3 ioc_fiubs 2 typ ; Flow C 0x2256 seq_br_type 7 Unconditional Call seq_branch_adr 2256 0x2256 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10f4 10f4 ioc_fiubs 2 typ ; Flow C cc=True 0x10fe seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 10fe 0x10fe seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 10f5 10f5 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 10f6 0x10f6 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 10f6 10f6 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10f7 10f7 ioc_fiubs 2 typ ; Flow C 0x2228 seq_br_type 7 Unconditional Call seq_branch_adr 2228 0x2228 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10f8 10f8 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 10f9 0x10f9 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_source 0 FIU_BUS 10f9 10f9 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10fa 10fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2248 seq_br_type 5 Call True seq_branch_adr 2248 0x2248 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 04 GP04 10fb 10fb fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 10fc 0x10fc seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL 10fc 10fc seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 10fd 10fd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10fe ; -------------------------------------------------------------------------------------- 10fe ; Comes from: 10fe ; 10f4 C True from color 0x10d7 10fe ; -------------------------------------------------------------------------------------- 10fe 10fe seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 10ff 10ff seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1100 ; -------------------------------------------------------------------------------------- 1100 ; 0x03b6 Declare_Variable Access,By_Allocation,With_Value 1100 ; -------------------------------------------------------------------------------------- 1100 MACRO_Declare_Variable_Access,By_Allocation,With_Value: 1100 1100 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1100 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1101 1101 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110f 0x110f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1102 1102 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1103 1103 <halt> ; Flow R 1104 ; -------------------------------------------------------------------------------------- 1104 ; 0x0396 Declare_Variable Heap_Access,By_Allocation,With_Value 1104 ; -------------------------------------------------------------------------------------- 1104 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value: 1104 1104 dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1104 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1105 1105 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110f 0x110f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1106 1106 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1107 1107 <halt> ; Flow R 1108 ; -------------------------------------------------------------------------------------- 1108 ; 0x03b5 Declare_Variable Access,Visible,By_Allocation,With_Value 1108 ; -------------------------------------------------------------------------------------- 1108 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value: 1108 1108 dispatch_brk_class 4 ; Flow C 0x109b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1108 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109b 0x109b typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 1109 1109 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110f 0x110f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 110a 110a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 110b 110b <halt> ; Flow R 110c ; -------------------------------------------------------------------------------------- 110c ; 0x0395 Declare_Variable Heap_Access,Visible,By_Allocation,With_Value 110c ; -------------------------------------------------------------------------------------- 110c MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value: 110c 110c dispatch_brk_class 4 ; Flow C 0x10a2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 110c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a2 0x10a2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 110d 110d fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110f 0x110f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 110e 110e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 110f ; -------------------------------------------------------------------------------------- 110f ; Comes from: 110f ; 1101 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 110f ; 1105 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 110f ; 1109 C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 110f ; 110d C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 110f ; -------------------------------------------------------------------------------------- 110f 110f ioc_fiubs 1 val ; Flow J 0x1123 seq_br_type 3 Unconditional Branch seq_branch_adr 1123 0x1123 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 1110 1110 ioc_fiubs 1 val ; Flow J 0x1131 seq_br_type 3 Unconditional Branch seq_branch_adr 1131 0x1131 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 1111 1111 seq_br_type 3 Unconditional Branch; Flow J 0x113f seq_branch_adr 113f 0x113f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1112 1112 seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 1113 1113 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1114 1114 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1115 1115 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1116 1116 seq_br_type 3 Unconditional Branch; Flow J 0x1149 seq_branch_adr 1149 0x1149 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 1117 1117 seq_br_type 3 Unconditional Branch; Flow J 0x115a seq_branch_adr 115a 0x115a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 1118 1118 ioc_fiubs 0 fiu ; Flow J 0x1161 seq_br_type 3 Unconditional Branch seq_branch_adr 1161 0x1161 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1119 1119 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 111a 111a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 111b 111b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 111c 111c seq_br_type 3 Unconditional Branch; Flow J 0x1171 seq_branch_adr 1171 0x1171 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH 111d 111d ioc_fiubs 1 val ; Flow J 0x11b4 seq_br_type 3 Unconditional Branch seq_branch_adr 11b4 0x11b4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 11 111e 111e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 111f 111f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand a PASS_B_HIGH 1120 1120 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1121 1121 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1122 1122 seq_br_type 3 Unconditional Branch; Flow J 0x11b4 seq_branch_adr 11b4 0x11b4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 1123 1123 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x112d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 112d 0x112d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1124 1124 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1125 1125 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1126 1126 fiu_fill_mode_src 0 ; Flow J cc=False 0x112a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 112a 0x112a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1127 1127 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1128 1128 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1129 1129 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 112a 112a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 112b 112b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 112c 112c fiu_mem_start 4 continue; Flow J 0x1128 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1128 0x1128 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 112d 112d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 112e 112e <default> 112f 112f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1130 1130 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 1131 1131 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 1132 1132 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1136 seq_br_type 1 Branch True seq_branch_adr 1136 0x1136 typ_c_adr 3c GP03 val_c_adr 3c GP03 1133 1133 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1138 seq_br_type 1 Branch True seq_branch_adr 1138 0x1138 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1134 1134 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1135 1135 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1126 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1126 0x1126 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1136 1136 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1138 seq_br_type 1 Branch True seq_branch_adr 1138 0x1138 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 1137 1137 seq_br_type 1 Branch True; Flow J cc=True 0x1134 seq_branch_adr 1134 0x1134 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1138 1138 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1139 1139 seq_b_timing 1 Latch Condition; Flow J cc=True 0x113c seq_br_type 1 Branch True seq_branch_adr 113c 0x113c 113a 113a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 113b 113b seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 113c 113c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3278 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 113d 113d seq_br_type 5 Call True; Flow C cc=True 0x326e seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 113e 113e seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 113f 113f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1142 seq_br_type 1 Branch True seq_branch_adr 1142 0x1142 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1140 1140 seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1141 1141 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1144 seq_br_type 0 Branch False seq_branch_adr 1144 0x1144 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1142 1142 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1143 1143 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1126 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1126 0x1126 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1144 1144 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1145 1145 <default> 1146 1146 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1147 1147 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a 1148 1148 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1149 1149 seq_b_timing 1 Latch Condition; Flow J cc=True 0x114c seq_br_type 1 Branch True seq_branch_adr 114c 0x114c typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 114a 114a seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 114b 114b seq_b_timing 1 Latch Condition; Flow J cc=False 0x1144 seq_br_type 0 Branch False seq_branch_adr 1144 0x1144 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 114c 114c fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 114d 114d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_b_adr 02 GP02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 114e 114e fiu_fill_mode_src 0 ; Flow J cc=False 0x1152 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1152 0x1152 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 114f 114f fiu_fill_mode_src 0 ; Flow C cc=True 0x1156 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1156 0x1156 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1150 1150 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1151 1151 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1152 1152 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1153 1153 fiu_fill_mode_src 0 ; Flow C cc=True 0x1156 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1156 0x1156 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1154 1154 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR 1155 1155 ioc_load_wdr 0 ; Flow J 0x1151 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1151 0x1151 val_b_adr 04 GP04 1156 ; -------------------------------------------------------------------------------------- 1156 ; Comes from: 1156 ; 114f C True from color 0x110f 1156 ; 1153 C True from color 0x110f 1156 ; -------------------------------------------------------------------------------------- 1156 1156 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32b1 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1157 1157 fiu_fill_mode_src 0 ; Flow J cc=False 0x1159 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1159 0x1159 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1158 1158 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1159 1159 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 115a 115a ioc_fiubs 0 fiu ; Flow C cc=False 0x1160 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1160 0x1160 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 115b 115b fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 115c 115c ioc_fiubs 1 val ; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 115d 115d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 115e 115e seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 115f 115f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1160 ; -------------------------------------------------------------------------------------- 1160 ; Comes from: 1160 ; 115a C False from color 0x1117 1160 ; -------------------------------------------------------------------------------------- 1160 1160 fiu_mem_start 2 start-rd; Flow J 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1161 1161 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x116a fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 116a 0x116a typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1162 1162 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1163 1163 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x116b seq_br_type f Unconditional Case Call seq_branch_adr 116b 0x116b seq_en_micro 0 1164 1164 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1165 1165 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1166 1166 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1167 1167 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1168 1168 ioc_load_wdr 0 ; Flow C 0x1eee ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1169 1169 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 116a ; -------------------------------------------------------------------------------------- 116a ; Comes from: 116a ; 1161 C False from color 0x1118 116a ; -------------------------------------------------------------------------------------- 116a 116a fiu_mem_start 2 start-rd; Flow J 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 116b ; -------------------------------------------------------------------------------------- 116b ; Comes from: 116b ; 1163 C #0x0 from color 0x1118 116b ; -------------------------------------------------------------------------------------- 116b 116b seq_br_type 3 Unconditional Branch; Flow J 0x116f seq_branch_adr 116f 0x116f typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 116c 116c fiu_load_oreg 1 hold_oreg; Flow C 0x24e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 24e5 0x24e5 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 116d 116d seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 116e 0x116e 116e 116e seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 116f 116f ioc_fiubs 2 typ ; Flow C 0x2458 seq_br_type 7 Unconditional Call seq_branch_adr 2458 0x2458 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 01 GP01 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1170 1170 seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1171 1171 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x11b3 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11b3 0x11b3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1172 1172 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1173 1173 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x119a seq_br_type f Unconditional Case Call seq_branch_adr 119a 0x119a seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 1174 1174 fiu_load_var 1 hold_var; Flow J cc=True 0x117a fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 117a 0x117a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 05 GP05 typ_b_adr 01 GP01 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1175 1175 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1176 1176 seq_br_type 1 Branch True; Flow J cc=True 0x1196 seq_branch_adr 1196 0x1196 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 1177 1177 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1178 1178 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1196 seq_br_type 1 Branch True seq_branch_adr 1196 0x1196 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 1179 1179 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 117a 117a fiu_load_var 1 hold_var; Flow J cc=True 0x117e fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 117e 0x117e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 117b 117b ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 117c 117c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 117d 117d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 117e 117e val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 117f 117f fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1180 1180 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 05 GP05 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1181 1181 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 1182 1182 fiu_fill_mode_src 0 ; Flow J cc=True 0x1186 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1186 0x1186 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1183 1183 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 1184 1184 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1185 1185 fiu_load_var 1 hold_var; Flow J 0x1187 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1187 0x1187 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1186 1186 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1187 1187 ioc_load_wdr 0 ; Flow J cc=True 0x1191 ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 1191 0x1191 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1188 1188 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x118c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 118c 0x118c typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1189 1189 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 118a 118a seq_br_type 1 Branch True; Flow J cc=True 0x1193 seq_branch_adr 1193 0x1193 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 118b 118b seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 118c ; -------------------------------------------------------------------------------------- 118c ; Comes from: 118c ; 10eb C from color 0x10d6 118c ; -------------------------------------------------------------------------------------- 118c 118c fiu_fill_mode_src 0 ; Flow J cc=True 0x1190 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1190 0x1190 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 39 GP06 val_c_source 0 FIU_BUS 118d 118d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 118e 118e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 30 GP0f typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 118f 118f fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1190 1190 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1191 1191 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1192 1192 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 1193 1193 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1194 1194 ioc_fiubs 1 val ; Flow C 0x228c seq_br_type 7 Unconditional Call seq_branch_adr 228c 0x228c typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1195 1195 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1196 1196 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1197 1197 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1199 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1199 0x1199 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1198 1198 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eee fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1199 1199 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 119a ; -------------------------------------------------------------------------------------- 119a ; Comes from: 119a ; 1173 C #0x0 from color 0x111c 119a ; -------------------------------------------------------------------------------------- 119a 119a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x119c fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 119c 0x119c typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 119b 119b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x11a2 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11a2 0x11a2 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 119c 119c fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 119d 119d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 119e 119e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 119f 0x119f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 119f 119f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 11a0 11a0 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11a1 11a1 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11a2 11a2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 11a3 11a3 fiu_fill_mode_src 0 ; Flow C 0x11a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 11a8 0x11a8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 11a4 11a4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 11a5 11a5 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 11a6 0x11a6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 11a6 11a6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 11a7 11a7 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 11a8 ; -------------------------------------------------------------------------------------- 11a8 ; Comes from: 11a8 ; 11a3 C from color 0x119b 11a8 ; -------------------------------------------------------------------------------------- 11a8 11a8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11b0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11b0 0x11b0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 11a9 11a9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11aa 11aa fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11ab 0x11ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11ab 11ab fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 11ac 11ac fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11ae seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11ae 0x11ae seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11ad 11ad fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11ae 11ae fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11af 11af fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11b0 11b0 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11b1 11b1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11b2 11b2 fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True ; Flow J cc=False 0x11ab fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11ab 0x11ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11b3 ; -------------------------------------------------------------------------------------- 11b3 ; Comes from: 11b3 ; 1171 C False from color 0x111c 11b3 ; 11b4 C False from color 0x111d 11b3 ; -------------------------------------------------------------------------------------- 11b3 11b3 fiu_mem_start 2 start-rd; Flow J 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11b4 11b4 ioc_fiubs 2 typ ; Flow C cc=False 0x11b3 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11b3 0x11b3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 11b5 11b5 ioc_fiubs 2 typ ; Flow C cc=True 0x32a9 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11b6 11b6 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11c7 seq_br_type 1 Branch True seq_branch_adr 11c7 0x11c7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 11b7 11b7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1194 seq_br_type 1 Branch True seq_branch_adr 1194 0x1194 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 11b8 11b8 seq_br_type 7 Unconditional Call; Flow C 0x2296 seq_branch_adr 2296 0x2296 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11b9 11b9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11bb seq_br_type 1 Branch True seq_branch_adr 11bb 0x11bb val_c_adr 3c GP03 val_c_mux_sel 2 ALU 11ba 11ba seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 11bb 11bb ioc_fiubs 2 typ ; Flow C 0x2256 seq_br_type 7 Unconditional Call seq_branch_adr 2256 0x2256 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11bc 11bc seq_br_type 1 Branch True; Flow J cc=True 0x1196 seq_branch_adr 1196 0x1196 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 11bd 11bd seq_br_type 3 Unconditional Branch; Flow J 0x1196 seq_branch_adr 1196 0x1196 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 11be 11be ioc_fiubs 1 val ; Flow C 0x226d seq_br_type 7 Unconditional Call seq_branch_adr 226d 0x226d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 11bf 11bf seq_b_timing 1 Latch Condition; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11c0 11c0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x11d6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 11d6 0x11d6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 11c1 11c1 ioc_fiubs 2 typ ; Flow C cc=True 0x11e1 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 11e1 0x11e1 typ_a_adr 17 LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11c2 11c2 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11c3 11c3 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11c4 11c4 ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11c5 11c5 seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11c6 11c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11c7 11c7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11be seq_br_type 1 Branch True seq_branch_adr 11be 0x11be typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11c8 11c8 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11c9 11c9 ioc_fiubs 2 typ ; Flow C cc=False 0x3272 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11ca 11ca fiu_mem_start 2 start-rd; Flow C cc=True 0x11e1 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 11e1 0x11e1 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11cb 11cb <default> 11cc 11cc fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 11cd 11cd seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11ce 11ce fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11cf 11cf ioc_fiubs 2 typ ; Flow C 0x2228 seq_br_type 7 Unconditional Call seq_branch_adr 2228 0x2228 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11d0 11d0 fiu_load_tar 1 hold_tar; Flow J cc=True 0x11d3 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 11d3 0x11d3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11d1 11d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eee fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11d2 11d2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11d3 11d3 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11d4 11d4 seq_br_type 7 Unconditional Call; Flow C 0x2248 seq_branch_adr 2248 0x2248 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11d5 11d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11d6 ; -------------------------------------------------------------------------------------- 11d6 ; Comes from: 11d6 ; 11c0 C from color 0x111d 11d6 ; -------------------------------------------------------------------------------------- 11d6 11d6 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x11da seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 11da 0x11da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 11d7 11d7 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11d8 11d8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11d9 11d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x11dc fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11dc 0x11dc seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11da 11da fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11db 11db fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11dc 11dc seq_br_type 0 Branch False; Flow J cc=False 0x11de seq_branch_adr 11de 0x11de seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_rand c START_MULTIPLY 11dd 11dd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 11de 11de seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 11df 11df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 11e0 11e0 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 11e1 ; -------------------------------------------------------------------------------------- 11e1 ; Comes from: 11e1 ; 11c1 C True from color 0x111d 11e1 ; 11ca C True from color 0x111d 11e1 ; -------------------------------------------------------------------------------------- 11e1 11e1 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 11e2 11e2 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 11e3 11e3 <halt> ; Flow R 11e4 ; -------------------------------------------------------------------------------------- 11e4 ; 0x03b8 Declare_Variable Access,By_Allocation,With_Subtype 11e4 ; -------------------------------------------------------------------------------------- 11e4 MACRO_Declare_Variable_Access,By_Allocation,With_Subtype: 11e4 11e4 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 11e4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 11e5 11e5 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f3 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f3 0x11f3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11e6 11e6 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 11e7 11e7 <halt> ; Flow R 11e8 ; -------------------------------------------------------------------------------------- 11e8 ; 0x0398 Declare_Variable Heap_Access,By_Allocation,With_Subtype 11e8 ; -------------------------------------------------------------------------------------- 11e8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype: 11e8 11e8 dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 11e8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 11e9 11e9 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f3 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f3 0x11f3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11ea 11ea seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 11eb 11eb <halt> ; Flow R 11ec ; -------------------------------------------------------------------------------------- 11ec ; 0x03b7 Declare_Variable Access,Visible,By_Allocation,With_Subtype 11ec ; -------------------------------------------------------------------------------------- 11ec MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype: 11ec 11ec dispatch_brk_class 4 ; Flow C 0x109b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 11ec fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109b 0x109b typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 11ed 11ed fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f3 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f3 0x11f3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11ee 11ee seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 11ef 11ef <halt> ; Flow R 11f0 ; -------------------------------------------------------------------------------------- 11f0 ; 0x0397 Declare_Variable Heap_Access,Visible,By_Allocation,With_Subtype 11f0 ; -------------------------------------------------------------------------------------- 11f0 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype: 11f0 11f0 dispatch_brk_class 4 ; Flow C 0x10a2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 11f0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a2 0x10a2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 11f1 11f1 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f3 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f3 0x11f3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11f2 11f2 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 11f3 ; -------------------------------------------------------------------------------------- 11f3 ; Comes from: 11f3 ; 11e5 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 11f3 ; 11e9 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 11f3 ; 11ed C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 11f3 ; 11f1 C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 11f3 ; -------------------------------------------------------------------------------------- 11f3 11f3 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11f4 11f4 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11f5 11f5 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11f6 11f6 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11f7 11f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11f8 11f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11f9 11f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11fa 11fa seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11fb 11fb seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 11fc 11fc seq_br_type 3 Unconditional Branch; Flow J 0x1207 seq_branch_adr 1207 0x1207 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 11fd 11fd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11fe 11fe seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11ff 11ff seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1200 1200 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x120e fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 120e 0x120e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_frame 2 1201 1201 fiu_load_var 1 hold_var; Flow R cc=False ; Flow J cc=True 0x122c fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 122c 0x122c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 11 1202 1202 fiu_mem_start 9 start_continue_if_true; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1203 0x1203 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR 1203 1203 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH 1204 1204 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1205 1205 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1206 1206 seq_br_type 3 Unconditional Branch; Flow J 0x122c seq_branch_adr 122c 0x122c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1207 1207 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1208 1208 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1209 1209 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 120a 120a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 120b 120b fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 120c 120c fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 120d 120d seq_br_type 3 Unconditional Branch; Flow J 0x10cf seq_branch_adr 10cf 0x10cf seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 120e 120e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 120f 120f fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1210 1210 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1211 1211 fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1212 1212 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1213 1213 fiu_load_var 1 hold_var; Flow J cc=True 0x1219 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1219 0x1219 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1214 1214 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1215 1215 ioc_fiubs 0 fiu ; Flow C cc=False 0x32ac ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 1216 1216 seq_br_type 2 Push (branch address); Flow J 0x1217 seq_branch_adr 329c 0x329c typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1217 1217 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x121e fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 121e 0x121e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 06 GP06 val_a_adr 03 GP03 1218 1218 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1219 1219 fiu_mem_start 2 start-rd; Flow C cc=False 0x32ac ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 121a 121a seq_br_type 2 Push (branch address); Flow J 0x121b seq_branch_adr 329c 0x329c val_c_adr 3b GP04 val_c_mux_sel 2 ALU 121b 121b fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 121c 121c seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 121d 121d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x121f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 121f 0x121f seq_en_micro 0 val_a_adr 03 GP03 121e 121e fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x1220 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 9 Return False seq_branch_adr 1220 0x1220 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 121f 121f seq_br_type 3 Unconditional Branch; Flow J 0x1220 seq_branch_adr 1220 0x1220 val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 1220 1220 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3596 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A 1221 1221 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1222 1222 fiu_fill_mode_src 0 ; Flow J cc=False 0x1229 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1229 0x1229 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1223 1223 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1224 1224 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 1225 1225 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1226 0x1226 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 1226 1226 seq_b_timing 1 Latch Condition; Flow J cc=True 0x10eb seq_br_type 1 Branch True seq_branch_adr 10eb 0x10eb 1227 1227 seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1228 1228 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1229 1229 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 122a 122a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 122b 122b fiu_load_var 1 hold_var; Flow J 0x1224 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1224 0x1224 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 122c 122c fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 122d 122d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 122e 122e ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 122f 122f fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1230 1230 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1231 1231 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1239 seq_br_type 1 Branch True seq_branch_adr 1239 0x1239 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 05 GP05 val_alu_func 0 PASS_A 1232 1232 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1233 1233 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1234 1234 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1235 1235 seq_br_type 7 Unconditional Call; Flow C 0x2228 seq_branch_adr 2228 0x2228 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1236 1236 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1237 0x1237 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1237 1237 seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1238 1238 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1239 1239 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 123a 123a val_a_adr 04 GP04 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 123b 123b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 123c 123c fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 123d 123d seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 123e 123e seq_br_type 7 Unconditional Call; Flow C 0x2228 seq_branch_adr 2228 0x2228 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 123f 123f seq_br_type 7 Unconditional Call; Flow C 0x2248 seq_branch_adr 2248 0x2248 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1240 1240 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1241 1241 <halt> ; Flow R 1242 ; -------------------------------------------------------------------------------------- 1242 ; 0x03ba Declare_Variable Access,By_Allocation,With_Constraint 1242 ; -------------------------------------------------------------------------------------- 1242 MACRO_Declare_Variable_Access,By_Allocation,With_Constraint: 1242 1242 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1242 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1243 1243 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1251 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1251 0x1251 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1244 1244 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1245 1245 <halt> ; Flow R 1246 ; -------------------------------------------------------------------------------------- 1246 ; 0x039a Declare_Variable Heap_Access,By_Allocation,With_Constraint 1246 ; -------------------------------------------------------------------------------------- 1246 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint: 1246 1246 dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1246 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1247 1247 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1251 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1251 0x1251 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1248 1248 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1249 1249 <halt> ; Flow R 124a ; -------------------------------------------------------------------------------------- 124a ; 0x03b9 Declare_Variable Access,Visible,By_Allocation,With_Constraint 124a ; -------------------------------------------------------------------------------------- 124a MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint: 124a 124a dispatch_brk_class 4 ; Flow C 0x109b dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 124a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109b 0x109b typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 124b 124b fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1251 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1251 0x1251 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 124c 124c seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 124d 124d <halt> ; Flow R 124e ; -------------------------------------------------------------------------------------- 124e ; 0x0399 Declare_Variable Heap_Access,Visible,By_Allocation,With_Constraint 124e ; -------------------------------------------------------------------------------------- 124e MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint: 124e 124e dispatch_brk_class 4 ; Flow C 0x10a2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 124e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a2 0x10a2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 124f 124f fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1251 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1251 0x1251 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1250 1250 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1251 ; -------------------------------------------------------------------------------------- 1251 ; Comes from: 1251 ; 1243 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 1251 ; 1247 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 1251 ; 124b C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 1251 ; 124f C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 1251 ; -------------------------------------------------------------------------------------- 1251 1251 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1252 1252 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1253 1253 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1254 1254 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1255 1255 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1256 1256 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1257 1257 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1258 1258 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1259 1259 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 125a 125a seq_br_type 3 Unconditional Branch; Flow J 0x1261 seq_branch_adr 1261 0x1261 125b 125b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125c 125c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125d 125d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125e 125e fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x127b ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 127b 0x127b seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 125f 125f fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x128e ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 128e 0x128e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1260 1260 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_random 05 ? 1261 1261 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1262 1262 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 1263 1263 seq_b_timing 0 Early Condition; Flow J cc=True 0x126e seq_br_type 1 Branch True seq_branch_adr 126e 0x126e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1264 1264 ioc_fiubs 1 val ; Flow J 0x1265 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 1268 0x1268 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1265 1265 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2482 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2482 0x2482 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR05:00 typ_c_adr 37 GP08 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 1266 1266 seq_br_type 1 Branch True; Flow J cc=True 0x2482 seq_branch_adr 2482 0x2482 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 1267 1267 seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 1268 1268 ioc_load_wdr 0 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1269 1269 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 126a 126a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 126b 126b ioc_tvbs 2 fiu+val; Flow C cc=True 0x2a2e seq_br_type 5 Call True seq_branch_adr 2a2e 0x2a2e seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 126c 126c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 126d 126d fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x1270 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1270 0x1270 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 126e 126e fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 126f 126f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x1270 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1270 0x1270 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 1270 1270 fiu_fill_mode_src 0 ; Flow J cc=False 0x1272 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1272 0x1272 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_c_adr 39 GP06 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1271 1271 fiu_fill_mode_src 0 ; Flow J 0x1275 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1275 0x1275 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA 1272 1272 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 1273 1273 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1274 1274 fiu_load_var 1 hold_var; Flow J 0x1275 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1275 0x1275 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1275 1275 ioc_load_wdr 0 ; Flow C 0x1316 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1316 0x1316 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1276 1276 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1277 1277 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1278 1278 ioc_tvbs 2 fiu+val; Flow J 0x1279 seq_br_type 2 Push (branch address) seq_branch_adr 127a 0x127a seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN 1279 1279 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2a2e ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2a2e 0x2a2e seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 127a 127a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 127b 127b fiu_load_tar 1 hold_tar; Flow J cc=False 0x127d fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 127d 0x127d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 127c 127c seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 127d 127d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 127e 127e ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 127f 127f fiu_load_var 1 hold_var; Flow C cc=False 0x1286 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 1286 0x1286 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1280 1280 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x128b seq_br_type 0 Branch False seq_branch_adr 128b 0x128b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1281 1281 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1282 1282 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1289 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1289 0x1289 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 1283 1283 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1284 1284 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1285 1285 seq_br_type 3 Unconditional Branch; Flow J 0x1289 seq_branch_adr 1289 0x1289 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1286 ; -------------------------------------------------------------------------------------- 1286 ; Comes from: 1286 ; 127f C False from color 0x10d6 1286 ; -------------------------------------------------------------------------------------- 1286 1286 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1287 0x1287 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1287 1287 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1288 1288 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1289 1289 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 128a 128a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x10e4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 10e4 0x10e4 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 128b 128b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 128c 128c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 128d 128d seq_br_type 3 Unconditional Branch; Flow J 0x1289 seq_branch_adr 1289 0x1289 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 val_c_mux_sel 2 ALU 128e 128e fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 128f 128f fiu_mem_start 4 continue typ_a_adr 2f TR09:0f typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1290 1290 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x12c5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 12c5 0x12c5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1291 1291 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1292 1292 ioc_tvbs 3 fiu+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1293 1293 ioc_fiubs 2 typ ; Flow C cc=True 0x12c7 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 12c7 0x12c7 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1294 1294 seq_br_type 4 Call False; Flow C cc=False 0x12c7 seq_branch_adr 12c7 0x12c7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 1295 1295 fiu_load_var 1 hold_var; Flow J cc=True 0x1299 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1299 0x1299 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1296 1296 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1297 1297 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1298 1298 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1299 1299 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 129a 129a fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 129b 129b fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 129c 129c fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 129d 129d fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 04 GP04 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 129e 129e ioc_fiubs 2 typ ; Flow C cc=False 0x32ac seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 06 GP06 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 129f 129f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_b_adr 03 GP03 12a0 12a0 ioc_tvbs 2 fiu+val; Flow J cc=True 0x12a7 seq_br_type 1 Branch True seq_branch_adr 12a7 0x12a7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12a1 12a1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val 12a2 12a2 fiu_load_var 1 hold_var; Flow C cc=False 0x32ac fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 12a3 12a3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12a4 12a4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 12a5 12a5 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 12a6 12a6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12af fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12af 0x12af typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 12a7 12a7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 12a8 12a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 12a9 12a9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 12aa 12aa fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 12ab 12ab seq_b_timing 1 Latch Condition; Flow J cc=True 0x12af seq_br_type 1 Branch True seq_branch_adr 12af 0x12af seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 12ac 12ac seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12ad 12ad seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 12ae 12ae seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 12af 12af seq_b_timing 0 Early Condition; Flow C cc=False 0x12bf seq_br_type 4 Call False seq_branch_adr 12bf 0x12bf seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12b0 12b0 fiu_mem_start 2 start-rd; Flow C 0x3596 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3596 0x3596 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 12b1 12b1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12c0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12c0 0x12c0 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 12b2 12b2 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 12b3 12b3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x12c0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12c0 0x12c0 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12b4 12b4 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12b5 12b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12c0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12c0 0x12c0 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12b6 12b6 ioc_load_wdr 0 ; Flow J cc=True 0x12ba ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 12ba 0x12ba seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12b7 12b7 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12b8 12b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12c0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12c0 0x12c0 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA 12b9 12b9 ioc_load_wdr 0 ; Flow J 0x12bc ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12bc 0x12bc 12ba 12ba seq_br_type 1 Branch True; Flow J cc=True 0x12bc seq_branch_adr 12bc 0x12bc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 12bb 12bb seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 12bc 12bc ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12bd 12bd seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 12be 12be fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 12bf ; -------------------------------------------------------------------------------------- 12bf ; Comes from: 12bf ; 12af C False from color 0x125f 12bf ; -------------------------------------------------------------------------------------- 12bf 12bf seq_br_type a Unconditional Return; Flow R val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 8 12c0 ; -------------------------------------------------------------------------------------- 12c0 ; Comes from: 12c0 ; 12b1 C from color 0x125f 12c0 ; 12b3 C from color 0x125f 12c0 ; 12b5 C from color 0x125f 12c0 ; 12b8 C from color 0x125f 12c0 ; -------------------------------------------------------------------------------------- 12c0 12c0 fiu_fill_mode_src 0 ; Flow J cc=False 0x12c2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12c2 0x12c2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 12c1 12c1 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 12c2 12c2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 12c3 12c3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12c4 12c4 fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12c5 ; -------------------------------------------------------------------------------------- 12c5 ; Comes from: 12c5 ; 1290 C False from color 0x125f 12c5 ; -------------------------------------------------------------------------------------- 12c5 12c5 seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 12c6 12c6 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12c7 ; -------------------------------------------------------------------------------------- 12c7 ; Comes from: 12c7 ; 1293 C True from color 0x125f 12c7 ; 1294 C False from color 0x125f 12c7 ; -------------------------------------------------------------------------------------- 12c7 12c7 seq_b_timing 0 Early Condition; Flow R cc=False ; Flow J cc=True 0x3272 seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12c8 ; -------------------------------------------------------------------------------------- 12c8 ; 0x02fe Declare_Variable Variant_Record,Visible 12c8 ; -------------------------------------------------------------------------------------- 12c8 MACRO_Declare_Variable_Variant_Record,Visible: 12c8 12c8 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 12c8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 12c9 12c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12ca 12ca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12ce fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 12ce 0x12ce seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12cb 12cb seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12cc 12cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12cd 12cd val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 12ce 12ce fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 12cf 12cf fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x12d2 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 1 Branch True seq_branch_adr 12d2 0x12d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12d0 12d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 12d1 12d1 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 12d2 12d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x29b5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 29b5 0x29b5 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 12d3 12d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 12d4 ; -------------------------------------------------------------------------------------- 12d4 ; 0x02ff Declare_Variable Variant_Record 12d4 ; -------------------------------------------------------------------------------------- 12d4 MACRO_Declare_Variable_Variant_Record: 12d4 12d4 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 12d4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 12d5 12d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12ca fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 12ca 0x12ca seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12d6 ; -------------------------------------------------------------------------------------- 12d6 ; 0x02fb Declare_Variable Variant_Record,Visible,With_Constraint 12d6 ; -------------------------------------------------------------------------------------- 12d6 MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint: 12d6 12d6 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 12d6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 12d7 12d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12d8 12d8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12dc fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 12dc 0x12dc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 12d9 12d9 seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 12da 12da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 12db 12db val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 12dc 12dc fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12dd 12dd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x12e0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12e0 0x12e0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 12de 12de fiu_load_var 1 hold_var; Flow J cc=False 0x12e5 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 12e5 0x12e5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12df 12df fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x12ea fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 12ea 0x12ea typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12e0 12e0 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3275 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 12e1 12e1 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x12e3 seq_br_type 1 Branch True seq_branch_adr 12e3 0x12e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 12e2 12e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 12e3 12e3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2482 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2482 0x2482 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_b_adr 03 GP03 12e4 12e4 ioc_tvbs 2 fiu+val; Flow J cc=True 0x12e7 seq_br_type 1 Branch True seq_branch_adr 12e7 0x12e7 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12e5 12e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 12e6 12e6 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 12e7 12e7 seq_br_type 5 Call True; Flow C cc=True 0x2a2e seq_branch_adr 2a2e 0x2a2e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12e8 12e8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 12e9 12e9 fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x12ea fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 12ea 0x12ea typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12ea 12ea fiu_fill_mode_src 0 ; Flow J cc=False 0x12ec fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12ec 0x12ec seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 12eb 12eb fiu_fill_mode_src 0 ; Flow J 0x12ef fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 12ef 0x12ef typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12ec 12ec fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 12ed 12ed fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12ee 12ee fiu_load_var 1 hold_var; Flow J 0x12ef fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12ef 0x12ef seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12ef 12ef ioc_load_wdr 0 ; Flow C 0x1316 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1316 0x1316 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 12f0 12f0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x12f3 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 12f3 0x12f3 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 03 GP03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 03 GP03 12f1 12f1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 12f2 12f2 ioc_tvbs 3 fiu+fiu; Flow C 0x2a2e seq_br_type 7 Unconditional Call seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 12f3 12f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12f8 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 12f8 0x12f8 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_b_adr 03 GP03 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 12f4 12f4 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12f5 12f5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL 12f6 12f6 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 12f7 12f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 12f8 12f8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 21 VR02:01 val_frame 2 12f9 12f9 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x1301 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1301 0x1301 typ_b_adr 2e TR08:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR06:02 val_frame 6 12fa 12fa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 12fb 12fb fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_load_wdr 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 12fc 12fc ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12fd 12fd fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 12fe 12fe fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 12ff 12ff ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 1300 1300 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1301 1301 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1302 1302 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1303 1303 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1304 1304 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 1305 1305 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1306 1306 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 22 TR02:02 typ_b_adr 04 GP04 typ_frame 2 val_b_adr 04 GP04 1307 1307 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL 1308 1308 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 1309 1309 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 06 GP06 130a 130a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 130b 130b <halt> ; Flow R 130c ; -------------------------------------------------------------------------------------- 130c ; 0x02fc Declare_Variable Variant_Record,With_Constraint 130c ; -------------------------------------------------------------------------------------- 130c MACRO_Declare_Variable_Variant_Record,With_Constraint: 130c 130c dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 130c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 130d 130d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12d8 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 12d8 0x12d8 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 130e ; -------------------------------------------------------------------------------------- 130e ; 0x02fd Declare_Variable Variant_Record,Duplicate 130e ; -------------------------------------------------------------------------------------- 130e MACRO_Declare_Variable_Variant_Record,Duplicate: 130e 130e dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 130e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 130f 130f fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1310 1310 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1313 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1313 0x1313 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 1311 1311 seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1312 1312 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1313 1313 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1314 1314 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1315 1315 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1316 ; -------------------------------------------------------------------------------------- 1316 ; Comes from: 1316 ; 1275 C from color 0x0000 1316 ; 12ef C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 1316 ; -------------------------------------------------------------------------------------- 1316 1316 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 1317 1317 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 1318 0x1318 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1318 1318 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1319 1319 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 131a 131a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x131d fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 131d 0x131d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 131b 131b seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 131c 131c fiu_mem_start 2 start-rd seq_en_micro 0 131d 131d typ_c_adr 37 GP08 val_rand 2 DEC_LOOP_COUNTER 131e 131e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 131f 131f ioc_fiubs 0 fiu typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 36 GP09 val_c_source 0 FIU_BUS 1320 1320 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1321 1321 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 08 GP08 1322 1322 fiu_fill_mode_src 0 ; Flow J cc=False 0x1324 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1324 0x1324 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 09 GP09 1323 1323 fiu_fill_mode_src 0 ; Flow J 0x1327 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1327 0x1327 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1324 1324 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1325 1325 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1326 1326 fiu_load_var 1 hold_var; Flow J 0x1327 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1327 0x1327 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1327 1327 ioc_load_wdr 0 ; Flow J cc=False 0x1319 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1319 0x1319 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1328 1328 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 1329 1329 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 132a ; -------------------------------------------------------------------------------------- 132a ; 0x0337 Declare_Variable Array 132a ; -------------------------------------------------------------------------------------- 132a MACRO_Declare_Variable_Array: 132a 132a dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 132a fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 132b 132b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1338 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1338 0x1338 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR0a:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 132c 132c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x132e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 132e 0x132e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 132d 132d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1333 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1333 0x1333 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 1c ? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 132e 132e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x132f seq_br_type 2 Push (branch address) seq_branch_adr 1332 0x1332 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 132f 132f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1339 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1339 0x1339 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 1330 1330 ioc_fiubs 2 typ ; Flow J cc=False 0x1333 seq_br_type 0 Branch False seq_branch_adr 1333 0x1333 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1331 1331 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a2e ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a2e 0x2a2e seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP 1332 1332 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1333 1333 ioc_fiubs 2 typ ; Flow J cc=True 0x1335 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1335 0x1335 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1334 1334 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 1335 1335 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1336 1336 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1337 1337 fiu_mem_start 2 start-rd; Flow J 0x1333 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1333 0x1333 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1338 1338 ioc_tvbs 2 fiu+val; Flow C 0x32a7 seq_br_type 7 Unconditional Call seq_branch_adr 32a7 0x32a7 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 1339 1339 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 133a 133a val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 133b 133b seq_br_type a Unconditional Return; Flow R val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 133c ; -------------------------------------------------------------------------------------- 133c ; 0x0336 Declare_Variable Array,Visible 133c ; -------------------------------------------------------------------------------------- 133c MACRO_Declare_Variable_Array,Visible: 133c 133c dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 133c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133d 133d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3279 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133e 133e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x132e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 132e 0x132e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 133f 133f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1333 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1333 0x1333 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1340 ; -------------------------------------------------------------------------------------- 1340 ; 0x0335 Declare_Variable Array,Duplicate 1340 ; -------------------------------------------------------------------------------------- 1340 MACRO_Declare_Variable_Array,Duplicate: 1340 1340 dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1340 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1341 1341 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1342 1342 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1347 fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1347 0x1347 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1343 1343 seq_b_timing 1 Latch Condition; Flow C cc=True 0x136e seq_br_type 5 Call True seq_branch_adr 136e 0x136e 1344 1344 ioc_fiubs 2 typ ; Flow J cc=False 0x1333 seq_br_type 0 Branch False seq_branch_adr 1333 0x1333 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1345 1345 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1346 1346 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1347 1347 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x136e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 136e 0x136e typ_c_adr 39 GP06 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1348 1348 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1349 1349 fiu_len_fill_lit 4b zero-fill 0xb fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 134a 134a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x134d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 134d 0x134d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 134b 134b fiu_fill_mode_src 0 ; Flow C cc=False 0x1350 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1350 0x1350 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 134c 134c seq_br_type 3 Unconditional Branch; Flow J 0x1354 seq_branch_adr 1354 0x1354 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 134d 134d fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 134e 134e fiu_fill_mode_src 0 ; Flow C cc=False 0x1350 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1350 0x1350 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 134f 134f seq_br_type 3 Unconditional Branch; Flow J 0x1354 seq_branch_adr 1354 0x1354 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1350 ; -------------------------------------------------------------------------------------- 1350 ; Comes from: 1350 ; 134b C False from color 0x0000 1350 ; 134e C False from color 0x0000 1350 ; -------------------------------------------------------------------------------------- 1350 1350 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1352 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1352 0x1352 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1351 1351 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1352 1352 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1353 1353 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1354 1354 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1358 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1358 0x1358 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1355 1355 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1356 1356 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1357 1357 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1358 1358 ioc_tvbs 1 typ+fiu; Flow J 0x1359 seq_br_type 2 Push (branch address) seq_branch_adr 135d 0x135d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1359 1359 ioc_fiubs 1 val ; Flow J cc=True 0x135b seq_br_type 1 Branch True seq_branch_adr 135b 0x135b seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 135a 135a val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 135b 135b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1360 seq_br_type 1 Branch True seq_branch_adr 1360 0x1360 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 135c 135c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1360 seq_br_type 1 Branch True seq_branch_adr 1360 0x1360 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 135d 135d ioc_fiubs 2 typ ; Flow J cc=False 0x1337 seq_br_type 0 Branch False seq_branch_adr 1337 0x1337 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 135e 135e ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 135f 135f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1360 1360 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1361 1361 ioc_fiubs 0 fiu typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1362 1362 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1365 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1365 0x1365 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1363 1363 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1364 1364 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1365 1365 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1369 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1369 0x1369 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1366 1366 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1367 1367 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x136b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 136b 0x136b seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1368 1368 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x1362 seq_br_type 8 Return True seq_branch_adr 1362 0x1362 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1369 1369 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 136a 136a fiu_fill_mode_src 0 ; Flow J 0x1367 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1367 0x1367 136b 136b fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_b_adr 05 GP05 136c 136c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 136d 136d ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 136e ; -------------------------------------------------------------------------------------- 136e ; Comes from: 136e ; 1343 C True from color 0x0000 136e ; 1347 C True from color 0x0000 136e ; -------------------------------------------------------------------------------------- 136e 136e val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 136f 136f val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1370 1370 seq_br_type a Unconditional Return; Flow R val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1371 1371 <halt> ; Flow R 1372 ; -------------------------------------------------------------------------------------- 1372 ; 0x0334 Declare_Variable Array,With_Constraint 1372 ; -------------------------------------------------------------------------------------- 1372 MACRO_Declare_Variable_Array,With_Constraint: 1372 1372 dispatch_brk_class 4 ; Flow J 0x1373 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1372 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 3fff 0x3fff seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 21 TR0c:01 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1373 1373 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x139f fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 139f 0x139f seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1374 1374 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1375 1375 fiu_tivi_src 1 tar_val; Flow J cc=True 0x1394 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1394 0x1394 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 1376 1376 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3a GP05 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1377 1377 fiu_fill_mode_src 0 ; Flow J cc=True 0x1382 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1382 0x1382 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1378 1378 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1379 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 137a 0x137a typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1379 1379 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1385 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1385 0x1385 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 137a 137a seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 137b 137b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 137c 137c fiu_fill_mode_src 0 ; Flow J cc=False 0x137f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 137f 0x137f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 137d 137d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 137e 137e ioc_load_wdr 0 ; Flow J 0x1391 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1391 0x1391 137f 137f fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1380 1380 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 1381 1381 fiu_load_var 1 hold_var; Flow J 0x137e fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 137e 0x137e seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1382 1382 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1383 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 1391 0x1391 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1383 1383 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3272 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1384 1384 fiu_mem_start 2 start-rd; Flow C cc=False 0x3272 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 1385 1385 fiu_fill_mode_src 0 ; Flow J cc=False 0x138d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 138d 0x138d seq_en_micro 0 typ_a_adr 07 GP07 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1386 1386 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1387 1387 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1388 1388 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1389 0x1389 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1389 1389 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 138a 138a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 138b 138b seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 138c 0x138c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 138c 138c seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 138d 138d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 138e 138e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 138f 138f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1390 1390 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x1389 seq_br_type 8 Return True seq_branch_adr 1389 0x1389 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1391 1391 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x139c ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 139c 0x139c seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1392 1392 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1393 0x1393 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1393 1393 ioc_fiubs 2 typ ; Flow C 0x329c seq_br_type 7 Unconditional Call seq_branch_adr 329c 0x329c typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1394 1394 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 1395 1395 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1396 1396 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1399 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1399 0x1399 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 1397 1397 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1376 seq_br_type 0 Branch False seq_branch_adr 1376 0x1376 1398 1398 ioc_fiubs 1 val ; Flow J 0x1376 seq_br_type 3 Unconditional Branch seq_branch_adr 1376 0x1376 seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 1399 ; -------------------------------------------------------------------------------------- 1399 ; Comes from: 1399 ; 1396 C True from color MACRO_Declare_Variable_Array,With_Constraint 1399 ; 13b9 C True from color MACRO_Declare_Variable_Array,With_Constraint 1399 ; -------------------------------------------------------------------------------------- 1399 1399 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 139a 139a seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 139b 139b ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 139c ; -------------------------------------------------------------------------------------- 139c ; Comes from: 139c ; 1391 C True from color MACRO_Declare_Variable_Array,With_Constraint 139c ; -------------------------------------------------------------------------------------- 139c 139c ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 139d 139d seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 139e 139e seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 139f 139f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a0 13a0 fiu_mem_start 4 continue; Flow J cc=True 0x13b7 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13b7 0x13b7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 13a1 13a1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13a2 13a2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x13e9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13e9 0x13e9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a3 13a3 fiu_fill_mode_src 0 ; Flow J cc=True 0x13a7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13a7 0x13a7 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13a4 13a4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a5 13a5 ioc_fiubs 1 val ; Flow C cc=False 0x32ac seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 2b TR08:0b typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13a6 13a6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13ab fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13ab 0x13ab typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13a7 13a7 typ_c_adr 3b GP04 val_c_adr 3b GP04 13a8 13a8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13a9 13a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3272 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2f TR09:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13aa 13aa fiu_mem_start 2 start-rd; Flow C cc=False 0x3272 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13ab 13ab fiu_fill_mode_src 0 ; Flow J cc=False 0x13b2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13b2 0x13b2 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 13ac 13ac fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13ad 13ad ioc_load_wdr 0 ; Flow J cc=True 0x13bf ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13bf 0x13bf seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13ae 13ae seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13af 13af seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13b0 13b0 seq_br_type 1 Branch True; Flow J cc=True 0x13bf seq_branch_adr 13bf 0x13bf seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13b1 13b1 seq_br_type 3 Unconditional Branch; Flow J 0x13bf seq_branch_adr 13bf 0x13bf val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 13b2 13b2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 13b3 13b3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 13b4 13b4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13b5 13b5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x13bf seq_br_type 1 Branch True seq_branch_adr 13bf 0x13bf seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13b6 13b6 seq_br_type 3 Unconditional Branch; Flow J 0x13af seq_branch_adr 13af 0x13af seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13b7 13b7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 13b8 13b8 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 13b9 13b9 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1399 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1399 0x1399 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 13ba 13ba fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x13a1 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13a1 0x13a1 13bb 13bb fiu_mem_start 2 start-rd; Flow J 0x13a1 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 13a1 0x13a1 seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 13bc ; -------------------------------------------------------------------------------------- 13bc ; Comes from: 13bc ; 13e6 C True from color MACRO_Declare_Variable_Array,With_Constraint 13bc ; -------------------------------------------------------------------------------------- 13bc 13bc ioc_fiubs 1 val ; Flow R cc=False seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 13bd 0x13bd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13bd 13bd seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 13be 13be seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 13bf 13bf fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13c0 13c0 fiu_fill_mode_src 0 ; Flow J cc=False 0x13c2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13c2 0x13c2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 13c1 13c1 fiu_fill_mode_src 0 ; Flow J 0x13c5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 13c5 0x13c5 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13c2 13c2 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13c3 13c3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 13c4 13c4 fiu_load_var 1 hold_var; Flow J 0x13c5 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13c5 0x13c5 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13c5 13c5 ioc_load_wdr 0 ; Flow J 0x13c6 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13c6 0x13c6 13c6 13c6 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1c TOP - 4 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13c7 13c7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13c8 13c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13c9 13c9 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x13ce fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13ce 0x13ce seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13ca 13ca fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13cb 13cb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value val_b_adr 1d TOP - 3 13cc 13cc ioc_fiubs 0 fiu ; Flow C cc=False 0x32ac seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_frame 6 13cd 13cd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13d0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13d0 0x13d0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13ce 13ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3272 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13cf 13cf fiu_mem_start 2 start-rd; Flow C cc=False 0x3272 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13d0 13d0 fiu_fill_mode_src 0 ; Flow J cc=False 0x13d7 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13d7 0x13d7 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 13d1 13d1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13d2 13d2 ioc_load_wdr 0 ; Flow J cc=True 0x13dd ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13dd 0x13dd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 13d3 13d3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13d4 13d4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13d5 13d5 seq_br_type 1 Branch True; Flow J cc=True 0x13dd seq_branch_adr 13dd 0x13dd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13d6 13d6 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 13d7 13d7 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13d8 13d8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 13d9 13d9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13da 13da ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13db 13db seq_b_timing 1 Latch Condition; Flow J cc=True 0x13dd seq_br_type 1 Branch True seq_branch_adr 13dd 0x13dd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 13dc 13dc seq_br_type 3 Unconditional Branch; Flow J 0x13d4 seq_branch_adr 13d4 0x13d4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13dd 13dd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 6 13de 13de ioc_fiubs 2 typ ; Flow J cc=True 0x13e6 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 13e6 0x13e6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 0f GP0f typ_csa_cntl 7 FINISH_POP_DOWN 13df 13df fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 13e0 13e0 fiu_fill_mode_src 0 ; Flow J cc=False 0x13e3 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13e3 0x13e3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 13e1 13e1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 13e2 13e2 ioc_load_wdr 0 ; Flow J 0x13e6 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13e6 0x13e6 13e3 13e3 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13e4 13e4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 7 13e5 13e5 fiu_load_var 1 hold_var; Flow J 0x13e2 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13e2 0x13e2 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13e6 13e6 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x13bc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 13bc 0x13bc seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 13e7 13e7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 13e8 0x13e8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13e8 13e8 ioc_fiubs 2 typ ; Flow C 0x329c seq_br_type 7 Unconditional Call seq_branch_adr 329c 0x329c typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 13e9 13e9 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 13ea 13ea fiu_len_fill_lit 4d zero-fill 0xd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 13eb 13eb seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 13ec 13ec fiu_mem_start 2 start-rd; Flow C cc=False 0x329c ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 13ed 13ed ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13ee 13ee ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13ef 13ef seq_br_type 7 Unconditional Call; Flow C 0x1411 seq_branch_adr 1411 0x1411 typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 13f0 13f0 ioc_fiubs 2 typ ; Flow J cc=True 0x1402 seq_br_type 1 Branch True seq_branch_adr 1402 0x1402 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 37 TR05:17 typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 13f1 13f1 val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 13f2 13f2 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 13f3 13f3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13f4 13f4 ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13f5 13f5 seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 13f6 13f6 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x13f9 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 13f9 0x13f9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 13f7 13f7 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 13f8 13f8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 13f9 13f9 fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 13fa 13fa ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13fb 13fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x13fd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 13fd 0x13fd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 13fc 13fc seq_br_type 3 Unconditional Branch; Flow J 0x13fe seq_branch_adr 13fe 0x13fe val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 13fd 13fd seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 13fe 13fe fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 13ff 13ff fiu_fill_mode_src 0 ; Flow J cc=False 0x1409 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1409 0x1409 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 1400 1400 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 1401 1401 ioc_load_wdr 0 ; Flow J cc=False 0x13f6 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13f6 0x13f6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1402 1402 ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1403 1403 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 1404 1404 fiu_tivi_src 4 fiu_var ioc_tvbs 2 fiu+val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f 1405 1405 seq_b_timing 1 Latch Condition; Flow C cc=True 0x140c seq_br_type 5 Call True seq_branch_adr 140c 0x140c typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1406 1406 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1407 0x1407 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1407 1407 ioc_fiubs 2 typ ; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1408 1408 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 1409 1409 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 140a 140a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 140b 140b fiu_load_var 1 hold_var; Flow J 0x1401 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1401 0x1401 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 140c ; -------------------------------------------------------------------------------------- 140c ; Comes from: 140c ; 1405 C True from color MACRO_Declare_Variable_Array,With_Constraint 140c ; -------------------------------------------------------------------------------------- 140c 140c ioc_fiubs 1 val ; Flow J cc=True 0x140f seq_br_type 1 Branch True seq_branch_adr 140f 0x140f seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B 140d 140d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 140e 140e seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 140f 140f ioc_fiubs 1 val ; Flow C 0x2a2e seq_br_type 7 Unconditional Call seq_branch_adr 2a2e 0x2a2e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1410 1410 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1411 ; -------------------------------------------------------------------------------------- 1411 ; Comes from: 1411 ; 13ef C from color MACRO_Declare_Variable_Array,With_Constraint 1411 ; -------------------------------------------------------------------------------------- 1411 1411 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1412 1412 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1413 1413 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1414 1414 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 06 GP06 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1415 1415 seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3a GP05 val_frame 6 1416 1416 ioc_load_wdr 0 ; Flow J cc=True 0x1427 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1427 0x1427 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1417 1417 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1418 1418 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_c_adr 3b GP04 1419 1419 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3272 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 141a 141a fiu_fill_mode_src 0 ; Flow J cc=False 0x1428 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1428 0x1428 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 141b 141b fiu_fill_mode_src 0 ; Flow J cc=True 0x142b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 142b 0x142b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 141c 141c ioc_load_wdr 0 ; Flow C cc=True 0x3272 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 141d 141d seq_br_type 0 Branch False; Flow J cc=False 0x1422 seq_branch_adr 1422 0x1422 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 141e 141e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 141f 141f fiu_fill_mode_src 0 ; Flow J cc=False 0x1433 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1433 0x1433 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1420 1420 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1421 1421 ioc_fiubs 2 typ ; Flow J 0x1411 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1411 0x1411 typ_a_adr 04 GP04 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1422 1422 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1423 1423 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1424 1424 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1425 1425 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x141f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 141f 0x141f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1426 1426 seq_br_type 3 Unconditional Branch; Flow J 0x141f seq_branch_adr 141f 0x141f val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1427 1427 seq_br_type 3 Unconditional Branch; Flow J 0x1418 seq_branch_adr 1418 0x1418 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 37 TR05:17 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1428 1428 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1429 1429 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 142a 142a fiu_load_var 1 hold_var; Flow J cc=False 0x141c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 141c 0x141c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 142b 142b ioc_load_wdr 0 ; Flow C cc=True 0x3272 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 142c 142c seq_br_type 0 Branch False; Flow J cc=False 0x142e seq_branch_adr 142e 0x142e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 142d 142d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 142e 142e seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 142f 142f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1430 1430 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1431 1431 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1432 0x1432 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1432 1432 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1433 1433 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1434 1434 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1435 1435 fiu_load_var 1 hold_var; Flow J 0x1421 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1421 0x1421 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1436 ; -------------------------------------------------------------------------------------- 1436 ; 0x0333 Declare_Variable Array,Visible,With_Constraint 1436 ; -------------------------------------------------------------------------------------- 1436 MACRO_Declare_Variable_Array,Visible,With_Constraint: 1436 1436 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1436 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 07 Push_stack+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 1437 1437 fiu_mem_start 2 start-rd; Flow J 0x1373 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1373 0x1373 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1438 ; -------------------------------------------------------------------------------------- 1438 ; 0x01ae Execute Matrix,Not_Equal 1438 ; 0x01af Execute Matrix,Equal 1438 ; -------------------------------------------------------------------------------------- 1438 MACRO_Execute_Matrix,Equal: 1438 MACRO_Execute_Matrix,Not_Equal: 1438 1438 dispatch_brk_class 8 ; Flow J cc=True 0x143a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1438 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 143a 0x143a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1439 1439 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 143a 143a fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x144b ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 144b 0x144b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 143b 143b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 143c 143c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1443 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1443 0x1443 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 143d 143d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 143e 143e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 143f 143f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1441 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1441 0x1441 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1440 1440 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1447 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1447 0x1447 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1441 1441 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1442 1442 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1447 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1447 0x1447 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1443 1443 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3077 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1444 1444 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 1445 1445 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1446 1446 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1447 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1447 0x1447 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1447 1447 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1448 1448 seq_b_timing 1 Latch Condition; Flow J cc=True 0x144e seq_br_type 1 Branch True seq_branch_adr 144e 0x144e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1449 1449 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 144a 144a seq_br_type 3 Unconditional Branch; Flow J 0x144e seq_branch_adr 144e 0x144e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 144b 144b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 144c 144c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 144d 144d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x144e fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 144e 0x144e typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 144e 144e fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x145f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 145f 0x145f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 144f 144f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1450 1450 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1457 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1457 0x1457 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR07:14 val_frame 7 1451 1451 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1452 1452 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 1453 1453 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1455 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1455 0x1455 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1454 1454 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x145b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 145b 0x145b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1455 1455 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1456 1456 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x145b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 145b 0x145b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1457 1457 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3077 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1458 1458 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1459 1459 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 145a 145a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x145b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 145b 0x145b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 145b 145b seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 145c 145c seq_b_timing 1 Latch Condition; Flow J cc=True 0x1462 seq_br_type 1 Branch True seq_branch_adr 1462 0x1462 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 145d 145d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 145e 145e seq_br_type 3 Unconditional Branch; Flow J 0x1462 seq_branch_adr 1462 0x1462 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 145f 145f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1460 1460 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1461 1461 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1462 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1462 0x1462 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1462 1462 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1465 seq_br_type 1 Branch True seq_branch_adr 1465 0x1465 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1463 1463 ioc_fiubs 1 val ; Flow C cc=True 0x26fc seq_br_type 5 Call True seq_branch_adr 26fc 0x26fc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 1464 1464 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1465 1465 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1464 seq_br_type 0 Branch False seq_branch_adr 1464 0x1464 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 04 GP04 val_alu_func 0 PASS_A 1466 1466 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1464 seq_br_type 0 Branch False seq_branch_adr 1464 0x1464 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 0 PASS_A val_alu_func 0 PASS_A 1467 1467 seq_br_type 3 Unconditional Branch; Flow J 0x1464 seq_branch_adr 1464 0x1464 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1468 ; -------------------------------------------------------------------------------------- 1468 ; 0x01ad Execute Matrix,First 1468 ; -------------------------------------------------------------------------------------- 1468 MACRO_Execute_Matrix,First: 1468 1468 dispatch_brk_class 8 ; Flow J cc=True 0x1472 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1468 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1472 0x1472 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1469 1469 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1477 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1477 0x1477 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 20 TR14:00 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 146a 146a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x146c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 146c 0x146c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 146b 146b fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 146c 146c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 146d 146d fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 146e 146e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1470 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1470 0x1470 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 146f 146f fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32a9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1470 1470 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1471 1471 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32a9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1472 1472 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1474 seq_br_type 1 Branch True seq_branch_adr 1474 0x1474 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1473 1473 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x146e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 146e 0x146e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 1474 1474 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1475 1475 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1c DEC_A 1476 1476 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1477 1477 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1478 1478 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1479 1479 <halt> ; Flow R 147a ; -------------------------------------------------------------------------------------- 147a ; 0x01ab Execute Matrix,Length 147a ; -------------------------------------------------------------------------------------- 147a MACRO_Execute_Matrix,Length: 147a 147a dispatch_brk_class 8 ; Flow J cc=True 0x1481 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 147a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1481 0x1481 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 147b 147b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1484 seq_br_type 1 Branch True seq_branch_adr 1484 0x1484 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 147c 147c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 147d 147d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x147f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 147f 0x147f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 147e 147e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 147f 147f fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1480 1480 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1481 1481 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 1482 1482 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1484 seq_br_type 1 Branch True seq_branch_adr 1484 0x1484 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 1483 1483 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x147d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 147d 0x147d typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1484 1484 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1485 1485 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1486 ; -------------------------------------------------------------------------------------- 1486 ; Comes from: 1486 ; 14a2 C from color MACRO_Execute_Matrix,Last 1486 ; 14a4 C from color MACRO_Execute_Matrix,Bounds 1486 ; 14a8 C from color MACRO_Execute_Matrix,Reverse_Bounds 1486 ; -------------------------------------------------------------------------------------- 1486 1486 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1497 seq_br_type 1 Branch True seq_branch_adr 1497 0x1497 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1487 1487 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1499 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1499 0x1499 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1488 1488 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x148c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 148c 0x148c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1489 1489 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 148a 148a fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 148b 148b ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x1490 seq_br_type 8 Return True seq_branch_adr 1490 0x1490 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 148c 148c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 148d 148d fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 148e 148e fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 148f 148f ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1490 0x1490 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1490 1490 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1492 seq_br_type 1 Branch True seq_branch_adr 1492 0x1492 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 1491 1491 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1493 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1493 0x1493 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1492 1492 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 1493 ; -------------------------------------------------------------------------------------- 1493 ; Comes from: 1493 ; 14ce C from color 0x0aa2 1493 ; 14d3 C from color 0x0aa2 1493 ; -------------------------------------------------------------------------------------- 1493 1493 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1495 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1495 0x1495 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1494 1494 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1495 1495 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1496 1496 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1497 1497 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 1498 1498 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1488 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1488 0x1488 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1499 1499 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 149a 149a ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 149b 149b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14a0 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 14a0 0x14a0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 149c 149c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 149d 149d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x149f seq_br_type 1 Branch True seq_branch_adr 149f 0x149f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 149e 149e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 149f 149f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 14a0 14a0 ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 14a1 14a1 <halt> ; Flow R 14a2 ; -------------------------------------------------------------------------------------- 14a2 ; 0x01ac Execute Matrix,Last 14a2 ; -------------------------------------------------------------------------------------- 14a2 MACRO_Execute_Matrix,Last: 14a2 14a2 dispatch_brk_class 8 ; Flow C 0x1486 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a2 seq_br_type 7 Unconditional Call seq_branch_adr 1486 0x1486 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a3 14a3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a4 ; -------------------------------------------------------------------------------------- 14a4 ; 0x01aa Execute Matrix,Bounds 14a4 ; -------------------------------------------------------------------------------------- 14a4 MACRO_Execute_Matrix,Bounds: 14a4 14a4 dispatch_brk_class 8 ; Flow C 0x1486 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a4 seq_br_type 7 Unconditional Call seq_branch_adr 1486 0x1486 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a5 14a5 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a6 14a6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14a7 14a7 <halt> ; Flow R 14a8 ; -------------------------------------------------------------------------------------- 14a8 ; 0x01a9 Execute Matrix,Reverse_Bounds 14a8 ; -------------------------------------------------------------------------------------- 14a8 MACRO_Execute_Matrix,Reverse_Bounds: 14a8 14a8 dispatch_brk_class 8 ; Flow C 0x1486 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a8 seq_br_type 7 Unconditional Call seq_branch_adr 1486 0x1486 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a9 14a9 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14aa 14aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14ab 14ab <halt> ; Flow R 14ac ; -------------------------------------------------------------------------------------- 14ac ; 0x01a8 Execute Matrix,Element_Type 14ac ; -------------------------------------------------------------------------------------- 14ac MACRO_Execute_Matrix,Element_Type: 14ac 14ac dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 14ac fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 14ad 14ad typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 14ae 14ae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 14af 14af <halt> ; Flow R 14b0 ; -------------------------------------------------------------------------------------- 14b0 ; 0x019d Execute Matrix,In_Type 14b0 ; -------------------------------------------------------------------------------------- 14b0 MACRO_Execute_Matrix,In_Type: 14b0 14b0 dispatch_brk_class 8 ; Flow C cc=False 0x14f1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14b0 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14f1 0x14f1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14b1 14b1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14bc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14bc 0x14bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b2 14b2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14b3 14b3 <halt> ; Flow R 14b4 ; -------------------------------------------------------------------------------------- 14b4 ; 0x019c Execute Matrix,Not_In_Type 14b4 ; -------------------------------------------------------------------------------------- 14b4 MACRO_Execute_Matrix,Not_In_Type: 14b4 14b4 dispatch_brk_class 8 ; Flow C cc=False 0x14f1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14b4 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14f1 0x14f1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14b5 14b5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14bc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14bc 0x14bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b6 14b6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 14b7 14b7 <halt> ; Flow R 14b8 ; -------------------------------------------------------------------------------------- 14b8 ; 0x019b Execute Matrix,Check_In_Type 14b8 ; -------------------------------------------------------------------------------------- 14b8 MACRO_Execute_Matrix,Check_In_Type: 14b8 14b8 dispatch_brk_class 8 ; Flow C cc=False 0x14f1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14b8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14f1 0x14f1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14b9 14b9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14bc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14bc 0x14bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14ba 14ba fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 14bb 0x14bb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 31 VR02:11 val_frame 2 14bb 14bb seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 14bc ; -------------------------------------------------------------------------------------- 14bc ; Comes from: 14bc ; 14b1 C from color 0x0a7a 14bc ; 14b5 C from color 0x0a8e 14bc ; -------------------------------------------------------------------------------------- 14bc 14bc fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14e3 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14e3 0x14e3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 14bd 14bd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14cb fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14cb 0x14cb typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14be 14be <default> 14bf 14bf fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14c0 14c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14ca seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14c1 14c1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14c5 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 14c5 0x14c5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14c2 14c2 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c3 14c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c4 14c4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14ca seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 14c5 14c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14ca seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 14c6 14c6 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 14c7 0x14c7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14c7 14c7 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c8 14c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 14c9 14c9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14ca 0x14ca seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 14ca 14ca seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 14cb 14cb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x14d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14d7 0x14d7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 14cc 14cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14ca seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14cd 14cd seq_br_type 1 Branch True; Flow J cc=True 0x14d1 seq_branch_adr 14d1 0x14d1 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14ce 14ce fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x1493 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1493 0x1493 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 14cf 14cf fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 14d0 14d0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14ca seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 14d1 14d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14ca seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 14d2 14d2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 14d3 0x14d3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14d3 14d3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x1493 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1493 0x1493 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 14d4 14d4 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14d5 14d5 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14d6 0x14d6 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 14d6 14d6 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 14d7 ; -------------------------------------------------------------------------------------- 14d7 ; Comes from: 14d7 ; 14cb C from color 0x0aa2 14d7 ; 14e8 C from color 0x0aa2 14d7 ; -------------------------------------------------------------------------------------- 14d7 14d7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14dd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14dd 0x14dd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14d8 14d8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 14d9 14d9 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 14da 14da fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14e0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14e0 0x14e0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14db 14db fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 14dc 14dc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 14dd 14dd fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14de 14de fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 14df 14df fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x14da fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 14da 0x14da typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 14e0 14e0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14e1 14e1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 14e2 14e2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 14e3 14e3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14e8 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14e8 0x14e8 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14e4 14e4 <default> 14e5 14e5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14e6 14e6 fiu_load_var 1 hold_var; Flow J cc=True 0x14ca fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 14e7 14e7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x14ea seq_br_type 3 Unconditional Branch seq_branch_adr 14ea 0x14ea typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14e8 14e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x14d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14d7 0x14d7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 14e9 14e9 fiu_load_var 1 hold_var; Flow J cc=True 0x14ca fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 14ea 14ea fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 14eb 14eb fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 14ec 14ec seq_br_type 0 Branch False; Flow J cc=False 0x14ca seq_branch_adr 14ca 0x14ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 14ed 14ed fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 14ee 14ee ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 14ef 14ef seq_br_type 0 Branch False; Flow J cc=False 0x14ca seq_branch_adr 14ca 0x14ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 14f0 14f0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x14ca seq_br_type 9 Return False seq_branch_adr 14ca 0x14ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 14f1 ; -------------------------------------------------------------------------------------- 14f1 ; Comes from: 14f1 ; 14b0 C False from color 0x0a7a 14f1 ; 14b4 C False from color 0x0a8e 14f1 ; 14b8 C False from color 0x0aa2 14f1 ; 1552 C False from color 0x0000 14f1 ; 15c8 C False from color 0x0000 14f1 ; -------------------------------------------------------------------------------------- 14f1 14f1 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 14f2 14f2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 14f3 14f3 seq_br_type a Unconditional Return; Flow R 14f4 ; -------------------------------------------------------------------------------------- 14f4 ; 0x01a4 Execute Matrix,Structure_Write 14f4 ; -------------------------------------------------------------------------------------- 14f4 MACRO_Execute_Matrix,Structure_Write: 14f4 14f4 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14f4 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14f5 14f5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0e 0x1e0e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14f6 ; -------------------------------------------------------------------------------------- 14f6 ; 0x01a6 Execute Matrix,Field_Write 14f6 ; -------------------------------------------------------------------------------------- 14f6 MACRO_Execute_Matrix,Field_Write: 14f6 14f6 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14f6 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 14f7 14f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1505 fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1505 0x1505 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14f8 14f8 ioc_fiubs 1 val ; Flow J cc=False 0x14ff ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 14ff 0x14ff seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 14f9 14f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 14fa 14fa fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14fb 14fb seq_random 02 ? typ_csa_cntl 3 POP_CSA 14fc 14fc fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1502 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1502 0x1502 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 14fd 14fd fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 14fe 14fe seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 14ff 14ff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1500 1500 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1501 1501 seq_br_type 3 Unconditional Branch; Flow J 0x14fa seq_branch_adr 14fa 0x14fa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1502 1502 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1503 1503 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1504 1504 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1505 1505 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1531 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1531 0x1531 typ_b_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1506 1506 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1502 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1502 0x1502 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1507 1507 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1508 1508 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1509 1509 <halt> ; Flow R 150a ; -------------------------------------------------------------------------------------- 150a ; 0x01a5 Execute Matrix,Field_Reference 150a ; -------------------------------------------------------------------------------------- 150a MACRO_Execute_Matrix,Field_Reference: 150a 150a dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 150a dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 150b 150b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1517 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1517 0x1517 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 150c 150c fiu_mem_start 2 start-rd; Flow J cc=False 0x1511 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1511 0x1511 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 150d 150d fiu_mem_start 4 continue; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 150e 150e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 150f 150f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1514 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1514 0x1514 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1510 1510 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3272 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1511 1511 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1512 1512 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1513 1513 fiu_mem_start 4 continue; Flow J 0x150e seq_br_type 3 Unconditional Branch seq_branch_adr 150e 0x150e seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1514 1514 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1515 1515 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1516 0x1516 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1516 1516 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1517 1517 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1531 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1531 0x1531 typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1518 1518 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1514 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1514 0x1514 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1519 1519 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3272 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 151a ; -------------------------------------------------------------------------------------- 151a ; 0x01a7 Execute Matrix,Field_Read 151a ; -------------------------------------------------------------------------------------- 151a MACRO_Execute_Matrix,Field_Read: 151a 151a dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 151a dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 151b 151b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x152c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 152c 0x152c typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 151c 151c fiu_mem_start 2 start-rd; Flow J cc=False 0x1525 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1525 0x1525 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 151d 151d fiu_mem_start 4 continue; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 151e 151e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 151f 151f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x152e fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 152e 0x152e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1520 1520 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x3272 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1521 1521 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1523 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1523 0x1523 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 1522 1522 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1528 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1528 0x1528 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1523 1523 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1524 1524 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1528 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1528 0x1528 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1525 1525 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1526 1526 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1527 1527 fiu_mem_start 4 continue; Flow J 0x151e seq_br_type 3 Unconditional Branch seq_branch_adr 151e 0x151e seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1528 1528 seq_br_type 0 Branch False; Flow J cc=False 0x152b seq_branch_adr 152b 0x152b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 1529 1529 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 152a 0x152a seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 152a 152a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 152b 152b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 152c 152c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1531 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1531 0x1531 typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 152d 152d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1520 fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1520 0x1520 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 152e 152e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 152f 152f seq_br_type 2 Push (branch address); Flow J 0x1530 seq_branch_adr 1521 0x1521 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1530 1530 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x3272 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1531 ; -------------------------------------------------------------------------------------- 1531 ; Comes from: 1531 ; 1505 C from color 0x0000 1531 ; 1517 C from color 0x0000 1531 ; 152c C from color 0x0000 1531 ; -------------------------------------------------------------------------------------- 1531 1531 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1542 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1542 0x1542 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1532 1532 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1533 1533 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1534 1534 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x153d ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 153d 0x153d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1535 1535 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1536 1536 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3272 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 1537 1537 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x153f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 153f 0x153f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1538 1538 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 1539 1539 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 153a 153a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 153b 153b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 153c 153c fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 153d 153d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3272 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 153e 153e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1538 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1538 0x1538 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 153f 153f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1540 1540 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1541 1541 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return typ_b_adr 21 TR05:01 typ_frame 5 1542 1542 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1543 1543 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1544 1544 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x154d fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 154d 0x154d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1545 1545 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 1546 1546 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3272 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 7 1547 1547 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1548 1548 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x154a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 154a 0x154a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1549 1549 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1551 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1551 0x1551 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 154a 154a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 154b 154b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 154c 154c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1551 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1551 0x1551 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 154d 154d fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 154e 154e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3272 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 154f 154f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x154a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 154a 0x154a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1550 1550 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1551 1551 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1552 ; -------------------------------------------------------------------------------------- 1552 ; 0x019f Execute Matrix,Convert 1552 ; -------------------------------------------------------------------------------------- 1552 MACRO_Execute_Matrix,Convert: 1552 1552 dispatch_brk_class 4 ; Flow C cc=False 0x14f1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1552 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14f1 0x14f1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1553 1553 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1554 1554 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1579 seq_br_type 1 Branch True seq_branch_adr 1579 0x1579 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1555 1555 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1564 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1564 0x1564 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1556 1556 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1557 1557 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1558 1558 ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1559 1559 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x155b fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 155b 0x155b typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 155a 155a seq_br_type 1 Branch True; Flow J cc=True 0x155d seq_branch_adr 155d 0x155d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 155b 155b ioc_fiubs 2 typ ; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 155c 155c seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 02 GP02 val_alu_func 0 PASS_A 155d 155d fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 155e 155e fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 155f 155f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1561 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1561 0x1561 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1560 1560 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1561 1561 seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 36 GP09 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1562 1562 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1563 1563 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1564 1564 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1569 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1569 0x1569 typ_a_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1565 1565 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 1566 1566 ioc_fiubs 1 val ; Flow J cc=True 0x155b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 155b 0x155b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1567 1567 seq_br_type 1 Branch True; Flow J cc=True 0x155d seq_branch_adr 155d 0x155d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1568 1568 seq_br_type 3 Unconditional Branch; Flow J 0x155b seq_branch_adr 155b 0x155b 1569 ; -------------------------------------------------------------------------------------- 1569 ; Comes from: 1569 ; 1564 C from color 0x0000 1569 ; 157f C from color 0x0000 1569 ; 15d5 C from color 0x0000 1569 ; -------------------------------------------------------------------------------------- 1569 1569 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1571 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1571 0x1571 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 156a 156a fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 156b 156b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 156c 156c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1574 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1574 0x1574 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 156d 156d fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 156e 156e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1576 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1576 0x1576 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 156f 156f fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1570 1570 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1571 1571 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1572 1572 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 1573 1573 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x156c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 156c 0x156c typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1574 1574 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1575 1575 fiu_fill_mode_src 0 ; Flow J 0x156e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 156e 0x156e val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 1576 1576 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1577 1577 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1578 1578 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1579 1579 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x157f fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 157f 0x157f typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 157a 157a fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 157b 157b fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 157c 157c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 157d 157d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1588 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1588 0x1588 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 157e 157e seq_br_type 3 Unconditional Branch; Flow J 0x1581 seq_branch_adr 1581 0x1581 157f 157f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1569 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1569 0x1569 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1580 1580 fiu_load_var 1 hold_var; Flow J cc=True 0x1588 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1588 0x1588 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 1581 1581 fiu_load_var 1 hold_var; Flow J cc=True 0x1587 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1587 0x1587 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1582 1582 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1583 1583 ioc_tvbs 1 typ+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1584 1584 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1585 1585 fiu_mem_start 2 start-rd; Flow J cc=True 0x15b3 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 15b3 0x15b3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 1586 1586 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1587 1587 fiu_mem_start 2 start-rd; Flow J 0x15b3 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 15b3 0x15b3 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1588 1588 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1589 1589 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 158a 158a seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 158b 158b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 158c 158c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1587 seq_br_type 1 Branch True seq_branch_adr 1587 0x1587 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 06 GP06 158d 158d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 158e 158e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 158f 158f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x15bd seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15bd 0x15bd val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1590 1590 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1591 1591 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 1592 1592 ioc_fiubs 1 val ; Flow C cc=True 0x3279 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1593 1593 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1594 1594 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1596 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1596 0x1596 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1595 1595 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1596 1596 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 05 GP05 1597 1597 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1598 1598 fiu_fill_mode_src 0 ; Flow J cc=False 0x15a6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a6 0x15a6 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 1599 1599 fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 159a 159a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 159b 159b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 159c 159c fiu_fill_mode_src 0 ; Flow J cc=False 0x15a8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a8 0x15a8 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 07 GP07 159d 159d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 159e 159e ioc_load_wdr 0 ; Flow C cc=False 0x32ac ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 159f 159f fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 06 GP06 val_b_adr 06 GP06 15a0 15a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 15a1 15a1 fiu_fill_mode_src 0 ; Flow J cc=False 0x15aa fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15aa 0x15aa seq_cond_sel 65 CROSS_WORD_FIELD~ 15a2 15a2 fiu_fill_mode_src 0 ; Flow J cc=False 0x15ac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15ac 0x15ac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15a3 15a3 ioc_load_wdr 0 ; Flow C cc=False 0x329c ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 15a4 15a4 seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 15a5 15a5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15a6 15a6 fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 15a7 15a7 fiu_fill_mode_src 0 ; Flow J 0x159a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 159a 0x159a typ_mar_cntl 6 INCREMENT_MAR 15a8 15a8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15a9 15a9 fiu_fill_mode_src 0 ; Flow J 0x159e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 159e 0x159e typ_mar_cntl 6 INCREMENT_MAR 15aa 15aa fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15ab 15ab fiu_fill_mode_src 0 ; Flow J cc=True 0x15a3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 15a3 0x15a3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 15ac 15ac ioc_load_wdr 0 ; Flow C cc=False 0x329c ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR08:0c val_frame 8 15ad 15ad fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 03 GP03 val_b_adr 03 GP03 15ae 15ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 15af 15af fiu_fill_mode_src 0 ; Flow J cc=False 0x15b1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15b1 0x15b1 seq_cond_sel 65 CROSS_WORD_FIELD~ 15b0 15b0 fiu_fill_mode_src 0 ; Flow J 0x15a3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15a3 0x15a3 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15b1 15b1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15b2 15b2 fiu_fill_mode_src 0 ; Flow J 0x15a3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 15a3 0x15a3 typ_mar_cntl 6 INCREMENT_MAR 15b3 15b3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x15bb seq_br_type 1 Branch True seq_branch_adr 15bb 0x15bb 15b4 15b4 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15b5 15b5 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 15b6 15b6 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR02:01 val_frame 2 15b7 15b7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 15b8 15b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 15b9 15b9 ioc_fiubs 2 typ ; Flow J 0x15ba seq_br_type 2 Push (branch address) seq_branch_adr 1594 0x1594 typ_a_adr 03 GP03 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 15ba 15ba seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 15bb 15bb fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15bc 15bc fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x15c3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 15c3 0x15c3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 15bd 15bd fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15be 15be ioc_fiubs 2 typ ; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 05 GP05 typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 15bf 15bf seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 15c0 15c0 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x15c3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15c3 0x15c3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 15c1 15c1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 15c2 15c2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 15c3 15c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x15c5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15c5 0x15c5 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15c4 15c4 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 15c5 15c5 ioc_fiubs 1 val ; Flow C cc=False 0x329c seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 15c6 15c6 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 15c7 15c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 15c8 ; -------------------------------------------------------------------------------------- 15c8 ; 0x019e Execute Matrix,Convert_To_Formal 15c8 ; -------------------------------------------------------------------------------------- 15c8 MACRO_Execute_Matrix,Convert_To_Formal: 15c8 15c8 dispatch_brk_class 4 ; Flow C cc=False 0x14f1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 15c8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14f1 0x14f1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 15c9 15c9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 15ca 15ca seq_b_timing 1 Latch Condition; Flow J cc=True 0x1579 seq_br_type 1 Branch True seq_branch_adr 1579 0x1579 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15cb 15cb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x15d5 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15d5 0x15d5 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 15cc 15cc ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 15cd 15cd fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 15ce 15ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 15cf 15cf fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 15d0 15d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 15d1 15d1 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15d2 15d2 fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x155d ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 155d 0x155d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15d3 15d3 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 15d4 15d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x15e2 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e2 0x15e2 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 15d5 15d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1569 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1569 0x1569 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 15d6 15d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 15d7 15d7 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 15d8 15d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 15d9 15d9 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15da 15da fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x155d ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 155d 0x155d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15db 15db fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 15dc 15dc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x15df seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15df 0x15df seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 15dd 15dd fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 15de 15de fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x15e2 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e2 0x15e2 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 15df 15df fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15e0 15e0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 15e1 15e1 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x15e2 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e2 0x15e2 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 15e2 15e2 <default> 15e3 15e3 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 15e4 15e4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15e5 15e5 seq_br_type 3 Unconditional Branch; Flow J 0x155d seq_branch_adr 155d 0x155d 15e6 ; -------------------------------------------------------------------------------------- 15e6 ; 0x01a3 Execute Matrix,Subarray 15e6 ; -------------------------------------------------------------------------------------- 15e6 MACRO_Execute_Matrix,Subarray: 15e6 15e6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 15e6 dispatch_uses_tos 1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 15e7 15e7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 15e8 15e8 ioc_fiubs 1 val ; Flow J cc=False 0x15ec ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 15ec 0x15ec seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 15e9 15e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 15ea 15ea ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15eb 15eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR08:0d typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 15ec 15ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 15ed 15ed seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 15ee 15ee seq_br_type 3 Unconditional Branch; Flow J 0x15ea seq_branch_adr 15ea 0x15ea seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 15ef 15ef <halt> ; Flow R 15f0 ; -------------------------------------------------------------------------------------- 15f0 ; 0x2c00-0x2cff Execute Variant_Record,Field_Read,Fixed,Direct,fieldnum 15f0 ; -------------------------------------------------------------------------------------- 15f0 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum: 15f0 15f0 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 15f0 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 15f1 15f1 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x15f6 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 15f6 0x15f6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 15f2 15f2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x15f4 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15f4 0x15f4 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 15f3 15f3 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x15f8 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f8 0x15f8 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f4 15f4 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15f5 15f5 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x15f8 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f8 0x15f8 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f6 15f6 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 15f7 0x15f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f7 15f7 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 15f8 15f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f9 0x15f9 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15f9 15f9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15fa ; -------------------------------------------------------------------------------------- 15fa ; 0x2e00-0x2eff Execute Variant_Record,Field_Read,Variant,Direct,fieldnum 15fa ; -------------------------------------------------------------------------------------- 15fa MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum: 15fa 15fa dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 15fa dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_frame 4 15fb 15fb fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1604 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1604 0x1604 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 15fc 15fc fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 3d GP02 val_c_source 0 FIU_BUS 15fd 15fd fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=False 0x1607 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1607 0x1607 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 15fe 15fe fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1602 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1602 0x1602 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 15ff 15ff fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1600 0x1600 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1600 1600 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 1601 1601 seq_br_type 7 Unconditional Call; Flow C 0x3275 seq_branch_adr 3275 0x3275 seq_en_micro 0 1602 1602 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1603 1603 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1600 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1600 0x1600 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1604 1604 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 4 continue fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1605 1605 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1606 1606 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x15fe fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15fe 0x15fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1607 1607 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1610 seq_br_type 0 Branch False seq_branch_adr 1610 0x1610 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_c_lit 2 typ_frame 18 1608 1608 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x160c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 160c 0x160c seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1609 1609 fiu_fill_mode_src 0 ; Flow J cc=True 0x1600 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1600 0x1600 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 160a 160a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 160b 0x160b seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 160b 160b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 160c 160c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 160d 160d fiu_fill_mode_src 0 ; Flow J cc=True 0x1600 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1600 0x1600 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 160e 160e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 160f 0x160f seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 160f 160f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1610 1610 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1611 0x1611 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1611 1611 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1612 1612 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1600 seq_br_type 1 Branch True seq_branch_adr 1600 0x1600 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1613 1613 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1614 0x1614 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1614 1614 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x161c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 161c 0x161c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1615 1615 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 1616 1616 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1623 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1623 0x1623 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1617 1617 ioc_fiubs 1 val ; Flow C 0x1eee ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 03 GP03 1618 1618 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1619 1619 ioc_tvbs 2 fiu+val; Flow J 0x161a seq_br_type 2 Push (branch address) seq_branch_adr 1618 0x1618 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 161a 161a ioc_fiubs 1 val ; Flow J cc=False 0x1eee ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1eee 0x1eee seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 161b 161b seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 161c 161c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1616 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1616 0x1616 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 161d 161d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 161e 161e fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 161f 161f fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1620 1620 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1622 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1622 0x1622 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 1621 1621 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1622 1622 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1617 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1617 0x1617 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1623 1623 fiu_tivi_src c mar_0xc; Flow J cc=True 0x1619 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1619 0x1619 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1624 1624 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1625 1625 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c seq_en_micro 0 1626 ; -------------------------------------------------------------------------------------- 1626 ; 0x2800-0x28ff Execute Variant_Record,Field_Write,Fixed,Direct,fieldnum 1626 ; -------------------------------------------------------------------------------------- 1626 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum: 1626 1626 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1626 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1627 1627 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1628 ; -------------------------------------------------------------------------------------- 1628 ; 0x2900-0x29ff Execute Variant_Record,Field_Write,Fixed,Indirect,fieldnum 1628 ; -------------------------------------------------------------------------------------- 1628 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum: 1628 1628 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1628 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1629 1629 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 162a 162a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x162c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 162c 0x162c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 162b 162b fiu_fill_mode_src 0 ; Flow J 0x162e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 162e 0x162e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 162c 162c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 162d 162d fiu_fill_mode_src 0 ; Flow J 0x162e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 162e 0x162e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 162e 162e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d48 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d48 0x1d48 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 162f 162f seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 1630 ; -------------------------------------------------------------------------------------- 1630 ; 0x2a00-0x2aff Execute Variant_Record,Field_Write,Variant,Direct,fieldnum 1630 ; -------------------------------------------------------------------------------------- 1630 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum: 1630 1630 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1630 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1631 1631 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 1632 1632 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1637 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1637 0x1637 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 1633 1633 fiu_len_fill_lit 47 zero-fill 0x7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1634 1634 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d48 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d48 0x1d48 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1635 1635 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1636 1636 seq_br_type 7 Unconditional Call; Flow C 0x3275 seq_branch_adr 3275 0x3275 seq_en_micro 0 1637 1637 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1638 1638 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x1634 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1634 0x1634 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1639 1639 <halt> ; Flow R 163a ; -------------------------------------------------------------------------------------- 163a ; 0x2b00-0x2bff Execute Variant_Record,Field_Write,Variant,Indirect,fieldnum 163a ; -------------------------------------------------------------------------------------- 163a MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum: 163a 163a dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 163a dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 163b 163b fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 163c 163c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x163e ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 163e 0x163e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 163d 163d fiu_fill_mode_src 0 ; Flow J 0x1640 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1640 0x1640 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 163e 163e fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 163f 163f fiu_fill_mode_src 0 ; Flow J 0x1640 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1640 0x1640 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1640 1640 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1643 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1643 0x1643 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1641 1641 fiu_fill_mode_src 0 ; Flow J cc=True 0x1646 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1646 0x1646 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1642 1642 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1643 1643 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1644 1644 fiu_fill_mode_src 0 ; Flow J cc=True 0x1646 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1646 0x1646 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1645 1645 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1646 1646 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d48 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d48 0x1d48 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1647 1647 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1648 1648 seq_br_type 7 Unconditional Call; Flow C 0x3275 seq_branch_adr 3275 0x3275 seq_en_micro 0 1649 1649 <halt> ; Flow R 164a ; -------------------------------------------------------------------------------------- 164a ; 0x2400-0x24ff Execute Variant_Record,Field_Reference,Fixed,Direct,fieldnum 164a ; -------------------------------------------------------------------------------------- 164a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum: 164a 164a dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 164a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 164b 164b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 164c ; -------------------------------------------------------------------------------------- 164c ; 0x2500-0x25ff Execute Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 164c ; -------------------------------------------------------------------------------------- 164c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum: 164c 164c dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 164c dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 164d 164d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 164e 164e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1650 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1650 0x1650 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 164f 164f fiu_fill_mode_src 0 ; Flow J 0x1652 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1652 0x1652 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1650 1650 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1651 1651 fiu_fill_mode_src 0 ; Flow J 0x1652 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1652 0x1652 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1652 1652 fiu_load_var 1 hold_var; Flow C cc=True 0x32ae fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_b_adr 10 TOP 1653 1653 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1654 0x1654 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1654 1654 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1655 1655 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1656 1656 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x166e ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 166e 0x166e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1657 1657 <halt> ; Flow R 1658 ; -------------------------------------------------------------------------------------- 1658 ; 0x2600-0x26ff Execute Variant_Record,Field_Reference,Variant,Direct,fieldnum 1658 ; -------------------------------------------------------------------------------------- 1658 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum: 1658 1658 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1658 dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 1659 1659 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 165a 165a fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x165c fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 165c 0x165c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 165b 165b fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x1610 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1610 0x1610 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 165c 165c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 165d 165d fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x1610 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1610 0x1610 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 165e ; -------------------------------------------------------------------------------------- 165e ; 0x2700-0x27ff Execute Variant_Record,Field_Reference,Variant,Indirect,fieldnum 165e ; -------------------------------------------------------------------------------------- 165e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum: 165e 165e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 165e dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 165f 165f fiu_load_mdr 1 hold_mdr; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1660 1660 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1662 fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1662 0x1662 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1661 1661 fiu_fill_mode_src 0 ; Flow J 0x1664 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1664 0x1664 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1662 1662 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1663 1663 fiu_fill_mode_src 0 ; Flow J 0x1664 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1664 0x1664 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1664 1664 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1667 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1667 0x1667 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1665 1665 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x166a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 166a 0x166a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1666 1666 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1667 1667 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1668 1668 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x166a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 166a 0x166a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1669 1669 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 166a 166a fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 166b 0x166b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 166b 166b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 166c 166c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x167d seq_br_type 1 Branch True seq_branch_adr 167d 0x167d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 166d 166d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 166e 0x166e seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 166e 166e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 166f 166f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1671 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1671 0x1671 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1670 1670 fiu_fill_mode_src 0 ; Flow J 0x1673 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1673 0x1673 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1671 1671 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1672 1672 fiu_fill_mode_src 0 ; Flow J 0x1673 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1673 0x1673 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1673 1673 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 1674 1674 fiu_load_tar 1 hold_tar; Flow J 0x1675 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 167c 0x167c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1675 1675 ioc_tvbs 2 fiu+val; Flow J cc=True 0x1eee seq_br_type 1 Branch True seq_branch_adr 1eee 0x1eee seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 1676 1676 seq_br_type 1 Branch True; Flow J cc=True 0x1679 seq_branch_adr 1679 0x1679 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1677 1677 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1678 1678 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 1679 1679 ioc_tvbs 2 fiu+val; Flow J 0x167a seq_br_type 2 Push (branch address) seq_branch_adr 167c 0x167c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 167a 167a ioc_fiubs 1 val ; Flow J cc=False 0x1eee ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1eee 0x1eee seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 167b 167b seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 167c 167c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 167d 167d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 167e 167e seq_br_type 7 Unconditional Call; Flow C 0x3275 seq_branch_adr 3275 0x3275 seq_en_micro 0 167f ; -------------------------------------------------------------------------------------- 167f ; Comes from: 167f ; 1684 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 167f ; 1690 C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 167f ; 1696 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 167f ; -------------------------------------------------------------------------------------- 167f 167f fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1680 1680 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1681 1681 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 1682 0x1682 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 1682 1682 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1683 1683 <halt> ; Flow R 1684 ; -------------------------------------------------------------------------------------- 1684 ; 0x0160 Execute Variant_Record,Field_Read_Dynamic 1684 ; -------------------------------------------------------------------------------------- 1684 MACRO_Execute_Variant_Record,Field_Read_Dynamic: 1684 1684 dispatch_brk_class 8 ; Flow C 0x167f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1684 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167f 0x167f typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 22 VR12:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 1685 1685 seq_b_timing 0 Early Condition; Flow J cc=True 0x1686 ; Flow J cc=#0x0 0x1686 seq_br_type b Case False seq_branch_adr 1686 0x1686 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 1686 1686 seq_br_type 3 Unconditional Branch; Flow J 0x15f0 seq_branch_adr 15f0 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 1687 1687 seq_br_type 3 Unconditional Branch; Flow J 0x164c seq_branch_adr 164c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 1688 1688 seq_br_type 3 Unconditional Branch; Flow J 0x15fa seq_branch_adr 15fa MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum 1689 1689 seq_br_type 3 Unconditional Branch; Flow J 0x165e seq_branch_adr 165e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 168a ; -------------------------------------------------------------------------------------- 168a ; 0x015f Execute Variant_Record,Field_Write_Dynamic 168a ; -------------------------------------------------------------------------------------- 168a MACRO_Execute_Variant_Record,Field_Write_Dynamic: 168a 168a dispatch_brk_class 2 ; Flow C 0x167f dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 168a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167f 0x167f typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 21 VR12:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 168b 168b seq_b_timing 0 Early Condition; Flow J cc=True 0x168c ; Flow J cc=#0x0 0x168c seq_br_type b Case False seq_branch_adr 168c 0x168c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 168c 168c seq_br_type 3 Unconditional Branch; Flow J 0x1626 seq_branch_adr 1626 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum 168d 168d seq_br_type 3 Unconditional Branch; Flow J 0x1628 seq_branch_adr 1628 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 168e 168e seq_br_type 3 Unconditional Branch; Flow J 0x1630 seq_branch_adr 1630 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum 168f 168f seq_br_type 3 Unconditional Branch; Flow J 0x163a seq_branch_adr 163a MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 1690 ; -------------------------------------------------------------------------------------- 1690 ; 0x015e Execute Variant_Record,Field_Reference_Dynamic 1690 ; -------------------------------------------------------------------------------------- 1690 MACRO_Execute_Variant_Record,Field_Reference_Dynamic: 1690 1690 dispatch_brk_class 8 ; Flow C 0x167f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1690 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167f 0x167f typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3c VR05:1c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1691 1691 seq_b_timing 0 Early Condition; Flow J cc=True 0x1692 ; Flow J cc=#0x0 0x1692 seq_br_type b Case False seq_branch_adr 1692 0x1692 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 1692 1692 seq_br_type 3 Unconditional Branch; Flow J 0x164a seq_branch_adr 164a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 1693 1693 seq_br_type 3 Unconditional Branch; Flow J 0x164c seq_branch_adr 164c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 1694 1694 seq_br_type 3 Unconditional Branch; Flow J 0x1658 seq_branch_adr 1658 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum 1695 1695 seq_br_type 3 Unconditional Branch; Flow J 0x165e seq_branch_adr 165e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 1696 ; -------------------------------------------------------------------------------------- 1696 ; 0x015d Execute Variant_Record,Field_Type_Dynamic 1696 ; -------------------------------------------------------------------------------------- 1696 MACRO_Execute_Variant_Record,Field_Type_Dynamic: 1696 1696 dispatch_brk_class 8 ; Flow C 0x167f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1696 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 167f 0x167f typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 2c VR05:0c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1697 1697 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1698 1698 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1699 0x1699 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1699 1699 seq_br_type 7 Unconditional Call; Flow C 0x32b0 seq_branch_adr 32b0 0x32b0 169a ; -------------------------------------------------------------------------------------- 169a ; 0x2d00-0x2dff Execute Variant_Record,Field_Append,Fixed,Indirect,fieldnum 169a ; 0x2f00-0x2fff Execute Variant_Record,Field_Append,Variant,Indirect,fieldnum 169a ; -------------------------------------------------------------------------------------- 169a MACRO_Execute_Variant_Record,Field_Append,Fixed,Indirect,fieldnum: 169a MACRO_Execute_Variant_Record,Field_Append,Variant,Indirect,fieldnum: 169a 169a dispatch_brk_class 8 ; Flow C cc=False 0x32ab dispatch_csa_valid 3 dispatch_uadr 169a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 1e TOP - 2 typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 169b 169b fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 169c 169c fiu_vmux_sel 1 fill value; Flow C cc=True 0x32b0 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 169d 169d ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x169f seq_br_type 1 Branch True seq_branch_adr 169f 0x169f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 169e 169e fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 169f 169f fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x16a4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 16a4 0x16a4 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 16a0 16a0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16a1 16a1 seq_b_timing 0 Early Condition; Flow C cc=True 0x32ae seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16a2 16a2 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2458 seq_br_type 7 Unconditional Call seq_branch_adr 2458 0x2458 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16a3 16a3 seq_br_type 3 Unconditional Branch; Flow J 0x16b6 seq_branch_adr 16b6 0x16b6 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16a4 16a4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16a6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 16a6 0x16a6 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 16a5 16a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal 16a6 16a6 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x32ae fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 16a7 16a7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 16a8 16a8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16ab seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16ab 0x16ab seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 16a9 16a9 fiu_fill_mode_src 0 ; Flow J cc=True 0x16ae fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16ae 0x16ae typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16aa 16aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16af fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16af 0x16af typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16ab 16ab fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16ac 16ac fiu_fill_mode_src 0 ; Flow J cc=True 0x16ae fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16ae 0x16ae typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16ad 16ad fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16af fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16af 0x16af typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16ae 16ae <default> 16af 16af fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 09 GP09 val_alu_func 1b A_OR_B val_b_adr 08 GP08 val_rand c START_MULTIPLY 16b0 16b0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16b1 16b1 ioc_fiubs 1 val ; Flow J cc=True 0x16b4 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16b4 0x16b4 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 16b2 16b2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 16b3 16b3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 16b4 16b4 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 16b5 16b5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x16c8 seq_br_type 5 Call True seq_branch_adr 16c8 0x16c8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16b6 16b6 fiu_mem_start 2 start-rd; Flow C cc=True 0x32b0 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16b7 16b7 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16b8 16b8 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2458 seq_br_type 7 Unconditional Call seq_branch_adr 2458 0x2458 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16b9 16b9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 04 GP04 val_b_adr 03 GP03 16ba 16ba fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16bb 16bb fiu_fill_mode_src 0 ; Flow J cc=False 0x16c1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16c1 0x16c1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16bc 16bc fiu_fill_mode_src 0 ; Flow C cc=True 0x32b0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16bd 16bd fiu_fill_mode_src 0 ; Flow C cc=True 0x32b0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16be 16be ioc_load_wdr 0 ; Flow J 0x16c6 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16c6 0x16c6 seq_random 02 ? 16bf 16bf fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16c0 16c0 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 16c1 16c1 fiu_load_var 1 hold_var; Flow C cc=True 0x32b0 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16c2 16c2 fiu_fill_mode_src 0 ; Flow J cc=False 0x16bf fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 16bf 0x16bf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 16c3 16c3 fiu_fill_mode_src 0 ; Flow C cc=True 0x32b0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16c4 16c4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR 16c5 16c5 ioc_load_wdr 0 ; Flow J 0x16c6 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 16c6 0x16c6 val_b_adr 07 GP07 16c6 16c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16c7 16c7 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16c8 ; -------------------------------------------------------------------------------------- 16c8 ; Comes from: 16c8 ; 16b5 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 16c8 ; -------------------------------------------------------------------------------------- 16c8 16c8 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 16c9 16c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16cd fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16cd 0x16cd typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 16ca 16ca fiu_mem_start a start_continue_if_false; Flow J cc=True 0x16c7 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 16c7 0x16c7 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16cb 16cb fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16cc 16cc fiu_fill_mode_src 0 ; Flow J 0x16c8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16c8 0x16c8 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16cd 16cd seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 16ce 0x16ce seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 16ce 16ce seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16cf 16cf <halt> ; Flow R 16d0 ; -------------------------------------------------------------------------------------- 16d0 ; 0x2300-0x23ff Execute Variant_Record,Field_Type,fieldnum 16d0 ; -------------------------------------------------------------------------------------- 16d0 MACRO_Execute_Variant_Record,Field_Type,fieldnum: 16d0 16d0 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16d0 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 16d1 16d1 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16d2 16d2 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 16d3 0x16d3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 16d3 16d3 seq_br_type 7 Unconditional Call; Flow C 0x32b0 seq_branch_adr 32b0 0x32b0 seq_en_micro 0 seq_random 02 ? 16d4 ; -------------------------------------------------------------------------------------- 16d4 ; 0x2200-0x22ff Execute Variant_Record,Field_Constrain,fieldnum 16d4 ; -------------------------------------------------------------------------------------- 16d4 MACRO_Execute_Variant_Record,Field_Constrain,fieldnum: 16d4 16d4 dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16d4 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 16d5 16d5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 8 16d6 16d6 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x16d9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16d9 0x16d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 16d7 16d7 fiu_load_tar 1 hold_tar; Flow J cc=True 0x16e1 fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 16e1 0x16e1 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16d8 16d8 seq_br_type 7 Unconditional Call; Flow C 0x32b0 seq_branch_adr 32b0 0x32b0 16d9 16d9 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32b0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16da 16da fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16dc fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16dc 0x16dc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16db 16db fiu_fill_mode_src 0 ; Flow J 0x16de fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16de 0x16de typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16dc 16dc fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16dd 16dd fiu_fill_mode_src 0 ; Flow J 0x16de fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16de 0x16de typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16de 16de seq_br_type 1 Branch True; Flow J cc=True 0x16e1 seq_branch_adr 16e1 0x16e1 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B 16df 16df seq_b_timing 0 Early Condition; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 16e0 16e0 seq_br_type 7 Unconditional Call; Flow C 0x32b0 seq_branch_adr 32b0 0x32b0 16e1 16e1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16e8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16e8 0x16e8 typ_c_adr 36 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 16e2 16e2 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16e4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16e4 0x16e4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16e3 16e3 fiu_fill_mode_src 0 ; Flow J 0x16e6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16e6 0x16e6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16e4 16e4 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16e5 16e5 fiu_fill_mode_src 0 ; Flow J 0x16e6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16e6 0x16e6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16e6 16e6 seq_br_type 1 Branch True; Flow J cc=True 0x16e8 seq_branch_adr 16e8 0x16e8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 16e7 16e7 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 16e8 16e8 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16f2 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 16f2 0x16f2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16e9 16e9 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x16ee fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 16ee 0x16ee seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16ea 16ea fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16ec seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16ec 0x16ec seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16eb 16eb fiu_fill_mode_src 0 ; Flow J 0x16ee fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ee 0x16ee val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16ec 16ec fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16ed 16ed fiu_fill_mode_src 0 ; Flow J 0x16ee fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ee 0x16ee val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16ee 16ee fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x16f1 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16f1 0x16f1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16ef 16ef seq_br_type 0 Branch False; Flow J cc=False 0x16f1 seq_branch_adr 16f1 0x16f1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c 16f0 16f0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x29b5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 29b5 0x29b5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 16f1 16f1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 16f2 16f2 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x16f1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 16f1 0x16f1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 16f3 16f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x16f1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 16f1 0x16f1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 08 GP08 typ_frame 8 16f4 16f4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 16f5 16f5 ioc_load_wdr 0 ; Flow J 0x16f1 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16f1 0x16f1 seq_random 02 ? 16f6 ; -------------------------------------------------------------------------------------- 16f6 ; 0x2100-0x21ff Execute Variant_Record,Set_Bounds,fieldnum 16f6 ; -------------------------------------------------------------------------------------- 16f6 MACRO_Execute_Variant_Record,Set_Bounds,fieldnum: 16f6 16f6 dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16f6 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 16f7 16f7 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16f8 16f8 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16f9 16f9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a9 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 16fa 16fa fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x32a9 fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16fb 16fb fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1703 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1703 0x1703 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16fc 16fc fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16fd 16fd fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16ff fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16ff 0x16ff seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16fe 16fe fiu_fill_mode_src 0 ; Flow J 0x1701 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1701 0x1701 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16ff 16ff fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1700 1700 fiu_fill_mode_src 0 ; Flow J 0x1701 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1701 0x1701 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1701 1701 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1704 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1704 0x1704 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1702 1702 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1703 1703 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1704 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1704 0x1704 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1704 1704 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1705 1705 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1706 1706 fiu_mem_start 2 start-rd; Flow J 0x170d ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 170d 0x170d seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1707 1707 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1708 1708 ioc_fiubs 1 val ; Flow J cc=True 0x170b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 170b 0x170b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1709 1709 seq_b_timing 1 Latch Condition; Flow J cc=True 0x170b seq_br_type 1 Branch True seq_branch_adr 170b 0x170b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 170a 170a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 170b 170b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1727 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1727 0x1727 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 170c 170c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 170d 170d val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 170e 170e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 170f 170f fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1710 1710 fiu_load_var 1 hold_var; Flow C cc=False 0x32ac fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 1711 1711 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1712 1712 ioc_fiubs 0 fiu ; Flow J cc=True 0x1718 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1718 0x1718 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 20 TR05:00 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1713 1713 ioc_fiubs 1 val ; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1714 1714 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 1715 1715 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1719 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1719 0x1719 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0f GP0f val_a_adr 03 GP03 val_alu_func 7 INC_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1716 1716 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1717 1717 seq_br_type 3 Unconditional Branch; Flow J 0x1719 seq_branch_adr 1719 0x1719 1718 1718 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1719 1719 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1727 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1727 0x1727 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 171a 171a seq_b_timing 0 Early Condition; Flow J cc=False 0x1707 seq_br_type 0 Branch False seq_branch_adr 1707 0x1707 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 171b 171b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1724 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1724 0x1724 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 171c 171c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 171d 171d fiu_load_var 1 hold_var; Flow C cc=False 0x32ac fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 171e 171e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1727 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1727 0x1727 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 171f 171f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1724 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1724 0x1724 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1720 1720 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x171d seq_br_type 0 Branch False seq_branch_adr 171d 0x171d seq_cond_sel 67 REFRESH_MACRO_EVENT 1721 1721 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1722 1722 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 1723 1723 seq_br_type 3 Unconditional Branch; Flow J 0x171d seq_branch_adr 171d 0x171d 1724 1724 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1725 1725 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1726 1726 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1727 ; -------------------------------------------------------------------------------------- 1727 ; Comes from: 1727 ; 170b C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1727 ; 1719 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1727 ; 171e C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1727 ; -------------------------------------------------------------------------------------- 1727 1727 fiu_fill_mode_src 0 ; Flow J cc=False 0x172a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 172a 0x172a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1728 1728 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1729 1729 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 172a 172a fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 172b 172b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 172c 172c fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 172d 172d ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 172e ; -------------------------------------------------------------------------------------- 172e ; 0x2000-0x20ff Execute Variant_Record,Set_Variant,fieldnum 172e ; -------------------------------------------------------------------------------------- 172e MACRO_Execute_Variant_Record,Set_Variant,fieldnum: 172e 172e dispatch_brk_class 8 ; Flow C cc=True 0x32a9 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 172e dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 172f 172f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1730 1730 fiu_fill_mode_src 0 ; Flow J cc=False 0x1738 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1738 0x1738 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1731 1731 fiu_fill_mode_src 0 ; Flow C cc=False 0x32a9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 1732 1732 fiu_fill_mode_src 0 ; Flow C cc=False 0x32a9 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1733 1733 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1734 1734 ioc_load_wdr 0 ; Flow J cc=False 0x173f ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 173f 0x173f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1735 1735 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1736 1736 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1737 1737 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1738 1738 fiu_load_var 1 hold_var; Flow C cc=False 0x32a9 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1739 1739 fiu_fill_mode_src 0 ; Flow J cc=False 0x1736 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1736 0x1736 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 173a 173a fiu_fill_mode_src 0 ; Flow C cc=False 0x32a9 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3c GP03 173b 173b fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 173c 173c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 173d 173d ioc_load_wdr 0 ; Flow J cc=False 0x173f ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 173f 0x173f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 03 GP03 173e 173e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 173f 173f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1740 1740 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 1741 1741 fiu_vmux_sel 1 fill value; Flow C 0x2a2e ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a2e 0x2a2e val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1742 1742 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1743 1743 <halt> ; Flow R 1744 ; -------------------------------------------------------------------------------------- 1744 ; 0x016e Execute Variant_Record,Not_Equal 1744 ; 0x016f Execute Variant_Record,Equal 1744 ; -------------------------------------------------------------------------------------- 1744 MACRO_Execute_Variant_Record,Equal: 1744 MACRO_Execute_Variant_Record,Not_Equal: 1744 1744 dispatch_brk_class 8 ; Flow J cc=True 0x1746 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1744 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1746 0x1746 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1745 1745 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1746 1746 ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1747 1747 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1749 seq_br_type 1 Branch True seq_branch_adr 1749 0x1749 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1748 1748 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1749 1749 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 174a 174a ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 174b 174b seq_br_type 7 Unconditional Call; Flow C 0x26fc seq_branch_adr 26fc 0x26fc typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 174c 174c fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 174d 174d <halt> ; Flow R 174e ; -------------------------------------------------------------------------------------- 174e ; 0x016d Execute Variant_Record,Structure_Write 174e ; -------------------------------------------------------------------------------------- 174e MACRO_Execute_Variant_Record,Structure_Write: 174e 174e dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 174e dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 174f 174f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db9 0x1db9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1750 ; -------------------------------------------------------------------------------------- 1750 ; 0x016c Execute Variant_Record,Is_Constrained 1750 ; -------------------------------------------------------------------------------------- 1750 MACRO_Execute_Variant_Record,Is_Constrained: 1750 1750 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1750 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1751 1751 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1752 ; -------------------------------------------------------------------------------------- 1752 ; 0x015c Execute Variant_Record,Is_Constrained_Object 1752 ; -------------------------------------------------------------------------------------- 1752 MACRO_Execute_Variant_Record,Is_Constrained_Object: 1752 1752 dispatch_brk_class 8 ; Flow C 0x32fe dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1752 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 1753 1753 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1754 ; -------------------------------------------------------------------------------------- 1754 ; 0x015b Execute Variant_Record,Make_Constrained 1754 ; -------------------------------------------------------------------------------------- 1754 MACRO_Execute_Variant_Record,Make_Constrained: 1754 1754 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1754 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 1755 1755 <halt> ; Flow R 1756 ; -------------------------------------------------------------------------------------- 1756 ; 0x016b Execute Variant_Record,Read_Variant 1756 ; -------------------------------------------------------------------------------------- 1756 MACRO_Execute_Variant_Record,Read_Variant: 1756 1756 dispatch_brk_class 8 ; Flow J cc=True 0x1759 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1756 dispatch_uses_tos 1 seq_br_type 1 Branch True seq_branch_adr 1759 0x1759 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1757 1757 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1759 seq_br_type 0 Branch False seq_branch_adr 1759 0x1759 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1758 1758 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1759 1759 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1760 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1760 0x1760 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 175a 175a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x175c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 175c 0x175c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 175b 175b fiu_fill_mode_src 0 ; Flow J 0x175e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 175e 0x175e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 175c 175c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 175d 175d fiu_fill_mode_src 0 ; Flow J 0x175e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 175e 0x175e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 175e 175e fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 175f 0x175f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 175f 175f seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 1760 1760 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 1761 1761 <halt> ; Flow R 1762 ; -------------------------------------------------------------------------------------- 1762 ; 0x016a Execute Variant_Record,Indirects_Appended 1762 ; -------------------------------------------------------------------------------------- 1762 MACRO_Execute_Variant_Record,Indirects_Appended: 1762 1762 dispatch_brk_class 8 ; Flow C cc=False 0x32ab dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1762 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 1f TOP - 1 typ_frame 1f 1763 1763 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1764 1764 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 21 TR02:01 typ_b_adr 1f TOP - 1 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1765 1765 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1768 fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1768 0x1768 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 1e TR02:01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1766 1766 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 1767 0x1767 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 1767 1767 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? 1768 1768 fiu_load_var 1 hold_var; Flow J cc=True 0x176c fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 176c 0x176c typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1769 1769 fiu_mem_start 3 start-wr ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 176a 176a ioc_fiubs 1 val ; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 176b 176b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 176c 176c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 176d 176d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 176e 176e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32ae fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 176f 176f fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 typ_c_adr 1d TR02:02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1770 1770 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 01 GP01 1771 1771 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1772 ; -------------------------------------------------------------------------------------- 1772 ; 0x0169 Execute Variant_Record,Read_Discriminant_Constraint 1772 ; -------------------------------------------------------------------------------------- 1772 MACRO_Execute_Variant_Record,Read_Discriminant_Constraint: 1772 1772 dispatch_brk_class 8 ; Flow C cc=True 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1772 dispatch_uses_tos 1 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 2d TR09:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 1773 1773 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1774 1774 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B 1775 1775 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 30 TR05:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1776 1776 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1777 1777 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 1778 1778 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1779 1779 <halt> ; Flow R 177a ; -------------------------------------------------------------------------------------- 177a ; 0x0168 Execute Variant_Record,Reference_Makes_Copy 177a ; -------------------------------------------------------------------------------------- 177a MACRO_Execute_Variant_Record,Reference_Makes_Copy: 177a 177a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 177a dispatch_uses_tos 1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 177b 177b fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1780 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 21 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1780 0x1780 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 177c 177c ioc_tvbs 2 fiu+val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 177d 177d fiu_fill_mode_src 0 ; Flow J cc=False 0x177f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 177f 0x177f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 177e 177e seq_b_timing 0 Early Condition; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 177f 177f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1780 1780 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x177f fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 177f 0x177f 1781 1781 <halt> ; Flow R 1782 ; -------------------------------------------------------------------------------------- 1782 ; 0x0167 Execute Variant_Record,Structure_Query 1782 ; -------------------------------------------------------------------------------------- 1782 MACRO_Execute_Variant_Record,Structure_Query: 1782 1782 dispatch_brk_class 8 dispatch_csa_free 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1782 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1783 1783 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1785 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1785 0x1785 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1784 1784 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x1787 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1787 0x1787 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1785 1785 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1786 1786 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1787 1787 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1788 1788 fiu_mem_start 6 start_rd_if_false; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1789 1789 ioc_fiubs 1 val ; Flow C cc=True 0x1796 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1796 0x1796 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1e val_rand 2 DEC_LOOP_COUNTER 178a 178a fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 178b 178b fiu_load_var 1 hold_var; Flow J cc=False 0x1788 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1788 0x1788 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR10:01 typ_frame 10 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 178c 178c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x1793 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1793 0x1793 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 178d 178d fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1791 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1791 0x1791 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 7 178e 178e fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1794 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1794 0x1794 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 178f 178f fiu_load_var 1 hold_var; Flow C cc=True 0x1796 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1796 0x1796 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 1790 1790 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x178e seq_br_type 1 Branch True seq_branch_adr 178e 0x178e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 1791 1791 ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 1792 1792 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1793 1793 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 1794 1794 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1795 1795 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1796 ; -------------------------------------------------------------------------------------- 1796 ; Comes from: 1796 ; 1789 C True from color 0x1789 1796 ; 178f C True from color MACRO_Execute_Variant_Record,Structure_Query 1796 ; -------------------------------------------------------------------------------------- 1796 1796 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1797 1797 fiu_mem_start 2 start-rd; Flow J 0x32fe ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 1798 ; -------------------------------------------------------------------------------------- 1798 ; 0x0166 Execute Variant_Record,Component_Offset 1798 ; -------------------------------------------------------------------------------------- 1798 MACRO_Execute_Variant_Record,Component_Offset: 1798 1798 dispatch_brk_class 8 ; Flow C cc=False 0x32ae dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1798 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 1799 1799 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 179a 179a fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 179b 179b fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 179c 0x179c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 179c 179c seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? 179d 179d <halt> ; Flow R 179e ; -------------------------------------------------------------------------------------- 179e ; 0x0165 Execute Variant_Record,Convert 179e ; -------------------------------------------------------------------------------------- 179e MACRO_Execute_Variant_Record,Convert: 179e 179e dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 179e dispatch_uses_tos 1 ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 179f 179f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x17a2 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 17a2 0x17a2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 17a0 17a0 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 24e5 0x24e5 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17a1 17a1 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3274 seq_br_type 4 Call False seq_branch_adr 3274 0x3274 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 17a2 17a2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x17a5 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 17a5 0x17a5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 17a3 17a3 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17a4 17a4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 17a5 17a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR06:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 17a6 17a6 fiu_load_tar 1 hold_tar; Flow C cc=True 0x17ab fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 17ab 0x17ab seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 17a7 17a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2454 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17a8 17a8 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 17a9 17a9 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17aa 17aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2f TOP val_c_mux_sel 2 ALU 17ab ; -------------------------------------------------------------------------------------- 17ab ; Comes from: 17ab ; 17a6 C True from color 0x0a32 17ab ; -------------------------------------------------------------------------------------- 17ab 17ab seq_br_type 1 Branch True; Flow J cc=True 0x17ae seq_branch_adr 17ae 0x17ae seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17ac 17ac ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17ad 17ad seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 17ae 17ae ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17af 17af ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 17b0 ; -------------------------------------------------------------------------------------- 17b0 ; 0x0164 Execute Variant_Record,In_Type 17b0 ; -------------------------------------------------------------------------------------- 17b0 MACRO_Execute_Variant_Record,In_Type: 17b0 17b0 dispatch_brk_class 8 ; Flow J cc=True 0x17b2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17b0 seq_br_type 1 Branch True seq_branch_adr 17b2 0x17b2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17b1 17b1 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17b2 17b2 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e5 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e5 0x24e5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17b3 17b3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 17b4 ; -------------------------------------------------------------------------------------- 17b4 ; 0x0163 Execute Variant_Record,Not_In_Type 17b4 ; -------------------------------------------------------------------------------------- 17b4 MACRO_Execute_Variant_Record,Not_In_Type: 17b4 17b4 dispatch_brk_class 8 ; Flow J cc=True 0x17b6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17b4 seq_br_type 1 Branch True seq_branch_adr 17b6 0x17b6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17b5 17b5 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17b6 17b6 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e5 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e5 0x24e5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17b7 17b7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 17b8 ; -------------------------------------------------------------------------------------- 17b8 ; 0x0162 Execute Variant_Record,Check_In_Type 17b8 ; -------------------------------------------------------------------------------------- 17b8 MACRO_Execute_Variant_Record,Check_In_Type: 17b8 17b8 dispatch_brk_class 8 ; Flow J cc=True 0x17ba dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17b8 seq_br_type 1 Branch True seq_branch_adr 17ba 0x17ba seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17b9 17b9 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17ba 17ba fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e5 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e5 0x24e5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17bb 17bb fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17bc 0x17bc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 17bc 17bc seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 seq_en_micro 0 seq_random 02 ? 17bd 17bd <halt> ; Flow R 17be ; -------------------------------------------------------------------------------------- 17be ; 0x0161 Execute Variant_Record,Check_In_Formal_Type 17be ; -------------------------------------------------------------------------------------- 17be MACRO_Execute_Variant_Record,Check_In_Formal_Type: 17be 17be dispatch_brk_class 8 ; Flow J cc=True 0x17c0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17be seq_br_type 1 Branch True seq_branch_adr 17c0 0x17c0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17bf 17bf fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17c0 17c0 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e5 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e5 0x24e5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17c1 17c1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3274 seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 17c2 17c2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 17c3 17c3 <halt> ; Flow R 17c4 ; -------------------------------------------------------------------------------------- 17c4 ; 0x0125 Execute Any,Set_Constraint 17c4 ; -------------------------------------------------------------------------------------- 17c4 MACRO_Execute_Any,Set_Constraint: 17c4 17c4 dispatch_brk_class 8 ; Flow J cc=False 0x17d1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17c4 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 17d1 0x17d1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17c5 17c5 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x17c8 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17c8 0x17c8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17c6 17c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x17ca fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17ca 0x17ca seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 36 GP09 val_c_adr 36 GP09 17c7 17c7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x29b5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 29b5 0x29b5 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 17c8 17c8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17c9 0x17c9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 17c9 17c9 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? 17ca 17ca fiu_fill_mode_src 0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 17cb 17cb fiu_mem_start a start_continue_if_false; Flow J cc=False 0x17cd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17cd 0x17cd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 17cc 17cc fiu_fill_mode_src 0 ; Flow J 0x17cf fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17cf 0x17cf val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17cd 17cd fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 17ce 17ce fiu_fill_mode_src 0 ; Flow J 0x17cf fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17cf 0x17cf val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17cf 17cf seq_b_timing 0 Early Condition; Flow C cc=True 0x29b5 seq_br_type 5 Call True seq_branch_adr 29b5 0x29b5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 17d0 17d0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 17d1 17d1 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17d2 0x17d2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 17d2 17d2 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 17d3 17d3 <halt> ; Flow R 17d4 ; -------------------------------------------------------------------------------------- 17d4 ; 0x3c00-0x3cff Execute Record,Field_Read,fieldnum 17d4 ; -------------------------------------------------------------------------------------- 17d4 MACRO_Execute_Record,Field_Read,fieldnum: 17d4 17d4 dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17d4 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17d5 17d5 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x17de fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17de 0x17de seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17d6 17d6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x17d8 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17d8 0x17d8 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 17d7 17d7 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x17da fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17da 0x17da seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17d8 17d8 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 17d9 17d9 fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17da 0x17da seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17da 17da fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17db 0x17db seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 17db 17db fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17dc ; -------------------------------------------------------------------------------------- 17dc ; 0x017a Execute Record,Field_Read_Dynamic 17dc ; -------------------------------------------------------------------------------------- 17dc MACRO_Execute_Record,Field_Read_Dynamic: 17dc 17dc dispatch_brk_class 8 ; Flow C 0x1811 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17dc fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1811 0x1811 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17dd 17dd fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x17d6 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 17d6 0x17d6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17de 17de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 17df 17df <halt> ; Flow R 17e0 ; -------------------------------------------------------------------------------------- 17e0 ; 0x3800-0x38ff Execute Record,Field_Write,fieldnum 17e0 ; -------------------------------------------------------------------------------------- 17e0 MACRO_Execute_Record,Field_Write,fieldnum: 17e0 17e0 dispatch_brk_class 2 ; Flow C cc=True 0x32ae dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17e0 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17e1 17e1 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e2 ; -------------------------------------------------------------------------------------- 17e2 ; 0x0179 Execute Record,Field_Write_Dynamic 17e2 ; -------------------------------------------------------------------------------------- 17e2 MACRO_Execute_Record,Field_Write_Dynamic: 17e2 17e2 dispatch_brk_class 2 ; Flow C 0x1811 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 17e2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1811 0x1811 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17e3 17e3 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e4 ; -------------------------------------------------------------------------------------- 17e4 ; 0x3400-0x34ff Execute Record,Field_Reference,fieldnum 17e4 ; -------------------------------------------------------------------------------------- 17e4 MACRO_Execute_Record,Field_Reference,fieldnum: 17e4 17e4 dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17e4 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17e5 17e5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e6 ; -------------------------------------------------------------------------------------- 17e6 ; 0x0178 Execute Record,Field_Reference_Dynamic 17e6 ; -------------------------------------------------------------------------------------- 17e6 MACRO_Execute_Record,Field_Reference_Dynamic: 17e6 17e6 dispatch_brk_class 8 ; Flow C 0x1811 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17e6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1811 0x1811 seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 17e7 17e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e8 ; -------------------------------------------------------------------------------------- 17e8 ; 0x3000-0x30ff Execute Record,Field_Type,fieldnum 17e8 ; -------------------------------------------------------------------------------------- 17e8 MACRO_Execute_Record,Field_Type,fieldnum: 17e8 17e8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17e8 dispatch_uses_tos 1 ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17e9 17e9 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17ea 0x17ea seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 17ea 17ea seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 17eb 17eb <halt> ; Flow R 17ec ; -------------------------------------------------------------------------------------- 17ec ; 0x0177 Execute Record,Field_Type_Dynamic 17ec ; -------------------------------------------------------------------------------------- 17ec MACRO_Execute_Record,Field_Type_Dynamic: 17ec 17ec dispatch_brk_class 8 ; Flow C 0x1816 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17ec fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1816 0x1816 seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 17ed 17ed fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17ee 0x17ee seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 17ee 17ee seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 17ef 17ef <halt> ; Flow R 17f0 ; -------------------------------------------------------------------------------------- 17f0 ; 0x017e Execute Record,Not_Equal 17f0 ; 0x017f Execute Record,Equal 17f0 ; -------------------------------------------------------------------------------------- 17f0 MACRO_Execute_Record,Equal: 17f0 MACRO_Execute_Record,Not_Equal: 17f0 17f0 dispatch_brk_class 8 ; Flow C cc=False 0x1817 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17f0 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1817 0x1817 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 17f1 17f1 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32ae fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 17f2 17f2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x26fc fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 26fc 0x26fc typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 17f3 17f3 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 17f4 ; -------------------------------------------------------------------------------------- 17f4 ; 0x017d Execute Record,Structure_Write 17f4 ; -------------------------------------------------------------------------------------- 17f4 MACRO_Execute_Record,Structure_Write: 17f4 17f4 dispatch_brk_class 2 ; Flow C cc=False 0x1817 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17f4 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1817 0x1817 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17f5 17f5 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 17f6 17f6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x17f9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 17f9 0x17f9 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 17f7 17f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ab seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 17f8 17f8 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 17f9 17f9 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 17fa 17fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1eee seq_br_type 4 Call False seq_branch_adr 1eee 0x1eee seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 17fb 17fb fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17fc 0x17fc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 17fc 17fc seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 17fd 17fd <halt> ; Flow R 17fe ; -------------------------------------------------------------------------------------- 17fe ; 0x017c Execute Record,Component_Offset 17fe ; -------------------------------------------------------------------------------------- 17fe MACRO_Execute_Record,Component_Offset: 17fe 17fe dispatch_brk_class 8 ; Flow C cc=False 0x32ae dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17fe fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 17ff 17ff fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1800 1800 <default> 1801 1801 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1802 1802 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1803 0x1803 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1803 1803 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? 1804 ; -------------------------------------------------------------------------------------- 1804 ; 0x017b Execute Record,Convert 1804 ; -------------------------------------------------------------------------------------- 1804 MACRO_Execute_Record,Convert: 1804 1804 dispatch_brk_class 4 ; Flow C cc=False 0x1817 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1804 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 1817 0x1817 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1805 1805 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1806 1806 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x180a fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 180a 0x180a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1807 1807 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1808 1808 seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1809 1809 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180a 180a seq_br_type 1 Branch True; Flow J cc=True 0x180d seq_branch_adr 180d 0x180d seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180b 180b ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180c 180c seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 180d 180d ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180e 180e ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 180f 180f ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1810 1810 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1811 ; -------------------------------------------------------------------------------------- 1811 ; Comes from: 1811 ; 17dc C from color MACRO_Execute_Record,Field_Read,fieldnum 1811 ; 17e2 C from color 0x0000 1811 ; 17e6 C from color MACRO_Execute_Record,Field_Reference_Dynamic 1811 ; -------------------------------------------------------------------------------------- 1811 1811 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ae fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1812 1812 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ae seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1813 1813 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1814 1814 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1815 0x1815 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 10 TOP val_alu_func 19 X_XOR_B 1815 1815 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1816 ; -------------------------------------------------------------------------------------- 1816 ; Comes from: 1816 ; 17ec C from color MACRO_Execute_Record,Field_Type_Dynamic 1816 ; -------------------------------------------------------------------------------------- 1816 1816 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1812 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1812 0x1812 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1817 ; -------------------------------------------------------------------------------------- 1817 ; Comes from: 1817 ; 17f0 C False from color 0x09ad 1817 ; 17f4 C False from color MACRO_Execute_Record,Structure_Write 1817 ; 1804 C False from color 0x0a31 1817 ; -------------------------------------------------------------------------------------- 1817 1817 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand 8 SPARE_0x08 1818 1818 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1819 1819 <halt> ; Flow R 181a ; -------------------------------------------------------------------------------------- 181a ; 0x01de Execute Vector,Not_Equal 181a ; 0x01df Execute Vector,Equal 181a ; -------------------------------------------------------------------------------------- 181a MACRO_Execute_Vector,Equal: 181a MACRO_Execute_Vector,Not_Equal: 181a 181a dispatch_brk_class 8 ; Flow J cc=True 0x181c dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 181a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 181c 0x181c seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 181b 181b fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 181c 181c fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1827 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1827 0x1827 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 181d 181d fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 181e 181e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 181f 181f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1821 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1821 0x1821 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1820 1820 fiu_fill_mode_src 0 ; Flow J 0x1823 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1823 0x1823 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1821 1821 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1822 1822 fiu_fill_mode_src 0 ; Flow J 0x1823 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1823 0x1823 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1823 1823 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1824 1824 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1828 seq_br_type 1 Branch True seq_branch_adr 1828 0x1828 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1825 1825 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1826 1826 seq_br_type 3 Unconditional Branch; Flow J 0x1828 seq_branch_adr 1828 0x1828 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1827 1827 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1828 1828 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1833 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1833 0x1833 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1829 1829 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 182a 182a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 182b 182b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x182d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 182d 0x182d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 182c 182c fiu_fill_mode_src 0 ; Flow J 0x182f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 182f 0x182f val_c_adr 39 GP06 val_c_source 0 FIU_BUS 182d 182d fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 182e 182e fiu_fill_mode_src 0 ; Flow J 0x182f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 182f 0x182f val_c_adr 39 GP06 val_c_source 0 FIU_BUS 182f 182f seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1830 1830 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1834 seq_br_type 1 Branch True seq_branch_adr 1834 0x1834 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1831 1831 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1832 1832 seq_br_type 3 Unconditional Branch; Flow J 0x1834 seq_branch_adr 1834 0x1834 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1833 1833 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1834 1834 ioc_fiubs 1 val ; Flow C cc=True 0x26fc seq_br_type 5 Call True seq_branch_adr 26fc 0x26fc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1835 1835 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1836 0x1836 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1836 1836 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1837 0x1837 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1837 1837 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1839 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 1839 0x1839 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1838 1838 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1839 1839 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x183b ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 183b 0x183b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE 183a 183a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 183b 183b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 183c 0x183c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 183c 183c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 183d 183d <halt> ; Flow R 183e ; -------------------------------------------------------------------------------------- 183e ; 0x01c0 Execute Vector,Greater_Equal 183e ; -------------------------------------------------------------------------------------- 183e MACRO_Execute_Vector,Greater_Equal: 183e 183e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 183e ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 183f 183f fiu_mem_start 2 start-rd; Flow J 0x1842 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1842 MACRO_Execute_Vector,Less_Equal typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 1840 ; -------------------------------------------------------------------------------------- 1840 ; 0x01c2 Execute Vector,Greater 1840 ; -------------------------------------------------------------------------------------- 1840 MACRO_Execute_Vector,Greater: 1840 1840 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1840 ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 1841 1841 fiu_mem_start 2 start-rd; Flow J 0x1848 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1848 MACRO_Execute_Vector,Less typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 1842 ; -------------------------------------------------------------------------------------- 1842 ; 0x01bf Execute Vector,Less_Equal 1842 ; -------------------------------------------------------------------------------------- 1842 MACRO_Execute_Vector,Less_Equal: 1842 1842 dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1842 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1843 1843 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x184a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 184a 0x184a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 1844 1844 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1846 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1846 0x1846 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1845 1845 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x184a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 184a 0x184a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1846 1846 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1847 1847 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x184a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 184a 0x184a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1848 ; -------------------------------------------------------------------------------------- 1848 ; 0x01c1 Execute Vector,Less 1848 ; -------------------------------------------------------------------------------------- 1848 MACRO_Execute_Vector,Less: 1848 1848 dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1848 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 13 ONES typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1849 1849 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1844 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1844 0x1844 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 184a 184a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 184b 184b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 184c 184c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 184d 184d fiu_fill_mode_src 0 ; Flow J cc=False 0x1852 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1852 0x1852 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 184e 184e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1850 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1850 0x1850 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 184f 184f fiu_fill_mode_src 0 ; Flow J 0x1852 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1852 0x1852 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1850 1850 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1851 1851 fiu_fill_mode_src 0 ; Flow J 0x1852 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1852 0x1852 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1852 1852 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1853 1853 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1854 1854 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x185a fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 185a 0x185a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1855 1855 fiu_load_var 1 hold_var; Flow J cc=False 0x185d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 185d 0x185d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 11 TOP + 1 val_a_adr 05 GP05 val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 1856 1856 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1858 fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1858 0x1858 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1857 1857 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1858 1858 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x185e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 185e 0x185e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 val_m_b_src 2 Bits 32…47 1859 1859 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x185d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 185d 0x185d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 20 VR00:00 185a 185a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 185b 185b fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 185c 185c fiu_fill_mode_src 0 ; Flow J cc=False 0x1862 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1862 0x1862 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 185d 185d fiu_mem_start 2 start-rd; Flow J cc=True 0x1863 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1863 0x1863 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 185e 185e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1864 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1864 0x1864 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 185f 185f fiu_fill_mode_src 0 ; Flow J cc=True 0x1866 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1866 0x1866 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1860 1860 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x185b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 185b 0x185b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1861 1861 fiu_fill_mode_src 0 ; Flow J cc=True 0x185d fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 185d 0x185d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1862 1862 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1859 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1859 0x1859 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1863 1863 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1864 1864 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1865 1865 fiu_fill_mode_src 0 ; Flow J cc=False 0x1860 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1860 0x1860 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1866 1866 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1867 1867 fiu_mem_start 2 start-rd; Flow J 0x1860 seq_br_type 3 Unconditional Branch seq_branch_adr 1860 0x1860 1868 ; -------------------------------------------------------------------------------------- 1868 ; 0x01dd Execute Vector,First 1868 ; -------------------------------------------------------------------------------------- 1868 MACRO_Execute_Vector,First: 1868 1868 dispatch_brk_class 8 ; Flow J cc=True 0x186d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1868 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 186d 0x186d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1869 1869 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x186b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 186b 0x186b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 186a 186a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 186b 186b fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 186c 186c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 186d 186d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1869 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1869 0x1869 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 186e ; -------------------------------------------------------------------------------------- 186e ; 0x01dc Execute Vector,Last 186e ; -------------------------------------------------------------------------------------- 186e MACRO_Execute_Vector,Last: 186e 186e dispatch_brk_class 8 ; Flow J cc=True 0x1877 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 186e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1877 0x1877 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 186f 186f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1872 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1872 0x1872 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1870 1870 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1871 1871 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1875 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1875 0x1875 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1872 1872 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1873 1873 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1874 1874 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1875 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1875 0x1875 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1875 1875 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 1876 0x1876 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1876 1876 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1869 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1869 0x1869 seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 1877 1877 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1878 1878 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1879 1879 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 187a 187a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x187d fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 187d 0x187d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 187b 187b fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 187c 0x187c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 187c 187c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1869 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1869 0x1869 seq_en_micro 0 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 187d 187d fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 7 187e ; -------------------------------------------------------------------------------------- 187e ; 0x01db Execute Vector,Length 187e ; -------------------------------------------------------------------------------------- 187e MACRO_Execute_Vector,Length: 187e 187e dispatch_brk_class 8 ; Flow J cc=True 0x1869 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 187e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1869 0x1869 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 187f 187f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1869 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1869 0x1869 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1880 ; -------------------------------------------------------------------------------------- 1880 ; 0x01da Execute Vector,Bounds 1880 ; -------------------------------------------------------------------------------------- 1880 MACRO_Execute_Vector,Bounds: 1880 1880 dispatch_brk_class 8 ; Flow J cc=True 0x1887 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1880 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1887 0x1887 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1881 1881 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1884 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1884 0x1884 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1882 1882 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 1883 1883 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1875 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1875 0x1875 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1884 1884 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1885 1885 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 1886 1886 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1875 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1875 0x1875 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1887 1887 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1888 1888 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1889 1889 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 188a 188a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x187a seq_br_type 3 Unconditional Branch seq_branch_adr 187a 0x187a seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 188b 188b <halt> ; Flow R 188c ; -------------------------------------------------------------------------------------- 188c ; 0x01d9 Execute Vector,Reverse_Bounds 188c ; -------------------------------------------------------------------------------------- 188c MACRO_Execute_Vector,Reverse_Bounds: 188c 188c dispatch_brk_class 8 ; Flow J cc=True 0x1895 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 188c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1895 0x1895 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 188d 188d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1890 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1890 0x1890 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 188e 188e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 188f 188f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1893 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1893 0x1893 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1890 1890 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1891 1891 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 1892 1892 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1893 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1893 0x1893 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1893 1893 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 1894 0x1894 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1894 1894 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x189d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 189d 0x189d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 1895 1895 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1896 1896 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1897 1897 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1898 1898 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1899 1899 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x189c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 189c 0x189c typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 189a 189a fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 189b 0x189b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 189b 189b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x189d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 189d 0x189d typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 189c 189c fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 189d 189d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x189f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 189f 0x189f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 189e 189e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 189f 189f fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18a0 18a0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 18a1 18a1 <halt> ; Flow R 18a2 ; -------------------------------------------------------------------------------------- 18a2 ; 0x01d8 Execute Vector,Element_Type 18a2 ; -------------------------------------------------------------------------------------- 18a2 MACRO_Execute_Vector,Element_Type: 18a2 18a2 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18a2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18a3 18a3 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 18a4 18a4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 18a5 18a5 <halt> ; Flow R 18a6 ; -------------------------------------------------------------------------------------- 18a6 ; 0x01d7 Execute Vector,Field_Read 18a6 ; -------------------------------------------------------------------------------------- 18a6 MACRO_Execute_Vector,Field_Read: 18a6 18a6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18a6 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18a7 18a7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18b5 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18b5 0x18b5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18a8 18a8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18b2 fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18b2 0x18b2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18a9 18a9 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18bb fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18bb 0x18bb seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18aa 18aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18ac fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18ac 0x18ac seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 18ab 18ab fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x18ae fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18ae 0x18ae seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18ac 18ac fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18ad 18ad fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18ae 0x18ae seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18ae 18ae seq_br_type 0 Branch False; Flow J cc=False 0x18b1 seq_branch_adr 18b1 0x18b1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 18af 18af fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 18b0 0x18b0 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 18b0 18b0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18b1 18b1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 18b2 18b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18b3 18b3 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18aa fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18aa 0x18aa seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18b4 18b4 fiu_load_oreg 1 hold_oreg; Flow J 0x18aa fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18aa 0x18aa seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18b5 18b5 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18b6 18b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18bc fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18bc 0x18bc seq_cond_sel 64 OFFSET_REGISTER_???? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18b7 18b7 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18b8 18b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18bf fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18bf 0x18bf seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18b9 18b9 ioc_fiubs 1 val ; Flow J cc=False 0x18c2 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18c2 0x18c2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18ba 18ba fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x18aa fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 18aa 0x18aa seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18bb 18bb seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 18bc 18bc fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18bd 18bd fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18be 18be fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18b9 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18b9 0x18b9 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18bf 18bf ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18c0 18c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18c1 18c1 fiu_load_oreg 1 hold_oreg; Flow J 0x18aa fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18aa 0x18aa seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18c2 18c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18c3 18c3 fiu_load_oreg 1 hold_oreg; Flow J 0x18aa fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18aa 0x18aa seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18c4 ; -------------------------------------------------------------------------------------- 18c4 ; 0x018b Execute Subvector,Field_Read 18c4 ; -------------------------------------------------------------------------------------- 18c4 MACRO_Execute_Subvector,Field_Read: 18c4 18c4 dispatch_brk_class 8 ; Flow J 0x18a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18c4 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18a7 0x18a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18c5 18c5 <halt> ; Flow R 18c6 ; -------------------------------------------------------------------------------------- 18c6 ; 0x01d6 Execute Vector,Field_Write 18c6 ; -------------------------------------------------------------------------------------- 18c6 MACRO_Execute_Vector,Field_Write: 18c6 18c6 dispatch_brk_class 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18c6 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18c7 18c7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18ce fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18ce 0x18ce seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18c8 18c8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18cb fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18cb 0x18cb seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18c9 18c9 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18ca 18ca seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 18cb 18cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18cc 18cc fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d48 0x1d48 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18cd 18cd fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18ce 18ce fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18cf 18cf fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18d5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18d5 0x18d5 seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18d0 18d0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18d1 18d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18d8 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18d8 0x18d8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18d2 18d2 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x18db fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18db 0x18db typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 01 GP01 val_rand c START_MULTIPLY 18d3 18d3 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18d4 18d4 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 18d5 18d5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18d6 18d6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18d7 18d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18d2 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18d2 0x18d2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18d8 18d8 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18d9 18d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18da 18da fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18db 18db seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18dc 18dc fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18dd 18dd <halt> ; Flow R 18de ; -------------------------------------------------------------------------------------- 18de ; 0x018a Execute Subvector,Field_Write 18de ; -------------------------------------------------------------------------------------- 18de MACRO_Execute_Subvector,Field_Write: 18de 18de dispatch_brk_class 2 ; Flow J 0x18c7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18de dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18c7 0x18c7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18df 18df <halt> ; Flow R 18e0 ; -------------------------------------------------------------------------------------- 18e0 ; 0x01d5 Execute Vector,Field_Reference 18e0 ; -------------------------------------------------------------------------------------- 18e0 MACRO_Execute_Vector,Field_Reference: 18e0 18e0 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18e0 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18e1 18e1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18e8 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18e8 0x18e8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18e2 18e2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18e5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18e5 0x18e5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18e3 18e3 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 18e4 0x18e4 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18e4 18e4 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 18e5 18e5 ioc_tvbs 2 fiu+val; Flow J cc=False 0x18e4 seq_br_type 0 Branch False seq_branch_adr 18e4 0x18e4 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18e6 18e6 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 18e7 0x18e7 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18e7 18e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18e8 18e8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18e9 18e9 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18f0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18f0 0x18f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18ea 18ea fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18eb 18eb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18f3 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18f3 0x18f3 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18ec 18ec fiu_load_tar 1 hold_tar; Flow J cc=False 0x18ee fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18ee 0x18ee typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18ed 18ed fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x18e4 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 18e4 0x18e4 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18ee 18ee seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18ef 18ef fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18f0 18f0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18f1 18f1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18f2 18f2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18ec fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18ec 0x18ec seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18f3 18f3 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18f4 18f4 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18f5 18f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18f6 ; -------------------------------------------------------------------------------------- 18f6 ; 0x0189 Execute Subvector,Field_Reference 18f6 ; -------------------------------------------------------------------------------------- 18f6 MACRO_Execute_Subvector,Field_Reference: 18f6 18f6 dispatch_brk_class 8 ; Flow J 0x18e1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f6 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_br_type 3 Unconditional Branch seq_branch_adr 18e1 0x18e1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18f7 18f7 <halt> ; Flow R 18f8 ; -------------------------------------------------------------------------------------- 18f8 ; 0x01d4 Execute Vector,Structure_Write 18f8 ; -------------------------------------------------------------------------------------- 18f8 MACRO_Execute_Vector,Structure_Write: 18f8 18f8 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f8 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18f9 18f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1dea fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dea 0x1dea seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 18fa ; -------------------------------------------------------------------------------------- 18fa ; 0x01d1 Execute Vector,Xor 18fa ; 0x01d2 Execute Vector,Or 18fa ; 0x01d3 Execute Vector,And 18fa ; -------------------------------------------------------------------------------------- 18fa MACRO_Execute_Vector,And: 18fa MACRO_Execute_Vector,Or: 18fa MACRO_Execute_Vector,Xor: 18fa 18fa dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18fa dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18fb 18fb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1900 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1900 0x1900 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 18fc 18fc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18fe seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18fe 0x18fe seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 18fd 18fd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1901 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1901 0x1901 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18fe 18fe fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18ff 18ff fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1901 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1901 0x1901 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1900 1900 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1901 1901 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_frame 2 1902 1902 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1903 1903 fiu_fill_mode_src 0 ; Flow J cc=True 0x1905 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1905 0x1905 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1904 1904 ioc_fiubs 2 typ ; Flow J 0x190f seq_br_type 3 Unconditional Branch seq_branch_adr 190f 0x190f val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1905 1905 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1907 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1907 0x1907 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 1906 1906 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1909 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1909 0x1909 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1907 1907 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1908 1908 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1909 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1909 0x1909 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1909 1909 fiu_fill_mode_src 0 ; Flow J cc=False 0x190b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 190b 0x190b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 190a 190a fiu_fill_mode_src 0 ; Flow J 0x190d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 190d 0x190d typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 190b 190b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 190c 190c fiu_fill_mode_src 0 ; Flow J 0x190d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 190d 0x190d typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 190d 190d ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 190e 190e ioc_fiubs 2 typ ; Flow J 0x190f seq_br_type 3 Unconditional Branch seq_branch_adr 190f 0x190f typ_a_adr 03 GP03 val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 190f 190f fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3273 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1910 1910 fiu_len_fill_lit 7d zero-fill 0x3d; Flow J cc=True 0x1913 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1913 0x1913 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1911 1911 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x191d seq_br_type f Unconditional Case Call seq_branch_adr 191d 0x191d seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1912 1912 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1913 1913 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1918 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1918 0x1918 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1914 1914 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1919 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1919 0x1919 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 1915 1915 fiu_fill_mode_src 0 ; Flow J 0x1916 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1916 0x1916 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1916 1916 fiu_fill_mode_src 0 ; Flow J cc=False 0x191b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 191b 0x191b seq_cond_sel 65 CROSS_WORD_FIELD~ 1917 1917 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1918 1918 ioc_load_wdr 0 ; Flow J 0x1912 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1912 0x1912 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 1919 1919 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 191a 191a fiu_fill_mode_src 0 ; Flow J 0x1916 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1916 0x1916 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 191b 191b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 191c 191c fiu_fill_mode_src 0 ; Flow J 0x1918 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1918 0x1918 typ_mar_cntl 6 INCREMENT_MAR 191d ; -------------------------------------------------------------------------------------- 191d ; Comes from: 191d ; 1911 C #0x0 from color MACRO_Execute_Vector,And 191d ; -------------------------------------------------------------------------------------- 191d 191d seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191e 191e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191f 191f seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1920 1920 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1921 1921 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192d 0x192d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1922 1922 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1931 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1931 0x1931 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1923 1923 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1921 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1921 0x1921 1924 1924 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1925 1925 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192d 0x192d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1926 1926 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1931 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1931 0x1931 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1927 1927 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1925 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1925 0x1925 1928 1928 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1929 1929 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192d 0x192d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 192a 192a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1931 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1931 0x1931 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 192b 192b ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1929 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1929 0x1929 192c 192c seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 192d ; -------------------------------------------------------------------------------------- 192d ; Comes from: 192d ; 1921 C from color 0x191d 192d ; 1925 C from color 0x1924 192d ; 1929 C from color 0x1928 192d ; -------------------------------------------------------------------------------------- 192d 192d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1933 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1933 0x1933 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 192e 192e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 192f 192f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1935 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1935 0x1935 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1930 1930 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1931 ; -------------------------------------------------------------------------------------- 1931 ; Comes from: 1931 ; 1922 C from color 0x191d 1931 ; 1926 C from color 0x1924 1931 ; 192a C from color 0x1928 1931 ; -------------------------------------------------------------------------------------- 1931 1931 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1937 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1937 0x1937 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1932 1932 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 1933 1933 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1934 1934 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x192f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 192f 0x192f seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1935 1935 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1936 1936 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1937 1937 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1938 1938 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1939 1939 <halt> ; Flow R 193a ; -------------------------------------------------------------------------------------- 193a ; 0x01d0 Execute Vector,Complement 193a ; -------------------------------------------------------------------------------------- 193a MACRO_Execute_Vector,Complement: 193a 193a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 193a dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 193b 193b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3e GP01 val_c_source 0 FIU_BUS 193c 193c fiu_fill_mode_src 0 ; Flow J cc=True 0x193e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 193e 0x193e seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 193d 193d ioc_fiubs 2 typ ; Flow J 0x1948 seq_br_type 3 Unconditional Branch seq_branch_adr 1948 0x1948 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 193e 193e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1940 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1940 0x1940 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 193f 193f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1942 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1942 0x1942 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1940 1940 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1941 1941 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1942 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1942 0x1942 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1942 1942 fiu_fill_mode_src 0 ; Flow J cc=False 0x1944 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1944 0x1944 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1943 1943 fiu_fill_mode_src 0 ; Flow J 0x1946 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 1944 1944 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1945 1945 fiu_fill_mode_src 0 ; Flow J 0x1946 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1946 1946 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1947 1947 ioc_fiubs 2 typ ; Flow J 0x1948 seq_br_type 3 Unconditional Branch seq_branch_adr 1948 0x1948 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1948 1948 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1959 seq_br_type 1 Branch True seq_branch_adr 1959 0x1959 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1949 1949 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 194a 194a seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 194b 194b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x194e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 194e 0x194e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B 194c 194c seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 194d 194d fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B 194e 194e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1955 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1955 0x1955 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 194f 194f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1950 1950 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1951 1951 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1957 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1957 0x1957 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1952 1952 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1953 1953 ioc_load_wdr 0 ; Flow J cc=False 0x194b ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 194b 0x194b 1954 1954 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1955 1955 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1956 1956 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1950 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1950 0x1950 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1957 1957 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1958 1958 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1953 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1953 0x1953 typ_mar_cntl 6 INCREMENT_MAR 1959 1959 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x195e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 195e 0x195e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS 195a 195a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x195f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 195f 0x195f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 195b 195b fiu_fill_mode_src 0 ; Flow J 0x195c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 195c 0x195c typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 195c 195c fiu_fill_mode_src 0 ; Flow J cc=False 0x1961 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1961 0x1961 seq_cond_sel 65 CROSS_WORD_FIELD~ 195d 195d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 195e 195e ioc_load_wdr 0 ; Flow J 0x1954 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1954 0x1954 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 195f 195f fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1960 1960 fiu_fill_mode_src 0 ; Flow J 0x195c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 195c 0x195c typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1961 1961 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1962 1962 fiu_fill_mode_src 0 ; Flow J 0x195e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 195e 0x195e typ_mar_cntl 6 INCREMENT_MAR 1963 1963 <halt> ; Flow R 1964 ; -------------------------------------------------------------------------------------- 1964 ; 0x01cf Execute Vector,Slice_Read 1964 ; -------------------------------------------------------------------------------------- 1964 MACRO_Execute_Vector,Slice_Read: 1964 1964 dispatch_brk_class 8 ; Flow C cc=True 0x32ae dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1964 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP 1965 1965 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1966 1966 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1986 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1986 0x1986 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1967 1967 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x196a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 196a 0x196a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1968 1968 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1969 1969 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 196a 196a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 196b 196b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x197d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 197d 0x197d seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 196c 196c ioc_fiubs 0 fiu ; Flow C cc=False 0x329c ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 196d 196d ioc_fiubs 1 val ; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 196e 196e ioc_tvbs 2 fiu+val; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 196f 196f fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1970 1970 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1971 1971 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x197a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 197a 0x197a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1972 1972 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32ac ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 1973 1973 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1974 1974 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1975 1975 fiu_mem_start 2 start-rd; Flow J cc=False 0x1979 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1979 0x1979 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1976 1976 ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1977 1977 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1978 1978 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1979 1979 ioc_fiubs 2 typ ; Flow C 0x329c seq_br_type 7 Unconditional Call seq_branch_adr 329c 0x329c seq_en_micro 0 typ_a_adr 05 GP05 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 197a 197a fiu_tivi_src c mar_0xc; Flow C cc=False 0x32ac ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 197b 197b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 197c 197c fiu_fill_mode_src 0 ; Flow J 0x1974 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1974 0x1974 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 197d 197d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 197e 197e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1982 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1982 0x1982 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 197f 197f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1980 1980 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 1981 1981 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x196d fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 196d 0x196d typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1982 1982 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1983 1983 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 1984 1984 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 1985 1985 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x196d fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 196d 0x196d typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1986 1986 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32ac fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 30 TR05:10 typ_frame 5 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 1987 1987 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1988 1988 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1989 1989 fiu_fill_mode_src 0 ; Flow J cc=False 0x1990 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1990 0x1990 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 198a 198a fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 198b 198b fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 198c 198c fiu_fill_mode_src 0 ; Flow J cc=True 0x1993 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1993 0x1993 seq_cond_sel 64 OFFSET_REGISTER_???? 198d 198d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 198e 198e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 198f 198f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1990 1990 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1991 1991 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1992 1992 fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1993 1993 fiu_fill_mode_src 0 ; Flow J 0x198e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 198e 0x198e seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1994 ; -------------------------------------------------------------------------------------- 1994 ; 0x01ce Execute Vector,Slice_Write 1994 ; -------------------------------------------------------------------------------------- 1994 MACRO_Execute_Vector,Slice_Write: 1994 1994 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1994 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 1995 1995 fiu_load_tar 1 hold_tar; Flow C cc=False 0x19bc fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19bc 0x19bc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1996 1996 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19b7 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19b7 0x19b7 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1997 1997 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x199a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 199a 0x199a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1998 1998 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1999 1999 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 199a 199a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19a5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19a5 0x19a5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 199b 199b ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 199c 199c ioc_fiubs 1 val ; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 199d 199d ioc_tvbs 2 fiu+val; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 199e 199e fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 199f 199f fiu_mem_start a start_continue_if_false seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 1d TOP - 3 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19a0 19a0 ioc_load_wdr 0 ; Flow J cc=True 0x19ae ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ae 0x19ae seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_latch 1 typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 19a1 19a1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x19b9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b9 0x19b9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19a2 19a2 ioc_fiubs 1 val ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19a3 19a3 ioc_fiubs 1 val ; Flow C cc=True 0x1eee seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 19a4 19a4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 19a5 19a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 19a6 19a6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19aa seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19aa 0x19aa seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 19a7 19a7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 19a8 19a8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19a9 19a9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199c fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199c 0x199c typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19aa 19aa fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19ab 19ab fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 19ac 19ac fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19ad 19ad fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199c fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199c 0x199c typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19ae 19ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 19af 19af fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19b3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19b3 0x19b3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19b0 19b0 fiu_fill_mode_src 0 ; Flow C cc=False 0x19b9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b9 0x19b9 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19b1 19b1 ioc_fiubs 1 val ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19b2 19b2 seq_br_type 3 Unconditional Branch; Flow J 0x19a3 seq_branch_adr 19a3 0x19a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19b3 19b3 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19b4 19b4 fiu_fill_mode_src 0 ; Flow C cc=False 0x19b9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b9 0x19b9 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19b5 19b5 ioc_fiubs 1 val ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19b6 19b6 seq_br_type 3 Unconditional Branch; Flow J 0x19a3 seq_branch_adr 19a3 0x19a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19b7 19b7 ioc_fiubs 1 val ; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 19b8 19b8 seq_br_type 3 Unconditional Branch; Flow J 0x199e seq_branch_adr 199e 0x199e val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 19b9 ; -------------------------------------------------------------------------------------- 19b9 ; Comes from: 19b9 ; 19a1 C False from color MACRO_Execute_Vector,Slice_Write 19b9 ; 19b0 C False from color MACRO_Execute_Vector,Slice_Write 19b9 ; 19b4 C False from color MACRO_Execute_Vector,Slice_Write 19b9 ; -------------------------------------------------------------------------------------- 19b9 19b9 ioc_fiubs 1 val ; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 19ba 19ba ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 19bb 0x19bb seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 19bb 19bb seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 19bc ; -------------------------------------------------------------------------------------- 19bc ; Comes from: 19bc ; 1995 C False from color MACRO_Execute_Vector,Slice_Write 19bc ; -------------------------------------------------------------------------------------- 19bc 19bc fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19bd 19bd fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19be 19be seq_br_type a Unconditional Return; Flow R 19bf 19bf <halt> ; Flow R 19c0 ; -------------------------------------------------------------------------------------- 19c0 ; 0x01cd Execute Vector,Slice_Reference 19c0 ; -------------------------------------------------------------------------------------- 19c0 MACRO_Execute_Vector,Slice_Reference: 19c0 19c0 dispatch_brk_class 2 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19c0 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19c1 19c1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x19ca fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 19ca 0x19ca seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19c2 19c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ae fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 26 TR06:06 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 10 TOP 19c3 19c3 fiu_mem_start 4 continue ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 19c4 19c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19c9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 19c9 0x19c9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19c5 19c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3273 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19c6 19c6 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 19c7 19c7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3273 seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 19c8 19c8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19c9 19c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19ca ; -------------------------------------------------------------------------------------- 19ca ; Comes from: 19ca ; 19c1 C True from color MACRO_Execute_Vector,Slice_Reference 19ca ; -------------------------------------------------------------------------------------- 19ca 19ca fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19cd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19cd 0x19cd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 19cb 19cb fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19cc 19cc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 19cd 19cd fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19ce 19ce fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19cf 19cf fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 19d0 ; -------------------------------------------------------------------------------------- 19d0 ; 0x01cc Execute Vector,Catenate 19d0 ; -------------------------------------------------------------------------------------- 19d0 MACRO_Execute_Vector,Catenate: 19d0 19d0 dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19d0 dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19d1 19d1 fiu_fill_mode_src 0 ; Flow J cc=False 0x19d8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 19d8 0x19d8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19d2 19d2 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19d5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19d5 0x19d5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 19d3 19d3 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 19d4 19d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19d9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19d9 0x19d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d5 19d5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19d6 19d6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 19d7 19d7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19d9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19d9 0x19d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d8 19d8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d9 19d9 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 19da 19da fiu_mem_start a start_continue_if_false; Flow C cc=True 0x3279 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 19db 19db fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19dc 19dc fiu_fill_mode_src 0 ; Flow J cc=False 0x19e3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 19e3 0x19e3 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_source 0 FIU_BUS 19dd 19dd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19e0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19e0 0x19e0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19de 19de fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 19df 19df fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19e3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19e3 0x19e3 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19e0 19e0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19e1 19e1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 19e2 19e2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19e3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19e3 0x19e3 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19e3 19e3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19e4 19e4 fiu_load_var 1 hold_var; Flow J cc=True 0x19e6 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19e6 0x19e6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 19e5 19e5 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32ac seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac 19e6 19e6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_b_adr 05 GP05 val_rand c START_MULTIPLY 19e7 19e7 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 19e8 19e8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 19e9 19e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19f8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19f8 0x19f8 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 19ea 19ea fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3272 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 19eb 19eb fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 19ec 19ec seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19ed 19ed ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 19ee 19ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19ef 19ef fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 19f0 19f0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x19f2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19f2 0x19f2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 19f1 19f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x19f4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19f4 0x19f4 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 19f2 19f2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 19f3 19f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x19f4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 19f4 0x19f4 typ_mar_cntl 6 INCREMENT_MAR 19f4 19f4 ioc_load_wdr 0 ; Flow C 0x1eee ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 seq_random 02 ? 19f5 19f5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19f6 19f6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eee fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19f7 19f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 19f8 19f8 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19f9 19f9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 19fa 19fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19ef fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ef 0x19ef seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19fb 19fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x19fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 19fe 0x19fe seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 19fc 19fc fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 19fd 19fd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19ff seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19ff 0x19ff seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 19fe 19fe fiu_fill_mode_src 0 ; Flow J 0x1a02 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a02 0x1a02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 19ff 19ff fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a00 1a00 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1a01 1a01 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a02 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1a02 0x1a02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 1a02 1a02 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a09 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a09 0x1a09 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 1a03 1a03 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a04 1a04 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a05 1a05 fiu_fill_mode_src 0 ; Flow J cc=True 0x1a0c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1a0c 0x1a0c seq_cond_sel 64 OFFSET_REGISTER_???? 1a06 1a06 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 1a07 1a07 ioc_fiubs 2 typ ; Flow C cc=True 0x32ac ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a08 1a08 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a09 1a09 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a0a 1a0a fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a0b 1a0b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a0c 1a0c fiu_fill_mode_src 0 ; Flow J 0x1a07 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 1a07 0x1a07 typ_mar_cntl 6 INCREMENT_MAR 1a0d 1a0d <halt> ; Flow R 1a0e ; -------------------------------------------------------------------------------------- 1a0e ; 0x01cb Execute Vector,Append 1a0e ; -------------------------------------------------------------------------------------- 1a0e MACRO_Execute_Vector,Append: 1a0e 1a0e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a0e fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a0f 1a0f fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a10 1a10 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a11 1a11 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a12 1a12 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a13 1a13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a22 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a22 0x1a22 typ_c_adr 3c GP03 val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a14 1a14 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a15 1a15 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1a17 seq_br_type 1 Branch True seq_branch_adr 1a17 0x1a17 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a16 1a16 val_c_adr 3c GP03 1a17 1a17 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a18 1a18 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a19 1a19 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a1a 1a1a fiu_fill_mode_src 0 ; Flow J cc=False 0x1a20 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a20 0x1a20 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a1b 1a1b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a1c 1a1c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 1a1d 1a1d fiu_vmux_sel 1 fill value; Flow C cc=True 0x1eee ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a1e 1a1e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a1f 1a1f fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a20 1a20 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a21 1a21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a1c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a1c 0x1a1c typ_mar_cntl 6 INCREMENT_MAR 1a22 1a22 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1a23 1a23 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a2c ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a2c 0x1a2c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a24 1a24 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a25 1a25 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a2f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1a2f 0x1a2f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a26 1a26 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a27 1a27 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3272 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a28 1a28 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a29 1a29 ioc_fiubs 1 val ; Flow J cc=True 0x1a19 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a19 0x1a19 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a2a 1a2a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a19 seq_br_type 1 Branch True seq_branch_adr 1a19 0x1a19 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a2b 1a2b seq_br_type 3 Unconditional Branch; Flow J 0x1a19 seq_branch_adr 1a19 0x1a19 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a2c 1a2c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a2d 1a2d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a2e 1a2e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a26 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1a26 0x1a26 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a2f 1a2f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator 1a30 1a30 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32ac seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_frame 6 1a31 1a31 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a26 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a26 0x1a26 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 1a32 ; -------------------------------------------------------------------------------------- 1a32 ; 0x01ca Execute Vector,Prepend 1a32 ; -------------------------------------------------------------------------------------- 1a32 MACRO_Execute_Vector,Prepend: 1a32 1a32 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a32 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a33 1a33 fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a34 1a34 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a35 1a35 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a36 1a36 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a37 1a37 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1a44 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a44 0x1a44 typ_c_adr 3c GP03 val_a_adr 07 GP07 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a38 1a38 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a39 1a39 fiu_load_tar 1 hold_tar; Flow C cc=False 0x3272 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a3a 1a3a fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a3b 1a3b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a3c 1a3c fiu_fill_mode_src 0 ; Flow J cc=False 0x1a42 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a42 0x1a42 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a3d 1a3d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a3e 1a3e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 6 1a3f 1a3f fiu_vmux_sel 1 fill value; Flow C cc=True 0x1eee ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a40 1a40 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a41 1a41 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a42 1a42 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a43 1a43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a3e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a3e 0x1a3e typ_mar_cntl 6 INCREMENT_MAR 1a44 1a44 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1a45 1a45 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1a4c fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a4c 0x1a4c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a46 1a46 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a47 1a47 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a48 1a48 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a49 1a49 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1a3a fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a3a 0x1a3a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a4a 1a4a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a3a seq_br_type 1 Branch True seq_branch_adr 1a3a 0x1a3a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a4b 1a4b seq_br_type 3 Unconditional Branch; Flow J 0x1a3a seq_branch_adr 1a3a 0x1a3a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a4c 1a4c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a4d 1a4d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a4e 1a4e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a47 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 1a47 0x1a47 1a4f ; -------------------------------------------------------------------------------------- 1a4f ; Comes from: 1a4f ; 1a9c C True from color 0x0a2f 1a4f ; 1aa4 C True from color 0x0a2f 1a4f ; 1aba C True from color 0x0aa1 1a4f ; -------------------------------------------------------------------------------------- 1a4f 1a4f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1a50 1a50 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a52 seq_br_type 1 Branch True seq_branch_adr 1a52 0x1a52 1a51 1a51 fiu_fill_mode_src 0 ; Flow J 0x1a53 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a53 0x1a53 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1a52 1a52 fiu_fill_mode_src 0 ; Flow J 0x1a53 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a53 0x1a53 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a53 1a53 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a55 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a55 0x1a55 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1a54 1a54 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a55 1a55 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a56 1a56 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a57 1a57 <halt> ; Flow R 1a58 ; -------------------------------------------------------------------------------------- 1a58 ; 0x01c7 Execute Vector,Convert 1a58 ; -------------------------------------------------------------------------------------- 1a58 MACRO_Execute_Vector,Convert: 1a58 1a58 dispatch_brk_class 4 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a58 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a59 1a59 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a5a 1a5a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a72 seq_br_type 1 Branch True seq_branch_adr 1a72 0x1a72 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a5b 1a5b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a65 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a65 0x1a65 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a5c 1a5c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1a5d 1a5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1a5e 1a5e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1a5f 1a5f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1a60 1a60 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a62 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a62 0x1a62 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a61 1a61 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a62 1a62 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 1a63 1a63 ioc_fiubs 1 val ; Flow C cc=True 0x1eee seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1a64 1a64 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a65 ; -------------------------------------------------------------------------------------- 1a65 ; Comes from: 1a65 ; 1a5b C True from color 0x0a2f 1a65 ; 1a72 C True from color 0x0a2f 1a65 ; 1a9b C True from color 0x0a2f 1a65 ; -------------------------------------------------------------------------------------- 1a65 1a65 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a68 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a68 0x1a68 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a66 1a66 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a67 1a67 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a68 1a68 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a69 1a69 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a6a 1a6a fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a6b ; -------------------------------------------------------------------------------------- 1a6b ; Comes from: 1a6b ; 1a8d C False from color 0x0a2f 1a6b ; -------------------------------------------------------------------------------------- 1a6b 1a6b fiu_mem_start 2 start-rd; Flow J 0x1a70 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1a70 0x1a70 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6c ; -------------------------------------------------------------------------------------- 1a6c ; Comes from: 1a6c ; 1a73 C False from color 0x0a2f 1a6c ; -------------------------------------------------------------------------------------- 1a6c 1a6c fiu_mem_start 2 start-rd; Flow C 0x1a70 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1a70 0x1a70 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6d 1a6d fiu_mem_start 2 start-rd; Flow J 0x32fe ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6e ; -------------------------------------------------------------------------------------- 1a6e ; Comes from: 1a6e ; 1a77 C False from color 0x0a2f 1a6e ; -------------------------------------------------------------------------------------- 1a6e 1a6e fiu_mem_start 2 start-rd; Flow C 0x1a70 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1a70 0x1a70 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6f 1a6f fiu_mem_start 2 start-rd; Flow J 0x32fe ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a70 1a70 <default> 1a71 1a71 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1a72 1a72 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a65 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a65 0x1a65 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a73 1a73 fiu_load_var 1 hold_var; Flow C cc=False 0x1a6c fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 1a6c 0x1a6c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B 1a74 1a74 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a75 1a75 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1a8c seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a8c 0x1a8c typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a76 1a76 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a77 1a77 seq_br_type 4 Call False; Flow C cc=False 0x1a6e seq_branch_adr 1a6e 0x1a6e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1a78 1a78 ioc_fiubs 1 val ; Flow C cc=True 0x3279 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1a79 1a79 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a7a 1a7a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a7c fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a7c 0x1a7c seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a7b 1a7b ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a7c 1a7c fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 04 GP04 1a7d 1a7d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a7e 1a7e fiu_fill_mode_src 0 ; Flow J cc=False 0x1a88 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a88 0x1a88 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1a7f 1a7f fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1a80 1a80 ioc_load_wdr 0 ; Flow C cc=True 0x1eee ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1a81 1a81 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1a82 0x1a82 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a82 1a82 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1a83 1a83 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a84 1a84 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a8a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a8a 0x1a8a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1a85 1a85 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a86 1a86 ioc_load_wdr 0 ; Flow C cc=True 0x32ac ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_rand 6 CHECK_CLASS_A_??_B 1a87 1a87 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a88 1a88 fiu_fill_mode_src 0 ; Flow C cc=False 0x32ac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1a89 1a89 fiu_fill_mode_src 0 ; Flow J 0x1a80 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a80 0x1a80 typ_mar_cntl 6 INCREMENT_MAR 1a8a 1a8a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a8b 1a8b fiu_fill_mode_src 0 ; Flow J 0x1a86 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a86 0x1a86 typ_mar_cntl 6 INCREMENT_MAR 1a8c 1a8c fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a8d 1a8d ioc_fiubs 2 typ ; Flow C cc=False 0x1a6b seq_br_type 4 Call False seq_branch_adr 1a6b 0x1a6b seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a8e 1a8e ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1a8f 1a8f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1a92 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a92 0x1a92 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1a90 1a90 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a91 1a91 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a92 1a92 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a94 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a94 0x1a94 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a93 1a93 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a94 1a94 ioc_fiubs 1 val ; Flow J cc=True 0x1a96 seq_br_type 1 Branch True seq_branch_adr 1a96 0x1a96 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 1a95 1a95 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1a96 1a96 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1a97 1a97 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a98 ; -------------------------------------------------------------------------------------- 1a98 ; 0x01c6 Execute Vector,Convert_To_Formal 1a98 ; -------------------------------------------------------------------------------------- 1a98 MACRO_Execute_Vector,Convert_To_Formal: 1a98 1a98 dispatch_brk_class 4 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a98 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a99 1a99 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a9a 1a9a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a72 seq_br_type 1 Branch True seq_branch_adr 1a72 0x1a72 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a9b 1a9b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a65 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a65 0x1a65 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a9c 1a9c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4f seq_br_type 5 Call True seq_branch_adr 1a4f 0x1a4f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1a9d 1a9d fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1a9e 1a9e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1a5e seq_br_type 0 Branch False seq_branch_adr 1a5e 0x1a5e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1a9f 1a9f seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1aa0 ; -------------------------------------------------------------------------------------- 1aa0 ; 0x01c5 Execute Vector,In_Type 1aa0 ; -------------------------------------------------------------------------------------- 1aa0 MACRO_Execute_Vector,In_Type: 1aa0 1aa0 dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1aa0 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1aa1 1aa1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1aa2 1aa2 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1ab1 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ab1 0x1ab1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 1aa3 1aa3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa7 0x1aa7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1aa4 1aa4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4f seq_br_type 5 Call True seq_branch_adr 1a4f 0x1a4f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1aa5 1aa5 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1aa6 0x1aa6 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 1aa6 1aa6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1aa7 ; -------------------------------------------------------------------------------------- 1aa7 ; Comes from: 1aa7 ; 1aa3 C True from color 0x0a2f 1aa7 ; 1ab1 C True from color 0x0a2f 1aa7 ; 1ab9 C True from color 0x0aa1 1aa7 ; 1abd C True from color 0x0aa1 1aa7 ; -------------------------------------------------------------------------------------- 1aa7 1aa7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1aaa seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1aaa 0x1aaa seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1aa8 1aa8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1aa9 1aa9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1aaa 1aaa fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1aab 1aab fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1aac 1aac fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1aad 1aad <halt> ; Flow R 1aae ; -------------------------------------------------------------------------------------- 1aae ; 0x01c4 Execute Vector,Not_In_Type 1aae ; -------------------------------------------------------------------------------------- 1aae MACRO_Execute_Vector,Not_In_Type: 1aae 1aae dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1aae dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1aaf 1aaf fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ab0 1ab0 fiu_tivi_src 4 fiu_var; Flow J cc=False 0x1aa3 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1aa3 0x1aa3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 1ab1 1ab1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa7 0x1aa7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1ab2 1ab2 fiu_load_var 1 hold_var; Flow J cc=False 0x1aa6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 1aa6 0x1aa6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 1ab3 1ab3 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ab4 1ab4 ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ab5 1ab5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1aa6 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1aa6 0x1aa6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1ab6 ; -------------------------------------------------------------------------------------- 1ab6 ; 0x01c3 Execute Vector,Check_In_Type 1ab6 ; -------------------------------------------------------------------------------------- 1ab6 MACRO_Execute_Vector,Check_In_Type: 1ab6 1ab6 dispatch_brk_class 8 ; Flow C cc=False 0x1ac3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ab6 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac3 0x1ac3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1ab7 1ab7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ab8 1ab8 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1abd seq_br_type 1 Branch True seq_branch_adr 1abd 0x1abd seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 1ab9 1ab9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa7 0x1aa7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1aba 1aba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4f seq_br_type 5 Call True seq_branch_adr 1a4f 0x1a4f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1abb 1abb fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1abc 0x1abc seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1abc 1abc seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 1abd 1abd fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa7 0x1aa7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1abe 1abe fiu_load_var 1 hold_var; Flow C cc=False 0x3272 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3272 0x3272 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 1abf 1abf fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ac0 1ac0 ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ac1 1ac1 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1ac2 0x1ac2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1ac2 1ac2 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1ac3 ; -------------------------------------------------------------------------------------- 1ac3 ; Comes from: 1ac3 ; 1842 C False from color MACRO_Execute_Vector,Greater_Equal 1ac3 ; 1848 C False from color MACRO_Execute_Vector,Greater_Equal 1ac3 ; 18fa C False from color MACRO_Execute_Vector,And 1ac3 ; 19c0 C False from color MACRO_Execute_Vector,Slice_Reference 1ac3 ; 19d0 C False from color MACRO_Execute_Vector,Catenate 1ac3 ; 1a58 C False from color 0x0a2f 1ac3 ; 1a98 C False from color 0x0a2f 1ac3 ; 1aa0 C False from color 0x0a2f 1ac3 ; 1aae C False from color 0x0a2f 1ac3 ; -------------------------------------------------------------------------------------- 1ac3 1ac3 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ac4 1ac4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1ac5 1ac5 seq_br_type a Unconditional Return; Flow R 1ac6 ; -------------------------------------------------------------------------------------- 1ac6 ; 0x022f Execute Access,Equal 1ac6 ; -------------------------------------------------------------------------------------- 1ac6 MACRO_Execute_Access,Equal: 1ac6 1ac6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ac6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1ac7 1ac7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 ; 0x022e Execute Access,Not_Equal 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 MACRO_Execute_Access,Not_Equal: 1ac8 1ac8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ac8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1ac9 1ac9 <halt> ; Flow R 1aca ; -------------------------------------------------------------------------------------- 1aca ; 0x022d Execute Access,Is_Null 1aca ; -------------------------------------------------------------------------------------- 1aca MACRO_Execute_Access,Is_Null: 1aca 1aca dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1aca fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1acb 1acb <halt> ; Flow R 1acc ; -------------------------------------------------------------------------------------- 1acc ; 0x022c Execute Access,Not_Null 1acc ; -------------------------------------------------------------------------------------- 1acc MACRO_Execute_Access,Not_Null: 1acc 1acc dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1acc fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1acd 1acd <halt> ; Flow R 1ace ; -------------------------------------------------------------------------------------- 1ace ; 0x022b Execute Access,Set_Null 1ace ; -------------------------------------------------------------------------------------- 1ace MACRO_Execute_Access,Set_Null: 1ace 1ace dispatch_brk_class 2 ; Flow J cc=True 0x1ad2 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ace fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ad2 0x1ad2 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 14 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1acf 1acf fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 1ad0 1ad0 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 1ad1 1ad1 ioc_load_wdr 0 ; Flow J 0x1ac7 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1ac7 0x1ac7 val_b_adr 39 VR02:19 val_frame 2 1ad2 1ad2 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3279 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 1ad3 1ad3 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x1ad5 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ad5 0x1ad5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 1ad4 1ad4 fiu_fill_mode_src 0 ; Flow J 0x1ad8 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ad8 0x1ad8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1ad5 1ad5 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ad6 1ad6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1ad7 1ad7 fiu_load_var 1 hold_var; Flow J 0x1ad8 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ad8 0x1ad8 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1ad8 1ad8 ioc_load_wdr 0 ; Flow J 0x1ac7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac7 0x1ac7 1ad9 1ad9 <halt> ; Flow R 1ada ; -------------------------------------------------------------------------------------- 1ada ; 0x022a Execute Access,Element_Type 1ada ; -------------------------------------------------------------------------------------- 1ada MACRO_Execute_Access,Element_Type: 1ada 1ada dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ada dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1adb 1adb fiu_load_tar 1 hold_tar; Flow J cc=False 0x1ade fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1ade 0x1ade seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1adc 1adc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1add 1add fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1ade 1ade fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 1adf 0x1adf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 1adf 1adf seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 1ae0 ; -------------------------------------------------------------------------------------- 1ae0 ; 0x0229 Execute Access,All_Read 1ae0 ; -------------------------------------------------------------------------------------- 1ae0 MACRO_Execute_Access,All_Read: 1ae0 1ae0 dispatch_brk_class 8 ; Flow C cc=True 0x3271 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ae0 dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 1ae1 1ae1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ae7 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1ae7 0x1ae7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1ae2 1ae2 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1ae3 1ae3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ae5 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ae5 0x1ae5 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1ae4 1ae4 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1ae8 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1ae8 0x1ae8 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ae5 1ae5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ae6 1ae6 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1ae8 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1ae8 0x1ae8 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ae7 1ae7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ae8 1ae8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ae9 0x1ae9 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ae9 1ae9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1aea ; -------------------------------------------------------------------------------------- 1aea ; 0x0228 Execute Access,All_Write 1aea ; -------------------------------------------------------------------------------------- 1aea MACRO_Execute_Access,All_Write: 1aea 1aea dispatch_brk_class 2 ; Flow C cc=True 0x3271 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1aea dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 1aeb 1aeb fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d48 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d48 0x1d48 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1aec 1aec fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1aed 1aed fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1aee 1aee fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 1aef 1aef <halt> ; Flow R 1af0 ; -------------------------------------------------------------------------------------- 1af0 ; 0x0227 Execute Access,All_Reference 1af0 ; -------------------------------------------------------------------------------------- 1af0 MACRO_Execute_Access,All_Reference: 1af0 1af0 dispatch_brk_class 8 ; Flow C cc=True 0x3271 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1af0 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1af1 1af1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1af2 ; -------------------------------------------------------------------------------------- 1af2 ; 0x0226 Execute Access,Convert 1af2 ; -------------------------------------------------------------------------------------- 1af2 MACRO_Execute_Access,Convert: 1af2 1af2 dispatch_brk_class 4 ; Flow J cc=True 0x1af4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af2 seq_br_type 1 Branch True seq_branch_adr 1af4 0x1af4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 1af3 1af3 seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1af4 1af4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b0b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b0b 0x1b0b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1af5 1af5 <halt> ; Flow R 1af6 ; -------------------------------------------------------------------------------------- 1af6 ; 0x0222 Execute Access,Convert_Reference 1af6 ; -------------------------------------------------------------------------------------- 1af6 MACRO_Execute_Access,Convert_Reference: 1af6 1af6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1af7 1af7 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 1af8 1af8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 1af9 1af9 typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 1afa 1afa fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1afb 0x1afb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 1afb 1afb seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_csa_cntl 3 POP_CSA 1afc ; -------------------------------------------------------------------------------------- 1afc ; 0x0225 Execute Access,In_Type 1afc ; -------------------------------------------------------------------------------------- 1afc MACRO_Execute_Access,In_Type: 1afc 1afc dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1afc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1afd 0x1afd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1afd 1afd ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1afe 1afe typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1aff 1aff seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b00 1b00 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1b01 1b01 <halt> ; Flow R 1b02 ; -------------------------------------------------------------------------------------- 1b02 ; 0x0224 Execute Access,Not_In_Type 1b02 ; -------------------------------------------------------------------------------------- 1b02 MACRO_Execute_Access,Not_In_Type: 1b02 1b02 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b02 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b03 0x1b03 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1b03 1b03 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b04 1b04 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1b05 1b05 seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b06 1b06 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b07 1b07 <halt> ; Flow R 1b08 ; -------------------------------------------------------------------------------------- 1b08 ; 0x0223 Execute Access,Check_In_Type 1b08 ; -------------------------------------------------------------------------------------- 1b08 MACRO_Execute_Access,Check_In_Type: 1b08 1b08 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b08 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 1b09 1b09 seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b0a 1b0a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b0b 0x1b0b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1b0b 1b0b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1b0c 1b0c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1b0d 1b0d seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1b0e ; -------------------------------------------------------------------------------------- 1b0e ; 0x0114 Execute Access,Size 1b0e ; -------------------------------------------------------------------------------------- 1b0e MACRO_Execute_Access,Size: 1b0e 1b0e dispatch_brk_class 8 ; Flow J cc=False 0x1b12 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b0e dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 1b12 0x1b12 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 10 1b0f 1b0f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b10 1b10 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1b11 1b11 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b12 1b12 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 10 TOP 1b13 1b13 seq_br_type 3 Unconditional Branch; Flow J 0x1b0f seq_branch_adr 1b0f 0x1b0f typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 1b14 ; -------------------------------------------------------------------------------------- 1b14 ; 0x0220 Execute Access,Deallocate 1b14 ; -------------------------------------------------------------------------------------- 1b14 MACRO_Execute_Access,Deallocate: 1b14 1b14 dispatch_brk_class 8 ; Flow J cc=True 0x1b1f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b14 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b1f 0x1b1f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1b15 1b15 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b16 1b16 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b17 1b17 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b18 1b18 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1b1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b1f 0x1b1f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 13 1b19 1b19 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b1a 1b1a fiu_fill_mode_src 0 ; Flow J cc=False 0x1b20 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b20 0x1b20 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 1b1b 1b1b fiu_fill_mode_src 0 ; Flow J cc=False 0x1b25 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b25 0x1b25 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b1c 1b1c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b1d 1b1d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b1e 1b1e ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 1b1f 1b1f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b20 1b20 fiu_fill_mode_src 0 ; Flow J cc=False 0x1b25 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b25 0x1b25 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1b21 1b21 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b22 1b22 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_c_adr 30 GP0f 1b23 1b23 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 0f GP0f 1b24 1b24 seq_br_type 3 Unconditional Branch; Flow J 0x1b1d seq_branch_adr 1b1d 0x1b1d val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b25 1b25 fiu_mem_start 2 start-rd; Flow C 0x3575 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3575 0x3575 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b26 1b26 fiu_mem_start 2 start-rd; Flow J cc=True 0x1b17 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b17 0x1b17 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b27 1b27 <halt> ; Flow R 1b28 ; -------------------------------------------------------------------------------------- 1b28 ; 0x0221 Execute Access,Allow_Deallocate 1b28 ; -------------------------------------------------------------------------------------- 1b28 MACRO_Execute_Access,Allow_Deallocate: 1b28 1b28 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b28 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b29 1b29 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b2a 1b2a fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1ac7 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac7 0x1ac7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b2b 1b2b typ_c_adr 3d GP02 1b2c 1b2c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b2d 1b2d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1ac7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac7 0x1ac7 val_a_adr 21 VR13:01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 1b2e 1b2e ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1ac7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ac7 0x1ac7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 39 GP06 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1b2f 1b2f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 1b30 1b30 ioc_load_wdr 0 ; Flow J 0x1ac7 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac7 0x1ac7 typ_b_adr 06 GP06 1b31 1b31 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32a9 seq_br_type 1 Branch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 1b32 1b32 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a9 seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_frame 11 1b33 1b33 <halt> ; Flow R 1b34 ; -------------------------------------------------------------------------------------- 1b34 ; 0x0080 QQUnknown InMicrocode 1b34 ; -------------------------------------------------------------------------------------- 1b34 MACRO_1b34_QQUnknown_InMicrocode: 1b34 1b34 dispatch_brk_class 0 ; Flow J cc=False 0x32ab dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b34 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32ab 0x32ab seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1b35 1b35 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b36 1b36 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 1b37 1b37 ioc_fiubs 2 typ ; Flow J cc=True 0x32ab ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ab 0x32ab seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b38 1b38 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 01 GP01 val_b_adr 01 GP01 1b39 1b39 ioc_load_wdr 0 ; Flow J 0x1ac7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac7 0x1ac7 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1b3a ; -------------------------------------------------------------------------------------- 1b3a ; 0x0082 QQUnknown InMicrocode 1b3a ; -------------------------------------------------------------------------------------- 1b3a MACRO_1b3a_QQUnknown_InMicrocode: 1b3a 1b3a dispatch_brk_class 0 ; Flow J cc=False 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b3a dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1b3b 1b3b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b3c 1b3c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b3d 1b3d fiu_mem_start 3 start-wr; Flow J cc=True 0x32a9 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1b3e 1b3e ioc_load_wdr 0 ; Flow J 0x1ac7 seq_br_type 3 Unconditional Branch seq_branch_adr 1ac7 0x1ac7 typ_csa_cntl 3 POP_CSA 1b3f 1b3f <halt> ; Flow R 1b40 ; -------------------------------------------------------------------------------------- 1b40 ; 0x0081 QQUnknown InMicrocode 1b40 ; -------------------------------------------------------------------------------------- 1b40 MACRO_1b40_QQUnknown_InMicrocode: 1b40 1b40 dispatch_brk_class 0 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b40 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b41 1b41 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b42 1b42 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b43 1b43 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b44 ; -------------------------------------------------------------------------------------- 1b44 ; 0x01fe Execute Array,Not_Equal 1b44 ; 0x01ff Execute Array,Equal 1b44 ; -------------------------------------------------------------------------------------- 1b44 MACRO_Execute_Array,Equal: 1b44 MACRO_Execute_Array,Not_Equal: 1b44 1b44 dispatch_brk_class 8 ; Flow J cc=True 0x1b46 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b44 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1b46 0x1b46 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1b45 1b45 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b46 1b46 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b47 1b47 seq_br_type 2 Push (branch address); Flow J 0x1b48 seq_branch_adr 1b75 0x1b75 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1b48 1b48 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x1b60 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1b60 0x1b60 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1b49 1b49 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b4a 1b4a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b4b 1b4b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b4c 1b4c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b53 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b53 0x1b53 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b4d 1b4d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b4e 1b4e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1b70 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1b70 0x1b70 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b4f 1b4f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b57 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b57 0x1b57 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b50 1b50 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b51 1b51 seq_br_type 1 Branch True; Flow J cc=True 0x22b4 seq_branch_adr 22b4 0x22b4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b52 1b52 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b53 1b53 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b54 1b54 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b55 1b55 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1b70 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1b70 0x1b70 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b56 1b56 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1b50 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1b50 0x1b50 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b57 1b57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b5a 0x1b5a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b58 1b58 seq_br_type 1 Branch True; Flow J cc=True 0x22bc seq_branch_adr 22bc 0x22bc seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b59 1b59 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b5a ; -------------------------------------------------------------------------------------- 1b5a ; Comes from: 1b5a ; 1b57 C from color 0x09a8 1b5a ; 1b68 C from color 0x09a8 1b5a ; -------------------------------------------------------------------------------------- 1b5a 1b5a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b5d ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b5d 0x1b5d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1b5b 1b5b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b5c 1b5c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b6b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b6b 0x1b6b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b5d 1b5d fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b5e 1b5e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b5f 1b5f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b6b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b6b 0x1b6b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b60 1b60 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b61 1b61 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1b62 1b62 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b66 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b66 0x1b66 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b63 1b63 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b64 1b64 seq_br_type 1 Branch True; Flow J cc=True 0x22ae seq_branch_adr 22ae 0x22ae seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b65 1b65 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b66 1b66 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b67 1b67 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b68 1b68 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b5a 0x1b5a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b69 1b69 seq_br_type 1 Branch True; Flow J cc=True 0x22aa seq_branch_adr 22aa 0x22aa seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b6a 1b6a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b6b 1b6b seq_br_type 0 Branch False; Flow J cc=False 0x1b6d seq_branch_adr 1b6d 0x1b6d seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1b6c 1b6c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1b6d 1b6d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1b6e 1b6e seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1b6f 0x1b6f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1b6f 1b6f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1b70 ; -------------------------------------------------------------------------------------- 1b70 ; Comes from: 1b70 ; 1b4e C from color 0x09a8 1b70 ; 1b55 C from color 0x09a8 1b70 ; -------------------------------------------------------------------------------------- 1b70 1b70 seq_br_type 0 Branch False; Flow J cc=False 0x1b72 seq_branch_adr 1b72 0x1b72 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 1b71 1b71 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b72 1b72 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1b73 1b73 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1b74 0x1b74 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1b74 1b74 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1b75 1b75 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1b78 seq_br_type 0 Branch False seq_branch_adr 1b78 0x1b78 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b76 1b76 ioc_fiubs 1 val ; Flow C 0x26fc seq_br_type 7 Unconditional Call seq_branch_adr 26fc 0x26fc seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 07 GP07 1b77 1b77 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1b78 1b78 seq_br_type 7 Unconditional Call; Flow C 0x1b7e seq_branch_adr 1b7e 0x1b7e typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1b79 1b79 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1b7b seq_br_type 1 Branch True seq_branch_adr 1b7b 0x1b7b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1b7a 1b7a seq_br_type 7 Unconditional Call; Flow C 0x1b7e seq_branch_adr 1b7e 0x1b7e typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1b7b 1b7b seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b7c 1b7c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b7d 0x1b7d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1b7d 1b7d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b7e ; -------------------------------------------------------------------------------------- 1b7e ; Comes from: 1b7e ; 1b78 C from color 0x1b75 1b7e ; 1b7a C from color 0x1b75 1b7e ; -------------------------------------------------------------------------------------- 1b7e 1b7e ioc_fiubs 2 typ ; Flow J cc=False 0x2256 seq_br_type 0 Branch False seq_branch_adr 2256 0x2256 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 07 GP07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1b7f 1b7f ioc_fiubs 1 val ; Flow J 0x225e seq_br_type 3 Unconditional Branch seq_branch_adr 225e 0x225e seq_en_micro 0 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1b80 ; -------------------------------------------------------------------------------------- 1b80 ; Comes from: 1b80 ; 1b98 C from color MACRO_Execute_Array,First 1b80 ; 1b9a C from color MACRO_Execute_Array,Last 1b80 ; 1b9c C from color MACRO_Execute_Array,Length 1b80 ; 1b9e C from color MACRO_Execute_Array,Last 1b80 ; 1ba0 C from color MACRO_Execute_Array,First 1b80 ; -------------------------------------------------------------------------------------- 1b80 1b80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1b8c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b8c 0x1b8c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP 1b81 1b81 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b82 1b82 fiu_len_fill_lit 77 zero-fill 0x37; Flow C cc=True 0x32a9 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1b83 1b83 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b84 1b84 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1b86 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b86 0x1b86 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1c DEC_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b85 1b85 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b86 1b86 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 04 GP04 1b87 1b87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1b88 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1b88 0x1b88 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1b88 1b88 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b8a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b8a 0x1b8a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1b89 1b89 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1b8a 1b8a fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b8b 1b8b fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1b8c 1b8c fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1b81 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b81 0x1b81 typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1b8d 1b8d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1b8e 1b8e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b90 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b90 0x1b90 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 1b8f 1b8f fiu_fill_mode_src 0 ; Flow J 0x1b92 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b92 0x1b92 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b90 1b90 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b91 1b91 fiu_fill_mode_src 0 ; Flow J 0x1b92 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b92 0x1b92 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b92 1b92 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1b94 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b94 0x1b94 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1b93 1b93 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b94 1b94 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b95 1b95 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1b96 1b96 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1b88 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1b88 0x1b88 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 1b97 1b97 <halt> ; Flow R 1b98 ; -------------------------------------------------------------------------------------- 1b98 ; 0x01fd Execute Array,First 1b98 ; -------------------------------------------------------------------------------------- 1b98 MACRO_Execute_Array,First: 1b98 1b98 dispatch_brk_class 8 ; Flow C 0x1b80 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b98 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b99 1b99 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9a ; -------------------------------------------------------------------------------------- 1b9a ; 0x01fc Execute Array,Last 1b9a ; -------------------------------------------------------------------------------------- 1b9a MACRO_Execute_Array,Last: 1b9a 1b9a dispatch_brk_class 8 ; Flow C 0x1b80 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9a dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9b 1b9b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9c ; -------------------------------------------------------------------------------------- 1b9c ; 0x01fb Execute Array,Length 1b9c ; -------------------------------------------------------------------------------------- 1b9c MACRO_Execute_Array,Length: 1b9c 1b9c dispatch_brk_class 8 ; Flow C 0x1b80 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9c dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9d 1b9d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9e ; -------------------------------------------------------------------------------------- 1b9e ; 0x01fa Execute Array,Bounds 1b9e ; -------------------------------------------------------------------------------------- 1b9e MACRO_Execute_Array,Bounds: 1b9e 1b9e dispatch_brk_class 8 ; Flow C 0x1b80 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9e dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9f 1b9f seq_br_type 3 Unconditional Branch; Flow J 0x1b9b seq_branch_adr 1b9b 0x1b9b typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 ; 0x01f9 Execute Array,Reverse_Bounds 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 MACRO_Execute_Array,Reverse_Bounds: 1ba0 1ba0 dispatch_brk_class 8 ; Flow C 0x1b80 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ba0 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1ba1 1ba1 seq_br_type 3 Unconditional Branch; Flow J 0x1b99 seq_branch_adr 1b99 0x1b99 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ba2 ; -------------------------------------------------------------------------------------- 1ba2 ; 0x01f8 Execute Array,Element_Type 1ba2 ; -------------------------------------------------------------------------------------- 1ba2 MACRO_Execute_Array,Element_Type: 1ba2 1ba2 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ba2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ba3 1ba3 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 1ba4 1ba4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1ba5 1ba5 <halt> ; Flow R 1ba6 ; -------------------------------------------------------------------------------------- 1ba6 ; 0x01ed Execute Array,In_Type 1ba6 ; -------------------------------------------------------------------------------------- 1ba6 MACRO_Execute_Array,In_Type: 1ba6 1ba6 dispatch_brk_class 8 ; Flow C cc=False 0x1bd3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ba6 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd3 0x1bd3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ba7 1ba7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1ba8 1ba8 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bae fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bae 0x1bae seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ba9 1ba9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bac seq_br_type 1 Branch True seq_branch_adr 1bac 0x1bac 1baa 1baa seq_br_type 7 Unconditional Call; Flow C 0x2296 seq_branch_adr 2296 0x2296 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bab 1bab fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bac 1bac ioc_fiubs 1 val ; Flow C 0x228c seq_br_type 7 Unconditional Call seq_branch_adr 228c 0x228c typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bad 1bad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bae 1bae seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bb1 seq_br_type 1 Branch True seq_branch_adr 1bb1 0x1bb1 1baf 1baf seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bb0 1bb0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bb1 1bb1 ioc_fiubs 1 val ; Flow C 0x226d seq_br_type 7 Unconditional Call seq_branch_adr 226d 0x226d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bb2 1bb2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bb3 1bb3 <halt> ; Flow R 1bb4 ; -------------------------------------------------------------------------------------- 1bb4 ; 0x01ec Execute Array,Not_In_Type 1bb4 ; -------------------------------------------------------------------------------------- 1bb4 MACRO_Execute_Array,Not_In_Type: 1bb4 1bb4 dispatch_brk_class 8 ; Flow C cc=False 0x1bd3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bb4 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd3 0x1bd3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bb5 1bb5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bb6 1bb6 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bbc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bbc 0x1bbc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bb7 1bb7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bba seq_br_type 1 Branch True seq_branch_adr 1bba 0x1bba 1bb8 1bb8 seq_br_type 7 Unconditional Call; Flow C 0x2296 seq_branch_adr 2296 0x2296 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bb9 1bb9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bba 1bba ioc_fiubs 1 val ; Flow C 0x228c seq_br_type 7 Unconditional Call seq_branch_adr 228c 0x228c typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bbb 1bbb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bbc 1bbc seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bbf seq_br_type 1 Branch True seq_branch_adr 1bbf 0x1bbf 1bbd 1bbd seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bbe 1bbe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bbf 1bbf ioc_fiubs 1 val ; Flow C 0x226d seq_br_type 7 Unconditional Call seq_branch_adr 226d 0x226d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bc0 1bc0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bc1 1bc1 <halt> ; Flow R 1bc2 ; -------------------------------------------------------------------------------------- 1bc2 ; 0x01eb Execute Array,Check_In_Type 1bc2 ; -------------------------------------------------------------------------------------- 1bc2 MACRO_Execute_Array,Check_In_Type: 1bc2 1bc2 dispatch_brk_class 8 ; Flow C cc=False 0x1bd3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bc2 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd3 0x1bd3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bc3 1bc3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bc4 1bc4 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bcc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bcc 0x1bcc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bc5 1bc5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bc9 seq_br_type 1 Branch True seq_branch_adr 1bc9 0x1bc9 1bc6 1bc6 seq_br_type 7 Unconditional Call; Flow C 0x2296 seq_branch_adr 2296 0x2296 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bc7 1bc7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bc8 0x1bc8 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bc8 1bc8 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 1bc9 1bc9 ioc_fiubs 1 val ; Flow C 0x228c seq_br_type 7 Unconditional Call seq_branch_adr 228c 0x228c typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bca 1bca fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bcb 0x1bcb seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bcb 1bcb seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 1bcc 1bcc seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bd0 seq_br_type 1 Branch True seq_branch_adr 1bd0 0x1bd0 1bcd 1bcd seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bce 1bce fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bcf 0x1bcf seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bcf 1bcf seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 1bd0 1bd0 ioc_fiubs 1 val ; Flow C 0x226d seq_br_type 7 Unconditional Call seq_branch_adr 226d 0x226d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bd1 1bd1 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bd2 0x1bd2 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bd2 1bd2 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 1bd3 ; -------------------------------------------------------------------------------------- 1bd3 ; Comes from: 1bd3 ; 1ba6 C False from color 0x0a78 1bd3 ; 1bb4 C False from color 0x0a8c 1bd3 ; -------------------------------------------------------------------------------------- 1bd3 1bd3 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd4 1bd4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd5 1bd5 <halt> ; Flow R 1bd6 ; -------------------------------------------------------------------------------------- 1bd6 ; 0x01ef Execute Array,Convert 1bd6 ; -------------------------------------------------------------------------------------- 1bd6 MACRO_Execute_Array,Convert: 1bd6 1bd6 dispatch_brk_class 4 ; Flow J cc=True 0x1bd8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bd6 seq_br_type 1 Branch True seq_branch_adr 1bd8 0x1bd8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bd7 1bd7 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd8 1bd8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd9 1bd9 ioc_fiubs 2 typ ; Flow J cc=True 0x1bef seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bef 0x1bef seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1bda 1bda fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bdf fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bdf 0x1bdf typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bdb 1bdb seq_br_type 7 Unconditional Call; Flow C 0x22ae seq_branch_adr 22ae 0x22ae typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bdc 1bdc fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1be7 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be7 0x1be7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bdd 1bdd ioc_fiubs 2 typ ; Flow C 0x2256 seq_br_type 7 Unconditional Call seq_branch_adr 2256 0x2256 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bde 1bde seq_br_type 3 Unconditional Branch; Flow J 0x1be4 seq_branch_adr 1be4 0x1be4 1bdf 1bdf ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1be0 1be0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1be1 1be1 ioc_fiubs 1 val ; Flow C 0x22aa seq_br_type 7 Unconditional Call seq_branch_adr 22aa 0x22aa typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1be2 1be2 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1be7 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be7 0x1be7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1be3 1be3 ioc_fiubs 2 typ ; Flow C 0x225e seq_br_type 7 Unconditional Call seq_branch_adr 225e 0x225e typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1be4 1be4 ioc_fiubs 2 typ ; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1be5 1be5 seq_br_type 7 Unconditional Call; Flow C 0x2256 seq_branch_adr 2256 0x2256 1be6 1be6 fiu_mem_start 2 start-rd; Flow C cc=True 0x3272 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1be7 1be7 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1be8 1be8 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1be9 1be9 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1bea 1bea fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1bec fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bec 0x1bec seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1beb 1beb ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a2 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bec 1bec seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 37 GP08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1bed 1bed ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1bee 1bee fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bef 1bef fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bf0 1bf0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bf4 seq_br_type 1 Branch True seq_branch_adr 1bf4 0x1bf4 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1bf1 1bf1 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1bf2 1bf2 fiu_mem_start 2 start-rd; Flow J cc=True 0x1bf7 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bf7 0x1bf7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1bf3 1bf3 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1bf4 1bf4 seq_br_type 2 Push (branch address); Flow J 0x1bf5 seq_branch_adr 1c27 0x1c27 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1bf5 1bf5 ioc_fiubs 1 val ; Flow C 0x226d seq_br_type 7 Unconditional Call seq_branch_adr 226d 0x226d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bf6 1bf6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3272 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3272 0x3272 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1bf7 1bf7 <default> 1bf8 1bf8 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bf9 1bf9 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1bfa 1bfa ioc_fiubs 1 val ; Flow C cc=True 0x3279 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1bfb 1bfb fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bfc 1bfc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1bfe fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bfe 0x1bfe seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bfd 1bfd ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bfe 1bfe fiu_mem_start 2 start-rd; Flow C cc=False 0x329c ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_rand 2 DEC_LOOP_COUNTER 1bff 1bff fiu_mem_start 4 continue typ_c_adr 37 GP08 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c00 1c00 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1c01 1c01 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1c02 1c02 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c03 1c03 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c04 1c04 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c15 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c15 0x1c15 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c05 1c05 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c06 1c06 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1c07 1c07 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c08 1c08 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c17 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c17 0x1c17 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 06 GP06 1c09 1c09 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c0a 1c0a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 1c0b 1c0b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 1c0c 1c0c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1c00 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c00 0x1c00 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 1c0d 1c0d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1c0e 1c0e fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c0f 1c0f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c10 1c10 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c19 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c19 0x1c19 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c11 1c11 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c1b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1c1b 0x1c1b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c12 1c12 ioc_load_wdr 0 ; Flow C cc=True 0x329c ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1c13 1c13 seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1c14 1c14 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c15 1c15 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c16 1c16 fiu_fill_mode_src 0 ; Flow J 0x1c06 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c06 0x1c06 typ_mar_cntl 6 INCREMENT_MAR 1c17 1c17 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c18 1c18 fiu_fill_mode_src 0 ; Flow J 0x1c0a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c0a 0x1c0a typ_mar_cntl 6 INCREMENT_MAR 1c19 1c19 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c1a 1c1a fiu_fill_mode_src 0 ; Flow J cc=True 0x1c12 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c12 0x1c12 typ_mar_cntl 6 INCREMENT_MAR 1c1b 1c1b ioc_load_wdr 0 ; Flow J 0x1c1d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c1d 0x1c1d val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c1c 1c1c ioc_load_wdr 0 ; Flow J cc=True 0x1c12 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c12 0x1c12 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 1c1d 1c1d fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 1c1e 1c1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 6 1c1f 1c1f fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c20 1c20 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c21 1c21 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c24 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c24 0x1c24 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c22 1c22 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c1c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c1c 0x1c1c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 1c23 1c23 ioc_load_wdr 0 ; Flow J 0x1c12 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c12 0x1c12 val_rand 2 DEC_LOOP_COUNTER 1c24 1c24 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c25 1c25 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c1c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c1c 0x1c1c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1c26 1c26 ioc_load_wdr 0 ; Flow J 0x1c12 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c12 0x1c12 val_rand 2 DEC_LOOP_COUNTER 1c27 1c27 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1c2b seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c2b 0x1c2b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1c28 1c28 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c29 1c29 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c2a 1c2a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1c2d fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c2d 0x1c2d typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c2b 1c2b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c2c 1c2c fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c2d 1c2d seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1c2e 1c2e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1c2f 1c2f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x1c32 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1c32 0x1c32 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_c_adr 37 GP08 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1c30 1c30 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c35 seq_br_type 1 Branch True seq_branch_adr 1c35 0x1c35 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c31 1c31 seq_br_type 3 Unconditional Branch; Flow J 0x1c3a seq_branch_adr 1c3a 0x1c3a 1c32 1c32 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1c33 1c33 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c34 1c34 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1c3a seq_br_type 1 Branch True seq_branch_adr 1c3a 0x1c3a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c35 1c35 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1c37 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c37 0x1c37 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c36 1c36 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329c seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329c 0x329c val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1c37 1c37 ioc_fiubs 1 val ; Flow C cc=False 0x329c seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1c38 1c38 ioc_fiubs 1 val ; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1c39 1c39 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1c3a 1c3a val_a_adr 04 GP04 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 1c3b 1c3b seq_br_type 3 Unconditional Branch; Flow J 0x1c35 seq_branch_adr 1c35 0x1c35 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c3c ; -------------------------------------------------------------------------------------- 1c3c ; 0x01ee Execute Array,Convert_To_Formal 1c3c ; -------------------------------------------------------------------------------------- 1c3c MACRO_Execute_Array,Convert_To_Formal: 1c3c 1c3c dispatch_brk_class 4 ; Flow J cc=True 0x1c3e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c3c seq_br_type 1 Branch True seq_branch_adr 1c3e 0x1c3e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1c3d 1c3d fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c3e 1c3e fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c3f 1c3f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bef seq_br_type 1 Branch True seq_branch_adr 1bef 0x1bef seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c40 1c40 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1c44 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c44 0x1c44 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c41 1c41 seq_br_type 7 Unconditional Call; Flow C 0x2296 seq_branch_adr 2296 0x2296 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1c42 1c42 fiu_mem_start 2 start-rd; Flow J cc=True 0x1be7 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be7 0x1be7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c43 1c43 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1c44 1c44 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1c45 1c45 seq_br_type 2 Push (branch address); Flow J 0x1c46 seq_branch_adr 1be7 0x1be7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c46 1c46 ioc_fiubs 1 val ; Flow C 0x228c seq_br_type 7 Unconditional Call seq_branch_adr 228c 0x228c typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c47 1c47 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3272 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3272 0x3272 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c48 ; -------------------------------------------------------------------------------------- 1c48 ; 0x01f4 Execute Array,Structure_Write 1c48 ; -------------------------------------------------------------------------------------- 1c48 MACRO_Execute_Array,Structure_Write: 1c48 1c48 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1c48 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c49 1c49 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e4a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e4a 0x1e4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c4a ; -------------------------------------------------------------------------------------- 1c4a ; Comes from: 1c4a ; 1c6a C from color MACRO_Execute_Array,Field_Read 1c4a ; 1c72 C from color MACRO_Execute_Array,Field_Read 1c4a ; 1c7c C from color MACRO_Execute_Array,Field_Reference 1c4a ; 1c7e C from color MACRO_Execute_Subarray,Field_Reference 1c4a ; -------------------------------------------------------------------------------------- 1c4a 1c4a fiu_mem_start 4 continue; Flow J cc=True 0x1c58 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c58 0x1c58 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1c4b 1c4b fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4c 1c4c fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1c53 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c53 0x1c53 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c4d 1c4d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c4e 1c4e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4f 1c4f fiu_mem_start 4 continue; Flow C cc=True 0x1c55 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1c55 0x1c55 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1c50 1c50 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1c4c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c4c 0x1c4c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c51 1c51 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=False 0x1c53 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c53 0x1c53 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c52 1c52 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3272 seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c53 ; -------------------------------------------------------------------------------------- 1c53 ; Comes from: 1c53 ; 1c4c C False from color 0x0000 1c53 ; 1c51 C False from color 0x0000 1c53 ; 1c5e C False from color 0x0000 1c53 ; -------------------------------------------------------------------------------------- 1c53 1c53 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c54 1c54 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c55 ; -------------------------------------------------------------------------------------- 1c55 ; Comes from: 1c55 ; 1c4f C True from color 0x0000 1c55 ; -------------------------------------------------------------------------------------- 1c55 1c55 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1c56 1c56 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1c57 1c57 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1c58 1c58 fiu_len_fill_lit 45 zero-fill 0x5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_b_adr 10 TOP 1c59 1c59 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c5a 1c5a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1c65 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c65 0x1c65 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_frame 2 1c5b 1c5b fiu_fill_mode_src 0 ; Flow J cc=True 0x1c67 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c67 0x1c67 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c5c 1c5c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1c61 fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c61 0x1c61 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c5d 1c5d fiu_fill_mode_src 0 ; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c5e 1c5e fiu_mem_start 2 start-rd; Flow C cc=False 0x1c53 ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 1c53 0x1c53 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c5f 1c5f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c60 1c60 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c5a 0x1c5a typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 1c61 1c61 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c62 1c62 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c5e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1c5e 0x1c5e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c63 1c63 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1c64 1c64 seq_br_type 3 Unconditional Branch; Flow J 0x1c5e seq_branch_adr 1c5e 0x1c5e 1c65 1c65 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c66 1c66 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c5c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c5c 0x1c5c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c67 1c67 fiu_len_fill_lit 1f sign-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c68 1c68 seq_br_type 3 Unconditional Branch; Flow J 0x1c51 seq_branch_adr 1c51 0x1c51 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c69 1c69 <halt> ; Flow R 1c6a ; -------------------------------------------------------------------------------------- 1c6a ; 0x01f7 Execute Array,Field_Read 1c6a ; -------------------------------------------------------------------------------------- 1c6a MACRO_Execute_Array,Field_Read: 1c6a 1c6a dispatch_brk_class 8 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c6a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c6b 1c6b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1c74 fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 1c74 0x1c74 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1c6c 1c6c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1c6e fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c6e 0x1c6e seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR 1c6d 1c6d fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1c70 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c70 0x1c70 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c6e 1c6e fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c6f 1c6f fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c70 0x1c70 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c70 1c70 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c71 0x1c71 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c71 1c71 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c72 ; -------------------------------------------------------------------------------------- 1c72 ; 0x018f Execute Subarray,Field_Read 1c72 ; -------------------------------------------------------------------------------------- 1c72 MACRO_Execute_Subarray,Field_Read: 1c72 1c72 dispatch_brk_class 8 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c72 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c73 1c73 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1c6c fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 1c6c 0x1c6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1c74 1c74 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c75 1c75 <halt> ; Flow R 1c76 ; -------------------------------------------------------------------------------------- 1c76 ; 0x01f6 Execute Array,Field_Write 1c76 ; -------------------------------------------------------------------------------------- 1c76 MACRO_Execute_Array,Field_Write: 1c76 1c76 dispatch_brk_class 2 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c76 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c77 1c77 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c78 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c78 0x1c78 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c78 1c78 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 2e TOP + 1 1c79 1c79 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d48 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d48 0x1d48 seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c7a ; -------------------------------------------------------------------------------------- 1c7a ; 0x018e Execute Subarray,Field_Write 1c7a ; -------------------------------------------------------------------------------------- 1c7a MACRO_Execute_Subarray,Field_Write: 1c7a 1c7a dispatch_brk_class 2 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c7b 1c7b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c78 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c78 0x1c78 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c7c ; -------------------------------------------------------------------------------------- 1c7c ; 0x01f5 Execute Array,Field_Reference 1c7c ; -------------------------------------------------------------------------------------- 1c7c MACRO_Execute_Array,Field_Reference: 1c7c 1c7c dispatch_brk_class 8 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c7d 1c7d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c7e ; -------------------------------------------------------------------------------------- 1c7e ; 0x018d Execute Subarray,Field_Reference 1c7e ; -------------------------------------------------------------------------------------- 1c7e MACRO_Execute_Subarray,Field_Reference: 1c7e 1c7e dispatch_brk_class 8 ; Flow C 0x1c4a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c4a 0x1c4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c7f 1c7f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c80 ; -------------------------------------------------------------------------------------- 1c80 ; 0x01f3 Execute Array,Subarray 1c80 ; -------------------------------------------------------------------------------------- 1c80 MACRO_Execute_Array,Subarray: 1c80 1c80 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c80 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c81 1c81 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR1c:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c82 1c82 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a9 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c83 1c83 ioc_tvbs 5 seq+seq; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c84 1c84 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c85 1c85 fiu_mem_start 4 continue typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1c86 1c86 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c87 1c87 fiu_load_tar 1 hold_tar; Flow C 0x32fe fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1c88 1c88 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1c89 1c89 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1c8a 1c8a ioc_fiubs 1 val ; Flow C cc=False 0x1c92 seq_br_type 4 Call False seq_branch_adr 1c92 0x1c92 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1c8b 1c8b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c8c 1c8c fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1c85 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c85 0x1c85 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE 1c8d 1c8d ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 18 Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 1c8e 1c8e seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1c8f 1c8f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c91 seq_br_type 1 Branch True seq_branch_adr 1c91 0x1c91 typ_csa_cntl 3 POP_CSA 1c90 1c90 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 36 TR11:16 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1c91 1c91 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 35 TR11:15 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1c92 ; -------------------------------------------------------------------------------------- 1c92 ; Comes from: 1c92 ; 1c8a C False from color MACRO_Execute_Array,Subarray 1c92 ; -------------------------------------------------------------------------------------- 1c92 1c92 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c93 1c93 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c94 ; -------------------------------------------------------------------------------------- 1c94 ; 0xc000-0xc1ff Store llvl,ldelta 1c94 ; -------------------------------------------------------------------------------------- 1c94 MACRO_Store_llvl,ldelta: 1c94 1c94 dispatch_brk_class 2 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1c94 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c95 1c95 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0c 0x1d0c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c96 1c96 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0d 0x1d0d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1c97 1c97 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1c98 1c98 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 1c99 1c99 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1c9a ; -------------------------------------------------------------------------------------- 1c9a ; 0x009b Action Store_Dynamic 1c9a ; -------------------------------------------------------------------------------------- 1c9a MACRO_Action_Store_Dynamic: 1c9a 1c9a dispatch_brk_class 2 ; Flow C 0x2c70 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1c9a seq_br_type 7 Unconditional Call seq_branch_adr 2c70 0x2c70 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 1c9b 1c9b fiu_mem_start 2 start-rd; Flow J cc=True 0x1c94 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c94 MACRO_Store_llvl,ldelta 1c9c ; -------------------------------------------------------------------------------------- 1c9c ; 0xc200-0xdfff Store llvl,ldelta 1c9c ; -------------------------------------------------------------------------------------- 1c9c MACRO_Store_llvl,ldelta: 1c9c 1c9c dispatch_brk_class 2 ; Flow J cc=True 0x1ca3 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1c9c fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ca3 0x1ca3 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c9d 1c9d fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0c 0x1d0c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c9e 1c9e fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0d 0x1d0d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1c9f 1c9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d10 seq_br_type 1 Branch True seq_branch_adr 1d10 0x1d10 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1ca0 1ca0 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1ca1 1ca1 <halt> ; Flow R 1ca2 ; -------------------------------------------------------------------------------------- 1ca2 ; 0xa200-0xbfff Store_Unchecked llvl,ldelta 1ca2 ; -------------------------------------------------------------------------------------- 1ca2 MACRO_Store_Unchecked_llvl,ldelta: 1ca2 1ca2 dispatch_brk_class 2 ; Flow J cc=True 0x1c9d dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ca2 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1c9d 0x1c9d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3f TR05:1f typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ca3 1ca3 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0x1c9d fiu_mem_start 7 start_wr_if_true fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1c9d 0x1c9d seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ca4 1ca4 ioc_load_wdr 0 ; Flow J cc=True 0x1ca5 ; Flow J cc=#0x0 0x1ca5 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1ca5 0x1ca5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1ca5 1ca5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca6 1ca6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca7 1ca7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1cad ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cad 0x1cad seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca8 1ca8 seq_br_type 3 Unconditional Branch; Flow J 0x1cad seq_branch_adr 1cad 0x1cad typ_csa_cntl 3 POP_CSA 1ca9 1ca9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1caa 1caa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1cab 1cab seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1cac 1cac fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cad 0x1cad seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cad 1cad fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1cae 1cae seq_br_type 3 Unconditional Branch; Flow J 0x1c9d seq_branch_adr 1c9d 0x1c9d typ_b_adr 03 GP03 typ_mar_cntl 1 RESTORE_RDR val_b_adr 03 GP03 1caf 1caf <halt> ; Flow R 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 ; 0x0059 Store_Top Discrete,At_Offset_1 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 MACRO_Store_Top_Discrete,At_Offset_1: 1cb0 1cb0 dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cb0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cb1 1cb1 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cb2 ; -------------------------------------------------------------------------------------- 1cb2 ; 0x005a Store_Top Discrete,At_Offset_2 1cb2 ; -------------------------------------------------------------------------------------- 1cb2 MACRO_Store_Top_Discrete,At_Offset_2: 1cb2 1cb2 dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cb2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cb3 1cb3 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cb4 ; -------------------------------------------------------------------------------------- 1cb4 ; 0x005b Store_Top Discrete,At_Offset_3 1cb4 ; -------------------------------------------------------------------------------------- 1cb4 MACRO_Store_Top_Discrete,At_Offset_3: 1cb4 1cb4 dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cb4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cb5 1cb5 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cb6 ; -------------------------------------------------------------------------------------- 1cb6 ; 0x005c Store_Top Discrete,At_Offset_4 1cb6 ; -------------------------------------------------------------------------------------- 1cb6 MACRO_Store_Top_Discrete,At_Offset_4: 1cb6 1cb6 dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cb6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cb7 1cb7 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cb8 ; -------------------------------------------------------------------------------------- 1cb8 ; 0x005d Store_Top Discrete,At_Offset_5 1cb8 ; -------------------------------------------------------------------------------------- 1cb8 MACRO_Store_Top_Discrete,At_Offset_5: 1cb8 1cb8 dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cb8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cb9 1cb9 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cba ; -------------------------------------------------------------------------------------- 1cba ; 0x005e Store_Top Discrete,At_Offset_6 1cba ; -------------------------------------------------------------------------------------- 1cba MACRO_Store_Top_Discrete,At_Offset_6: 1cba 1cba dispatch_brk_class 2 ; Flow C 0x1cdf dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cba fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdf 0x1cdf seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cbb 1cbb fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1cbc ; -------------------------------------------------------------------------------------- 1cbc ; 0x0051 Store_Top_Unchecked Discrete,At_Offset_1 1cbc ; -------------------------------------------------------------------------------------- 1cbc MACRO_Store_Top_Unchecked_Discrete,At_Offset_1: 1cbc 1cbc dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cbd 1cbd <halt> ; Flow R 1cbe ; -------------------------------------------------------------------------------------- 1cbe ; 0x0052 Store_Top_Unchecked Discrete,At_Offset_2 1cbe ; -------------------------------------------------------------------------------------- 1cbe MACRO_Store_Top_Unchecked_Discrete,At_Offset_2: 1cbe 1cbe dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cbf 1cbf <halt> ; Flow R 1cc0 ; -------------------------------------------------------------------------------------- 1cc0 ; 0x0053 Store_Top_Unchecked Discrete,At_Offset_3 1cc0 ; -------------------------------------------------------------------------------------- 1cc0 MACRO_Store_Top_Unchecked_Discrete,At_Offset_3: 1cc0 1cc0 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cc1 1cc1 <halt> ; Flow R 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 ; 0x0054 Store_Top_Unchecked Discrete,At_Offset_4 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 MACRO_Store_Top_Unchecked_Discrete,At_Offset_4: 1cc2 1cc2 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cc3 1cc3 <halt> ; Flow R 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 ; 0x0055 Store_Top_Unchecked Discrete,At_Offset_5 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 MACRO_Store_Top_Unchecked_Discrete,At_Offset_5: 1cc4 1cc4 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cc4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cc5 1cc5 <halt> ; Flow R 1cc6 ; -------------------------------------------------------------------------------------- 1cc6 ; 0x0056 Store_Top_Unchecked Discrete,At_Offset_6 1cc6 ; -------------------------------------------------------------------------------------- 1cc6 MACRO_Store_Top_Unchecked_Discrete,At_Offset_6: 1cc6 1cc6 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cc6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cc7 1cc7 <halt> ; Flow R 1cc8 ; -------------------------------------------------------------------------------------- 1cc8 ; 0x0049 Store_Top Float,At_Offset_1 1cc8 ; -------------------------------------------------------------------------------------- 1cc8 MACRO_Store_Top_Float,At_Offset_1: 1cc8 1cc8 dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cc8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cc9 1cc9 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cca ; -------------------------------------------------------------------------------------- 1cca ; 0x004a Store_Top Float,At_Offset_2 1cca ; -------------------------------------------------------------------------------------- 1cca MACRO_Store_Top_Float,At_Offset_2: 1cca 1cca dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cca fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1ccb 1ccb fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1ccc ; -------------------------------------------------------------------------------------- 1ccc ; 0x004b Store_Top Float,At_Offset_3 1ccc ; -------------------------------------------------------------------------------------- 1ccc MACRO_Store_Top_Float,At_Offset_3: 1ccc 1ccc dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1ccc fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1ccd 1ccd fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cce ; -------------------------------------------------------------------------------------- 1cce ; 0x004c Store_Top Float,At_Offset_4 1cce ; -------------------------------------------------------------------------------------- 1cce MACRO_Store_Top_Float,At_Offset_4: 1cce 1cce dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cce fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1ccf 1ccf fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cd0 ; -------------------------------------------------------------------------------------- 1cd0 ; 0x004d Store_Top Float,At_Offset_5 1cd0 ; -------------------------------------------------------------------------------------- 1cd0 MACRO_Store_Top_Float,At_Offset_5: 1cd0 1cd0 dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cd0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cd1 1cd1 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 ; 0x004e Store_Top Float,At_Offset_6 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 MACRO_Store_Top_Float,At_Offset_6: 1cd2 1cd2 dispatch_brk_class 2 ; Flow C 0x1ce2 dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cd2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce2 0x1ce2 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cd3 1cd3 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1cd4 ; -------------------------------------------------------------------------------------- 1cd4 ; 0x0041 Store_Top_Unchecked Float,At_Offset_1 1cd4 ; -------------------------------------------------------------------------------------- 1cd4 MACRO_Store_Top_Unchecked_Float,At_Offset_1: 1cd4 1cd4 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cd4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cd5 1cd5 <halt> ; Flow R 1cd6 ; -------------------------------------------------------------------------------------- 1cd6 ; 0x0042 Store_Top_Unchecked Float,At_Offset_2 1cd6 ; -------------------------------------------------------------------------------------- 1cd6 MACRO_Store_Top_Unchecked_Float,At_Offset_2: 1cd6 1cd6 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cd6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cd7 1cd7 <halt> ; Flow R 1cd8 ; -------------------------------------------------------------------------------------- 1cd8 ; 0x0043 Store_Top_Unchecked Float,At_Offset_3 1cd8 ; -------------------------------------------------------------------------------------- 1cd8 MACRO_Store_Top_Unchecked_Float,At_Offset_3: 1cd8 1cd8 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cd8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cd9 1cd9 <halt> ; Flow R 1cda ; -------------------------------------------------------------------------------------- 1cda ; 0x0044 Store_Top_Unchecked Float,At_Offset_4 1cda ; -------------------------------------------------------------------------------------- 1cda MACRO_Store_Top_Unchecked_Float,At_Offset_4: 1cda 1cda dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cda fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cdb 1cdb <halt> ; Flow R 1cdc ; -------------------------------------------------------------------------------------- 1cdc ; 0x0045 Store_Top_Unchecked Float,At_Offset_5 1cdc ; -------------------------------------------------------------------------------------- 1cdc MACRO_Store_Top_Unchecked_Float,At_Offset_5: 1cdc 1cdc dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cdc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cdd 1cdd <halt> ; Flow R 1cde ; -------------------------------------------------------------------------------------- 1cde ; 0x0046 Store_Top_Unchecked Float,At_Offset_6 1cde ; -------------------------------------------------------------------------------------- 1cde MACRO_Store_Top_Unchecked_Float,At_Offset_6: 1cde 1cde dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cde fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cdf ; -------------------------------------------------------------------------------------- 1cdf ; Comes from: 1cdf ; 1cb0 C from color 0x0000 1cdf ; 1cb2 C from color 0x0000 1cdf ; 1cb4 C from color 0x0000 1cdf ; 1cb6 C from color 0x0000 1cdf ; 1cb8 C from color 0x0000 1cdf ; 1cba C from color 0x0000 1cdf ; -------------------------------------------------------------------------------------- 1cdf 1cdf ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP 1ce0 1ce0 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ce1 0x1ce1 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1ce1 1ce1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 1ce2 ; -------------------------------------------------------------------------------------- 1ce2 ; Comes from: 1ce2 ; 1cc8 C from color 0x0000 1ce2 ; 1cca C from color 0x0000 1ce2 ; 1ccc C from color 0x0000 1ce2 ; 1cce C from color 0x0000 1ce2 ; 1cd0 C from color 0x0000 1ce2 ; 1cd2 C from color 0x0000 1ce2 ; -------------------------------------------------------------------------------------- 1ce2 1ce2 ioc_fiubs 1 val ; Flow J cc=False 0x1ce0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ce0 0x1ce0 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ce3 1ce3 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1ce1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ce1 0x1ce1 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 1ce4 1ce4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1ce1 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1ce1 0x1ce1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1ce5 1ce5 <halt> ; Flow R 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 ; 0x0039 Store_Top Access,At_Offset_1 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 MACRO_Store_Top_Access,At_Offset_1: 1ce6 1ce6 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ce6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ce7 0x1ce7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1ce7 1ce7 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 ; 0x003a Store_Top Access,At_Offset_2 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 MACRO_Store_Top_Access,At_Offset_2: 1ce8 1ce8 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1ce8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ce9 0x1ce9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1ce9 1ce9 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cea ; -------------------------------------------------------------------------------------- 1cea ; 0x003b Store_Top Access,At_Offset_3 1cea ; -------------------------------------------------------------------------------------- 1cea MACRO_Store_Top_Access,At_Offset_3: 1cea 1cea dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cea fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ceb 0x1ceb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1ceb 1ceb fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cec ; -------------------------------------------------------------------------------------- 1cec ; 0x003c Store_Top Access,At_Offset_4 1cec ; -------------------------------------------------------------------------------------- 1cec MACRO_Store_Top_Access,At_Offset_4: 1cec 1cec dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cec fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ced 0x1ced seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1ced 1ced fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cee ; -------------------------------------------------------------------------------------- 1cee ; 0x003d Store_Top Access,At_Offset_5 1cee ; -------------------------------------------------------------------------------------- 1cee MACRO_Store_Top_Access,At_Offset_5: 1cee 1cee dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cee fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cef 0x1cef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cef 1cef fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 ; 0x003e Store_Top Access,At_Offset_6 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 MACRO_Store_Top_Access,At_Offset_6: 1cf0 1cf0 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cf0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf1 0x1cf1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cf1 1cf1 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 ; 0x0031 Store_Top Heap_Access,At_Offset_1 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 MACRO_Store_Top_Heap_Access,At_Offset_1: 1cf2 1cf2 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cf2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf3 0x1cf3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cf3 1cf3 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 ; 0x0032 Store_Top Heap_Access,At_Offset_2 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 MACRO_Store_Top_Heap_Access,At_Offset_2: 1cf4 1cf4 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cf4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf5 0x1cf5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cf5 1cf5 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 ; 0x0033 Store_Top Heap_Access,At_Offset_3 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 MACRO_Store_Top_Heap_Access,At_Offset_3: 1cf6 1cf6 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cf6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf7 0x1cf7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cf7 1cf7 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 ; 0x0034 Store_Top Heap_Access,At_Offset_4 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 MACRO_Store_Top_Heap_Access,At_Offset_4: 1cf8 1cf8 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cf8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf9 0x1cf9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cf9 1cf9 fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cfa ; -------------------------------------------------------------------------------------- 1cfa ; 0x0035 Store_Top Heap_Access,At_Offset_5 1cfa ; -------------------------------------------------------------------------------------- 1cfa MACRO_Store_Top_Heap_Access,At_Offset_5: 1cfa 1cfa dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cfa fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cfb 0x1cfb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cfb 1cfb fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cfc ; -------------------------------------------------------------------------------------- 1cfc ; 0x0036 Store_Top Heap_Access,At_Offset_6 1cfc ; -------------------------------------------------------------------------------------- 1cfc MACRO_Store_Top_Heap_Access,At_Offset_6: 1cfc 1cfc dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cfc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cfd 0x1cfd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cfd 1cfd fiu_mem_start 2 start-rd; Flow J 0x1c9c ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9c MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cfe ; -------------------------------------------------------------------------------------- 1cfe ; 0x1a00-0x1aff Execute Package,Field_Write,fieldnum 1cfe ; -------------------------------------------------------------------------------------- 1cfe MACRO_Execute_Package,Field_Write,fieldnum: 1cfe 1cfe dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 1cfe dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1cff 1cff ioc_random 17 force type bus receivers; Flow J cc=False 0x1d01 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1d01 0x1d01 seq_cond_sel 79 IOC.PFR seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d00 1d00 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x1d0c fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d0c 0x1d0c typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 1d01 1d01 seq_br_type 0 Branch False; Flow J cc=False 0x1d0a seq_branch_adr 1d0a 0x1d0a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 03 GP03 1d02 1d02 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0c 0x1d0c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 1d03 1d03 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0d 0x1d0d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d04 1d04 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1d05 1d05 <halt> ; Flow R 1d06 ; -------------------------------------------------------------------------------------- 1d06 ; 0x0097 Execute Package,Field_Write_Dynamic 1d06 ; -------------------------------------------------------------------------------------- 1d06 MACRO_Execute_Package,Field_Write_Dynamic: 1d06 1d06 dispatch_brk_class 2 ; Flow C cc=True 0x32a7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d06 fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 1d07 1d07 fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 1d08 1d08 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d09 1d09 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x1d02 seq_br_type 3 Unconditional Branch seq_branch_adr 1d02 0x1d02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d0a 1d0a fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32aa ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1d0b 1d0b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 1d0c 1d0c ioc_fiubs 1 val ; Flow J cc=True 0x1d0d ; Flow J cc=#0x0 0x1d28 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d28 0x1d28 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d0d 1d0d val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d0e 1d0e fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0c 0x1d0c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d0f 1d0f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d10 1d10 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d16 seq_br_type 1 Branch True seq_branch_adr 1d16 0x1d16 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 1d11 1d11 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1d14 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 1d14 0x1d14 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d12 1d12 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 1d13 1d13 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d14 1d14 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d12 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d12 0x1d12 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d15 1d15 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 1d16 1d16 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1d12 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d12 0x1d12 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 1d17 1d17 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d12 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d12 0x1d12 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1d18 1d18 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1d12 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1d12 0x1d12 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d19 1d19 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1d1c fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 71 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d1c 0x1d1c seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 1d1a 1d1a fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d26 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d26 0x1d26 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 1d1b 1d1b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1d1c 1d1c fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d1d 1d1d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1d1e 1d1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP val_b_adr 01 GP01 1d1f 1d1f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d20 1d20 ioc_load_wdr 0 ; Flow J 0x1d13 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d13 0x1d13 val_b_adr 10 TOP 1d21 1d21 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1d22 1d22 ioc_load_wdr 0 ; Flow J cc=True 0x1d27 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d27 0x1d27 val_b_adr 06 GP06 1d23 1d23 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1d26 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d26 0x1d26 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1d24 1d24 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1d25 1d25 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1d26 1d26 seq_br_type 3 Unconditional Branch; Flow J 0x1d21 seq_branch_adr 1d21 0x1d21 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d27 1d27 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1d1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d1f 0x1d1f typ_a_adr 10 TOP 1d28 1d28 fiu_mem_start 3 start-wr; Flow J 0x1d5c ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d5c 0x1d5c typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d29 1d29 fiu_mem_start 2 start-rd; Flow J 0x1d63 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d63 0x1d63 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d2a 1d2a fiu_mem_start 3 start-wr; Flow J 0x1d70 ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d70 0x1d70 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d2b 1d2b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1d77 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d77 0x1d77 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d2c 1d2c fiu_mem_start 7 start_wr_if_true; Flow J 0x1d88 ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1d88 0x1d88 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d2d 1d2d fiu_mem_start 2 start-rd; Flow J 0x1d93 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d93 0x1d93 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d2e 1d2e seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 1d2f 1d2f seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 1d30 1d30 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d31 1d31 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c 1d32 1d32 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d33 1d33 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c 1d34 1d34 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d35 1d35 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d36 1d36 fiu_mem_start 7 start_wr_if_true; Flow J 0x1d8d ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1d8d 0x1d8d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d37 1d37 fiu_mem_start 2 start-rd; Flow J 0x1d9e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d9e 0x1d9e typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d38 1d38 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d39 1d39 fiu_mem_start 2 start-rd; Flow J 0x1db2 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1db2 0x1db2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d3a 1d3a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3b 1d3b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db9 0x1db9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d3c 1d3c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3d 1d3d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3e 1d3e seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 1d3f 1d3f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d40 1d40 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d41 1d41 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d42 1d42 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d43 1d43 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1dea fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dea 0x1dea seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d44 1d44 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d45 1d45 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0e 0x1e0e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d46 1d46 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d47 1d47 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e4a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e4a 0x1e4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d48 1d48 ioc_fiubs 1 val ; Flow J cc=True 0x1d49 ; Flow J cc=#0x0 0x1d49 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d49 0x1d49 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d49 1d49 fiu_load_oreg 1 hold_oreg; Flow J 0x1d65 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d65 0x1d65 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d4a 1d4a fiu_load_oreg 1 hold_oreg; Flow J 0x1d77 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d77 0x1d77 typ_a_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d4b 1d4b fiu_load_oreg 1 hold_oreg; Flow J 0x1d97 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1d97 0x1d97 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d4c 1d4c seq_br_type 7 Unconditional Call; Flow C 0x32ab seq_branch_adr 32ab 0x32ab 1d4d 1d4d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d4e 1d4e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d4f 1d4f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d50 1d50 fiu_load_oreg 1 hold_oreg; Flow J 0x1da0 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1da0 0x1da0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1d51 1d51 fiu_mem_start 2 start-rd; Flow J 0x1db2 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1db2 0x1db2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d52 1d52 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db9 0x1db9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d53 1d53 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d54 1d54 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d55 1d55 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d56 1d56 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1dea fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dea 0x1dea seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d57 1d57 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0e 0x1e0e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d58 1d58 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e4a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e4a 0x1e4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d59 ; -------------------------------------------------------------------------------------- 1d59 ; Comes from: 1d59 ; 1db6 C False from color 0x1d39 1d59 ; 1e0f C False from color MACRO_Execute_Matrix,Structure_Write 1d59 ; 1e23 C False from color MACRO_Execute_Matrix,Structure_Write 1d59 ; -------------------------------------------------------------------------------------- 1d59 1d59 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1d5a 0x1d5a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1d5a 1d5a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ab seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 1d5b 1d5b ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 1d5c 1d5c ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_c_adr 3b GP04 1d5d 1d5d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d5e 0x1d5e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d5e 1d5e fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1d5f 1d5f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d60 1d60 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1d61 1d61 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326e seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1d62 1d62 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 1d63 1d63 ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d64 1d64 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d65 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d65 0x1d65 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d65 1d65 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d68 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d68 0x1d68 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 1d66 1d66 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d67 1d67 ioc_load_wdr 0 ; Flow J 0x1d6c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d6c 0x1d6c seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1d68 1d68 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1d69 1d69 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1d6a 1d6a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1d6b 1d6b ioc_load_wdr 0 ; Flow J 0x1d6c ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d6c 0x1d6c typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d6c 1d6c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d6d 0x1d6d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d6d 1d6d fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d6e 1d6e fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1d5f ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1d5f 0x1d5f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1d6f 1d6f ioc_load_wdr 0 ; Flow J 0x1d5f seq_br_type 3 Unconditional Branch seq_branch_adr 1d5f 0x1d5f typ_b_adr 05 GP05 val_b_adr 05 GP05 1d70 1d70 ioc_load_wdr 0 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_c_adr 3b GP04 1d71 1d71 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d73 seq_br_type 1 Branch True seq_branch_adr 1d73 0x1d73 typ_csa_cntl 3 POP_CSA 1d72 1d72 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d75 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d75 0x1d75 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d73 1d73 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d75 seq_br_type 1 Branch True seq_branch_adr 1d75 0x1d75 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 1d74 1d74 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d75 0x1d75 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d75 1d75 fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1d76 1d76 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e 1d77 1d77 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d7d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d7d 0x1d7d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_c_adr 3b GP04 1d78 1d78 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d79 1d79 ioc_load_wdr 0 ; Flow J cc=True 0x1d7b ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d7b 0x1d7b seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1d7a 1d7a fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d84 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d84 0x1d84 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d7b 1d7b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d84 seq_br_type 1 Branch True seq_branch_adr 1d84 0x1d84 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA 1d7c 1d7c fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1d84 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d84 0x1d84 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d7d 1d7d fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_c_adr 3b GP04 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1d7e 1d7e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1d7f 1d7f fiu_mem_start 4 continue; Flow J cc=True 0x1d82 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d82 0x1d82 seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1d80 1d80 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d81 1d81 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d84 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d84 0x1d84 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d82 1d82 ioc_load_wdr 0 ; Flow J cc=True 0x1d84 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d84 0x1d84 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d83 1d83 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d84 0x1d84 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d84 1d84 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d85 1d85 fiu_mem_start a start_continue_if_false ioc_load_wdr 0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1d86 1d86 ioc_load_wdr 0 ; Flow C cc=True 0x326e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 05 GP05 val_b_adr 05 GP05 1d87 1d87 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e 1d88 1d88 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d8c seq_br_type 1 Branch True seq_branch_adr 1d8c 0x1d8c seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d89 1d89 seq_br_type 7 Unconditional Call; Flow C 0x248a seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d8a 1d8a fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1d90 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d90 0x1d90 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d8b 1d8b ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1d8c 1d8c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d8d 1d8d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d8c seq_br_type 1 Branch True seq_branch_adr 1d8c 0x1d8c seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d8e 1d8e seq_br_type 7 Unconditional Call; Flow C 0x2494 seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d8f 1d8f fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1d8b ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d8b 0x1d8b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d90 1d90 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1d91 1d91 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1d92 1d92 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1d93 1d93 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1d94 1d94 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d97 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d97 0x1d97 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d95 1d95 fiu_load_tar 1 hold_tar; Flow C 0x248a fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 248a 0x248a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d96 1d96 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1d90 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d90 0x1d90 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d97 1d97 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d9b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d9b 0x1d9b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1d98 1d98 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d95 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d95 0x1d95 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d99 1d99 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 1d9a 1d9a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d9b 1d9b fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1d9c 1d9c fiu_fill_mode_src 0 ; Flow J cc=False 0x1d95 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d95 0x1d95 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1d9d 1d9d fiu_load_var 1 hold_var; Flow J 0x1d99 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d99 0x1d99 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1d9e 1d9e fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1d9f 1d9f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1da0 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1da0 0x1da0 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1da0 1da0 fiu_fill_mode_src 0 ; Flow J cc=False 0x1da3 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1da3 0x1da3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 1da1 1da1 fiu_fill_mode_src 0 ; Flow C cc=True 0x1dae fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dae 0x1dae typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1da2 1da2 ioc_load_wdr 0 ; Flow J 0x1da7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1da7 0x1da7 seq_random 02 ? typ_c_adr 3b GP04 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 1da3 1da3 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1da4 1da4 fiu_fill_mode_src 0 ; Flow C cc=True 0x1dae fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dae 0x1dae typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 1da5 1da5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1da6 1da6 ioc_load_wdr 0 ; Flow J 0x1da7 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1da7 0x1da7 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1da7 1da7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1da8 0x1da8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1da8 1da8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1da9 1da9 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1dab ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1dab 0x1dab seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 1daa 1daa ioc_load_wdr 0 ; Flow J 0x1dab seq_br_type 3 Unconditional Branch seq_branch_adr 1dab 0x1dab typ_b_adr 05 GP05 val_b_adr 05 GP05 1dab 1dab fiu_load_tar 1 hold_tar; Flow C 0x2494 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2494 0x2494 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1dac 1dac fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1d90 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d90 0x1d90 typ_b_adr 1f TOP - 1 1dad 1dad fiu_load_oreg 1 hold_oreg; Flow J 0x1da0 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1da0 0x1da0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1dae ; -------------------------------------------------------------------------------------- 1dae ; Comes from: 1dae ; 1da1 C True from color 0x1d2a 1dae ; 1da4 C True from color 0x1d2a 1dae ; -------------------------------------------------------------------------------------- 1dae 1dae fiu_tivi_src c mar_0xc; Flow C cc=False 0x32b1 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1daf 1daf fiu_fill_mode_src 0 ; Flow J cc=False 0x1db1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1db1 0x1db1 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1db0 1db0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1db1 1db1 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1db2 1db2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1db6 seq_br_type 1 Branch True seq_branch_adr 1db6 0x1db6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1db3 1db3 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1db4 1db4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1db5 1db5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1db6 1db6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1db7 1db7 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1eee seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1db8 1db8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1db9 1db9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dbc seq_br_type 1 Branch True seq_branch_adr 1dbc 0x1dbc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 39 GP06 1dba 1dba fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dbb 1dbb fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dbc 1dbc fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1dbd 1dbd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1dc6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc6 0x1dc6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_c_adr 38 GP07 1dbe 1dbe ioc_tvbs 2 fiu+val; Flow J cc=True 0x1dc3 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dc3 0x1dc3 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dbf 1dbf seq_br_type 7 Unconditional Call; Flow C 0x26fc seq_branch_adr 26fc 0x26fc typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1dc0 1dc0 ioc_fiubs 1 val ; Flow C cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1dc1 1dc1 seq_br_type 7 Unconditional Call; Flow C 0x2458 seq_branch_adr 2458 0x2458 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1dc2 1dc2 ioc_fiubs 1 val ; Flow J 0x1dc6 seq_br_type 3 Unconditional Branch seq_branch_adr 1dc6 0x1dc6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1dc3 1dc3 fiu_load_oreg 1 hold_oreg; Flow C 0x24e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 24e5 0x24e5 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dc4 1dc4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1dc7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dc7 0x1dc7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1dc5 1dc5 seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 1dc6 1dc6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1dc7 1dc7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dd3 seq_br_type 1 Branch True seq_branch_adr 1dd3 0x1dd3 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1dc8 1dc8 fiu_fill_mode_src 0 ; Flow J cc=True 0x1dd5 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dd5 0x1dd5 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1dc9 1dc9 ioc_fiubs 1 val ; Flow J cc=False 0x1dd0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1dca 1dca fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dcb 1dcb seq_b_timing 0 Early Condition; Flow J cc=True 0x1dd0 seq_br_type 1 Branch True seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1dcc 1dcc fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dcd 1dcd ioc_fiubs 1 val ; Flow J cc=True 0x1dd0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1dce 1dce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1dd0 seq_br_type 1 Branch True seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 03 GP03 1dcf 1dcf seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1dd0 1dd0 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1dd1 1dd1 seq_br_type 7 Unconditional Call; Flow C 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_csa_cntl 3 POP_CSA typ_frame 5 1dd2 1dd2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dd3 1dd3 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1dd4 1dd4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dd5 1dd5 ioc_fiubs 1 val ; Flow J cc=False 0x1ddf seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ddf 0x1ddf seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1dd6 1dd6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dd7 1dd7 seq_b_timing 0 Early Condition; Flow J cc=True 0x1ddc seq_br_type 1 Branch True seq_branch_adr 1ddc 0x1ddc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1dd8 1dd8 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dd9 1dd9 ioc_fiubs 1 val ; Flow J cc=False 0x1dce seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1dce 0x1dce seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 1dda 1dda seq_br_type 1 Branch True; Flow J cc=True 0x1dd0 seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1ddb 1ddb seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1ddc 1ddc ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1de1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1de1 0x1de1 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 1ddd 1ddd seq_b_timing 1 Latch Condition; Flow J cc=True 0x1de1 seq_br_type 1 Branch True seq_branch_adr 1de1 0x1de1 1dde 1dde seq_br_type 3 Unconditional Branch; Flow J 0x1dd1 seq_branch_adr 1dd1 0x1dd1 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1ddf 1ddf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1de0 1de0 seq_b_timing 0 Early Condition; Flow J cc=True 0x1de4 seq_br_type 1 Branch True seq_branch_adr 1de4 0x1de4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1de1 1de1 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de2 1de2 seq_br_type 1 Branch True; Flow J cc=True 0x1dd0 seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de3 1de3 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1de4 1de4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1de7 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1de7 0x1de7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1de5 1de5 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de6 1de6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de7 1de7 seq_br_type 7 Unconditional Call; Flow C 0x2458 seq_branch_adr 2458 0x2458 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de8 1de8 seq_br_type 1 Branch True; Flow J cc=True 0x1dd0 seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de9 1de9 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1dea 1dea ioc_fiubs 0 fiu ; Flow J cc=True 0x1e02 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e02 0x1e02 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1deb 1deb fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1dec 1dec ioc_tvbs 2 fiu+val; Flow C cc=False 0x1eee seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_csa_cntl 3 POP_CSA typ_frame 5 1ded 1ded fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1dee 0x1dee seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dee 1dee seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 03 GP03 1def 1def fiu_mem_start 2 start-rd; Flow J cc=True 0x1df3 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df3 0x1df3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1df0 1df0 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1dff seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dff 0x1dff typ_mar_cntl 6 INCREMENT_MAR 1df1 1df1 <default> 1df2 1df2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1dfd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dfd 0x1dfd typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1df3 1df3 fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1df4 1df4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1df5 1df5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1df6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1df6 0x1df6 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1df6 1df6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1dfb seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dfb 0x1dfb seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1df7 1df7 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dfd fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1dfd 0x1dfd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1df8 1df8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1df9 1df9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1eee seq_br_type 4 Call False seq_branch_adr 1eee 0x1eee seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1dfa 1dfa fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3273 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3273 0x3273 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dfb 1dfb fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1dfc 1dfc fiu_fill_mode_src 0 ; Flow J cc=True 0x1df8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1df8 0x1df8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1dfd 1dfd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3273 seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 1dfe 1dfe fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dff 1dff seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1e00 1e00 seq_br_type 5 Call True; Flow C cc=True 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e01 1e01 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e02 1e02 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e03 1e03 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1df6 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1df6 0x1df6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e04 1e04 fiu_fill_mode_src 0 ; Flow J cc=True 0x1e08 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e08 0x1e08 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1e05 1e05 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 38 GP07 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1e06 1e06 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e07 1e07 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e08 1e08 ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 38 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1e09 1e09 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1e0a 1e0a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1df6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df6 0x1df6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e0b 1e0b seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e0d seq_br_type 1 Branch True seq_branch_adr 1e0d 0x1e0d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e0c 1e0c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e0d 1e0d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1df6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1df6 0x1df6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 1e0e 1e0e ioc_fiubs 0 fiu ; Flow J cc=True 0x1e23 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e23 0x1e23 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1e0f 1e0f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e10 1e10 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1e18 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e18 0x1e18 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1e11 1e11 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e1a seq_br_type 1 Branch True seq_branch_adr 1e1a 0x1e1a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 1e12 1e12 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1e15 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1e15 0x1e15 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1e13 1e13 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e14 1e14 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e41 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e15 1e15 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e16 1e16 seq_br_type 5 Call True; Flow C cc=True 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e17 1e17 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e18 1e18 ioc_tvbs 2 fiu+val; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1e19 1e19 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e1a 1e1a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e1b 1e1b fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e1e seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e1e 0x1e1e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e1c 1e1c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e1d 1e1d fiu_fill_mode_src 0 ; Flow J 0x1e1f fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e1f 0x1e1f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e1e 1e1e fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e1f 1e1f fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e22 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e22 0x1e22 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e20 1e20 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e21 1e21 fiu_fill_mode_src 0 ; Flow J 0x1e41 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e22 1e22 fiu_fill_mode_src 0 ; Flow J 0x1e41 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e23 1e23 fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d59 fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 1e24 1e24 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e25 1e25 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e28 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e28 0x1e28 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e26 1e26 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e27 1e27 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e29 0x1e29 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e28 1e28 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e29 1e29 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e2c seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e2c 0x1e2c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e2a 1e2a fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e2b 1e2b fiu_fill_mode_src 0 ; Flow J 0x1e2d fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e2d 0x1e2d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e2c 1e2c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e2d 1e2d fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e31 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e31 0x1e31 typ_mar_cntl 6 INCREMENT_MAR 1e2e 1e2e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e2f 1e2f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e30 1e30 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e41 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e31 1e31 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e32 1e32 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e3c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e3c 0x1e3c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e33 1e33 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e34 1e34 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e35 1e35 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e3f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e3f 0x1e3f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e36 1e36 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e37 1e37 ioc_fiubs 1 val ; Flow J cc=True 0x1e3b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e3b 0x1e3b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e38 1e38 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e3a seq_br_type 1 Branch True seq_branch_adr 1e3a 0x1e3a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e39 1e39 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e3a 1e3a ioc_fiubs 1 val ; Flow J 0x1e41 seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e3b 1e3b seq_br_type 3 Unconditional Branch; Flow J 0x1e41 seq_branch_adr 1e41 0x1e41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 1e3c 1e3c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e3d 1e3d fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e3e 1e3e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e35 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e35 0x1e35 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e3f 1e3f fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e40 1e40 fiu_fill_mode_src 0 ; Flow J 0x1e37 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e37 0x1e37 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e41 1e41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e46 seq_br_type 1 Branch True seq_branch_adr 1e46 0x1e46 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1e42 1e42 fiu_mem_start 2 start-rd; Flow C cc=False 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e43 1e43 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e44 1e44 seq_br_type 5 Call True; Flow C cc=True 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e45 1e45 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e46 1e46 fiu_mem_start 2 start-rd; Flow C cc=False 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e47 1e47 seq_br_type 4 Call False; Flow C cc=False 0x3273 seq_branch_adr 3273 0x3273 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 0 PASS_A 1e48 1e48 seq_br_type 4 Call False; Flow C cc=False 0x3273 seq_branch_adr 3273 0x3273 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A 1e49 1e49 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e4a 1e4a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e5d seq_br_type 1 Branch True seq_branch_adr 1e5d 0x1e5d seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e4b 1e4b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d59 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e4c 1e4c fiu_mem_start 2 start-rd; Flow J cc=False 0x1e79 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e79 0x1e79 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 1e4d 1e4d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e55 seq_br_type 1 Branch True seq_branch_adr 1e55 0x1e55 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1e4e 1e4e fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1e7b fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1e7b 0x1e7b typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e4f 1e4f seq_br_type 7 Unconditional Call; Flow C 0x22ae seq_branch_adr 22ae 0x22ae typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e50 1e50 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e79 seq_br_type 1 Branch True seq_branch_adr 1e79 0x1e79 1e51 1e51 ioc_fiubs 2 typ ; Flow C 0x2256 seq_br_type 7 Unconditional Call seq_branch_adr 2256 0x2256 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e52 1e52 ioc_fiubs 2 typ ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e53 1e53 seq_br_type 7 Unconditional Call; Flow C 0x2256 seq_branch_adr 2256 0x2256 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e54 1e54 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3273 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e55 1e55 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1e7b fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1e7b 0x1e7b typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e56 1e56 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e57 1e57 seq_br_type 7 Unconditional Call; Flow C 0x22aa seq_branch_adr 22aa 0x22aa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e58 1e58 ioc_fiubs 1 val ; Flow J cc=True 0x1e79 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e79 0x1e79 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e59 1e59 ioc_fiubs 2 typ ; Flow C 0x225e seq_br_type 7 Unconditional Call seq_branch_adr 225e 0x225e typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e5a 1e5a ioc_fiubs 2 typ ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e5b 1e5b seq_br_type 7 Unconditional Call; Flow C 0x2256 seq_branch_adr 2256 0x2256 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e5c 1e5c fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3273 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e5d 1e5d fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d59 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d59 0x1d59 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 03 GP03 1e5e 1e5e fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e5f 1e5f fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e60 1e60 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e61 1e61 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1e6a ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e6a 0x1e6a seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e62 1e62 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1e63 1e63 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1e7b fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1e7b 0x1e7b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e64 1e64 seq_br_type 7 Unconditional Call; Flow C 0x22b4 seq_branch_adr 22b4 0x22b4 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e65 1e65 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e79 seq_br_type 1 Branch True seq_branch_adr 1e79 0x1e79 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1e66 1e66 ioc_fiubs 2 typ ; Flow C 0x2256 seq_br_type 7 Unconditional Call seq_branch_adr 2256 0x2256 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e67 1e67 ioc_fiubs 1 val ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1e68 1e68 ioc_fiubs 2 typ ; Flow C 0x225e seq_br_type 7 Unconditional Call seq_branch_adr 225e 0x225e seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e69 1e69 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3273 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e6a 1e6a ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e6b 1e6b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1e7d fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e7d 0x1e7d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 1f TOP - 1 1e6c 1e6c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e6d 1e6d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e72 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e72 0x1e72 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e6e 1e6e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e6f 1e6f fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1e70 1e70 seq_br_type 4 Call False; Flow C cc=False 0x1e75 seq_branch_adr 1e75 0x1e75 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e71 1e71 ioc_fiubs 1 val ; Flow J 0x1e79 seq_br_type 3 Unconditional Branch seq_branch_adr 1e79 0x1e79 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 1e72 1e72 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e73 1e73 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e74 1e74 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e70 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e70 0x1e70 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1e75 1e75 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1e76 1e76 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e77 1e77 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e78 1e78 ioc_fiubs 1 val ; Flow J 0x1e79 seq_br_type 3 Unconditional Branch seq_branch_adr 1e79 0x1e79 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1e79 1e79 ioc_tvbs 2 fiu+val; Flow C 0x1eee seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1e7a 1e7a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e7b ; -------------------------------------------------------------------------------------- 1e7b ; Comes from: 1e7b ; 1e4e C False from color 0x0000 1e7b ; 1e55 C False from color 0x0000 1e7b ; 1e63 C False from color 0x0000 1e7b ; -------------------------------------------------------------------------------------- 1e7b 1e7b fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e7c 1e7c seq_br_type a Unconditional Return; Flow R 1e7d 1e7d ioc_fiubs 2 typ ; Flow C 0x225e ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 225e 0x225e typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e7e 1e7e ioc_fiubs 1 val ; Flow C cc=True 0x3273 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1e7f 1e7f ioc_fiubs 2 typ ; Flow C 0x225e seq_br_type 7 Unconditional Call seq_branch_adr 225e 0x225e seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e80 1e80 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3273 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e81 1e81 <halt> ; Flow R 1e82 ; -------------------------------------------------------------------------------------- 1e82 ; 0x032d Declare_Type Record,Defined 1e82 ; -------------------------------------------------------------------------------------- 1e82 MACRO_Declare_Type_Record,Defined: 1e82 1e82 dispatch_brk_class 4 ; Flow J 0x1e83 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e82 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e83 0x1e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e83 1e83 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_frame 1c val_a_adr 10 TOP val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e84 1e84 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1e85 1e85 ioc_tvbs 2 fiu+val typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1e86 1e86 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 1e87 1e87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x26b8 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 1e88 1e88 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 10 TOP 1e89 1e89 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1e8d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1e8d 0x1e8d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT 1e8a 1e8a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1e91 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1e91 0x1e91 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1e8b 1e8b ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1e8c 1e8c fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 22 TR08:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1e8d ; -------------------------------------------------------------------------------------- 1e8d ; Comes from: 1e8d ; 1e89 C False from color MACRO_Declare_Type_Record,Defined 1e8d ; 1eae C False from color MACRO_Complete_Type_Record,By_Defining 1e8d ; -------------------------------------------------------------------------------------- 1e8d 1e8d seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1e8e 0x1e8e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1e8e 1e8e seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1e8f 0x1e8f seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1e8f 1e8f seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1e90 ; -------------------------------------------------------------------------------------- 1e90 ; 0x0327 Declare_Type Record,Defined_Incomplete 1e90 ; -------------------------------------------------------------------------------------- 1e90 MACRO_Declare_Type_Record,Defined_Incomplete: 1e90 1e90 dispatch_brk_class 4 ; Flow J 0x1e83 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e90 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e83 0x1e83 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e91 ; -------------------------------------------------------------------------------------- 1e91 ; Comes from: 1e91 ; 1e8a C True from color MACRO_Declare_Type_Record,Defined 1e91 ; 1eaf C True from color MACRO_Complete_Type_Record,By_Defining 1e91 ; -------------------------------------------------------------------------------------- 1e91 1e91 fiu_mem_start 8 start_wr_if_false; Flow R cc=False fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1e92 0x1e92 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 1e92 1e92 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1d A_AND_NOT_B val_frame 2 1e93 1e93 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 1e94 ; -------------------------------------------------------------------------------------- 1e94 ; 0x032e Declare_Type Record,Defined,Visible 1e94 ; -------------------------------------------------------------------------------------- 1e94 MACRO_Declare_Type_Record,Defined,Visible: 1e94 1e94 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e94 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1e95 1e95 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1e83 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e83 0x1e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1e96 ; -------------------------------------------------------------------------------------- 1e96 ; 0x0328 Declare_Type Record,Defined_Incomplete,Visible 1e96 ; -------------------------------------------------------------------------------------- 1e96 MACRO_Declare_Type_Record,Defined_Incomplete,Visible: 1e96 1e96 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e96 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1e97 1e97 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1e83 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e83 0x1e83 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1e98 ; -------------------------------------------------------------------------------------- 1e98 ; 0x032a Declare_Type Record,Incomplete 1e98 ; -------------------------------------------------------------------------------------- 1e98 MACRO_Declare_Type_Record,Incomplete: 1e98 1e98 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1e98 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1e99 1e99 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1e9a 1e9a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1e9b 1e9b fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1e9c 1e9c fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e9f fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e9f 0x1e9f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 val_rand 2 DEC_LOOP_COUNTER 1e9d 1e9d ioc_load_wdr 0 ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1e9e 1e9e fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1e9d fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e9d 0x1e9d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 1e9f 1e9f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 1ea0 1ea0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1ea1 1ea1 <halt> ; Flow R 1ea2 ; -------------------------------------------------------------------------------------- 1ea2 ; 0x032b Declare_Type Record,Incomplete,Visible 1ea2 ; -------------------------------------------------------------------------------------- 1ea2 MACRO_Declare_Type_Record,Incomplete,Visible: 1ea2 1ea2 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ea2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1ea3 1ea3 fiu_load_oreg 1 hold_oreg; Flow J 0x1e99 fiu_offs_lit 44 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e99 0x1e99 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ea4 ; -------------------------------------------------------------------------------------- 1ea4 ; 0x0326 Complete_Type Record,By_Defining 1ea4 ; -------------------------------------------------------------------------------------- 1ea4 MACRO_Complete_Type_Record,By_Defining: 1ea4 1ea4 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ea4 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1e 1ea5 1ea5 ioc_load_wdr 0 ; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1c val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1ea6 1ea6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3279 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 1ea7 1ea7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1ea8 1ea8 ioc_fiubs 1 val ; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 1ea9 1ea9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1eaa 1eaa fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand c WRITE_OUTER_FRAME val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 1eab 1eab fiu_load_tar 1 hold_tar; Flow C cc=False 0x32ab fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 05 GP05 val_a_adr 16 PRODUCT 1eac 1eac ioc_tvbs 3 fiu+fiu; Flow C 0x26b8 seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ead 1ead fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 04 GP04 1eae 1eae fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1e8d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1e8d 0x1e8d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 7 FINISH_POP_DOWN typ_rand d SET_PASS_PRIVACY_BIT 1eaf 1eaf fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1e91 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1e91 0x1e91 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1eb0 1eb0 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 1eb1 1eb1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1eb2 ; -------------------------------------------------------------------------------------- 1eb2 ; 0x0325 Complete_Type Record,By_Renaming 1eb2 ; -------------------------------------------------------------------------------------- 1eb2 MACRO_Complete_Type_Record,By_Renaming: 1eb2 1eb2 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1eb2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1eb3 1eb3 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1eb4 1eb4 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 1eb5 1eb5 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 1eb6 1eb6 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 1eb7 1eb7 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 1eb8 1eb8 seq_br_type 4 Call False; Flow C cc=False 0x32ab seq_branch_adr 32ab 0x32ab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1eb9 1eb9 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 1eba 1eba ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1ebb 1ebb fiu_mem_start 3 start-wr; Flow J cc=True 0x1ec1 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ec1 0x1ec1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1ebc 1ebc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1ebd 1ebd fiu_mem_start 2 start-rd; Flow J 0x1eba ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1eba 0x1eba typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 1ebe ; -------------------------------------------------------------------------------------- 1ebe ; 0x0324 Complete_Type Record,By_Component_Completion 1ebe ; -------------------------------------------------------------------------------------- 1ebe MACRO_Complete_Type_Record,By_Component_Completion: 1ebe 1ebe dispatch_brk_class 4 ; Flow C 0x32fe dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ebe fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1ebf 1ebf fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 35 VR09:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 1ec0 1ec0 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1ec1 ; Flow J cc=#0x0 0x1ec1 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1ec1 0x1ec1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ec1 1ec1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ec2 1ec2 fiu_tivi_src c mar_0xc; Flow J 0x1ec5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ec5 0x1ec5 typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ec3 1ec3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1ec4 1ec4 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1ec5 1ec5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1ed3 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ed3 0x1ed3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ec6 1ec6 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 1ec7 1ec7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 1ec8 1ec8 ioc_load_wdr 0 ; Flow J cc=False 0x1ecd seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ecd 0x1ecd typ_b_adr 03 GP03 val_b_adr 03 GP03 1ec9 1ec9 fiu_load_tar 1 hold_tar; Flow C cc=True 0x1ed0 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1ed0 0x1ed0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 1eca 1eca ioc_tvbs 2 fiu+val; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 1ecb 1ecb ioc_fiubs 1 val ; Flow J cc=True 0x1ec5 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1ec5 0x1ec5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ecc 1ecc ioc_fiubs 1 val ; Flow J 0x1ec5 seq_br_type 3 Unconditional Branch seq_branch_adr 1ec5 0x1ec5 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ecd 1ecd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1ece 1ece seq_b_timing 1 Latch Condition; Flow C cc=True 0x1ed0 seq_br_type 5 Call True seq_branch_adr 1ed0 0x1ed0 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ecf 1ecf fiu_mem_start 3 start-wr; Flow J 0x1eca ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1eca 0x1eca typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 1ed0 ; -------------------------------------------------------------------------------------- 1ed0 ; Comes from: 1ed0 ; 1ec9 C True from color MACRO_Complete_Type_Record,By_Renaming 1ed0 ; 1ece C True from color MACRO_Complete_Type_Record,By_Renaming 1ed0 ; -------------------------------------------------------------------------------------- 1ed0 1ed0 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 1ed1 1ed1 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1ed2 0x1ed2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1ed2 1ed2 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3279 seq_br_type 9 Return False seq_branch_adr 3279 0x3279 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 1ed3 1ed3 ioc_fiubs 1 val seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ed4 1ed4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1ed5 1ed5 ioc_load_wdr 0 ; Flow J 0x1ec1 seq_br_type 3 Unconditional Branch seq_branch_adr 1ec1 0x1ec1 typ_b_adr 02 GP02 val_b_adr 02 GP02 1ed6 ; -------------------------------------------------------------------------------------- 1ed6 ; 0x0321 Declare_Variable Record,Visible 1ed6 ; -------------------------------------------------------------------------------------- 1ed6 MACRO_Declare_Variable_Record,Visible: 1ed6 1ed6 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ed6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 1ed7 1ed7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1eed fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1eed 0x1eed seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ed8 1ed8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ed9 0x1ed9 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) seq_random 04 Load_save_offset+? typ_a_adr 28 TR07:08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ed9 1ed9 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1ee1 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ee1 0x1ee1 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_frame 2 1eda 1eda seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1edd seq_br_type 1 Branch True seq_branch_adr 1edd 0x1edd seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 04 GP04 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1edb 1edb ioc_fiubs 1 val ; Flow C 0x2a2e seq_br_type 7 Unconditional Call seq_branch_adr 2a2e 0x2a2e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1edc 1edc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1edd 1edd fiu_tivi_src c mar_0xc; Flow J cc=False 0x1ee0 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 1ee0 0x1ee0 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 1ede 1ede seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a2e seq_br_type 5 Call True seq_branch_adr 2a2e 0x2a2e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1edf 1edf fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1ee0 0x1ee0 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ee0 1ee0 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ee1 1ee1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ee2 1ee2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_frame 2 val_rand 9 PASS_A_HIGH 1ee3 1ee3 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c seq_en_micro 0 1ee4 ; -------------------------------------------------------------------------------------- 1ee4 ; 0x0322 Declare_Variable Record 1ee4 ; -------------------------------------------------------------------------------------- 1ee4 MACRO_Declare_Variable_Record: 1ee4 1ee4 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ee4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 1ee5 1ee5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1ed8 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ed8 0x1ed8 seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ee6 ; -------------------------------------------------------------------------------------- 1ee6 ; 0x0320 Declare_Variable Record,Duplicate 1ee6 ; -------------------------------------------------------------------------------------- 1ee6 MACRO_Declare_Variable_Record,Duplicate: 1ee6 1ee6 dispatch_brk_class 4 ; Flow C cc=False 0x32a7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ee6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1ee7 1ee7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ee8 1ee8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1eeb fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1eeb 0x1eeb seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1ee9 1ee9 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x3279 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_frame 2 1eea 1eea fiu_tivi_src c mar_0xc; Flow C cc=False 0x329c ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1eeb 1eeb ioc_fiubs 1 val ; Flow C 0x1eee ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1eee 0x1eee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 1eec 1eec fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1eed 1eed seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1eee ; -------------------------------------------------------------------------------------- 1eee ; Comes from: 1eee ; 076e C from color 0x0767 1eee ; 115e C from color 0x1117 1eee ; 1168 C from color 0x1164 1eee ; 1192 C from color 0x111d 1eee ; 1198 C from color 0x111d 1eee ; 11c5 C from color 0x111d 1eee ; 11d1 C from color 0x111d 1eee ; 1314 C from color MACRO_Declare_Variable_Variant_Record,Duplicate 1eee ; 17a8 C from color 0x0a32 1eee ; 17fa C False from color MACRO_Execute_Record,Structure_Write 1eee ; 1808 C from color 0x0a31 1eee ; 180f C from color 0x0a31 1eee ; 1977 C from color MACRO_Execute_Vector,Slice_Read 1eee ; 19a3 C True from color MACRO_Execute_Vector,Slice_Write 1eee ; 19f4 C from color MACRO_Execute_Vector,Catenate 1eee ; 19f6 C from color MACRO_Execute_Vector,Catenate 1eee ; 1a63 C True from color 0x0a2f 1eee ; 1a80 C True from color 0x0a2f 1eee ; 1a96 C from color 0x0a2f 1eee ; 1c38 C from color 0x1c27 1eee ; 1db7 C True from color 0x1d39 1eee ; 1e16 C True from color MACRO_Execute_Matrix,Structure_Write 1eee ; 1e18 C from color MACRO_Execute_Matrix,Structure_Write 1eee ; 1e44 C True from color MACRO_Execute_Matrix,Structure_Write 1eee ; 1eeb C from color MACRO_Declare_Variable_Record,Duplicate 1eee ; -------------------------------------------------------------------------------------- 1eee 1eee fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1f4c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f4c 0x1f4c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1eef 1eef fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1efa fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1efa 0x1efa seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 1ef0 1ef0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1ef5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ef5 0x1ef5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 1ef1 1ef1 fiu_fill_mode_src 0 ; Flow J 0x1ef2 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ef2 1ef2 fiu_fill_mode_src 0 ; Flow J cc=False 0x1ef7 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ef7 0x1ef7 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1ef3 1ef3 fiu_fill_mode_src 0 ; Flow J 0x1ef4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef4 0x1ef4 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1ef4 1ef4 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1ef5 1ef5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ef6 1ef6 fiu_fill_mode_src 0 ; Flow J 0x1ef2 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ef7 1ef7 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ef8 1ef8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1ef9 1ef9 fiu_load_var 1 hold_var; Flow J 0x1ef4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ef4 0x1ef4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1efa 1efa fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1f03 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f03 0x1f03 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1efb 1efb fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f1e fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f1e 0x1f1e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 1efc 1efc fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1efd 1efd fiu_fill_mode_src 0 ; Flow J cc=True 0x1f07 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1f07 0x1f07 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1efe 1efe fiu_mem_start 2 start-rd; Flow J 0x1eff ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1eff 0x1eff seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1eff 1eff seq_br_type 3 Unconditional Branch; Flow J 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 1f00 1f00 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f01 1f01 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1ef0 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ef0 0x1ef0 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1f02 1f02 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1efb fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1efb 0x1efb seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1f03 1f03 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f21 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f21 0x1f21 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1f04 1f04 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f06 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f06 0x1f06 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1f05 1f05 seq_br_type 0 Branch False; Flow J cc=False 0x1eff seq_branch_adr 1eff 0x1eff seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1f06 1f06 fiu_fill_mode_src 0 ; Flow J 0x1f07 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f07 0x1f07 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f07 1f07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f0b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f0b 0x1f0b typ_mar_cntl 6 INCREMENT_MAR 1f08 1f08 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f09 1f09 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f0a 1f0a fiu_fill_mode_src 0 ; Flow J 0x1ef4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1ef4 0x1ef4 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f0b 1f0b fiu_load_tar 1 hold_tar; Flow J cc=False 0x1f11 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f11 0x1f11 seq_cond_sel 64 OFFSET_REGISTER_???? 1f0c 1f0c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f16 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1f16 0x1f16 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f0d 1f0d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f0e 1f0e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f0f 1f0f fiu_fill_mode_src 0 ; Flow J 0x1f10 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f10 0x1f10 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f10 1f10 fiu_mem_start 4 continue; Flow J 0x1ef4 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1ef4 0x1ef4 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 1f11 1f11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f16 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 1f16 0x1f16 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f12 1f12 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 1f13 1f13 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f15 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f15 0x1f15 seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f14 1f14 fiu_fill_mode_src 0 ; Flow J 0x1f10 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f10 0x1f10 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f15 1f15 fiu_fill_mode_src 0 ; Flow J 0x1f10 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f10 0x1f10 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f16 1f16 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f1b ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1f1b 0x1f1b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl 1 RESTORE_RDR val_c_adr 31 GP0e 1f17 1f17 seq_en_micro 0 1f18 1f18 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f1b ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1f1b 0x1f1b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f19 1f19 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 1f1a 1f1a ioc_adrbs 2 typ ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f1b 0x1f1b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA 1f1b 1f1b fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0e GP0e 1f1c 1f1c fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1f1d 1f1d fiu_mem_start 3 start-wr; Flow J 0x1eff ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1eff 0x1eff seq_random 06 Pop_stack+? 1f1e 1f1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f1f 1f1f fiu_fill_mode_src 0 ; Flow J cc=True 0x1f27 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f27 0x1f27 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f20 1f20 fiu_load_oreg 1 hold_oreg; Flow J 0x1f24 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 1f21 1f21 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f22 1f22 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1f29 seq_br_type 1 Branch True seq_branch_adr 1f29 0x1f29 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 1f23 1f23 fiu_fill_mode_src 0 ; Flow J 0x1f24 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f24 1f24 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f25 1f25 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f26 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f26 0x1f26 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f26 1f26 ioc_load_wdr 0 ; Flow J 0x1f2e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f2e 0x1f2e seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f27 1f27 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f2e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f2e 0x1f2e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f28 1f28 fiu_fill_mode_src 0 ; Flow J 0x1f2b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f2b 0x1f2b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f29 1f29 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f2e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f2e 0x1f2e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f2a 1f2a fiu_fill_mode_src 0 ; Flow J 0x1f2b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f2b 0x1f2b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f2b 1f2b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1f2c 1f2c fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 1f2d 1f2d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f26 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f26 0x1f26 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f2e 1f2e fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1f00 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f00 0x1f00 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f2f 1f2f fiu_mem_start 4 continue; Flow J cc=False 0x1f3e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f3e 0x1f3e seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f30 1f30 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f31 1f31 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f3b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f3b 0x1f3b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f32 1f32 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f33 1f33 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329c seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f34 1f34 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f35 1f35 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f38 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f38 0x1f38 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f36 1f36 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1f37 1f37 fiu_mem_start 2 start-rd; Flow C 0x32fe seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe 1f38 1f38 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f3a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f3a 0x1f3a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f39 1f39 fiu_load_oreg 1 hold_oreg; Flow J 0x1f34 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f34 0x1f34 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f3a 1f3a ioc_load_wdr 0 ; Flow J 0x1f00 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f00 0x1f00 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f3b 1f3b ioc_load_wdr 0 ; Flow J cc=False 0x1f00 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f00 0x1f00 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f3c 1f3c seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 1f3d 1f3d seq_br_type 3 Unconditional Branch; Flow J 0x1f00 seq_branch_adr 1f00 0x1f00 1f3e 1f3e fiu_load_var 1 hold_var; Flow J cc=False 0x1f49 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f49 0x1f49 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f3f 1f3f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f40 1f40 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f41 1f41 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329c seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f42 1f42 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f46 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f46 0x1f46 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f43 1f43 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a84 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f44 1f44 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f45 1f45 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f42 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f42 0x1f42 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f46 1f46 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f47 1f47 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1f48 1f48 ioc_load_wdr 0 ; Flow J 0x1f00 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f00 0x1f00 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f49 1f49 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f4a 1f4a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f4b 1f4b ioc_load_wdr 0 ; Flow J 0x1f00 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f00 0x1f00 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f4c ; -------------------------------------------------------------------------------------- 1f4c ; Comes from: 1f4c ; 1eee C True from color 0x0000 1f4c ; -------------------------------------------------------------------------------------- 1f4c 1f4c fiu_tivi_src 4 fiu_var; Flow R cc=False ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1f4d 0x1f4d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f4d 1f4d fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f4e 1f4e fiu_len_fill_lit 49 zero-fill 0x9 fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 1f4f 1f4f seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1f50 0x1f50 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 1f50 1f50 seq_br_type 7 Unconditional Call; Flow C 0x32c3 seq_branch_adr 32c3 0x32c3 1f51 1f51 <halt> ; Flow R 1f52 ; -------------------------------------------------------------------------------------- 1f52 ; 0x03d1 Declare_Type Access,Constrained 1f52 ; -------------------------------------------------------------------------------------- 1f52 MACRO_Declare_Type_Access,Constrained: 1f52 1f52 dispatch_brk_class 4 ; Flow J 0x1f5a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f52 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f5a 0x1f5a typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f53 1f53 <halt> ; Flow R 1f54 ; -------------------------------------------------------------------------------------- 1f54 ; 0x03d2 Declare_Type Access,Constrained,Visible 1f54 ; -------------------------------------------------------------------------------------- 1f54 MACRO_Declare_Type_Access,Constrained,Visible: 1f54 1f54 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f54 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f55 1f55 fiu_mem_start 2 start-rd; Flow J 0x1f5a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f5a 0x1f5a typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f56 ; -------------------------------------------------------------------------------------- 1f56 ; 0x03ab Declare_Type Heap_Access,Constrained 1f56 ; -------------------------------------------------------------------------------------- 1f56 MACRO_Declare_Type_Heap_Access,Constrained: 1f56 1f56 dispatch_brk_class 4 ; Flow J 0x1f5b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f56 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f5b 0x1f5b typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f57 1f57 <halt> ; Flow R 1f58 ; -------------------------------------------------------------------------------------- 1f58 ; 0x03ac Declare_Type Heap_Access,Constrained,Visible 1f58 ; -------------------------------------------------------------------------------------- 1f58 MACRO_Declare_Type_Heap_Access,Constrained,Visible: 1f58 1f58 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f58 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f59 1f59 fiu_mem_start 2 start-rd; Flow J 0x1f5b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f5b 0x1f5b typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f5a 1f5a fiu_load_tar 1 hold_tar; Flow J 0x1f5c fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f5c 0x1f5c seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 1f5b 1f5b fiu_load_tar 1 hold_tar; Flow J 0x1f5c fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f5c 0x1f5c seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 7 1f5c 1f5c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f5d 1f5d fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1f5e 1f5e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f5f 1f5f fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 1f60 1f60 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x1f66 seq_br_type f Unconditional Case Call seq_branch_adr 1f66 0x1f66 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1f61 1f61 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1f62 1f62 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 1f63 1f63 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 1f64 1f64 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 01 GP01 1f65 1f65 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1f66 ; -------------------------------------------------------------------------------------- 1f66 ; Comes from: 1f66 ; 1f60 C #0x0 from color MACRO_Declare_Type_Access,Constrained 1f66 ; -------------------------------------------------------------------------------------- 1f66 1f66 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f67 1f67 fiu_mem_start 2 start-rd; Flow J 0x1f6e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f6e 0x1f6e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1f68 1f68 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f69 1f69 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f6a 1f6a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f6b 1f6b seq_br_type 3 Unconditional Branch; Flow J 0x1f73 seq_branch_adr 1f73 0x1f73 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f6c 1f6c seq_br_type 3 Unconditional Branch; Flow J 0x1f73 seq_branch_adr 1f73 0x1f73 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f6d 1f6d fiu_mem_start 2 start-rd; Flow J 0x1f7b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f7b 0x1f7b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1f6e 1f6e ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1f6f 1f6f fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1f70 1f70 <default> 1f71 1f71 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1f72 1f72 fiu_mem_start 2 start-rd; Flow J 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3244 0x3244 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f73 1f73 ioc_fiubs 1 val ; Flow C cc=False 0x32a9 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1f74 1f74 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f75 0x1f75 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 1f75 1f75 fiu_mem_start 2 start-rd; Flow C 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3244 0x3244 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f76 1f76 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1f77 1f77 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1f78 1f78 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1f79 1f79 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f7a 0x1f7a typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 1f7a 1f7a seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1f7b 1f7b <default> 1f7c 1f7c fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x1f73 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f73 0x1f73 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1f7d 1f7d <halt> ; Flow R 1f7e ; -------------------------------------------------------------------------------------- 1f7e ; 0x0341 Complete_Type Array,By_Constraining 1f7e ; -------------------------------------------------------------------------------------- 1f7e MACRO_Complete_Type_Array,By_Constraining: 1f7e 1f7e dispatch_brk_class 4 ; Flow C cc=True 0x32ab dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1f7e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f7f 1f7f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1f80 1f80 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 1f81 1f81 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x1f86 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1f86 0x1f86 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 9 PASS_A_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f82 1f82 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1f83 1f83 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1f84 1f84 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1f8b seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f8b 0x1f8b seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 1f85 1f85 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 1f86 1f86 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1f87 1f87 <default> 1f88 1f88 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f89 1f89 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1f8a 0x1f8a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 1f8a 1f8a seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1f8b 1f8b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_lit 0 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1f8c 1f8c fiu_mem_start 4 continue; Flow J cc=False 0x1faa fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1faa 0x1faa typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f8d 1f8d fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1f8e 1f8e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1f99 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1f99 0x1f99 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f8f 1f8f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1fa7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fa7 0x1fa7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1f90 1f90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3272 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1f91 1f91 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1fa0 fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fa0 0x1fa0 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f92 1f92 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f93 1f93 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1d TOP - 3 1f94 1f94 ioc_load_wdr 0 ; Flow C cc=True 0x3272 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1f95 1f95 seq_b_timing 0 Early Condition; Flow C cc=False 0x1f97 seq_br_type 4 Call False seq_branch_adr 1f97 0x1f97 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA 1f96 1f96 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1f97 ; -------------------------------------------------------------------------------------- 1f97 ; Comes from: 1f97 ; 1f95 C False from color MACRO_Complete_Type_Array,By_Constraining 1f97 ; -------------------------------------------------------------------------------------- 1f97 1f97 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1f98 1f98 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 1f99 ; -------------------------------------------------------------------------------------- 1f99 ; Comes from: 1f99 ; 1f8e C True from color MACRO_Complete_Type_Array,By_Constraining 1f99 ; -------------------------------------------------------------------------------------- 1f99 1f99 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1f9a 1f9a fiu_mem_start 4 continue; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f9b 0x1f9b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1f9b 1f9b seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 1f9c ; -------------------------------------------------------------------------------------- 1f9c ; Comes from: 1f9c ; 1fac C True from color MACRO_Complete_Type_Array,By_Constraining 1f9c ; -------------------------------------------------------------------------------------- 1f9c 1f9c <default> 1f9d 1f9d fiu_mem_start 2 start-rd; Flow J 0x1f9a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f9a 0x1f9a typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f9e ; -------------------------------------------------------------------------------------- 1f9e ; Comes from: 1f9e ; 1fdb C True from color MACRO_Complete_Type_Array,By_Constraining 1f9e ; -------------------------------------------------------------------------------------- 1f9e 1f9e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1f9f 0x1f9f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 1f9f 1f9f seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 1fa0 ; -------------------------------------------------------------------------------------- 1fa0 ; Comes from: 1fa0 ; 1f91 C False from color MACRO_Complete_Type_Array,By_Constraining 1fa0 ; -------------------------------------------------------------------------------------- 1fa0 1fa0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1fa1 1fa1 ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fa2 1fa2 seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fa5 seq_br_type 4 Call False seq_branch_adr 1fa5 0x1fa5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fa3 1fa3 seq_br_type 4 Call False; Flow C cc=False 0x1fa6 seq_branch_adr 1fa6 0x1fa6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fa4 1fa4 fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 1fa5 ; -------------------------------------------------------------------------------------- 1fa5 ; Comes from: 1fa5 ; 1fa2 C False from color 0x1f9e 1fa5 ; -------------------------------------------------------------------------------------- 1fa5 1fa5 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fa6 0x1fa6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 1fa6 ; -------------------------------------------------------------------------------------- 1fa6 ; Comes from: 1fa6 ; 1fa3 C False from color 0x1f9e 1fa6 ; -------------------------------------------------------------------------------------- 1fa6 1fa6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1fa7 ; -------------------------------------------------------------------------------------- 1fa7 ; Comes from: 1fa7 ; 1f8f C False from color MACRO_Complete_Type_Array,By_Constraining 1fa7 ; -------------------------------------------------------------------------------------- 1fa7 1fa7 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fa8 1fa8 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fa9 1fa9 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1faa 1faa fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fab 1fab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fdb fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fdb 0x1fdb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 1fac 1fac fiu_mem_start 4 continue; Flow C cc=True 0x1f9c ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f9c 0x1f9c seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1b TOP - 5 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1fad 1fad fiu_mem_start 4 continue; Flow C cc=True 0x1fc5 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1fc5 0x1fc5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1fae 1fae fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fc8 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fc8 0x1fc8 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1faf 1faf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3272 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1fb0 1fb0 seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fcc seq_br_type 4 Call False seq_branch_adr 1fcc 0x1fcc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fb1 1fb1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1fb2 1fb2 ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fb3 1fb3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1fb4 1fb4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fb5 1fb5 val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fb6 1fb6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1b TOP - 5 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 1fb7 1fb7 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x1fd4 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd4 0x1fd4 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fb8 1fb8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 1fb9 1fb9 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1fba 1fba fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x1fd6 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd6 0x1fd6 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1fbb 1fbb fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 02 ? typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1fbc 1fbc fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1b TOP - 5 1fbd 1fbd fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1fbe 1fbe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fc2 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1fc2 0x1fc2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 1fbf 1fbf ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 1fc0 1fc0 typ_csa_cntl 3 POP_CSA 1fc1 1fc1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1fc2 1fc2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1fc3 1fc3 ioc_load_wdr 0 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 1fc4 1fc4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1fc5 ; -------------------------------------------------------------------------------------- 1fc5 ; Comes from: 1fc5 ; 1fad C True from color MACRO_Complete_Type_Array,By_Constraining 1fc5 ; -------------------------------------------------------------------------------------- 1fc5 1fc5 seq_br_type 4 Call False; Flow C cc=False 0x3272 seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 1fc6 1fc6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1fc7 1fc7 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1fc8 1fc8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fc9 1fc9 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fca 1fca fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fcb 1fcb seq_br_type 3 Unconditional Branch; Flow J 0x1fb1 seq_branch_adr 1fb1 0x1fb1 val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fcc ; -------------------------------------------------------------------------------------- 1fcc ; Comes from: 1fcc ; 1fb0 C False from color MACRO_Complete_Type_Array,By_Constraining 1fcc ; -------------------------------------------------------------------------------------- 1fcc 1fcc val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1fcd 1fcd fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1fce 1fce seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fcf 1fcf seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fd2 seq_br_type 4 Call False seq_branch_adr 1fd2 0x1fd2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd0 1fd0 seq_br_type 4 Call False; Flow C cc=False 0x1fd3 seq_branch_adr 1fd3 0x1fd3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1fd1 1fd1 seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fd2 ; -------------------------------------------------------------------------------------- 1fd2 ; Comes from: 1fd2 ; 1fcf C False from color 0x1fcc 1fd2 ; -------------------------------------------------------------------------------------- 1fd2 1fd2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fd3 0x1fd3 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 1fd3 ; -------------------------------------------------------------------------------------- 1fd3 ; Comes from: 1fd3 ; 1fd0 C False from color 0x1fcc 1fd3 ; -------------------------------------------------------------------------------------- 1fd3 1fd3 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1fd4 ; -------------------------------------------------------------------------------------- 1fd4 ; Comes from: 1fd4 ; 1fb7 C False from color MACRO_Complete_Type_Array,By_Constraining 1fd4 ; -------------------------------------------------------------------------------------- 1fd4 1fd4 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fd5 1fd5 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1c TOP - 4 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1fd6 ; -------------------------------------------------------------------------------------- 1fd6 ; Comes from: 1fd6 ; 1fba C False from color MACRO_Complete_Type_Array,By_Constraining 1fd6 ; -------------------------------------------------------------------------------------- 1fd6 1fd6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd7 1fd7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd8 1fd8 seq_br_type 4 Call False; Flow C cc=False 0x1fda seq_branch_adr 1fda 0x1fda seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 1fd9 1fd9 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 1fda ; -------------------------------------------------------------------------------------- 1fda ; Comes from: 1fda ; 1fd8 C False from color 0x1fd6 1fda ; -------------------------------------------------------------------------------------- 1fda 1fda seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1fdb 1fdb seq_b_timing 1 Latch Condition; Flow C cc=True 0x1f9e seq_br_type 5 Call True seq_branch_adr 1f9e 0x1f9e 1fdc 1fdc fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 1fdd 1fdd fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1fde 1fde typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 1fdf 1fdf fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1fe0 1fe0 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 1fe1 1fe1 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1fea fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1fea 0x1fea seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 1fe2 1fe2 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1fe3 1fe3 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 1fe4 1fe4 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 1fe5 1fe5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fe6 1fe6 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1fe7 1fe7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1fe8 1fe8 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1fe9 1fe9 fiu_load_tar 1 hold_tar; Flow J 0x1fea fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1fea 0x1fea typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1fea 1fea fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2000 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2000 0x2000 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 1feb 1feb fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 1fec 1fec ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fed 1fed ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1fee 1fee fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fef 1fef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ff0 1ff0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1ff1 1ff1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fff fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fff 0x1fff seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ff2 1ff2 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3272 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3272 0x3272 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1ff3 1ff3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1ff4 1ff4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 1ff5 1ff5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 1ff6 1ff6 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 1ff7 1ff7 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 1ff8 1ff8 ioc_fiubs 2 typ ; Flow J cc=True 0x1fea seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1fea 0x1fea seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ff9 1ff9 seq_br_type 0 Branch False; Flow J cc=False 0x1ffe seq_branch_adr 1ffe 0x1ffe seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffa 1ffa seq_br_type 0 Branch False; Flow J cc=False 0x1ffe seq_branch_adr 1ffe 0x1ffe seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffb 1ffb seq_br_type 0 Branch False; Flow J cc=False 0x1ffe seq_branch_adr 1ffe 0x1ffe seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffc 1ffc seq_br_type 0 Branch False; Flow J cc=False 0x1ffe seq_branch_adr 1ffe 0x1ffe seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffd 1ffd seq_br_type 1 Branch True; Flow J cc=True 0x1fea seq_branch_adr 1fea 0x1fea seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 1ffe 1ffe ioc_fiubs 2 typ ; Flow J 0x1fea seq_br_type 3 Unconditional Branch seq_branch_adr 1fea 0x1fea typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1fff 1fff seq_br_type 3 Unconditional Branch; Flow J 0x1ff4 seq_branch_adr 1ff4 0x1ff4 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2000 2000 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2001 2001 ioc_load_wdr 0 ; Flow C cc=False 0x2005 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2005 0x2005 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_b_adr 01 GP01 val_b_adr 0f GP0f 2002 2002 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 05 GP05 val_alu_func 0 PASS_A 2003 2003 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 2004 2004 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2005 ; -------------------------------------------------------------------------------------- 2005 ; Comes from: 2005 ; 2001 C False from color MACRO_Complete_Type_Array,By_Constraining 2005 ; -------------------------------------------------------------------------------------- 2005 2005 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2006 2006 ioc_fiubs 1 val ; Flow J 0x2217 seq_br_type 3 Unconditional Branch seq_branch_adr 2217 0x2217 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 2007 2007 <halt> ; Flow R 2008 ; -------------------------------------------------------------------------------------- 2008 ; 0x0343 Complete_Type Array,By_Defining 2008 ; -------------------------------------------------------------------------------------- 2008 MACRO_Complete_Type_Array,By_Defining: 2008 2008 dispatch_brk_class 4 ; Flow C cc=True 0x32ab dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2008 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2009 2009 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 200a 200a fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 200b 200b fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame a val_c_adr 37 GP08 val_c_source 0 FIU_BUS 200c 200c fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3b GP04 val_c_source 0 FIU_BUS 200d 200d fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 200e 200e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 200f 200f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 2010 2010 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2011 2011 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a8 seq_br_type f Unconditional Case Call seq_branch_adr 20a8 0x20a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2012 2012 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2017 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2017 0x2017 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2013 2013 seq_br_type 2 Push (branch address); Flow J 0x2014 seq_branch_adr 2017 0x2017 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 2014 2014 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2015 0x2015 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 2015 2015 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20b8 seq_br_type 1 Branch True seq_branch_adr 20b8 0x20b8 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 2d TR09:0d typ_frame 9 2016 2016 seq_br_type 3 Unconditional Branch; Flow J 0x20bb seq_branch_adr 20bb 0x20bb 2017 2017 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2034 seq_br_type 1 Branch True seq_branch_adr 2034 0x2034 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_rand 2 DEC_LOOP_COUNTER 2018 2018 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2019 2019 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 201a 201a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 201b 201b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2023 seq_br_type 1 Branch True seq_branch_adr 2023 0x2023 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 201c 201c seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 201d 201d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 201e 201e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2026 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2026 0x2026 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 201f 201f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2020 2020 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2021 2021 fiu_mem_start 3 start-wr; Flow J cc=True 0x2026 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2026 0x2026 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2022 2022 fiu_mem_start 3 start-wr; Flow J 0x2026 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2026 0x2026 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2023 2023 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2024 2024 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2025 2025 fiu_mem_start 3 start-wr; Flow J 0x2026 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2026 0x2026 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2026 2026 fiu_mem_start 4 continue; Flow C cc=True 0x32a7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2027 2027 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 2028 2028 fiu_load_var 1 hold_var; Flow J cc=True 0x202c fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 202c 0x202c typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2029 2029 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 202a 202a typ_csa_cntl 3 POP_CSA 202b 202b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 202c 202c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 202d 202d fiu_tivi_src 4 fiu_var; Flow J 0x202e ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 202a 0x202a val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 202e 202e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 202f 0x202f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 23 TR01:03 typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 202f 202f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2030 2030 <default> 2031 2031 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2032 2032 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2033 0x2033 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f val_b_adr 0f GP0f 2033 2033 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2034 2034 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2035 2035 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2036 2036 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x203f seq_br_type 1 Branch True seq_branch_adr 203f 0x203f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 2037 2037 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2038 2038 ioc_fiubs 1 val ; Flow C cc=False 0x3278 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2039 2039 seq_b_timing 1 Latch Condition; Flow J cc=True 0x203e seq_br_type 1 Branch True seq_branch_adr 203e 0x203e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 203a 203a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 203b 203b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 203c 203c seq_br_type 1 Branch True; Flow J cc=True 0x203e seq_branch_adr 203e 0x203e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 203d 203d seq_br_type 3 Unconditional Branch; Flow J 0x203e seq_branch_adr 203e 0x203e val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 203e 203e seq_br_type 3 Unconditional Branch; Flow J 0x2041 seq_branch_adr 2041 0x2041 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 203f 203f ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 2040 2040 seq_br_type 3 Unconditional Branch; Flow J 0x203e seq_branch_adr 203e 0x203e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2041 2041 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 2042 2042 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 04 GP04 val_rand 2 DEC_LOOP_COUNTER 2043 2043 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2044 2044 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x329b fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329b 0x329b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2045 2045 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 2046 2046 ioc_load_wdr 0 ; Flow J 0x2047 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2047 0x2047 val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2047 2047 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2048 2048 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2049 2049 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 204a 204a ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204b 204b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x204d seq_br_type 0 Branch False seq_branch_adr 204d 0x204d seq_cond_sel 67 REFRESH_MACRO_EVENT 204c 204c seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 204d 204d seq_br_type 0 Branch False; Flow J cc=False 0x2059 seq_branch_adr 2059 0x2059 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 204e 204e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204f 204f seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2050 2050 ioc_fiubs 1 val ; Flow C cc=False 0x3278 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2051 2051 seq_en_micro 0 2052 2052 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2057 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2057 0x2057 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2053 2053 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2054 2054 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2055 2055 fiu_mem_start 3 start-wr; Flow J cc=True 0x2057 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2057 0x2057 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2056 2056 fiu_mem_start 3 start-wr; Flow J 0x2057 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2057 0x2057 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2057 2057 fiu_mem_start 4 continue; Flow J 0x2058 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 2047 0x2047 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 2058 2058 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x205c ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 205c 0x205c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 2059 2059 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 205a 205a ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 205b 205b fiu_mem_start 3 start-wr; Flow J 0x2057 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2057 0x2057 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 205c 205c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 205d 205d fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 205e 205e ioc_load_wdr 0 ; Flow C cc=False 0x2062 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2062 0x2062 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 205f 205f ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2060 2060 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 2061 2061 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2062 2062 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2063 2063 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2064 2064 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 2065 2065 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 2066 2066 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2067 2067 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2068 2068 fiu_load_tar 1 hold_tar; Flow J 0x2069 fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 206a 0x206a typ_b_adr 01 GP01 2069 2069 seq_br_type 3 Unconditional Branch; Flow J 0x202e seq_branch_adr 202e 0x202e 206a 206a seq_br_type 3 Unconditional Branch; Flow J 0x2217 seq_branch_adr 2217 0x2217 206b 206b <halt> ; Flow R 206c ; -------------------------------------------------------------------------------------- 206c ; 0x0355 Declare_Type Array,Defined_Incomplete 206c ; -------------------------------------------------------------------------------------- 206c MACRO_Declare_Type_Array,Defined_Incomplete: 206c 206c dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 206c fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 206d 206d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206f seq_br_type f Unconditional Case Call seq_branch_adr 206f 0x206f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 206e 206e seq_br_type 7 Unconditional Call; Flow C 0x20cc seq_branch_adr 20cc MACRO_Declare_Type_Array,Defined 206f ; -------------------------------------------------------------------------------------- 206f ; Comes from: 206f ; 206d C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete 206f ; 209e C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 206f ; 20a1 C #0x0 from color 0x209f 206f ; 20a6 C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 206f ; -------------------------------------------------------------------------------------- 206f 206f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2084 seq_br_type 9 Return False seq_branch_adr 2084 0x2084 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2070 2070 seq_br_type a Unconditional Return; Flow R 2071 2071 seq_br_type a Unconditional Return; Flow R 2072 2072 seq_br_type a Unconditional Return; Flow R 2073 2073 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2074 2074 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2075 2075 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2076 2076 seq_br_type a Unconditional Return; Flow R 2077 2077 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2084 seq_br_type 9 Return False seq_branch_adr 2084 0x2084 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2078 2078 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x207f seq_br_type 9 Return False seq_branch_adr 207f 0x207f seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2079 2079 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 207a 207a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 207b 207b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 207c 207c ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2082 seq_br_type 9 Return False seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207d 207d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2082 seq_br_type 9 Return False seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207e 207e ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2082 seq_br_type 9 Return False seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207f 207f fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2084 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2084 0x2084 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE 2080 2080 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2084 seq_br_type 1 Branch True seq_branch_adr 2084 0x2084 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2081 2081 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2082 2082 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2084 seq_br_type 0 Branch False seq_branch_adr 2084 0x2084 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 2083 2083 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2084 2084 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2086 seq_br_type 0 Branch False seq_branch_adr 2086 0x2086 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 2085 2085 seq_br_type 3 Unconditional Branch; Flow J 0x20bd seq_branch_adr 20bd 0x20bd typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 2086 2086 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2087 2087 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2088 2088 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2089 2089 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2091 seq_br_type 1 Branch True seq_branch_adr 2091 0x2091 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 208a 208a seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 208b 208b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 208c 208c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2094 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2094 0x2094 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 208d 208d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 208e 208e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 208f 208f fiu_mem_start 3 start-wr; Flow J cc=True 0x2094 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2094 0x2094 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2090 2090 fiu_mem_start 3 start-wr; Flow J 0x2094 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2094 0x2094 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2091 2091 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2092 2092 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2093 2093 fiu_mem_start 3 start-wr; Flow J 0x2094 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2094 0x2094 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2094 2094 fiu_mem_start 4 continue; Flow C cc=True 0x32a7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2095 2095 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3b VR02:1b val_frame 2 2096 2096 fiu_load_var 1 hold_var; Flow J cc=True 0x2099 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2099 0x2099 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2097 2097 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2098 2098 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2099 2099 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 209a 209a fiu_tivi_src 4 fiu_var; Flow J 0x2098 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2098 0x2098 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 209b 209b <halt> ; Flow R 209c ; -------------------------------------------------------------------------------------- 209c ; 0x0356 Declare_Type Array,Defined_Incomplete,Visible 209c ; -------------------------------------------------------------------------------------- 209c MACRO_Declare_Type_Array,Defined_Incomplete,Visible: 209c 209c dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 209c seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 209d 209d fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 209e 209e seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206f seq_br_type f Unconditional Case Call seq_branch_adr 206f 0x206f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 209f 209f seq_br_type 7 Unconditional Call; Flow C 0x2114 seq_branch_adr 2114 MACRO_Declare_Type_Array,Defined,Visible 20a0 ; -------------------------------------------------------------------------------------- 20a0 ; 0x0348 Declare_Type Array,Defined_Incomplete,Bounds_With_Object 20a0 ; -------------------------------------------------------------------------------------- 20a0 MACRO_Declare_Type_Array,Defined_Incomplete,Bounds_With_Object: 20a0 20a0 dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20a0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20a1 20a1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206f seq_br_type f Unconditional Case Call seq_branch_adr 206f 0x206f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20a2 20a2 seq_br_type 7 Unconditional Call; Flow C 0x211a seq_branch_adr 211a MACRO_Declare_Type_Array,Defined,Bounds_With_Object 20a3 20a3 <halt> ; Flow R 20a4 ; -------------------------------------------------------------------------------------- 20a4 ; 0x0349 Declare_Type Array,Defined_Incomplete,Visible,Bounds_With_Object 20a4 ; -------------------------------------------------------------------------------------- 20a4 MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object: 20a4 20a4 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20a4 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 20a5 20a5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20a6 20a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206f seq_br_type f Unconditional Case Call seq_branch_adr 206f 0x206f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20a7 20a7 seq_br_type 7 Unconditional Call; Flow C 0x211e seq_branch_adr 211e MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object 20a8 ; -------------------------------------------------------------------------------------- 20a8 ; Comes from: 20a8 ; 2011 C #0x0 from color MACRO_Complete_Type_Array,By_Defining 20a8 ; 20cd C #0x0 from color MACRO_Declare_Type_Array,Defined 20a8 ; 2116 C #0x0 from color MACRO_Declare_Type_Array,Defined,Visible 20a8 ; 211b C #0x0 from color MACRO_Declare_Type_Array,Defined,Bounds_With_Object 20a8 ; 2120 C #0x0 from color 0x2012 20a8 ; -------------------------------------------------------------------------------------- 20a8 20a8 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20a9 20a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20aa 20aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ab 20ab fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ac 20ac seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ad 20ad seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ae 20ae seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20af 20af fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20b0 20b0 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b1 20b1 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20b8 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20b8 0x20b8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b2 20b2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b3 20b3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b4 20b4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b5 20b5 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20bb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20bb 0x20bb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b6 20b6 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20bb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20bb 0x20bb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b7 20b7 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20bb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20bb 0x20bb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b8 20b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20b9 0x20b9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 20b9 20b9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 20ba 0x20ba seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 20ba 20ba seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 20bb 20bb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20bc 0x20bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 val_a_adr 14 ZEROS 20bc 20bc seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 20bd 20bd fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ac fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20be 20be seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20bf 20bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20c9 seq_br_type 1 Branch True seq_branch_adr 20c9 0x20c9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20c0 20c0 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20c1 20c1 ioc_fiubs 1 val ; Flow C cc=False 0x3278 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20c2 20c2 ioc_tvbs 5 seq+seq; Flow J cc=True 0x20c7 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20c7 0x20c7 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20c3 20c3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20c4 20c4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20c5 20c5 seq_br_type 1 Branch True; Flow J cc=True 0x20c7 seq_branch_adr 20c7 0x20c7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20c6 20c6 seq_br_type 3 Unconditional Branch; Flow J 0x20c7 seq_branch_adr 20c7 0x20c7 val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20c7 20c7 seq_b_timing 0 Early Condition; Flow J cc=True 0x20e7 seq_br_type 1 Branch True seq_branch_adr 20e7 0x20e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 34 VR05:14 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 20c8 20c8 seq_br_type 3 Unconditional Branch; Flow J 0x20e7 seq_branch_adr 20e7 0x20e7 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 35 VR05:15 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20c9 20c9 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 20ca 20ca ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 20cb 20cb seq_br_type 3 Unconditional Branch; Flow J 0x20c7 seq_branch_adr 20c7 0x20c7 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20cc ; -------------------------------------------------------------------------------------- 20cc ; 0x035d Declare_Type Array,Defined 20cc ; Comes from: 20cc ; 206e C from color 0x2012 20cc ; -------------------------------------------------------------------------------------- 20cc MACRO_Declare_Type_Array,Defined: 20cc 20cc dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20cc fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20cd 20cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a8 seq_br_type f Unconditional Case Call seq_branch_adr 20a8 0x20a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20ce 20ce ioc_tvbs 2 fiu+val; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 20cf 20cf seq_b_timing 1 Latch Condition; Flow J cc=True 0x20bd seq_br_type 1 Branch True seq_branch_adr 20bd 0x20bd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 20d0 20d0 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 20d1 20d1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20d2 20d2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20d3 20d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20dd seq_br_type 1 Branch True seq_branch_adr 20dd 0x20dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20d4 20d4 seq_b_timing 1 Latch Condition; Flow C cc=False 0x20db seq_br_type 4 Call False seq_branch_adr 20db 0x20db seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20d5 20d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20d6 20d6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x20e0 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20e0 0x20e0 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20d7 20d7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20d8 20d8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20d9 20d9 fiu_mem_start 3 start-wr; Flow J cc=True 0x20e0 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 20e0 0x20e0 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20da 20da fiu_mem_start 3 start-wr; Flow J 0x20e0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20e0 0x20e0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20db ; -------------------------------------------------------------------------------------- 20db ; Comes from: 20db ; 20d4 C False from color 0x2012 20db ; -------------------------------------------------------------------------------------- 20db 20db seq_br_type 1 Branch True; Flow J cc=True 0x3278 seq_branch_adr 3278 0x3278 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 20dc 20dc seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 20dd 20dd ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 20de 20de typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 20df 20df fiu_mem_start 3 start-wr; Flow J 0x20e0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20e0 0x20e0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20e0 20e0 fiu_mem_start 4 continue; Flow C cc=True 0x32a7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 20e1 20e1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 20e2 20e2 fiu_load_var 1 hold_var; Flow J cc=True 0x20e5 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20e5 0x20e5 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 20e3 20e3 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20e4 20e4 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 20e5 20e5 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20e6 20e6 fiu_tivi_src 4 fiu_var; Flow J 0x20e4 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 20e4 0x20e4 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 20e7 20e7 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 20e8 20e8 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 10 TOP val_rand 2 DEC_LOOP_COUNTER 20e9 20e9 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ea 20ea fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x329b fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329b 0x329b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 20eb 20eb fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 20ec 20ec ioc_load_wdr 0 ; Flow J 0x20ed ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 20ed 0x20ed val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ed 20ed fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20ee 20ee fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ef 20ef ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 20f0 20f0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f1 20f1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x20f3 seq_br_type 0 Branch False seq_branch_adr 20f3 0x20f3 seq_cond_sel 67 REFRESH_MACRO_EVENT 20f2 20f2 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 20f3 20f3 seq_br_type 0 Branch False; Flow J cc=False 0x20ff seq_branch_adr 20ff 0x20ff seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 20f4 20f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f5 20f5 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3278 seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f6 20f6 ioc_fiubs 1 val ; Flow C cc=False 0x3278 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20f7 20f7 seq_en_micro 0 20f8 20f8 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x20fd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20fd 0x20fd seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20f9 20f9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20fa 20fa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20fb 20fb fiu_mem_start 3 start-wr; Flow J cc=True 0x20fd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 20fd 0x20fd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20fc 20fc fiu_mem_start 3 start-wr; Flow J 0x20fd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20fd 0x20fd typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20fd 20fd fiu_mem_start 4 continue; Flow J 0x20fe ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 20ed 0x20ed seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 20fe 20fe ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2102 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2102 0x2102 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 20ff 20ff typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2100 2100 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 2101 2101 fiu_mem_start 3 start-wr; Flow J 0x20fd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20fd 0x20fd typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2102 2102 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2106 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2106 0x2106 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2103 2103 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2104 2104 ioc_load_wdr 0 ; Flow C cc=False 0x210d seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 210d 0x210d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2105 2105 ioc_adrbs 2 typ ; Flow J 0x2109 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2109 0x2109 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2106 2106 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2107 2107 ioc_load_wdr 0 ; Flow C cc=False 0x210d seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 210d 0x210d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 3b VR02:1b val_frame 2 2108 2108 ioc_adrbs 2 typ ; Flow J 0x2109 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2109 0x2109 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2109 2109 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 210a 210a fiu_mem_start 3 start-wr fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 210b 210b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 210c 210c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 210d ; -------------------------------------------------------------------------------------- 210d ; Comes from: 210d ; 2104 C False from color 0x2012 210d ; 2107 C False from color 0x2012 210d ; -------------------------------------------------------------------------------------- 210d 210d val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 210e 210e ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 210f 210f fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 2110 2110 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 2111 2111 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2112 2112 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2113 2113 fiu_load_tar 1 hold_tar; Flow J 0x2217 fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2217 0x2217 typ_b_adr 01 GP01 2114 ; -------------------------------------------------------------------------------------- 2114 ; 0x035e Declare_Type Array,Defined,Visible 2114 ; Comes from: 2114 ; 209f C from color 0x209f 2114 ; -------------------------------------------------------------------------------------- 2114 MACRO_Declare_Type_Array,Defined,Visible: 2114 2114 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2114 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2115 2115 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 2116 2116 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a8 seq_br_type f Unconditional Case Call seq_branch_adr 20a8 0x20a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2117 2117 ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cf seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cf 0x20cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2118 2118 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2119 2119 <halt> ; Flow R 211a ; -------------------------------------------------------------------------------------- 211a ; 0x0350 Declare_Type Array,Defined,Bounds_With_Object 211a ; Comes from: 211a ; 20a2 C from color 0x20a2 211a ; -------------------------------------------------------------------------------------- 211a MACRO_Declare_Type_Array,Defined,Bounds_With_Object: 211a 211a dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 211a fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 211b 211b seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a8 seq_br_type f Unconditional Case Call seq_branch_adr 20a8 0x20a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 211c 211c ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cf seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cf 0x20cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 211d 211d seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 211e ; -------------------------------------------------------------------------------------- 211e ; 0x0351 Declare_Type Array,Defined,Visible,Bounds_With_Object 211e ; Comes from: 211e ; 20a7 C from color 0x20a7 211e ; -------------------------------------------------------------------------------------- 211e MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object: 211e 211e dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 211e seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 211f 211f fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2120 2120 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a8 seq_br_type f Unconditional Case Call seq_branch_adr 20a8 0x20a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2121 2121 ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cf seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cf 0x20cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2122 2122 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2123 2123 <halt> ; Flow R 2124 ; -------------------------------------------------------------------------------------- 2124 ; 0x035b Declare_Type Array,Constrained 2124 ; -------------------------------------------------------------------------------------- 2124 MACRO_Declare_Type_Array,Constrained: 2124 2124 dispatch_brk_class 4 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2124 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 2125 2125 fiu_mem_start 4 continue; Flow J cc=False 0x2146 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2146 0x2146 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2126 2126 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2127 2127 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2135 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2135 0x2135 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2128 2128 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2143 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2143 0x2143 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 24 TR07:04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2129 2129 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2132 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2132 0x2132 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 212a 212a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x213c fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 213c 0x213c seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 212b 212b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 212c 212c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1e TOP - 2 212d 212d ioc_load_wdr 0 ; Flow C cc=True 0x2134 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2134 0x2134 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 212e 212e fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 212f 0x212f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 212f 212f fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 2130 2130 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 2131 2131 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2132 ; -------------------------------------------------------------------------------------- 2132 ; Comes from: 2132 ; 2129 C True from color MACRO_Declare_Type_Array,Constrained 2132 ; -------------------------------------------------------------------------------------- 2132 2132 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3272 seq_br_type 1 Branch True seq_branch_adr 3272 0x3272 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 05 ? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2133 2133 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2134 ; -------------------------------------------------------------------------------------- 2134 ; Comes from: 2134 ; 212d C True from color MACRO_Declare_Type_Array,Constrained 2134 ; -------------------------------------------------------------------------------------- 2134 2134 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3272 seq_br_type 9 Return False seq_branch_adr 3272 0x3272 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2135 ; -------------------------------------------------------------------------------------- 2135 ; Comes from: 2135 ; 2127 C True from color MACRO_Declare_Type_Array,Constrained 2135 ; -------------------------------------------------------------------------------------- 2135 2135 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2136 2136 fiu_mem_start 4 continue; Flow R cc=False ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2137 0x2137 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2137 2137 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2138 ; -------------------------------------------------------------------------------------- 2138 ; Comes from: 2138 ; 2148 C True from color MACRO_Declare_Type_Array,Constrained 2138 ; -------------------------------------------------------------------------------------- 2138 2138 <default> 2139 2139 fiu_mem_start 2 start-rd; Flow J 0x2136 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2136 0x2136 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 213a ; -------------------------------------------------------------------------------------- 213a ; Comes from: 213a ; 2177 C True from color MACRO_Declare_Type_Array,Constrained 213a ; -------------------------------------------------------------------------------------- 213a 213a ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 213b 0x213b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 213b 213b seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 213c ; -------------------------------------------------------------------------------------- 213c ; Comes from: 213c ; 212a C False from color MACRO_Declare_Type_Array,Constrained 213c ; -------------------------------------------------------------------------------------- 213c 213c fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 213d 213d ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 213e 213e seq_b_timing 1 Latch Condition; Flow C cc=False 0x2141 seq_br_type 4 Call False seq_branch_adr 2141 0x2141 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 213f 213f seq_br_type 4 Call False; Flow C cc=False 0x2142 seq_branch_adr 2142 0x2142 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2140 2140 fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 2141 ; -------------------------------------------------------------------------------------- 2141 ; Comes from: 2141 ; 213e C False from color 0x213a 2141 ; -------------------------------------------------------------------------------------- 2141 2141 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2142 0x2142 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 2142 ; -------------------------------------------------------------------------------------- 2142 ; Comes from: 2142 ; 213f C False from color 0x213a 2142 ; -------------------------------------------------------------------------------------- 2142 2142 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 2143 ; -------------------------------------------------------------------------------------- 2143 ; Comes from: 2143 ; 2128 C False from color MACRO_Declare_Type_Array,Constrained 2143 ; -------------------------------------------------------------------------------------- 2143 2143 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2144 2144 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2145 2145 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2146 2146 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2147 2147 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2177 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2177 0x2177 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2148 2148 fiu_mem_start 4 continue; Flow C cc=True 0x2138 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2138 0x2138 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2149 2149 fiu_mem_start 4 continue; Flow C cc=True 0x2161 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2161 0x2161 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 214a 214a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2164 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2164 0x2164 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2d TR07:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 214b 214b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3272 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 214c 214c seq_b_timing 1 Latch Condition; Flow C cc=False 0x2168 seq_br_type 4 Call False seq_branch_adr 2168 0x2168 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 214d 214d fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 214e 214e ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 214f 214f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 2150 2150 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2151 2151 val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2152 2152 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2153 2153 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x2170 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2170 0x2170 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2154 2154 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 2155 2155 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 2156 2156 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x2172 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2172 0x2172 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2157 2157 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2158 2158 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1c TOP - 4 2159 2159 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 215a 215a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x215d fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 215d 0x215d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 215b 215b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 215c 215c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 215d 215d fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 215e 215e ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 215f 215f typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2160 2160 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2161 ; -------------------------------------------------------------------------------------- 2161 ; Comes from: 2161 ; 2149 C True from color MACRO_Declare_Type_Array,Constrained 2161 ; -------------------------------------------------------------------------------------- 2161 2161 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2162 2162 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2163 2163 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2164 2164 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2165 2165 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2166 2166 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2167 2167 seq_br_type 3 Unconditional Branch; Flow J 0x214d seq_branch_adr 214d 0x214d val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2168 ; -------------------------------------------------------------------------------------- 2168 ; Comes from: 2168 ; 214c C False from color MACRO_Declare_Type_Array,Constrained 2168 ; -------------------------------------------------------------------------------------- 2168 2168 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2169 2169 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 216a 216a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 216b 216b seq_b_timing 1 Latch Condition; Flow C cc=False 0x216e seq_br_type 4 Call False seq_branch_adr 216e 0x216e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 216c 216c seq_br_type 4 Call False; Flow C cc=False 0x216f seq_branch_adr 216f 0x216f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 216d 216d seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 216e ; -------------------------------------------------------------------------------------- 216e ; Comes from: 216e ; 216b C False from color 0x2168 216e ; -------------------------------------------------------------------------------------- 216e 216e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 216f 0x216f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 216f ; -------------------------------------------------------------------------------------- 216f ; Comes from: 216f ; 216c C False from color 0x2168 216f ; -------------------------------------------------------------------------------------- 216f 216f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 2170 ; -------------------------------------------------------------------------------------- 2170 ; Comes from: 2170 ; 2153 C False from color MACRO_Declare_Type_Array,Constrained 2170 ; -------------------------------------------------------------------------------------- 2170 2170 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2171 2171 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1d TOP - 3 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2172 ; -------------------------------------------------------------------------------------- 2172 ; Comes from: 2172 ; 2156 C False from color MACRO_Declare_Type_Array,Constrained 2172 ; -------------------------------------------------------------------------------------- 2172 2172 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2173 2173 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2174 2174 seq_br_type 4 Call False; Flow C cc=False 0x2176 seq_branch_adr 2176 0x2176 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2175 2175 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 2176 ; -------------------------------------------------------------------------------------- 2176 ; Comes from: 2176 ; 2174 C False from color 0x2172 2176 ; -------------------------------------------------------------------------------------- 2176 2176 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2177 2177 ioc_fiubs 0 fiu ; Flow C cc=True 0x213a seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 213a 0x213a typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 2178 2178 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 33 TR02:13 typ_alu_func 1a PASS_B typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2179 2179 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1 A_PLUS_B typ_b_adr 33 TR02:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 217a 217a typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 217b 217b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 217c 217c typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 32 TR08:12 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 217d 217d fiu_load_tar 1 hold_tar; Flow J cc=True 0x2187 fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2187 0x2187 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 217e 217e fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 217f 217f val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 2180 2180 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 2181 2181 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2182 2182 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 2183 2183 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2184 2184 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2185 2185 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2186 2186 fiu_load_tar 1 hold_tar; Flow J 0x2187 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2187 0x2187 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2187 2187 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x219f fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 219f 0x219f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 2188 2188 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2189 2189 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 218a 218a ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 218b 218b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 218c 218c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x218f seq_br_type 0 Branch False seq_branch_adr 218f 0x218f seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 218d 218d seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 218e 218e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 218f 218f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 2190 2190 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x219e fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 219e 0x219e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2191 2191 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3272 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3272 0x3272 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2192 2192 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 2193 2193 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 2194 2194 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 2195 2195 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 2196 2196 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2197 2197 ioc_fiubs 2 typ ; Flow J cc=True 0x2187 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2187 0x2187 seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2198 2198 seq_br_type 0 Branch False; Flow J cc=False 0x219d seq_branch_adr 219d 0x219d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2199 2199 seq_br_type 0 Branch False; Flow J cc=False 0x219d seq_branch_adr 219d 0x219d seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 219a 219a seq_br_type 0 Branch False; Flow J cc=False 0x219d seq_branch_adr 219d 0x219d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 219b 219b seq_br_type 0 Branch False; Flow J cc=False 0x219d seq_branch_adr 219d 0x219d seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 219c 219c seq_br_type 1 Branch True; Flow J cc=True 0x2187 seq_branch_adr 2187 0x2187 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 219d 219d ioc_fiubs 2 typ ; Flow J 0x2187 seq_br_type 3 Unconditional Branch seq_branch_adr 2187 0x2187 typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 219e 219e seq_br_type 3 Unconditional Branch; Flow J 0x2193 seq_branch_adr 2193 0x2193 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 219f 219f fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 21a0 21a0 ioc_load_wdr 0 ; Flow C cc=False 0x21a6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 21a6 0x21a6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 0f GP0f 21a1 21a1 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 2 val_a_adr 05 GP05 val_alu_func 0 PASS_A 21a2 21a2 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 21a3 21a3 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 21a4 21a4 ioc_load_wdr 0 val_b_adr 39 VR02:19 val_frame 2 21a5 21a5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 21a6 ; -------------------------------------------------------------------------------------- 21a6 ; Comes from: 21a6 ; 21a0 C False from color MACRO_Declare_Type_Array,Constrained 21a6 ; -------------------------------------------------------------------------------------- 21a6 21a6 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 21a7 21a7 ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 21a8 21a8 val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU 21a9 21a9 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 21aa 21aa ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 21ab 21ab ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 21ac 21ac seq_br_type 3 Unconditional Branch; Flow J 0x2217 seq_branch_adr 2217 0x2217 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 21ad 21ad <halt> ; Flow R 21ae ; -------------------------------------------------------------------------------------- 21ae ; 0x034e Declare_Type Array,Constrained,Bounds_With_Object 21ae ; -------------------------------------------------------------------------------------- 21ae MACRO_Declare_Type_Array,Constrained,Bounds_With_Object: 21ae 21ae dispatch_brk_class 4 ; Flow J 0x2125 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21af 21af <halt> ; Flow R 21b0 ; -------------------------------------------------------------------------------------- 21b0 ; 0x035c Declare_Type Array,Constrained,Visible 21b0 ; -------------------------------------------------------------------------------------- 21b0 MACRO_Declare_Type_Array,Constrained,Visible: 21b0 21b0 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b0 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b1 21b1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2125 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21b2 ; -------------------------------------------------------------------------------------- 21b2 ; 0x034f Declare_Type Array,Constrained,Visible,Bounds_With_Object 21b2 ; -------------------------------------------------------------------------------------- 21b2 MACRO_Declare_Type_Array,Constrained,Visible,Bounds_With_Object: 21b2 21b2 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b2 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b3 21b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2125 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21b4 ; -------------------------------------------------------------------------------------- 21b4 ; 0x0353 Declare_Type Array,Constrained_Incomplete 21b4 ; -------------------------------------------------------------------------------------- 21b4 MACRO_Declare_Type_Array,Constrained_Incomplete: 21b4 21b4 dispatch_brk_class 4 ; Flow J 0x2125 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 21b5 21b5 <halt> ; Flow R 21b6 ; -------------------------------------------------------------------------------------- 21b6 ; 0x0346 Declare_Type Array,Constrained_Incomplete,Bounds_With_Object 21b6 ; -------------------------------------------------------------------------------------- 21b6 MACRO_Declare_Type_Array,Constrained_Incomplete,Bounds_With_Object: 21b6 21b6 dispatch_brk_class 4 ; Flow J 0x2125 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21b7 21b7 <halt> ; Flow R 21b8 ; -------------------------------------------------------------------------------------- 21b8 ; 0x0354 Declare_Type Array,Constrained_Incomplete,Visible 21b8 ; -------------------------------------------------------------------------------------- 21b8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible: 21b8 21b8 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b8 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b9 21b9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2125 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21ba ; -------------------------------------------------------------------------------------- 21ba ; 0x0347 Declare_Type Array,Constrained_Incomplete,Visible,Bounds_With_Object 21ba ; -------------------------------------------------------------------------------------- 21ba MACRO_Declare_Type_Array,Constrained_Incomplete,Visible,Bounds_With_Object: 21ba 21ba dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21ba seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21bb 21bb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2125 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2125 0x2125 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21bc ; -------------------------------------------------------------------------------------- 21bc ; 0x03a3 Complete_Type Heap_Access,By_Defining 21bc ; -------------------------------------------------------------------------------------- 21bc MACRO_Complete_Type_Heap_Access,By_Defining: 21bc 21bc dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 21bc fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21bd 21bd ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21be 21be fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 21bf 21bf fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21c0 21c0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2214 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2214 0x2214 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 21c1 21c1 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21c2 21c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c 21c3 21c3 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 26 TR06:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 21c4 21c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x21c9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 21c9 0x21c9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_frame c 21c5 21c5 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 21c6 21c6 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 21c7 21c7 ioc_load_wdr 0 typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 21c8 21c8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21c9 ; -------------------------------------------------------------------------------------- 21c9 ; Comes from: 21c9 ; 21c4 C #0x0 from color 0x2005 21c9 ; -------------------------------------------------------------------------------------- 21c9 21c9 fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cf ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cf 0x21cf typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21ca 21ca fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cf ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cf 0x21cf typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21cb 21cb fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cf ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cf 0x21cf typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21cc 21cc seq_br_type 3 Unconditional Branch; Flow J 0x21cd seq_branch_adr 21cd 0x21cd typ_c_adr 3b GP04 21cd 21cd seq_br_type 4 Call False; Flow C cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 21ce 21ce fiu_mem_start 8 start_wr_if_false; Flow R cc=False ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cf 0x21cf typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21cf 21cf typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 21d0 21d0 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21d1 21d1 <halt> ; Flow R 21d2 ; -------------------------------------------------------------------------------------- 21d2 ; 0x03a2 Complete_Type Heap_Access,By_Renaming 21d2 ; -------------------------------------------------------------------------------------- 21d2 MACRO_Complete_Type_Heap_Access,By_Renaming: 21d2 21d2 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 21d2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21d3 21d3 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21d4 21d4 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 21d5 21d5 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21d6 21d6 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x2214 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2214 0x2214 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 21d7 21d7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 2b VR06:0b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 21d8 21d8 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 21d9 21d9 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 21da 21da fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 21db 21db fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 21dc 21dc fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 21dd 21dd fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 21de 21de fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 21df 21df ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 21e0 21e0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21e1 21e1 <halt> ; Flow R 21e2 ; -------------------------------------------------------------------------------------- 21e2 ; 0x03a1 Complete_Type Heap_Access,By_Constraining 21e2 ; -------------------------------------------------------------------------------------- 21e2 MACRO_Complete_Type_Heap_Access,By_Constraining: 21e2 21e2 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 21e2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21e3 21e3 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21e4 21e4 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 21e5 21e5 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21e6 21e6 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2214 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2214 0x2214 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 21e7 21e7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21e8 21e8 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 21e9 21e9 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 21ea 21ea fiu_load_tar 1 hold_tar; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 21eb 21eb ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 21ec 21ec fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 21ed 21ed ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x21f3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 21f3 0x21f3 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21ee 21ee fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 21ef 21ef fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 21f0 21f0 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 21f1 21f1 ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 21f2 21f2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21f3 ; -------------------------------------------------------------------------------------- 21f3 ; Comes from: 21f3 ; 21ed C #0x0 from color 0x2005 21f3 ; -------------------------------------------------------------------------------------- 21f3 21f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f4 21f4 fiu_mem_start 2 start-rd; Flow J 0x21fb ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 21fb 0x21fb typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 21f5 21f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f6 21f6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f7 21f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f8 21f8 seq_br_type 3 Unconditional Branch; Flow J 0x2200 seq_branch_adr 2200 0x2200 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 21f9 21f9 seq_br_type 3 Unconditional Branch; Flow J 0x2200 seq_branch_adr 2200 0x2200 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 21fa 21fa fiu_mem_start 2 start-rd; Flow J 0x2208 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2208 0x2208 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 21fb 21fb <default> 21fc 21fc fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 21fd 21fd <default> 21fe 21fe ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 21ff 21ff fiu_mem_start 2 start-rd; Flow J 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3244 0x3244 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2200 2200 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 2201 2201 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2202 0x2202 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 05 GP05 2202 2202 fiu_mem_start 2 start-rd; Flow C 0x3244 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3244 0x3244 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2203 2203 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2204 2204 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2205 2205 seq_br_type 7 Unconditional Call; Flow C 0x2262 seq_branch_adr 2262 0x2262 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2206 2206 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2207 0x2207 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 2207 2207 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 2208 2208 <default> 2209 2209 fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x2200 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2200 0x2200 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 220a ; -------------------------------------------------------------------------------------- 220a ; 0x03a0 Complete_Type Heap_Access,By_Component_Completion 220a ; -------------------------------------------------------------------------------------- 220a MACRO_Complete_Type_Heap_Access,By_Component_Completion: 220a 220a dispatch_brk_class 4 ; Flow C cc=True 0x32ab dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 220a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 220b 220b fiu_mem_start 4 continue typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 220c 220c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 220d 220d fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 220e 220e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 220f 220f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x2210 seq_br_type f Unconditional Case Call seq_branch_adr 2210 0x2210 seq_en_micro 0 2210 ; -------------------------------------------------------------------------------------- 2210 ; Comes from: 2210 ; 220f C #0x0 from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 2210 ; -------------------------------------------------------------------------------------- 2210 2210 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2211 2211 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2212 2212 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2213 2213 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2214 2214 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2215 2215 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ab seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 2216 2216 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2217 2217 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2218 2218 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 2219 2219 fiu_mem_start 4 continue typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 221a 221a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2224 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2224 0x2224 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 221b 221b fiu_load_var 1 hold_var; Flow J cc=True 0x221d fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 221d 0x221d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 221c 221c ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 221d 221d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 221e 221e fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 37 VR06:17 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 6 221f 221f ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2220 2220 fiu_load_var 1 hold_var; Flow J cc=True 0x2222 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2222 0x2222 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2221 2221 ioc_fiubs 0 fiu val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2222 2222 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2223 2223 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x2217 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2217 0x2217 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 08 GP08 2224 2224 fiu_load_var 1 hold_var; Flow J cc=True 0x2226 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2226 0x2226 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2225 2225 ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2226 2226 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2227 2227 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 08 GP08 val_b_adr 37 VR06:17 val_frame 6 2228 ; -------------------------------------------------------------------------------------- 2228 ; Comes from: 2228 ; 10f7 C from color 0x10d7 2228 ; 11cf C from color 0x111d 2228 ; 1235 C from color 0x1201 2228 ; 123e C from color 0x1201 2228 ; -------------------------------------------------------------------------------------- 2228 2228 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2229 2229 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 222a 222a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 222b 222b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a84 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 36 GP09 val_c_source 0 FIU_BUS 222c 222c fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 222d 222d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 222e 222e fiu_fill_mode_src 0 ; Flow J cc=False 0x223d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 223d 0x223d seq_cond_sel 65 CROSS_WORD_FIELD~ 222f 222f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2230 2230 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 2231 2231 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 2232 2232 fiu_fill_mode_src 0 ; Flow J cc=False 0x223f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 223f 0x223f seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2233 2233 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2234 2234 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2235 2235 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2236 2236 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x222a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 222a 0x222a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 2237 2237 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2238 2238 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 2239 2239 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223a 223a fiu_fill_mode_src 0 ; Flow J cc=False 0x2241 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2241 0x2241 seq_cond_sel 65 CROSS_WORD_FIELD~ 223b 223b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223c 223c ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 223d 223d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223e 223e fiu_fill_mode_src 0 ; Flow J 0x2230 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2230 0x2230 typ_mar_cntl 6 INCREMENT_MAR 223f 223f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2240 2240 fiu_fill_mode_src 0 ; Flow J 0x2234 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2234 0x2234 typ_mar_cntl 6 INCREMENT_MAR 2241 2241 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2242 2242 fiu_fill_mode_src 0 ; Flow J 0x223c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 223c 0x223c typ_mar_cntl 6 INCREMENT_MAR 2243 2243 ioc_load_wdr 0 ; Flow C cc=True 0x2a84 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2244 2244 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2245 2245 fiu_fill_mode_src 0 ; Flow J cc=False 0x2253 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2253 0x2253 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2246 2246 fiu_fill_mode_src 0 ; Flow J cc=True 0x223c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 223c 0x223c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 2247 2247 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2248 ; -------------------------------------------------------------------------------------- 2248 ; Comes from: 2248 ; 10fa C True from color 0x10d7 2248 ; 11d4 C from color 0x111d 2248 ; 123f C from color 0x1201 2248 ; -------------------------------------------------------------------------------------- 2248 2248 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2249 2249 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 10 224a 224a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 6 224b 224b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 6 224c 224c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 224d 224d fiu_fill_mode_src 0 ; Flow J cc=False 0x2250 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2250 0x2250 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 08 GP08 224e 224e fiu_fill_mode_src 0 ; Flow J cc=False 0x2243 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2243 0x2243 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 224f 224f ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2250 2250 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2251 2251 fiu_fill_mode_src 0 ; Flow J cc=False 0x2243 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2243 0x2243 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2252 2252 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2253 2253 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2254 2254 fiu_fill_mode_src 0 ; Flow J cc=False 0x2247 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2247 0x2247 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2255 2255 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2256 ; -------------------------------------------------------------------------------------- 2256 ; Comes from: 2256 ; 10f3 C from color 0x10d7 2256 ; 11bb C from color 0x111d 2256 ; 1bdd C from color 0x0000 2256 ; 1be5 C from color 0x0000 2256 ; 1e51 C from color 0x0000 2256 ; 1e53 C from color 0x0000 2256 ; 1e5b C from color 0x0000 2256 ; 1e66 C from color 0x0000 2256 ; -------------------------------------------------------------------------------------- 2256 2256 val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2257 2257 fiu_mem_start 2 start-rd; Flow J cc=False 0x225a ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 225a 0x225a seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2258 2258 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 2259 2259 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 225a 225a seq_b_timing 0 Early Condition; Flow J cc=True 0x225d seq_br_type 1 Branch True seq_branch_adr 225d 0x225d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 225b 225b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2257 seq_br_type 1 Branch True seq_branch_adr 2257 0x2257 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 225c 225c seq_br_type a Unconditional Return; Flow R val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 225d 225d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x225c seq_br_type 8 Return True seq_branch_adr 225c 0x225c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 225e ; -------------------------------------------------------------------------------------- 225e ; Comes from: 225e ; 1be3 C from color 0x0000 225e ; 1e59 C from color 0x0000 225e ; 1e68 C from color 0x0000 225e ; 1e7d C from color 0x0000 225e ; 1e7f C from color 0x0000 225e ; -------------------------------------------------------------------------------------- 225e 225e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 225f 225f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22c3 0x22c3 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 2260 2260 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x225c seq_br_type 1 Branch True seq_branch_adr 225c 0x225c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2261 2261 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x225e seq_br_type 8 Return True seq_branch_adr 225e 0x225e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2262 ; -------------------------------------------------------------------------------------- 2262 ; Comes from: 2262 ; 0506 C from color 0x04fa 2262 ; 11c8 C from color 0x111d 2262 ; 1230 C from color 0x1201 2262 ; 1baf C from color 0x0a78 2262 ; 1bbd C from color 0x0a8c 2262 ; 1bcd C from color 0x0aa0 2262 ; 1bf1 C from color 0x0000 2262 ; 1f78 C from color 0x1f6b 2262 ; 2205 C from color 0x21f8 2262 ; -------------------------------------------------------------------------------------- 2262 2262 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2263 0x2263 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2263 2263 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2264 2264 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22a8 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a8 0x22a8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2265 2265 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2266 2266 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x226b seq_br_type 0 Branch False seq_branch_adr 226b 0x226b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2267 2267 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x226c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 226c 0x226c seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2268 2268 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2269 2269 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 226a 226a seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x2262 seq_br_type 8 Return True seq_branch_adr 2262 0x2262 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 226b 226b ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 226c 0x226c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 226c 226c seq_br_type 3 Unconditional Branch; Flow J 0x2262 seq_branch_adr 2262 0x2262 typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 226d ; -------------------------------------------------------------------------------------- 226d ; Comes from: 226d ; 11be C from color 0x111d 226d ; 1bb1 C from color 0x0a78 226d ; 1bbf C from color 0x0a8c 226d ; 1bd0 C from color 0x0aa0 226d ; 1bf5 C from color 0x0000 226d ; -------------------------------------------------------------------------------------- 226d 226d fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 226e 0x226e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 226e 226e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 226f 226f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22a2 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22a2 0x22a2 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2270 2270 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2274 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 2274 0x2274 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 08 GP08 2271 2271 ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2272 2272 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2275 seq_br_type 1 Branch True seq_branch_adr 2275 0x2275 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2273 2273 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x226d seq_br_type 8 Return True seq_branch_adr 226d 0x226d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 2274 2274 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2275 0x2275 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2275 2275 seq_br_type 3 Unconditional Branch; Flow J 0x226d seq_branch_adr 226d 0x226d typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2276 ; -------------------------------------------------------------------------------------- 2276 ; Comes from: 2276 ; 227e C from color 0x227e 2276 ; 2280 C from color 0x2280 2276 ; -------------------------------------------------------------------------------------- 2276 2276 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2277 2277 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2278 2278 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 31 VR02:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 2279 2279 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 227a 227a fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 227b 227b seq_b_timing 1 Latch Condition; Flow J cc=True 0x227d seq_br_type 1 Branch True seq_branch_adr 227d 0x227d 227c 227c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 227d 227d fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 227e ; -------------------------------------------------------------------------------------- 227e ; Comes from: 227e ; 2294 C from color 0x228c 227e ; 22a0 C from color 0x2296 227e ; -------------------------------------------------------------------------------------- 227e 227e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2276 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2276 0x2276 typ_b_adr 06 GP06 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 227f 227f ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 2280 ; -------------------------------------------------------------------------------------- 2280 ; Comes from: 2280 ; 229f C from color 0x2296 2280 ; -------------------------------------------------------------------------------------- 2280 2280 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2276 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2276 0x2276 typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 2281 2281 ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2282 ; -------------------------------------------------------------------------------------- 2282 ; Comes from: 2282 ; 2293 C from color 0x228c 2282 ; -------------------------------------------------------------------------------------- 2282 2282 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 2283 2283 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2284 2284 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2285 2285 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 2286 2286 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2287 2287 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2288 2288 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x228a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 228a 0x228a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2289 2289 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 228a 228a fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 228b 228b fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 228c ; -------------------------------------------------------------------------------------- 228c ; Comes from: 228c ; 1194 C from color 0x111d 228c ; 1bac C from color 0x0a78 228c ; 1bba C from color 0x0a8c 228c ; 1bc9 C from color 0x0aa0 228c ; 1c46 C from color 0x0000 228c ; -------------------------------------------------------------------------------------- 228c 228c ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 228d 228d fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 228e 0x228e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 228e 228e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 228f 228f fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2290 2290 fiu_load_oreg 1 hold_oreg; Flow C 0x22a2 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22a2 0x22a2 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2291 2291 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2292 0x2292 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 2292 2292 seq_br_type 1 Branch True; Flow J cc=True 0x228d seq_branch_adr 228d 0x228d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2293 2293 ioc_fiubs 2 typ ; Flow C 0x2282 seq_br_type 7 Unconditional Call seq_branch_adr 2282 0x2282 typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2294 2294 ioc_fiubs 2 typ ; Flow C 0x227e seq_br_type 7 Unconditional Call seq_branch_adr 227e 0x227e typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2295 2295 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x228d seq_branch_adr 228d 0x228d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 2296 ; -------------------------------------------------------------------------------------- 2296 ; Comes from: 2296 ; 11b8 C from color 0x111d 2296 ; 1baa C from color 0x0a78 2296 ; 1bb8 C from color 0x0a8c 2296 ; 1bc6 C from color 0x0aa0 2296 ; 1c41 C from color 0x0000 2296 ; -------------------------------------------------------------------------------------- 2296 2296 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 2297 2297 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2298 0x2298 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2298 2298 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2299 2299 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 229a 229a fiu_mem_start 2 start-rd; Flow C cc=True 0x22a8 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a8 0x22a8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 229b 229b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 229c 229c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 229d 229d seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 229e 0x229e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 229e 229e seq_br_type 1 Branch True; Flow J cc=True 0x2297 seq_branch_adr 2297 0x2297 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 229f 229f ioc_fiubs 2 typ ; Flow C 0x2280 seq_br_type 7 Unconditional Call seq_branch_adr 2280 0x2280 typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a0 22a0 ioc_fiubs 2 typ ; Flow C 0x227e seq_br_type 7 Unconditional Call seq_branch_adr 227e 0x227e typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a1 22a1 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x2297 seq_branch_adr 2297 0x2297 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22a2 ; -------------------------------------------------------------------------------------- 22a2 ; Comes from: 22a2 ; 226f C from color 0x226d 22a2 ; 2290 C from color 0x228c 22a2 ; -------------------------------------------------------------------------------------- 22a2 22a2 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22a5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22a5 0x22a5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22a3 22a3 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a4 22a4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22a5 22a5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22a6 22a6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a7 22a7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22a8 ; -------------------------------------------------------------------------------------- 22a8 ; Comes from: 22a8 ; 2264 C True from color 0x2262 22a8 ; 229a C True from color 0x2296 22a8 ; 22b0 C True from color 0x09a8 22a8 ; -------------------------------------------------------------------------------------- 22a8 22a8 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 22a9 22a9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 22aa ; -------------------------------------------------------------------------------------- 22aa ; Comes from: 22aa ; 1be1 C from color 0x0000 22aa ; 1e57 C from color 0x0000 22aa ; -------------------------------------------------------------------------------------- 22aa 22aa fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22ab 0x22ab seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22ab 22ab seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22ac 22ac fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c3 0x22c3 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22ad 22ad seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22aa seq_branch_adr 22aa 0x22aa seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22ae ; -------------------------------------------------------------------------------------- 22ae ; Comes from: 22ae ; 1bdb C from color 0x0000 22ae ; 1e4f C from color 0x0000 22ae ; -------------------------------------------------------------------------------------- 22ae 22ae fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22af 0x22af seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22af 22af seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22b0 22b0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22a8 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a8 0x22a8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22b1 22b1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22b2 22b2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22b3 22b3 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ae seq_branch_adr 22ae 0x22ae seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22b4 ; -------------------------------------------------------------------------------------- 22b4 ; Comes from: 22b4 ; 1e64 C from color 0x0000 22b4 ; -------------------------------------------------------------------------------------- 22b4 22b4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22b5 0x22b5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22b5 22b5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22ba seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22ba 0x22ba seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22b6 22b6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22b7 22b7 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22b8 22b8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a84 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22b9 22b9 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22b4 seq_branch_adr 22b4 0x22b4 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22ba 22ba fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22bb 22bb fiu_fill_mode_src 0 ; Flow J 0x22b7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 22b7 0x22b7 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22bc ; -------------------------------------------------------------------------------------- 22bc ; Comes from: 22bc ; 1e6a C from color 0x0000 22bc ; -------------------------------------------------------------------------------------- 22bc 22bc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22bd 0x22bd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22bd 22bd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22c0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22c0 0x22c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22be 22be fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c3 0x22c3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22bf 22bf seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22bc seq_branch_adr 22bc 0x22bc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22c0 22c0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22c1 22c1 fiu_fill_mode_src 0 ; Flow C 0x22c3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c3 0x22c3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22c2 22c2 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22bc seq_branch_adr 22bc 0x22bc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22c3 ; -------------------------------------------------------------------------------------- 22c3 ; Comes from: 22c3 ; 225f C from color 0x1b7e 22c3 ; 22ac C from color 0x09a8 22c3 ; 22be C from color 0x09a8 22c3 ; 22c1 C from color 0x09a8 22c3 ; -------------------------------------------------------------------------------------- 22c3 22c3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22c5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22c5 0x22c5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22c4 22c4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22c5 22c5 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22c6 22c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22c7 22c7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 val_rand a PASS_B_HIGH 22c8 22c8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3d VR06:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 22c9 22c9 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x22ed fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ed 0x22ed seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22ca 22ca fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=#0x0 0x22cd fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 22cd 0x22cd seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22cb 22cb fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 22cc 22cc ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 22cd ; -------------------------------------------------------------------------------------- 22cd ; Comes from: 22cd ; 22ca C #0x0 from color 0x0000 22cd ; -------------------------------------------------------------------------------------- 22cd 22cd seq_br_type 3 Unconditional Branch; Flow J 0x3402 seq_branch_adr 3402 0x3402 seq_en_micro 0 seq_random 05 ? typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 22ce 22ce seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 22cf 22cf seq_br_type 3 Unconditional Branch; Flow J 0x22d1 seq_branch_adr 22d1 0x22d1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 22d0 22d0 seq_br_type 3 Unconditional Branch; Flow J 0x22d1 seq_branch_adr 22d1 0x22d1 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 22d1 22d1 seq_br_type 0 Branch False; Flow J cc=False 0x22ef seq_branch_adr 22ef 0x22ef seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22d2 22d2 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 22d3 22d3 ioc_tvbs 2 fiu+val; Flow C cc=True 0x22d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22d9 0x22d9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 22d4 22d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 22d5 0x22d5 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 0b GP0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 22d5 22d5 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 5 val_rand a PASS_B_HIGH 22d6 22d6 ioc_load_wdr 0 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 22d7 22d7 ioc_adrbs 2 typ ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 22d8 22d8 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 22d9 22d9 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x22d8 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 22d8 0x22d8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22da 22da ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 22db 22db seq_br_type 0 Branch False; Flow J cc=False 0x22ee seq_branch_adr 22ee 0x22ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22dc 22dc fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_a_adr 3a VR12:1a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 22dd 22dd fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 24 VR05:04 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 22de 22de ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x22e4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 22e4 0x22e4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 22df 22df fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x22ee fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ee 0x22ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR 22e0 22e0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22de fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 22de 0x22de seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 22e1 22e1 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ee fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 4c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ee 0x22ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22e2 22e2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 22e3 22e3 fiu_load_tar 1 hold_tar; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE 22e4 22e4 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ee fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ee 0x22ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 22e5 22e5 fiu_mem_start 3 start-wr ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 7 22e6 22e6 ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 7 22e7 22e7 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x22ec fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 22ec 0x22ec seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 0d GP0d val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22e8 22e8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 22e9 22e9 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ee fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ee 0x22ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 22ea 22ea ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0d GP0d 22eb 22eb ioc_adrbs 2 typ ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 22ec ; -------------------------------------------------------------------------------------- 22ec ; Comes from: 22ec ; 22e7 C True from color 0x0000 22ec ; -------------------------------------------------------------------------------------- 22ec 22ec seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1 22ed 22ed fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x22ef fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 22ef 0x22ef seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 22ee 22ee seq_br_type 3 Unconditional Branch; Flow J 0x22ef seq_branch_adr 22ef 0x22ef seq_en_micro 0 seq_random 06 Pop_stack+? 22ef 22ef fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 22f0 22f0 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x22c7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 22c7 0x22c7 typ_a_adr 05 GP05 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A 22f1 22f1 <halt> ; Flow R 22f2 ; -------------------------------------------------------------------------------------- 22f2 ; 0x0358 Declare_Type Array,Incomplete 22f2 ; -------------------------------------------------------------------------------------- 22f2 MACRO_Declare_Type_Array,Incomplete: 22f2 22f2 dispatch_brk_class 4 ; Flow J 0x22f3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 22f2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f3 0x22f3 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 22f3 22f3 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 22f4 22f4 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 22f5 22f5 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 22f6 22f6 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 22f7 22f7 fiu_mem_start 4 continue fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 22f8 22f8 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x22f9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 22f9 0x22f9 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 24 TR09:04 typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 22f9 22f9 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x22fd fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 22fd 0x22fd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 22fa 22fa fiu_mem_start 4 continue; Flow J cc=False 0x22f9 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 22f9 0x22f9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 22fb 22fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 22fc 22fc fiu_mem_start 3 start-wr; Flow J 0x22f9 seq_br_type 3 Unconditional Branch seq_branch_adr 22f9 0x22f9 22fd 22fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 22fe 22fe fiu_mem_start 3 start-wr val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 32 VR06:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 22ff 22ff fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 2300 2300 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2300 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2300 0x2300 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 37 VR06:17 val_frame 6 2301 2301 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR11:09 val_frame 11 2302 2302 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 2303 0x2303 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2303 2303 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2304 0x2304 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2304 2304 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2305 2305 <halt> ; Flow R 2306 ; -------------------------------------------------------------------------------------- 2306 ; 0x0359 Declare_Type Array,Incomplete,Visible 2306 ; -------------------------------------------------------------------------------------- 2306 MACRO_Declare_Type_Array,Incomplete,Visible: 2306 2306 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2306 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2307 2307 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x22f3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f3 0x22f3 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2308 ; -------------------------------------------------------------------------------------- 2308 ; 0x034b Declare_Type Array,Incomplete,Bounds_With_Object 2308 ; -------------------------------------------------------------------------------------- 2308 MACRO_Declare_Type_Array,Incomplete,Bounds_With_Object: 2308 2308 dispatch_brk_class 4 ; Flow J 0x22f3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2308 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f3 0x22f3 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2309 2309 <halt> ; Flow R 230a ; -------------------------------------------------------------------------------------- 230a ; 0x034c Declare_Type Array,Incomplete,Visible,Bounds_With_Object 230a ; -------------------------------------------------------------------------------------- 230a MACRO_Declare_Type_Array,Incomplete,Visible,Bounds_With_Object: 230a 230a dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 230a seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 230b 230b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x22f3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f3 0x22f3 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 230c ; -------------------------------------------------------------------------------------- 230c ; 0x0340 Complete_Type Array,By_Component_Completion 230c ; -------------------------------------------------------------------------------------- 230c MACRO_Complete_Type_Array,By_Component_Completion: 230c 230c dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 230c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 230d 230d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 230e 230e fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 230f 230f seq_b_timing 0 Early Condition; Flow J cc=True 0x2310 ; Flow J cc=#0x0 0x2310 seq_br_type b Case False seq_branch_adr 2310 0x2310 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 2310 2310 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2311 2311 fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x2314 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2314 0x2314 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2312 2312 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2313 2313 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2314 2314 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 2315 2315 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3279 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2316 2316 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 2d VR11:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 2317 2317 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2318 2318 seq_br_type 3 Unconditional Branch; Flow J 0x2319 seq_branch_adr 2319 0x2319 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 2319 2319 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 231a 231a ioc_load_wdr 0 231b 231b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 231c 231c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 231d 231d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 231e 231e seq_b_timing 1 Latch Condition; Flow J cc=True 0x2324 seq_br_type 1 Branch True seq_branch_adr 2324 0x2324 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 231f 231f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2320 2320 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2321 2321 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2323 seq_br_type 1 Branch True seq_branch_adr 2323 0x2323 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 2322 2322 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2324 seq_br_type 1 Branch True seq_branch_adr 2324 0x2324 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2323 2323 ioc_tvbs 1 typ+fiu; Flow J 0x2324 seq_br_type 3 Unconditional Branch seq_branch_adr 2324 0x2324 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2324 2324 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2328 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2328 0x2328 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2325 2325 <default> 2326 2326 ioc_tvbs c mem+mem+csa+dummy val_a_adr 2b VR06:0b val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2327 2327 seq_br_type 3 Unconditional Branch; Flow J 0x2319 seq_branch_adr 2319 0x2319 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2328 2328 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 3b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 01 GP01 2329 2329 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert 232a 232a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 232b 232b ioc_load_wdr 0 ; Flow J 0x2310 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2310 0x2310 val_b_adr 02 GP02 232c ; -------------------------------------------------------------------------------------- 232c ; 0x0342 Complete_Type Array,By_Renaming 232c ; -------------------------------------------------------------------------------------- 232c MACRO_Complete_Type_Array,By_Renaming: 232c 232c dispatch_brk_class 4 ; Flow C cc=True 0x32ab dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 232c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 232d 232d fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 232e 232e fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 232f 232f fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_rand 9 PASS_A_HIGH val_c_adr 39 GP06 val_c_source 0 FIU_BUS 2330 2330 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 2331 2331 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand e CHECK_CLASS_SYSTEM_B 2332 2332 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2333 2333 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2334 2334 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2335 2335 fiu_mem_start 4 continue; Flow C cc=True 0x3279 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 2336 2336 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 2337 2337 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2338 2338 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 2339 2339 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 233a 233a fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 233b 233b ioc_load_wdr 0 ; Flow J cc=True 0x2341 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2341 0x2341 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 233c 233c fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 233d 233d fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 233e 233e ioc_load_wdr 0 ; Flow J cc=False 0x2339 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2339 0x2339 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 05 GP05 typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 05 GP05 233f 233f seq_b_timing 1 Latch Condition; Flow C cc=True 0x2344 seq_br_type 5 Call True seq_branch_adr 2344 0x2344 typ_csa_cntl 3 POP_CSA 2340 2340 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2341 2341 fiu_mem_start 3 start-wr; Flow J cc=False 0x2343 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2343 0x2343 seq_cond_sel 64 OFFSET_REGISTER_???? seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2342 2342 fiu_load_oreg 1 hold_oreg; Flow J 0x233e fiu_mem_start 4 continue fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 233e 0x233e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2343 2343 fiu_mem_start 4 continue; Flow J 0x233e seq_br_type 3 Unconditional Branch seq_branch_adr 233e 0x233e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2344 ; -------------------------------------------------------------------------------------- 2344 ; Comes from: 2344 ; 233f C True from color MACRO_Complete_Type_Array,By_Renaming 2344 ; -------------------------------------------------------------------------------------- 2344 2344 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2345 2345 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2346 2346 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2347 2347 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x2344 seq_br_type 8 Return True seq_branch_adr 2344 0x2344 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2348 ; -------------------------------------------------------------------------------------- 2348 ; 0x0305 Complete_Type Variant_Record,By_Constraining_Incomplete 2348 ; -------------------------------------------------------------------------------------- 2348 MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete: 2348 2348 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2348 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH 2349 2349 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 234a 234a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 234b 234b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2f TR13:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 234c 234c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 234d 234d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR13:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 234e 234e fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 234f 234f fiu_mem_start 4 continue typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2350 2350 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 24 TR09:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 2351 2351 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2352 2352 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 39 VR13:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 2353 2353 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2354 2354 seq_b_timing 0 Early Condition; Flow J cc=True 0x2358 seq_br_type 1 Branch True seq_branch_adr 2358 0x2358 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2355 2355 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2357 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2357 0x2357 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 2356 2356 seq_br_type 3 Unconditional Branch; Flow J 0x2358 seq_branch_adr 2358 0x2358 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2357 2357 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32ad seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2358 2358 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER 2359 2359 seq_br_type 7 Unconditional Call; Flow C 0x2482 seq_branch_adr 2482 0x2482 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 235a 235a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 235b 235b fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 235c 235c ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 235d 235d typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 235e 235e fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 235f 235f fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x236e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 236e 0x236e typ_a_adr 14 ZEROS 2360 2360 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2361 2361 fiu_mem_start 4 continue typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2362 2362 ioc_load_wdr 0 ; Flow C 0x2371 seq_br_type 7 Unconditional Call seq_branch_adr 2371 0x2371 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2363 2363 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value 2364 2364 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2365 2365 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 2366 2366 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 2367 2367 ioc_fiubs 0 fiu ; Flow J 0x2368 seq_br_type 2 Push (branch address) seq_branch_adr 2369 0x2369 seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2368 2368 seq_br_type 3 Unconditional Branch; Flow J 0x2381 seq_branch_adr 2381 0x2381 seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2369 2369 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 236a 236a ioc_load_wdr 0 236b 236b ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 236c 236c seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 236d 236d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 236e ; -------------------------------------------------------------------------------------- 236e ; Comes from: 236e ; 235f C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 236e ; -------------------------------------------------------------------------------------- 236e 236e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 22 TR02:02 typ_frame 2 236f 236f fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2370 2370 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2371 ; -------------------------------------------------------------------------------------- 2371 ; Comes from: 2371 ; 2362 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2371 ; -------------------------------------------------------------------------------------- 2371 2371 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2372 0x2372 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2372 2372 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2373 2373 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2374 2374 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 2375 2375 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x23ef ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23ef 0x23ef seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2376 2376 <default> 2377 2377 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2378 2378 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2379 2379 seq_b_timing 1 Latch Condition; Flow J cc=True 0x237c seq_br_type 1 Branch True seq_branch_adr 237c 0x237c seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 237a 237a fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 237b 237b ioc_load_wdr 0 ; Flow J 0x2371 seq_br_type 3 Unconditional Branch seq_branch_adr 2371 0x2371 typ_b_adr 2b TR08:0b typ_frame 8 val_b_adr 05 GP05 237c 237c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 237d 237d <default> 237e 237e fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 237f 237f ioc_load_wdr 0 ; Flow J 0x2371 seq_br_type 3 Unconditional Branch seq_branch_adr 2371 0x2371 seq_en_micro 0 typ_b_adr 06 GP06 val_b_adr 0f GP0f 2380 2380 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2381 2381 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2382 0x2382 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2382 2382 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2383 2383 fiu_mem_start 3 start-wr; Flow J 0x2380 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2380 0x2380 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2384 2384 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2385 2385 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2386 0x2386 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2386 2386 seq_br_type 2 Push (branch address); Flow J 0x2387 seq_branch_adr 2384 0x2384 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 2387 2387 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238c fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238c 0x238c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2388 2388 seq_br_type 7 Unconditional Call; Flow C 0x2390 seq_branch_adr 2390 0x2390 2389 2389 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 238a 238a seq_br_type 3 Unconditional Branch; Flow J 0x2381 seq_branch_adr 2381 0x2381 238b 238b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 238c 238c fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x238e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 238e 0x238e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 238d 238d ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x238b seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 238b 0x238b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 238e ; -------------------------------------------------------------------------------------- 238e ; Comes from: 238e ; 238c C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238e ; -------------------------------------------------------------------------------------- 238e 238e seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 238f 238f fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 2390 ; -------------------------------------------------------------------------------------- 2390 ; Comes from: 2390 ; 2388 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2390 ; 23bb C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2390 ; 23df C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2390 ; 23ea C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2390 ; -------------------------------------------------------------------------------------- 2390 2390 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 2391 2391 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var 2392 2392 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2393 2393 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2394 2394 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2395 0x2395 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2395 2395 seq_br_type 2 Push (branch address); Flow J 0x2396 seq_branch_adr 2393 0x2393 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2396 2396 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2397 2397 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2398 0x2398 2398 2398 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_frame 4 2399 2399 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 239a 239a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 239b 239b fiu_mem_start 2 start-rd; Flow J cc=True 0x23af ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 23af 0x23af typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 239c 239c typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 239d 239d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 239e 239e fiu_load_tar 1 hold_tar; Flow C 0x323f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 239f 239f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 23a0 23a0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23a1 23a1 ioc_load_wdr 0 ; Flow C cc=True 0x32ad ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 23a2 23a2 fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 23a3 23a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x23a7 seq_br_type 1 Branch True seq_branch_adr 23a7 0x23a7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 23a4 23a4 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 23a5 23a5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 23a6 23a6 fiu_load_var 1 hold_var; Flow J 0x23b3 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 23b3 0x23b3 seq_en_micro 0 val_a_adr 0f GP0f 23a7 23a7 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x23ad ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23ad 0x23ad seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 23a8 23a8 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 23a9 23a9 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23ac seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 23ac 0x23ac seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 23aa 23aa ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23a7 seq_br_type 1 Branch True seq_branch_adr 23a7 0x23a7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 23ab 23ab seq_br_type 3 Unconditional Branch; Flow J 0x23a4 seq_branch_adr 23a4 0x23a4 seq_en_micro 0 23ac 23ac fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x23b3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 23b3 0x23b3 seq_en_micro 0 23ad ; -------------------------------------------------------------------------------------- 23ad ; Comes from: 23ad ; 23a7 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23ad ; -------------------------------------------------------------------------------------- 23ad 23ad seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 23ae 23ae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 23af 23af fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 23b0 23b0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 23b1 23b1 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 23b2 23b2 fiu_load_tar 1 hold_tar; Flow C 0x323f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23b3 23b3 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 23b4 23b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x23b7 seq_br_type 5 Call True seq_branch_adr 23b7 0x23b7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 23b5 23b5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 23b6 23b6 seq_br_type a Unconditional Return; Flow R 23b7 ; -------------------------------------------------------------------------------------- 23b7 ; Comes from: 23b7 ; 23b4 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23b7 ; -------------------------------------------------------------------------------------- 23b7 23b7 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 23b8 23b8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23b9 0x23b9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23b9 23b9 seq_br_type 2 Push (branch address); Flow J 0x23ba seq_branch_adr 23b8 0x23b8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 23ba 23ba fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238c fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238c 0x238c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 23bb 23bb seq_br_type 7 Unconditional Call; Flow C 0x2390 seq_branch_adr 2390 0x2390 23bc 23bc fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23bd 23bd seq_b_timing 1 Latch Condition; Flow J cc=True 0x2393 seq_br_type 1 Branch True seq_branch_adr 2393 0x2393 23be 23be typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 23bf 23bf seq_br_type 3 Unconditional Branch; Flow J 0x2393 seq_branch_adr 2393 0x2393 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 23c0 ; -------------------------------------------------------------------------------------- 23c0 ; 0x0304 Complete_Type Variant_Record,By_Completing_Constraint 23c0 ; -------------------------------------------------------------------------------------- 23c0 MACRO_Complete_Type_Variant_Record,By_Completing_Constraint: 23c0 23c0 dispatch_brk_class 4 ; Flow C cc=True 0x32ab dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23c0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 23c1 23c1 fiu_mem_start 4 continue typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 23c2 23c2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23c3 23c3 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 23c4 23c4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23c5 23c5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 23c6 23c6 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3279 fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 23c7 23c7 fiu_mem_start 4 continue; Flow C cc=True 0x32a9 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 23c8 23c8 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 23c9 23c9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 23ca 23ca ioc_tvbs 2 fiu+val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 23cb 23cb seq_br_type 7 Unconditional Call; Flow C 0x2482 seq_branch_adr 2482 0x2482 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 23cc 23cc fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_b_adr 09 GP09 23cd 23cd fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23ce 23ce fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23cf 23cf fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 23d0 23d0 ioc_tvbs 2 fiu+val; Flow J cc=True 0x23e2 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 23e2 0x23e2 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 23d1 23d1 fiu_load_var 1 hold_var; Flow C 0x2381 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2381 0x2381 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 23d2 23d2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 23d3 23d3 ioc_fiubs 0 fiu ; Flow C 0x23dc seq_br_type 7 Unconditional Call seq_branch_adr 23dc 0x23dc typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 23d4 23d4 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 23d5 23d5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 23d6 23d6 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 23d7 23d7 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 23d8 23d8 ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 10 TOP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 23d9 23d9 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 23da 23da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x25ae seq_br_type 1 Branch True seq_branch_adr 25ae 0x25ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 5 23db 23db fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 23dc 23dc fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23dd 0x23dd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23dd 23dd seq_br_type 2 Push (branch address); Flow J 0x23de seq_branch_adr 23dc 0x23dc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 23de 23de fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238c fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238c 0x238c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23df 23df seq_br_type 7 Unconditional Call; Flow C 0x2390 seq_branch_adr 2390 0x2390 23e0 23e0 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23e1 23e1 seq_br_type 3 Unconditional Branch; Flow J 0x2381 seq_branch_adr 2381 0x2381 23e2 23e2 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x23e3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 23d4 0x23d4 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 23e3 23e3 ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 23e4 23e4 fiu_load_var 1 hold_var; Flow C 0x2393 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2393 0x2393 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 23e5 23e5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 23e6 23e6 ioc_fiubs 0 fiu ; Flow J 0x23e7 seq_br_type 3 Unconditional Branch seq_branch_adr 23e7 0x23e7 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 23e7 23e7 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23e8 0x23e8 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23e8 23e8 seq_br_type 2 Push (branch address); Flow J 0x23e9 seq_branch_adr 23b8 0x23b8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 23e9 23e9 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238c fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238c 0x238c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 23ea 23ea seq_br_type 7 Unconditional Call; Flow C 0x2390 seq_branch_adr 2390 0x2390 23eb 23eb fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23ec 23ec seq_b_timing 1 Latch Condition; Flow J cc=True 0x2393 seq_br_type 1 Branch True seq_branch_adr 2393 0x2393 23ed 23ed typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 23ee 23ee seq_br_type 3 Unconditional Branch; Flow J 0x2393 seq_branch_adr 2393 0x2393 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 23ef ; -------------------------------------------------------------------------------------- 23ef ; Comes from: 23ef ; 2375 C True from color 0x2371 23ef ; -------------------------------------------------------------------------------------- 23ef 23ef seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 23f0 23f0 fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 23f1 23f1 <halt> ; Flow R 23f2 ; -------------------------------------------------------------------------------------- 23f2 ; 0x031c Declare_Type Variant_Record,Constrained,Visible 23f2 ; -------------------------------------------------------------------------------------- 23f2 MACRO_Declare_Type_Variant_Record,Constrained,Visible: 23f2 23f2 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23f2 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 23f3 23f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x23f5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 23f5 0x23f5 seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 22 VR06:02 val_frame 6 23f4 ; -------------------------------------------------------------------------------------- 23f4 ; 0x031b Declare_Type Variant_Record,Constrained 23f4 ; -------------------------------------------------------------------------------------- 23f4 MACRO_Declare_Type_Variant_Record,Constrained: 23f4 23f4 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23f4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 39 VR02:19 val_frame 2 23f5 23f5 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 23f6 23f6 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR08:09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 23f7 23f7 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 23f8 23f8 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 23f9 23f9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 23fa 23fa seq_b_timing 0 Early Condition; Flow J cc=True 0x23fe seq_br_type 1 Branch True seq_branch_adr 23fe 0x23fe seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23fb 23fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x23fd fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 23fd 0x23fd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 23fc 23fc seq_br_type 3 Unconditional Branch; Flow J 0x23fe seq_branch_adr 23fe 0x23fe val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23fd 23fd ioc_tvbs 2 fiu+val; Flow C cc=False 0x32ad seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23fe 23fe fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 val_a_adr 17 LOOP_COUNTER 23ff 23ff seq_br_type 7 Unconditional Call; Flow C 0x2482 seq_branch_adr 2482 0x2482 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2400 2400 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2401 2401 fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2402 2402 ioc_fiubs 0 fiu ; Flow J cc=True 0x2420 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2420 0x2420 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2403 2403 seq_br_type 7 Unconditional Call; Flow C 0x240b seq_branch_adr 240b 0x240b typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2404 2404 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2405 2405 ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2406 2406 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 2407 2407 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 2408 2408 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 2409 2409 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 06 GP06 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 240a 240a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 240b ; -------------------------------------------------------------------------------------- 240b ; Comes from: 240b ; 2403 C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 240b ; 2421 C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 240b ; -------------------------------------------------------------------------------------- 240b 240b fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 240c 240c fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 240d 240d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 240e 240e fiu_mem_start a start_continue_if_false typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 240f 240f fiu_load_var 1 hold_var; Flow C 0x2415 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 2415 0x2415 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_b_adr 02 GP02 2410 2410 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2411 2411 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2412 2412 seq_br_type 7 Unconditional Call; Flow C 0x2424 seq_branch_adr 2424 0x2424 seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2413 2413 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 2414 2414 ioc_fiubs 0 fiu ; Flow J 0x2446 seq_br_type 3 Unconditional Branch seq_branch_adr 2446 0x2446 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2415 ; -------------------------------------------------------------------------------------- 2415 ; Comes from: 2415 ; 240f C from color 0x240b 2415 ; -------------------------------------------------------------------------------------- 2415 2415 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2416 0x2416 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2416 2416 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2417 2417 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2418 2418 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 2419 2419 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 241a 241a fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2452 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2452 0x2452 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 241b 241b seq_b_timing 1 Latch Condition; Flow J cc=True 0x241e seq_br_type 1 Branch True seq_branch_adr 241e 0x241e seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_a_adr 2b TR08:0b typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 241c 241c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 241d 241d ioc_load_wdr 0 ; Flow J 0x2415 seq_br_type 3 Unconditional Branch seq_branch_adr 2415 0x2415 typ_b_adr 06 GP06 val_b_adr 05 GP05 241e 241e fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 241f 241f fiu_mem_start 3 start-wr; Flow J 0x241d ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 241d 0x241d typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2420 2420 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2421 2421 ioc_tvbs 1 typ+fiu; Flow C 0x240b seq_br_type 7 Unconditional Call seq_branch_adr 240b 0x240b typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2422 2422 fiu_mem_start 3 start-wr; Flow C cc=True 0x32ad ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 0 PASS_A 2423 2423 ioc_load_wdr 0 ; Flow J 0x2404 seq_br_type 3 Unconditional Branch seq_branch_adr 2404 0x2404 typ_b_adr 01 GP01 val_b_adr 02 GP02 2424 ; -------------------------------------------------------------------------------------- 2424 ; Comes from: 2424 ; 2412 C from color 0x240b 2424 ; -------------------------------------------------------------------------------------- 2424 2424 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2425 0x2425 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2425 2425 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2426 2426 fiu_load_var 1 hold_var; Flow C cc=True 0x2452 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2452 0x2452 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2427 2427 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2424 seq_br_type 1 Branch True seq_branch_adr 2424 0x2424 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3a GP05 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_frame 7 2428 2428 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2429 2429 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 242a 242a fiu_mem_start 2 start-rd; Flow J cc=True 0x243e ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 243e 0x243e typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 242b 242b typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 242c 242c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 242d 242d fiu_load_tar 1 hold_tar; Flow C 0x323f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 242e 242e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 242f 242f fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2430 2430 ioc_load_wdr 0 ; Flow C cc=True 0x32ad ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2431 2431 fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 2432 2432 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2436 seq_br_type 1 Branch True seq_branch_adr 2436 0x2436 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2433 2433 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 2434 2434 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2435 2435 fiu_load_var 1 hold_var; Flow J 0x2442 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2442 0x2442 seq_en_micro 0 val_a_adr 0f GP0f 2436 2436 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x243c ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 243c 0x243c seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 2437 2437 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2438 2438 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x243b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 243b 0x243b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 2439 2439 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2436 seq_br_type 1 Branch True seq_branch_adr 2436 0x2436 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 243a 243a seq_br_type 3 Unconditional Branch; Flow J 0x2433 seq_branch_adr 2433 0x2433 seq_en_micro 0 243b 243b fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x2442 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2442 0x2442 seq_en_micro 0 243c ; -------------------------------------------------------------------------------------- 243c ; Comes from: 243c ; 2436 C True from color 0x0000 243c ; -------------------------------------------------------------------------------------- 243c 243c seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 243d 243d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 243e 243e fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 243f 243f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2440 2440 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2441 2441 fiu_load_tar 1 hold_tar; Flow C 0x323f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2442 2442 ioc_tvbs 1 typ+fiu; Flow J 0x2443 seq_br_type 2 Push (branch address) seq_branch_adr 2424 0x2424 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2443 2443 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2445 seq_br_type 5 Call True seq_branch_adr 2445 0x2445 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 2444 2444 fiu_mem_start 3 start-wr; Flow J 0x32fe ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 2445 ; -------------------------------------------------------------------------------------- 2445 ; Comes from: 2445 ; 2443 C True from color 0x0000 2445 ; -------------------------------------------------------------------------------------- 2445 2445 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2446 2446 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2447 0x2447 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2447 2447 seq_br_type 2 Push (branch address); Flow J 0x2448 seq_branch_adr 2446 0x2446 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 2448 2448 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x2450 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2450 0x2450 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2449 2449 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 244a 244a fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 244b 244b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2452 fiu_mem_start 8 start_wr_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2452 0x2452 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 244c 244c seq_b_timing 1 Latch Condition; Flow J cc=True 0x2424 seq_br_type 1 Branch True seq_branch_adr 2424 0x2424 244d 244d typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 244e 244e seq_br_type 3 Unconditional Branch; Flow J 0x2424 seq_branch_adr 2424 0x2424 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 244f 244f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2450 2450 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2452 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2452 0x2452 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 2451 2451 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x244f seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 244f 0x244f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 2452 ; -------------------------------------------------------------------------------------- 2452 ; Comes from: 2452 ; 241a C True from color 0x2415 2452 ; 2426 C True from color 0x0000 2452 ; 244b C True from color 0x0000 2452 ; 2450 C True from color 0x240b 2452 ; -------------------------------------------------------------------------------------- 2452 2452 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 2453 2453 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 2454 ; -------------------------------------------------------------------------------------- 2454 ; Comes from: 2454 ; 09f5 C from color MACRO_Execute_Any,Size 2454 ; 1313 C from color MACRO_Declare_Variable_Variant_Record,Duplicate 2454 ; 1749 C from color 0x09ae 2454 ; 17a7 C from color 0x0a32 2454 ; -------------------------------------------------------------------------------------- 2454 2454 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x2457 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2457 0x2457 typ_mar_cntl 6 INCREMENT_MAR 2455 2455 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2456 2456 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x2458 seq_br_type 8 Return True seq_branch_adr 2458 0x2458 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2457 2457 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x3279 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2458 ; -------------------------------------------------------------------------------------- 2458 ; Comes from: 2458 ; 116f C from color 0x116b 2458 ; 16a2 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2458 ; 16b8 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2458 ; -------------------------------------------------------------------------------------- 2458 2458 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x245f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 245f 0x245f seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 2459 2459 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x245c ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 245c 0x245c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 245a 245a fiu_fill_mode_src 0 ; Flow J cc=False 0x2487 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2487 0x2487 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 245b 245b seq_br_type 3 Unconditional Branch; Flow J 0x2457 seq_branch_adr 2457 0x2457 245c 245c fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 245d 245d fiu_fill_mode_src 0 ; Flow J cc=False 0x2487 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2487 0x2487 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 245e 245e seq_br_type 3 Unconditional Branch; Flow J 0x2457 seq_branch_adr 2457 0x2457 245f 245f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2460 2460 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2461 2461 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a84 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2462 2462 seq_b_timing 0 Early Condition; Flow J cc=True 0x246f seq_br_type 1 Branch True seq_branch_adr 246f 0x246f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2463 2463 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x246f ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 246f 0x246f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2464 2464 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2480 seq_br_type 5 Call True seq_branch_adr 2480 0x2480 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2465 2465 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2463 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2463 0x2463 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2466 2466 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2467 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2463 0x2463 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 2467 2467 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x246a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 246a 0x246a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2468 2468 fiu_fill_mode_src 0 ; Flow J 0x246c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 246c 0x246c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2469 2469 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x2468 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2468 0x2468 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 246a 246a fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 246b 246b fiu_fill_mode_src 0 ; Flow J 0x246c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 246c 0x246c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 246c 246c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 246d 0x246d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 246d 246d seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 246e 0x246e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_rand 5 CHECK_CLASS_B_LIT 246e 246e seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32ae seq_br_type 8 Return True seq_branch_adr 32ae 0x32ae seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 246f 246f fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2470 0x2470 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 2470 2470 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2472 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2472 0x2472 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 2471 2471 fiu_fill_mode_src 0 ; Flow J 0x2474 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2474 0x2474 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2472 2472 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2473 2473 fiu_fill_mode_src 0 ; Flow J 0x2474 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2474 0x2474 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2474 2474 fiu_mem_start 2 start-rd; Flow J cc=False 0x2476 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2476 0x2476 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2475 2475 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 2476 2476 seq_b_timing 0 Early Condition; Flow J cc=True 0x2479 seq_br_type 1 Branch True seq_branch_adr 2479 0x2479 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 2477 2477 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x2a84 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 2478 2478 fiu_mem_start 2 start-rd; Flow J 0x2476 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2476 0x2476 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2479 2479 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x247e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 247e 0x247e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 247a 247a fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 247b 247b fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 247c 0x247c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 247c 247c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2480 seq_br_type 5 Call True seq_branch_adr 2480 0x2480 seq_cond_sel 67 REFRESH_MACRO_EVENT 247d 247d fiu_load_tar 1 hold_tar; Flow J cc=True 0x247a fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 247a 0x247a seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 247e 247e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2469 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2469 0x2469 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 247f 247f fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x247c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 247c 0x247c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 2480 2480 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 2481 2481 fiu_mem_start 2 start-rd; Flow J 0x32fe seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe 2482 ; -------------------------------------------------------------------------------------- 2482 ; Comes from: 2482 ; 12e3 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2482 ; 2359 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2482 ; 23cb C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2482 ; 23ff C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 2482 ; -------------------------------------------------------------------------------------- 2482 2482 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0x2486 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2486 0x2486 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2483 2483 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 2484 2484 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2485 2485 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x32a9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2486 2486 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2487 2487 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2488 2488 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2489 0x2489 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2489 2489 seq_br_type 3 Unconditional Branch; Flow J 0x2485 seq_branch_adr 2485 0x2485 248a ; -------------------------------------------------------------------------------------- 248a ; Comes from: 248a ; 1140 C from color 0x110f 248a ; 1af3 C from color 0x0a33 248a ; 1aff C from color 0x0a7d 248a ; 1b05 C from color 0x0a91 248a ; 1b09 C from color 0x0a33 248a ; 1d89 C from color 0x1d2a 248a ; 1d95 C from color 0x1d2a 248a ; -------------------------------------------------------------------------------------- 248a 248a fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 248b 248b fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 248c 0x248c typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 248c 248c <default> 248d 248d fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 248e 248e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 248f 248f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2490 0x2490 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2490 2490 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A 2491 2491 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x249a ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 249a 0x249a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2492 2492 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x24e2 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 24e2 0x24e2 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 2493 2493 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2494 ; -------------------------------------------------------------------------------------- 2494 ; Comes from: 2494 ; 0c33 C from color 0x0a35 2494 ; 0c3f C from color 0x0a7e 2494 ; 0c45 C from color 0x0a92 2494 ; 0c49 C from color 0x0a35 2494 ; 114a C from color 0x110f 2494 ; 1d8e C from color 0x1d2a 2494 ; 1dab C from color 0x1d2a 2494 ; -------------------------------------------------------------------------------------- 2494 2494 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2495 2495 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2496 0x2496 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2496 2496 <default> 2497 2497 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 2498 2498 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2499 2499 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x2490 seq_br_type 8 Return True seq_branch_adr 2490 0x2490 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 249a 249a fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x249d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 249d 0x249d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 249b 249b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x24c6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24c6 0x24c6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 249c 249c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x24c6 seq_br_type 1 Branch True seq_branch_adr 24c6 0x24c6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS 249d 249d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x24ae seq_br_type 1 Branch True seq_branch_adr 24ae 0x24ae seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 249e 249e fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 249f 0x249f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 249f 249f typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24a0 24a0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24e0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24a1 24a1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24a3 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24a3 0x24a3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24a2 24a2 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x249e seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 249e 0x249e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24a3 24a3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24a4 0x24a4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24a4 24a4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_frame 12 val_rand c START_MULTIPLY 24a5 24a5 fiu_load_oreg 1 hold_oreg seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24a6 24a6 fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24a7 24a7 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24a8 24a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 24a9 24a9 typ_a_adr 09 GP09 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 24aa 24aa fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24ab 24ab <default> 24ac 24ac fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24ad 24ad seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x249e seq_branch_adr 249e 0x249e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24ae 24ae fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24af 0x24af seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 20 TR05:00 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24af 24af fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24b4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24b4 0x24b4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24b0 24b0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24b1 24b1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24e0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24b2 24b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24b9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24b9 0x24b9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24b3 24b3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24ae seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ae 0x24ae seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24b4 24b4 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24b5 24b5 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24b6 24b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24e0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24b7 24b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24b9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24b9 0x24b9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24b8 24b8 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24ae seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ae 0x24ae seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24b9 24b9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24ba 0x24ba seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24ba 24ba fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 24bb 24bb ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24bc 24bc fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 12 val_rand c START_MULTIPLY 24bd 24bd fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24be 24be fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B 24bf 24bf fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24c1 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24c1 0x24c1 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT 24c0 24c0 fiu_fill_mode_src 0 ; Flow J 0x24c3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24c3 0x24c3 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24c1 24c1 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24c2 24c2 fiu_fill_mode_src 0 ; Flow J 0x24c3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24c3 0x24c3 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24c3 24c3 typ_c_adr 36 GP09 24c4 24c4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24c5 24c5 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x24ae seq_branch_adr 24ae 0x24ae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24c6 24c6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x24d1 seq_br_type 1 Branch True seq_branch_adr 24d1 0x24d1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 24c7 24c7 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24c8 0x24c8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24c8 24c8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24c9 24c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24e0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24ca 24ca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24c7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24c7 0x24c7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24cb 24cb ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24cc 0x24cc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24cc 24cc fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24cd 24cd ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24ce 24ce fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 24cf 24cf seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x24c7 seq_br_type 8 Return True seq_branch_adr 24c7 0x24c7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24d0 24d0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24d1 0x24d1 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24d1 24d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x24da fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 24da 0x24da seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 24d2 24d2 fiu_load_var 1 hold_var; Flow J cc=True 0x24d8 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24d8 0x24d8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 09 GP09 24d3 24d3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24d4 0x24d4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24d4 24d4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24d5 24d5 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24d6 24d6 fiu_load_var 1 hold_var; Flow J cc=False 0x24d0 fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24d0 0x24d0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 24d7 24d7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x24d9 seq_br_type 8 Return True seq_branch_adr 24d9 0x24d9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24d8 24d8 seq_b_timing 0 Early Condition; Flow J cc=False 0x24d1 seq_br_type 0 Branch False seq_branch_adr 24d1 0x24d1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 24d9 24d9 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24da ; -------------------------------------------------------------------------------------- 24da ; Comes from: 24da ; 24d1 C from color 0x248a 24da ; -------------------------------------------------------------------------------------- 24da 24da fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24dd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24dd 0x24dd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 24db 24db fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24dc 24dc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x24e0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24dd 24dd fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24de 24de fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24df 24df fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 24e0 0x24e0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24e0 ; -------------------------------------------------------------------------------------- 24e0 ; Comes from: 24e0 ; 24a0 C True from color 0x248a 24e0 ; 24b1 C True from color 0x248a 24e0 ; 24b6 C True from color 0x248a 24e0 ; 24c9 C True from color 0x248a 24e0 ; -------------------------------------------------------------------------------------- 24e0 24e0 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 24e1 24e1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 24e2 24e2 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 24e3 24e3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x24e7 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24e7 0x24e7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 24e4 24e4 fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24e5 ; -------------------------------------------------------------------------------------- 24e5 ; Comes from: 24e5 ; 116c C from color 0x116b 24e5 ; 17a0 C True from color 0x0a32 24e5 ; 17b2 C True from color 0x0a7c 24e5 ; 17b6 C True from color 0x0a90 24e5 ; 17ba C True from color MACRO_Execute_Variant_Record,Check_In_Type 24e5 ; 17c0 C True from color 0x0aa4 24e5 ; 1dc3 C from color 0x0000 24e5 ; -------------------------------------------------------------------------------------- 24e5 24e5 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 24e6 24e6 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32ae fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 24e7 24e7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x24fd fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 24fd 0x24fd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24e8 24e8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 24e9 24e9 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24f0 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24f0 0x24f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 24ea 24ea fiu_fill_mode_src 0 ; Flow J cc=True 0x24f2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24f2 0x24f2 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 24eb 24eb seq_b_timing 0 Early Condition; Flow J cc=True 0x24f4 seq_br_type 1 Branch True seq_branch_adr 24f4 0x24f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24ec 24ec fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 24ed 24ed ioc_tvbs 1 typ+fiu; Flow J cc=True 0x24fc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24fc 0x24fc seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24ee 24ee fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 24ef 24ef fiu_mem_start a start_continue_if_false; Flow J cc=True 0x24ea seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 24ea 0x24ea seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 24f0 24f0 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24f1 24f1 fiu_fill_mode_src 0 ; Flow J cc=False 0x24eb fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 24eb 0x24eb seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 24f2 24f2 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 24f3 24f3 fiu_mem_start 2 start-rd; Flow J 0x24eb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 24eb 0x24eb typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 24f4 24f4 fiu_fill_mode_src 0 ; Flow J cc=True 0x24f9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24f9 0x24f9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 24f5 24f5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24fa seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24fa 0x24fa seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 24f6 24f6 fiu_fill_mode_src 0 ; Flow J cc=True 0x24fc fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24fc 0x24fc seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 24f7 24f7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 24f8 0x24f8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 24f8 24f8 seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 24f9 24f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 24fa 24fa fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24fb 24fb fiu_fill_mode_src 0 ; Flow J cc=True 0x24f7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24f7 0x24f7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 24fc 24fc fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24fd 24fd fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2500 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2500 0x2500 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 24fe 24fe fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2501 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2501 0x2501 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24ff 24ff fiu_fill_mode_src 0 ; Flow J 0x24f7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f7 0x24f7 2500 2500 fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2501 2501 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2502 2502 fiu_fill_mode_src 0 ; Flow J 0x24f7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f7 0x24f7 2503 2503 <halt> ; Flow R 2504 ; -------------------------------------------------------------------------------------- 2504 ; 0x0319 Declare_Type Variant_Record,Incomplete,Visible 2504 ; -------------------------------------------------------------------------------------- 2504 MACRO_Declare_Type_Variant_Record,Incomplete,Visible: 2504 2504 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2504 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2505 2505 seq_br_type 3 Unconditional Branch; Flow J 0x2507 seq_branch_adr 2507 0x2507 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2506 ; -------------------------------------------------------------------------------------- 2506 ; 0x0318 Declare_Type Variant_Record,Incomplete 2506 ; -------------------------------------------------------------------------------------- 2506 MACRO_Declare_Type_Variant_Record,Incomplete: 2506 2506 dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2506 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2507 2507 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2509 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2509 0x2509 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 2 2508 2508 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ad ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2509 2509 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ad fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 250a 250a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ad fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 250b 250b fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ad fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3a GP05 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 250c 250c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ad fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 250d 250d fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 250e 250e ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 26 VR05:06 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR05:00 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 250f 250f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2512 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2512 0x2512 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 2510 2510 fiu_tivi_src 6 fiu_fiu; Flow C cc=True 0x2a84 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 20 TR08:00 typ_frame 8 2511 2511 fiu_mem_start 3 start-wr; Flow J cc=True 0x2510 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2510 0x2510 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 2512 2512 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2513 2513 ioc_load_wdr 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2c TR09:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2514 2514 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_b_adr 21 TR00:01 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2515 2515 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2516 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2516 0x2516 typ_a_adr 05 GP05 val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2516 2516 fiu_load_var 1 hold_var; Flow J cc=True 0x251c fiu_mem_start 6 start_rd_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 251c 0x251c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 06 GP06 val_rand 2 DEC_LOOP_COUNTER 2517 2517 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 2518 2518 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fe fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2519 2519 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 251a 251a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a84 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 val_b_adr 02 GP02 251b 251b ioc_tvbs 1 typ+fiu; Flow J 0x2516 seq_br_type 3 Unconditional Branch seq_branch_adr 2516 0x2516 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 251c 251c ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 04 GP04 val_alu_func 0 PASS_A 251d 251d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2520 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2520 0x2520 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 251e 251e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 251f 251f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2520 ; -------------------------------------------------------------------------------------- 2520 ; Comes from: 2520 ; 251d C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2520 ; 252e C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2520 ; -------------------------------------------------------------------------------------- 2520 2520 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a84 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2521 2521 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x2520 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2520 0x2520 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2522 ; -------------------------------------------------------------------------------------- 2522 ; 0x0312 Declare_Type Variant_Record,Constrained_Incomplete,Visible 2522 ; -------------------------------------------------------------------------------------- 2522 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete,Visible: 2522 2522 dispatch_brk_class 4 ; Flow C cc=False 0x3279 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2522 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2523 2523 seq_br_type 3 Unconditional Branch; Flow J 0x2525 seq_branch_adr 2525 0x2525 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2524 ; -------------------------------------------------------------------------------------- 2524 ; 0x0311 Declare_Type Variant_Record,Constrained_Incomplete 2524 ; -------------------------------------------------------------------------------------- 2524 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete: 2524 2524 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2524 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2525 2525 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32ad fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 2526 2526 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2527 2527 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ad fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 2528 2528 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x252b fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 252b 0x252b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2529 2529 fiu_tivi_src 6 fiu_fiu; Flow C cc=True 0x2a84 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 2b TR08:0b typ_frame 8 val_rand 2 DEC_LOOP_COUNTER 252a 252a fiu_mem_start 3 start-wr; Flow J cc=False 0x2529 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2529 0x2529 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 252b 252b fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 252c 252c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 10 TOP 252d 252d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 3b VR02:1b val_b_adr 1f TOP - 1 val_frame 2 252e 252e fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2520 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2520 0x2520 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 27 TR08:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 252f 252f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x251f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 251f 0x251f seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2530 ; -------------------------------------------------------------------------------------- 2530 ; 0x0307 Complete_Type Variant_Record,By_Defining 2530 ; -------------------------------------------------------------------------------------- 2530 MACRO_Complete_Type_Variant_Record,By_Defining: 2530 2530 dispatch_brk_class 4 ; Flow C 0x32fe dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2530 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR02:02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2531 2531 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x3279 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 2532 2532 fiu_mem_start 4 continue; Flow C cc=True 0x32ab ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2533 2533 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ad fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR06:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 2534 2534 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR09:0e typ_frame 9 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2535 2535 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2536 2536 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2537 2537 fiu_tivi_src 1 tar_val; Flow J cc=True 0x2575 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2575 0x2575 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2538 2538 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1d TOP - 3 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2539 2539 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 253a 253a fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 253b 253b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 253c 253c ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 253d 253d seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 253e 253e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 253f 253f ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2540 2540 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2541 2541 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 2542 2542 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2543 2543 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 2544 2544 ioc_fiubs 0 fiu ; Flow C 0x26b8 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1d TOP - 3 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2545 2545 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2546 2546 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2547 2547 seq_b_timing 0 Early Condition; Flow J cc=False 0x2549 seq_br_type 0 Branch False seq_branch_adr 2549 0x2549 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 2548 2548 seq_br_type 3 Unconditional Branch; Flow J 0x254a seq_branch_adr 254a 0x254a val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2549 2549 seq_br_type 3 Unconditional Branch; Flow J 0x254a seq_branch_adr 254a 0x254a typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 254a 254a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 254b 254b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x255d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 255d 0x255d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 254c 254c ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 254d 254d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 254e 254e fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ad fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 254f 254f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2550 2550 seq_br_type 7 Unconditional Call; Flow C 0x26b8 seq_branch_adr 26b8 0x26b8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2551 2551 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2552 2552 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2555 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2555 0x2555 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2553 2553 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x254a seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 254a 0x254a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2554 2554 ioc_fiubs 0 fiu ; Flow J 0x254a seq_br_type 3 Unconditional Branch seq_branch_adr 254a 0x254a val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2555 ; -------------------------------------------------------------------------------------- 2555 ; Comes from: 2555 ; 2552 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Defining 2555 ; 25a7 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Defining 2555 ; 2610 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2555 ; -------------------------------------------------------------------------------------- 2555 2555 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2556 2556 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 2557 2557 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2558 2558 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2556 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2556 0x2556 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2559 2559 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 255a 255a fiu_mem_start 3 start-wr; Flow J 0x2556 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2556 0x2556 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 255b 255b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 255c 255c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2556 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2556 0x2556 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 255d 255d ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 255e 255e seq_b_timing 0 Early Condition; Flow C cc=False 0x256c seq_br_type 4 Call False seq_branch_adr 256c 0x256c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 255f 255f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ad seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2560 2560 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2561 2561 fiu_tivi_src c mar_0xc; Flow C cc=True 0x256a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 256a 0x256a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 2562 2562 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2563 2563 seq_b_timing 0 Early Condition; Flow C cc=False 0x2573 seq_br_type 4 Call False seq_branch_adr 2573 0x2573 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2564 2564 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2565 2565 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2566 2566 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2567 2567 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 2568 2568 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 2569 2569 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 256a ; -------------------------------------------------------------------------------------- 256a ; Comes from: 256a ; 2561 C True from color 0x255e 256a ; -------------------------------------------------------------------------------------- 256a 256a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 256b 256b seq_b_timing 0 Early Condition; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 256c ; -------------------------------------------------------------------------------------- 256c ; Comes from: 256c ; 255e C False from color 0x255e 256c ; -------------------------------------------------------------------------------------- 256c 256c seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 256d 0x256d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 256d 256d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 256e 256e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 256f 0x256f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 256f 256f seq_br_type 1 Branch True; Flow J cc=True 0x2572 seq_branch_adr 2572 0x2572 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2570 2570 seq_br_type 1 Branch True; Flow J cc=True 0x2572 seq_branch_adr 2572 0x2572 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2571 2571 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 2572 0x2572 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2572 2572 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 2573 ; -------------------------------------------------------------------------------------- 2573 ; Comes from: 2573 ; 2563 C False from color 0x255e 2573 ; -------------------------------------------------------------------------------------- 2573 2573 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2574 0x2574 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2574 2574 seq_br_type a Unconditional Return; Flow R typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2575 2575 seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1d TOP - 3 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2576 2576 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1c TOP - 4 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2577 2577 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2578 2578 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ad fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 1d TOP - 3 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 2579 2579 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 257a 257a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32ad fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 257b 257b ioc_tvbs 1 typ+fiu val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 257c 257c seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 257d 257d fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_b_adr 03 GP03 257e 257e fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 257f 257f seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2580 2580 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 2581 2581 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2582 2582 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2583 2583 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 2584 2584 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2585 2585 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 2586 2586 ioc_fiubs 0 fiu ; Flow C 0x26b8 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1c TOP - 4 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2587 2587 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2588 2588 seq_br_type 7 Unconditional Call; Flow C 0x26dd seq_branch_adr 26dd 0x26dd seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2589 2589 seq_br_type 1 Branch True; Flow J cc=True 0x258e seq_branch_adr 258e 0x258e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 258a 258a val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 258b 258b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 258c 258c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x258e seq_br_type 1 Branch True seq_branch_adr 258e 0x258e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 258d 258d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 258e 258e ioc_fiubs 1 val ; Flow J cc=True 0x2590 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2590 0x2590 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 258f 258f typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 2590 2590 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2591 2591 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 2592 2592 val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 2593 2593 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2594 2594 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 2595 2595 ioc_fiubs 0 fiu ; Flow J 0x2596 seq_br_type 3 Unconditional Branch seq_branch_adr 2596 0x2596 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2596 2596 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2597 2597 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x255d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 255d 0x255d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2598 2598 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2599 2599 ioc_fiubs 1 val ; Flow C cc=True 0x32ad ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 259a 259a fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ad fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 259b 259b ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 259c 259c fiu_load_var 1 hold_var; Flow C cc=True 0x2a84 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 259d 259d ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 259e 259e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 259f 259f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 25a0 25a0 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 25a1 25a1 seq_br_type 7 Unconditional Call; Flow C 0x26b8 seq_branch_adr 26b8 0x26b8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25a2 25a2 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 25a3 25a3 ioc_fiubs 2 typ ; Flow J cc=True 0x25a5 seq_br_type 1 Branch True seq_branch_adr 25a5 0x25a5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25a4 25a4 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 25a5 25a5 seq_br_type 7 Unconditional Call; Flow C 0x26dd seq_branch_adr 26dd 0x26dd val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25a6 25a6 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 25a7 25a7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2555 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2555 0x2555 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 25a8 25a8 seq_br_type 0 Branch False; Flow J cc=False 0x2596 seq_branch_adr 2596 0x2596 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 25a9 25a9 seq_br_type 3 Unconditional Branch; Flow J 0x2596 seq_branch_adr 2596 0x2596 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 25aa ; -------------------------------------------------------------------------------------- 25aa ; 0x0303 Complete_Type Variant_Record,By_Component_Completion 25aa ; -------------------------------------------------------------------------------------- 25aa MACRO_Complete_Type_Variant_Record,By_Component_Completion: 25aa 25aa dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 25aa fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25ab 25ab typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25ac 25ac fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25ad 25ad fiu_mem_start 2 start-rd; Flow J cc=True 0x25ae ; Flow J cc=#0x0 0x25b3 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 25b3 0x25b3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25ae 25ae fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 25af 25af typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25b0 25b0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25b1 25b1 fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25b2 25b2 seq_br_type 3 Unconditional Branch; Flow J 0x25b7 seq_branch_adr 25b7 0x25b7 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 25b3 25b3 seq_br_type 3 Unconditional Branch; Flow J 0x262a seq_branch_adr 262a 0x262a typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b4 25b4 ioc_fiubs 2 typ ; Flow J 0x25b7 seq_br_type 3 Unconditional Branch seq_branch_adr 25b7 0x25b7 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 38 GP07 val_c_source 0 FIU_BUS 25b5 25b5 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b6 25b6 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b7 25b7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 25b8 25b8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 25b9 25b9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25ba 25ba fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 31 GP0e val_c_source 0 FIU_BUS 25bb 25bb ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 25bc 25bc ioc_tvbs 3 fiu+fiu; Flow J 0x25bd seq_br_type 3 Unconditional Branch seq_branch_adr 25bd 0x25bd seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25bd 25bd fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x25ec ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 25ec 0x25ec seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 25be 25be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x25de seq_br_type 5 Call True seq_branch_adr 25de 0x25de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 25bf 25bf fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c0 25c0 ioc_fiubs 2 typ ; Flow J cc=False 0x25c6 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 25c6 0x25c6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 25c1 25c1 fiu_load_tar 1 hold_tar; Flow C cc=True 0x25e1 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25e1 0x25e1 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 25c2 25c2 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 25c3 25c3 seq_b_timing 1 Latch Condition; Flow C cc=False 0x25c9 seq_br_type 4 Call False seq_branch_adr 25c9 0x25c9 typ_c_adr 30 GP0f 25c4 25c4 ioc_fiubs 1 val ; Flow J cc=True 0x25bd ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 25bd 0x25bd seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c5 25c5 ioc_fiubs 1 val ; Flow J 0x25bd seq_br_type 3 Unconditional Branch seq_branch_adr 25bd 0x25bd val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c6 25c6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 25c7 25c7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x25e1 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 25e1 0x25e1 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 25c8 25c8 fiu_mem_start 3 start-wr; Flow J 0x25c4 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 25c4 0x25c4 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 25c9 ; -------------------------------------------------------------------------------------- 25c9 ; Comes from: 25c9 ; 25c3 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25c9 ; -------------------------------------------------------------------------------------- 25c9 25c9 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x25cb seq_br_type 1 Branch True seq_branch_adr 25cb 0x25cb seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25ca 25ca seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25cb 25cb seq_br_type 4 Call False; Flow C cc=False 0x25ce seq_branch_adr 25ce 0x25ce seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25cc 25cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 25cd 0x25cd seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25cd 25cd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25ce ; -------------------------------------------------------------------------------------- 25ce ; Comes from: 25ce ; 25cb C False from color 0x25c9 25ce ; 2605 C False from color 0x2603 25ce ; -------------------------------------------------------------------------------------- 25ce 25ce fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25cf 25cf fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 36 GP09 val_c_source 0 FIU_BUS 25d0 25d0 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x25d5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25d5 0x25d5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 2 25d1 25d1 seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25d2 25d2 seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 25d3 25d3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 25d4 25d4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 0c GP0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25d5 25d5 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x25dc ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25dc 0x25dc seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25d6 25d6 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 25d7 25d7 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x25da seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25da 0x25da seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 25d8 25d8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x25d5 seq_br_type 1 Branch True seq_branch_adr 25d5 0x25d5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 25d9 25d9 seq_br_type 3 Unconditional Branch; Flow J 0x25d2 seq_branch_adr 25d2 0x25d2 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25da 25da seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 25db 25db seq_br_type 3 Unconditional Branch; Flow J 0x25d2 seq_branch_adr 25d2 0x25d2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25dc ; -------------------------------------------------------------------------------------- 25dc ; Comes from: 25dc ; 25d5 C True from color 0x25ce 25dc ; -------------------------------------------------------------------------------------- 25dc 25dc seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 25dd 25dd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25de ; -------------------------------------------------------------------------------------- 25de ; Comes from: 25de ; 25be C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25de ; 25f8 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25de ; -------------------------------------------------------------------------------------- 25de 25de seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 25df 25df fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25e0 25e0 seq_br_type a Unconditional Return; Flow R 25e1 ; -------------------------------------------------------------------------------------- 25e1 ; Comes from: 25e1 ; 25c1 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25e1 ; 25c7 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25e1 ; -------------------------------------------------------------------------------------- 25e1 25e1 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x25e6 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25e6 0x25e6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 25e2 25e2 seq_b_timing 1 Latch Condition; Flow J cc=False 0x25e9 seq_br_type 0 Branch False seq_branch_adr 25e9 0x25e9 seq_en_micro 0 25e3 25e3 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e4 0x25e4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25e4 25e4 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e5 0x25e5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 25e5 25e5 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 25e6 ; -------------------------------------------------------------------------------------- 25e6 ; Comes from: 25e6 ; 2608 C True from color 0x2608 25e6 ; -------------------------------------------------------------------------------------- 25e6 25e6 seq_en_micro 0 typ_c_adr 32 GP0d 25e7 25e7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 25e8 0x25e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var seq_en_micro 0 typ_b_adr 0d GP0d typ_c_lit 1 typ_frame 9 25e8 25e8 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 25e9 25e9 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25ea 0x25ea seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25ea 25ea seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25eb 0x25eb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 25eb 25eb seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 25ec 25ec fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25ed 25ed ioc_fiubs 1 val typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 25ee 25ee seq_b_timing 1 Latch Condition; Flow J cc=True 0x25f0 seq_br_type 1 Branch True seq_branch_adr 25f0 0x25f0 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B 25ef 25ef typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 25f0 25f0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 25f1 25f1 fiu_vmux_sel 1 fill value; Flow J cc=True 0x25f3 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 25f3 0x25f3 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f2 25f2 seq_br_type 3 Unconditional Branch; Flow J 0x25f3 seq_branch_adr 25f3 0x25f3 seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 25f3 25f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2618 seq_br_type 1 Branch True seq_branch_adr 2618 0x2618 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25f4 25f4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25f5 25f5 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 25f6 25f6 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x25f7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 25f7 0x25f7 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 25f7 25f7 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x260c ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 260c 0x260c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 25f8 25f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x25de seq_br_type 5 Call True seq_branch_adr 25de 0x25de seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 25f9 25f9 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25fa 25fa ioc_fiubs 2 typ ; Flow J cc=False 0x2600 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2600 0x2600 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 25fb 25fb fiu_load_tar 1 hold_tar; Flow C cc=True 0x2608 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2608 0x2608 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 25fc 25fc ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 25fd 25fd seq_b_timing 1 Latch Condition; Flow C cc=False 0x2603 seq_br_type 4 Call False seq_branch_adr 2603 0x2603 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 03 GP03 typ_c_adr 30 GP0f 25fe 25fe ioc_fiubs 1 val ; Flow J cc=True 0x25f7 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 25f7 0x25f7 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25ff 25ff ioc_fiubs 1 val ; Flow J 0x25f7 seq_br_type 3 Unconditional Branch seq_branch_adr 25f7 0x25f7 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2600 2600 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 2601 2601 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2608 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2608 0x2608 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2602 2602 fiu_mem_start 3 start-wr; Flow J 0x25fe ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 25fe 0x25fe seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 2603 ; -------------------------------------------------------------------------------------- 2603 ; Comes from: 2603 ; 25fd C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2603 ; -------------------------------------------------------------------------------------- 2603 2603 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2605 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2605 0x2605 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2604 2604 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2605 2605 seq_br_type 4 Call False; Flow C cc=False 0x25ce seq_branch_adr 25ce 0x25ce seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2606 2606 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 2607 0x2607 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2607 2607 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2608 ; -------------------------------------------------------------------------------------- 2608 ; Comes from: 2608 ; 25fb C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2608 ; 2601 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2608 ; -------------------------------------------------------------------------------------- 2608 2608 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x25e6 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25e6 0x25e6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2609 2609 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 260a 0x260a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 260a 260a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 260b 0x260b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 260b 260b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 260c 260c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x260e fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 260e 0x260e seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 260d 260d val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 260e 260e fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2614 fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 2614 0x2614 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 03 GP03 260f 260f fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2610 2610 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2555 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2555 0x2555 seq_en_micro 0 2611 2611 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2613 seq_br_type 1 Branch True seq_branch_adr 2613 0x2613 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 2612 2612 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2613 2613 seq_br_type 3 Unconditional Branch; Flow J 0x25f3 seq_branch_adr 25f3 0x25f3 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 2614 2614 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 2615 2615 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2613 seq_br_type 1 Branch True seq_branch_adr 2613 0x2613 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2616 2616 seq_br_type 3 Unconditional Branch; Flow J 0x2612 seq_branch_adr 2612 0x2612 2617 ; -------------------------------------------------------------------------------------- 2617 ; Comes from: 2617 ; 2619 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2617 ; 261a C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2617 ; -------------------------------------------------------------------------------------- 2617 2617 seq_br_type a Unconditional Return; Flow R val_rand 1 INC_LOOP_COUNTER 2618 2618 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2619 2619 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2617 seq_br_type 5 Call True seq_branch_adr 2617 0x2617 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 261a 261a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2617 seq_br_type 5 Call True seq_branch_adr 2617 0x2617 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 261b 261b seq_b_timing 0 Early Condition; Flow J cc=False 0x261b seq_br_type 0 Branch False seq_branch_adr 261b 0x261b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_rand 2 DEC_LOOP_COUNTER 261c 261c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2625 seq_br_type 1 Branch True seq_branch_adr 2625 0x2625 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 typ_rand d SET_PASS_PRIVACY_BIT 261d 261d typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 261e 261e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 261f 261f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2625 seq_br_type 0 Branch False seq_branch_adr 2625 0x2625 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 2620 2620 seq_br_type 1 Branch True; Flow J cc=True 0x2624 seq_branch_adr 2624 0x2624 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 2621 2621 seq_b_timing 0 Early Condition; Flow J cc=False 0x2624 seq_br_type 0 Branch False seq_branch_adr 2624 0x2624 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2622 2622 seq_b_timing 0 Early Condition; Flow J cc=False 0x2624 seq_br_type 0 Branch False seq_branch_adr 2624 0x2624 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2623 2623 seq_b_timing 0 Early Condition; Flow J cc=True 0x2625 seq_br_type 1 Branch True seq_branch_adr 2625 0x2625 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 2624 2624 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 2625 2625 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2626 2626 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR11:13 val_frame 11 2627 2627 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2628 2628 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2629 2629 ioc_load_wdr 0 ; Flow J cc=True 0x262b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 262b 0x262b typ_b_adr 03 GP03 val_b_adr 03 GP03 262a 262a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 262b 262b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 262c ; -------------------------------------------------------------------------------------- 262c ; 0x0306 Complete_Type Variant_Record,By_Renaming 262c ; -------------------------------------------------------------------------------------- 262c MACRO_Complete_Type_Variant_Record,By_Renaming: 262c 262c dispatch_brk_class 4 ; Flow C 0x32fe dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 262c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 262d 262d fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 262e 262e fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 262f 262f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 2630 2630 fiu_load_var 1 hold_var; Flow C cc=False 0x32a9 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2631 2631 fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2632 2632 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3279 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2633 2633 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32ab fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2634 2634 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 27 VR08:07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 8 2635 2635 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 2636 2636 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x2637 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32a9 0x32a9 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER 2637 2637 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2639 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2639 0x2639 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2638 2638 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2639 2639 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 263a 263a fiu_mem_start 3 start-wr; Flow J cc=True 0x2638 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2638 0x2638 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 263b 263b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 263c ; -------------------------------------------------------------------------------------- 263c ; Comes from: 263c ; 2658 C from color MACRO_Declare_Type_Variant_Record,Defined 263c ; 2694 C from color MACRO_Declare_Type_Variant_Record,Defined 263c ; -------------------------------------------------------------------------------------- 263c 263c seq_b_timing 1 Latch Condition; Flow C cc=False 0x3279 seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 263d 263d ioc_fiubs 1 val ; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 39 GP06 val_c_mux_sel 2 ALU 263e 263e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x2642 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2642 0x2642 typ_a_adr 1f TOP - 1 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 263f 263f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2648 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2648 0x2648 typ_a_adr 1c TOP - 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2640 2640 fiu_len_fill_lit 7d zero-fill 0x3d; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1b TOP - 5 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1b TOP - 5 2641 2641 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x264b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 264b 0x264b typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1c TOP - 4 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2642 2642 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_b_adr 1c TOP - 4 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2643 2643 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2644 2644 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2645 2645 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2648 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2648 0x2648 typ_a_adr 1b TOP - 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1b TOP - 5 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2646 2646 fiu_len_fill_lit 7d zero-fill 0x3d; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1a TOP - 6 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1a TOP - 6 2647 2647 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x264b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 264b 0x264b typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1b TOP - 5 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2648 ; -------------------------------------------------------------------------------------- 2648 ; Comes from: 2648 ; 263f C from color 0x263c 2648 ; 2645 C from color 0x263c 2648 ; -------------------------------------------------------------------------------------- 2648 2648 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR05:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2649 2649 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 264a 264a fiu_len_fill_lit 78 zero-fill 0x38; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 28 VR05:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 264b 264b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 264c 264c fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ad fiu_offs_lit 50 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 264d 264d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 264e 264e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR05:00 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 26 VR05:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 264f 264f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2650 2650 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2651 0x2651 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 2651 2651 typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2652 2652 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fe fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2653 2653 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2654 2654 ioc_load_wdr 0 ; Flow C cc=True 0x2a84 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 2655 2655 ioc_tvbs 1 typ+fiu; Flow J 0x2650 seq_br_type 3 Unconditional Branch seq_branch_adr 2650 0x2650 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2656 ; -------------------------------------------------------------------------------------- 2656 ; 0x031e Declare_Type Variant_Record,Defined,Visible 2656 ; -------------------------------------------------------------------------------------- 2656 MACRO_Declare_Type_Variant_Record,Defined,Visible: 2656 2656 dispatch_brk_class 4 ; Flow J 0x2657 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2656 seq_br_type 2 Push (branch address) seq_branch_adr 2659 0x2659 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 2657 2657 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x263c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 263c 0x263c seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2658 ; -------------------------------------------------------------------------------------- 2658 ; 0x031d Declare_Type Variant_Record,Defined 2658 ; -------------------------------------------------------------------------------------- 2658 MACRO_Declare_Type_Variant_Record,Defined: 2658 2658 dispatch_brk_class 4 ; Flow C 0x263c dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2658 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 263c 0x263c seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2659 2659 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2696 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2696 0x2696 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 265a 265a ioc_fiubs 0 fiu ; Flow C 0x26b8 seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 265b 265b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 265c 265c typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 265d 265d typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 265e 265e seq_b_timing 0 Early Condition; Flow C cc=False 0x2685 seq_br_type 4 Call False seq_branch_adr 2685 0x2685 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 265f 265f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2660 2660 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x266a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 266a 0x266a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2661 2661 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2662 2662 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2663 2663 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ad fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2664 2664 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2665 2665 seq_br_type 7 Unconditional Call; Flow C 0x26b8 seq_branch_adr 26b8 0x26b8 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2666 2666 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2667 2667 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2678 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2678 0x2678 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2668 2668 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x265f seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 265f 0x265f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2669 2669 ioc_fiubs 0 fiu ; Flow J 0x265f seq_br_type 3 Unconditional Branch seq_branch_adr 265f 0x265f val_c_adr 37 GP08 val_c_source 0 FIU_BUS 266a 266a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR07:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 03 GP03 val_b_adr 1c TOP - 4 266b 266b ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 266c 266c fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x2680 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2680 0x2680 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 1e TOP - 2 266d 266d ioc_fiubs 0 fiu ; Flow C cc=True 0x32ad ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 266e 266e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_b_adr 10 TOP 266f 266f ioc_fiubs 0 fiu typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2670 2670 seq_b_timing 0 Early Condition; Flow C cc=False 0x2686 seq_br_type 4 Call False seq_branch_adr 2686 0x2686 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2671 2671 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 08 GP08 2672 2672 fiu_mem_start 4 continue ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 2673 2673 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 2674 2674 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2675 2675 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 23 VR08:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 2676 2676 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR08:1d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 2677 2677 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2678 ; -------------------------------------------------------------------------------------- 2678 ; Comes from: 2678 ; 2667 C #0x0 from color MACRO_Declare_Type_Variant_Record,Defined 2678 ; 26b4 C #0x0 from color MACRO_Declare_Type_Variant_Record,Defined 2678 ; -------------------------------------------------------------------------------------- 2678 2678 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2679 2679 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 267a 267a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 267b 267b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2679 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2679 0x2679 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 267c 267c fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 267d 267d fiu_mem_start 3 start-wr; Flow J 0x2679 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2679 0x2679 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 267e 267e fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 267f 267f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2679 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2679 0x2679 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2680 ; -------------------------------------------------------------------------------------- 2680 ; Comes from: 2680 ; 266c C False from color 0x266c 2680 ; -------------------------------------------------------------------------------------- 2680 2680 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2681 0x2681 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2681 2681 ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2682 0x2682 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2682 2682 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x2684 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 2684 0x2684 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 2683 2683 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 2684 0x2684 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 1c TOP - 4 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2684 2684 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f 2685 ; -------------------------------------------------------------------------------------- 2685 ; Comes from: 2685 ; 265e C False from color MACRO_Declare_Type_Variant_Record,Defined 2685 ; 269d C True from color MACRO_Declare_Type_Variant_Record,Defined 2685 ; -------------------------------------------------------------------------------------- 2685 2685 seq_br_type a Unconditional Return; Flow R typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 2686 ; -------------------------------------------------------------------------------------- 2686 ; Comes from: 2686 ; 2670 C False from color 0x266c 2686 ; -------------------------------------------------------------------------------------- 2686 2686 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2687 0x2687 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2687 2687 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2688 2688 fiu_tivi_src c mar_0xc; Flow R cc=False ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2689 0x2689 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 2689 2689 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 268a 268a fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 268b 268b ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 25 TR09:05 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 08 GP08 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 268c 268c fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR08:00 typ_frame 8 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 268d 268d fiu_len_fill_lit 7d zero-fill 0x3d; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 268e 0x268e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 21 VR05:01 val_frame 5 268e 268e ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 268f 268f fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_rand 2 DEC_LOOP_COUNTER 2690 2690 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2691 2691 fiu_mem_start 8 start_wr_if_false; Flow R cc=True ; Flow J cc=False 0x2690 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2690 0x2690 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2692 ; -------------------------------------------------------------------------------------- 2692 ; 0x0316 Declare_Type Variant_Record,Defined_Incomplete,Visible 2692 ; -------------------------------------------------------------------------------------- 2692 MACRO_Declare_Type_Variant_Record,Defined_Incomplete,Visible: 2692 2692 dispatch_brk_class 4 ; Flow J 0x2693 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2692 seq_br_type 2 Push (branch address) seq_branch_adr 2695 0x2695 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 2693 2693 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x263c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 263c 0x263c seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2694 ; -------------------------------------------------------------------------------------- 2694 ; 0x0315 Declare_Type Variant_Record,Defined_Incomplete 2694 ; -------------------------------------------------------------------------------------- 2694 MACRO_Declare_Type_Variant_Record,Defined_Incomplete: 2694 2694 dispatch_brk_class 4 ; Flow C 0x263c dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2694 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 263c 0x263c seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2695 2695 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x265a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 265a 0x265a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2696 2696 ioc_fiubs 0 fiu ; Flow C 0x26b8 seq_br_type 7 Unconditional Call seq_branch_adr 26b8 0x26b8 typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2697 2697 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2698 2698 seq_br_type 7 Unconditional Call; Flow C 0x26dd seq_branch_adr 26dd 0x26dd typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2699 2699 seq_br_type 1 Branch True; Flow J cc=True 0x269d seq_branch_adr 269d 0x269d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 269a 269a val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 269b 269b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x269d seq_br_type 1 Branch True seq_branch_adr 269d 0x269d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 269c 269c typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 269d 269d ioc_fiubs 1 val ; Flow C cc=True 0x2685 seq_br_type 5 Call True seq_branch_adr 2685 0x2685 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 269e 269e seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 269f 269f typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26a0 26a0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26a1 26a1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 26a2 26a2 ioc_fiubs 0 fiu ; Flow J 0x26a3 seq_br_type 3 Unconditional Branch seq_branch_adr 26a3 0x26a3 val_a_adr 1b TOP - 5 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26a3 26a3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26a4 26a4 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x26b7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 26b7 0x26b7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26a5 26a5 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 26a6 26a6 ioc_fiubs 1 val ; Flow C cc=True 0x32ad ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 26a7 26a7 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ad fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26a8 26a8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 26a9 26a9 fiu_load_var 1 hold_var; Flow C cc=True 0x2a84 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 26aa 26aa ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26ab 26ab ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 26ac 26ac fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 26ad 26ad ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ad seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26ae 26ae seq_br_type 7 Unconditional Call; Flow C 0x26b8 seq_branch_adr 26b8 0x26b8 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26af 26af val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 26b0 26b0 ioc_fiubs 2 typ ; Flow J cc=True 0x26b2 seq_br_type 1 Branch True seq_branch_adr 26b2 0x26b2 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26b1 26b1 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26b2 26b2 seq_br_type 7 Unconditional Call; Flow C 0x26dd seq_branch_adr 26dd 0x26dd val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 26b3 26b3 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 26b4 26b4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2678 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2678 0x2678 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 26b5 26b5 seq_br_type 0 Branch False; Flow J cc=False 0x26a3 seq_branch_adr 26a3 0x26a3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 26b6 26b6 seq_br_type 3 Unconditional Branch; Flow J 0x26a3 seq_branch_adr 26a3 0x26a3 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26b7 26b7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x266b fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 266b 0x266b typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_b_adr 1b TOP - 5 26b8 ; -------------------------------------------------------------------------------------- 26b8 ; Comes from: 26b8 ; 1e87 C from color MACRO_Declare_Type_Record,Defined 26b8 ; 1eac C from color MACRO_Complete_Type_Record,By_Defining 26b8 ; 2544 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b8 ; 2550 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b8 ; 2586 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b8 ; 25a1 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b8 ; 265a C from color MACRO_Declare_Type_Variant_Record,Defined 26b8 ; 2665 C from color MACRO_Declare_Type_Variant_Record,Defined 26b8 ; 2696 C from color MACRO_Declare_Type_Variant_Record,Defined 26b8 ; 26ae C from color MACRO_Declare_Type_Variant_Record,Defined 26b8 ; -------------------------------------------------------------------------------------- 26b8 26b8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26b9 0x26b9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 26b9 26b9 seq_br_type 3 Unconditional Branch; Flow J 0x26bb seq_branch_adr 26bb 0x26bb typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 26ba 26ba ioc_tvbs 1 typ+fiu; Flow C cc=False 0x26d8 seq_br_type 4 Call False seq_branch_adr 26d8 0x26d8 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 26bb 26bb fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 26bc 26bc fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x26bf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26bf 0x26bf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 26bd 26bd fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x26d5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 26d5 0x26d5 seq_en_micro 0 26be 26be seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 26bf ; -------------------------------------------------------------------------------------- 26bf ; Comes from: 26bf ; 26bc C #0x0 from color 0x26b8 26bf ; -------------------------------------------------------------------------------------- 26bf 26bf fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d5 0x26d5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c0 26c0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d5 0x26d5 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c1 26c1 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d5 0x26d5 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c2 26c2 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d5 0x26d5 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c3 26c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c4 26c4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c5 26c5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c6 26c6 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d5 0x26d5 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c7 26c7 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d5 0x26d5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 26c8 26c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26cf fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26cf 0x26cf typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26c9 26c9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26ca 26ca seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26cb 26cb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26cc 26cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26cd 26cd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26ce 26ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26cf 26cf fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d5 0x26d5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 1 RESTORE_RDR val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26d0 26d0 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x26d2 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d2 0x26d2 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE 26d1 26d1 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 26d2 26d2 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d5 0x26d5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 26d3 26d3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x26d5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d5 0x26d5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26d4 26d4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a9 seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26d5 26d5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26d9 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26d9 0x26d9 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU 26d6 26d6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x26ba fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 26ba 0x26ba seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 3c VR07:1c val_frame 7 26d7 26d7 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 26d8 0x26d8 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26d8 26d8 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 35 TR07:15 typ_frame 7 val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26d9 ; -------------------------------------------------------------------------------------- 26d9 ; Comes from: 26d9 ; 26f7 C #0x0 from color 0x26e5 26d9 ; -------------------------------------------------------------------------------------- 26d9 26d9 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26da 26da ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26db 26db ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26dc 26dc fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_offs_lit 40 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26dd ; -------------------------------------------------------------------------------------- 26dd ; Comes from: 26dd ; 2588 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26dd ; 25a5 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26dd ; 2698 C from color MACRO_Declare_Type_Variant_Record,Defined 26dd ; 26b2 C from color MACRO_Declare_Type_Variant_Record,Defined 26dd ; -------------------------------------------------------------------------------------- 26dd 26dd fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26de 0x26de seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26de 26de seq_br_type 3 Unconditional Branch; Flow J 0x26e0 seq_branch_adr 26e0 0x26e0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 2b VR08:0b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 26df 26df seq_br_type 4 Call False; Flow C cc=False 0x26d8 seq_branch_adr 26d8 0x26d8 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 2c VR07:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 26e0 26e0 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 26e1 26e1 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x26e4 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26e4 0x26e4 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26e2 26e2 fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x26f7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 26f7 0x26f7 seq_en_micro 0 26e3 26e3 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 26e4 ; -------------------------------------------------------------------------------------- 26e4 ; Comes from: 26e4 ; 26e1 C #0x0 from color 0x26b8 26e4 ; -------------------------------------------------------------------------------------- 26e4 26e4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e5 26e5 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x26ec fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26ec 0x26ec seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 26e6 26e6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e7 26e7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e8 26e8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e9 26e9 fiu_mem_start 2 start-rd; Flow J 0x26ee ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 26ee 0x26ee typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 26ea 26ea fiu_mem_start 2 start-rd; Flow J 0x26ef ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 26ef 0x26ef typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 26eb 26eb seq_br_type 3 Unconditional Branch; Flow J 0x26f0 seq_branch_adr 26f0 0x26f0 26ec 26ec seq_b_timing 0 Early Condition; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 26ed 26ed fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26f7 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26f7 0x26f7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 26ee 26ee seq_br_type 3 Unconditional Branch; Flow J 0x26f3 seq_branch_adr 26f3 0x26f3 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26ef 26ef seq_br_type 3 Unconditional Branch; Flow J 0x26f3 seq_branch_adr 26f3 0x26f3 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 7 26f0 26f0 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 5 26f1 26f1 fiu_len_fill_lit 7a zero-fill 0x3a fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 3f VR02:1f val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 26f2 26f2 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26f3 26f3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 26f4 26f4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x26f6 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 26f6 0x26f6 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_c_adr 30 GP0f val_a_adr 31 VR02:11 val_c_adr 30 GP0f val_frame 2 26f5 26f5 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26f6 26f6 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26f7 0x26f7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_b_adr 0f GP0f 26f7 ; -------------------------------------------------------------------------------------- 26f7 ; Comes from: 26f7 ; 26e2 C True from color 0x26e2 26f7 ; -------------------------------------------------------------------------------------- 26f7 26f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26d9 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26d9 0x26d9 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 26f8 26f8 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x26df ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 26df 0x26df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26f9 26f9 fiu_load_var 1 hold_var; Flow C cc=False 0x26fb fiu_tivi_src 1 tar_val seq_br_type 4 Call False seq_branch_adr 26fb 0x26fb seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 0 PASS_A 26fa 26fa fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True ; Flow J cc=False 0x26d8 fiu_offs_lit 50 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 26d8 0x26d8 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26fb ; -------------------------------------------------------------------------------------- 26fb ; Comes from: 26fb ; 26f9 C False from color 0x26b8 26fb ; -------------------------------------------------------------------------------------- 26fb 26fb seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26fc ; -------------------------------------------------------------------------------------- 26fc ; Comes from: 26fc ; 1463 C True from color 0x09ac 26fc ; 174b C from color 0x09ae 26fc ; 17f2 C from color 0x09ad 26fc ; 1834 C True from color 0x09ab 26fc ; 1b76 C from color 0x1b75 26fc ; 1dbf C from color 0x0000 26fc ; -------------------------------------------------------------------------------------- 26fc 26fc fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 26fd 26fd fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2708 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2708 0x2708 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 26fe 26fe fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2703 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2703 0x2703 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 26ff 26ff fiu_fill_mode_src 0 ; Flow J 0x2700 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2700 0x2700 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2700 2700 fiu_fill_mode_src 0 ; Flow J cc=False 0x2705 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2705 0x2705 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2701 2701 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2702 2702 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2703 2703 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2704 2704 fiu_fill_mode_src 0 ; Flow J 0x2700 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2700 0x2700 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2705 2705 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2706 2706 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2707 2707 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2708 2708 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x270f fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 270f 0x270f seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2709 2709 fiu_load_tar 1 hold_tar; Flow J cc=True 0x271c fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 271c 0x271c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 270a 270a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 270b 270b fiu_fill_mode_src 0 ; Flow J 0x2712 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2712 0x2712 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 270c 270c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 270d 270d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x26fe fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 26fe 0x26fe seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 270e 270e fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2709 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2709 0x2709 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 270f 270f fiu_load_tar 1 hold_tar; Flow J cc=True 0x271c fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 271c 0x271c 2710 2710 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2711 2711 fiu_fill_mode_src 0 ; Flow J 0x2712 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2712 0x2712 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2712 2712 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2716 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2716 0x2716 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2713 2713 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA 2714 2714 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2719 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2715 2715 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2702 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2702 0x2702 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2716 2716 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2717 2717 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2719 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2718 2718 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2702 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2702 0x2702 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2719 ; -------------------------------------------------------------------------------------- 2719 ; Comes from: 2719 ; 2714 C True from color 0x26fc 2719 ; 2717 C True from color 0x26fc 2719 ; 2730 C True from color 0x26fc 2719 ; 2734 C True from color 0x26fc 2719 ; 273b C True from color 0x26fc 2719 ; 2741 C True from color 0x26fc 2719 ; 2746 C True from color 0x26fc 2719 ; -------------------------------------------------------------------------------------- 2719 2719 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 271a 271a fiu_mem_start 2 start-rd 271b 271b seq_br_type a Unconditional Return; Flow R 271c 271c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2723 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2723 0x2723 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 271d 271d fiu_fill_mode_src 0 ; Flow J cc=True 0x272b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 272b 0x272b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 271e 271e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 271f 271f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2727 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2727 0x2727 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2720 2720 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2721 2721 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2722 2722 ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x272b seq_br_type 9 Return False seq_branch_adr 272b 0x272b seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2723 2723 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 2724 2724 fiu_fill_mode_src 0 ; Flow J cc=True 0x272b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 272b 0x272b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2725 2725 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2726 2726 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2720 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2720 0x2720 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2727 2727 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2728 2728 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2729 2729 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 272a 0x272a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 272a 272a ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 272b 0x272b seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 272b 272b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x270c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 270c 0x270c seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 272c 272c fiu_mem_start 4 continue; Flow J cc=False 0x2736 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2736 0x2736 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 272d 272d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 272e 272e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329c seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 272f 272f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2734 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2734 0x2734 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2730 2730 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2719 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2731 2731 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2732 0x2732 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2732 2732 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2733 2733 fiu_load_oreg 1 hold_oreg; Flow J 0x272f fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 272f 0x272f typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2734 2734 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2719 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2735 2735 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x270c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270c 0x270c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2736 2736 fiu_load_var 1 hold_var; Flow J cc=False 0x2744 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2744 0x2744 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2737 2737 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2738 2738 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 2739 2739 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329c seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 273a 273a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x273f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 273f 0x273f typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 273b 273b fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2719 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 273c 273c ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273d 0x273d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 273d 273d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 273e 273e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x273a fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 273a 0x273a typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 273f 273f fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2740 2740 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2741 0x2741 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2741 2741 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2719 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT 2742 2742 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2743 0x2743 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2743 2743 ioc_tvbs 2 fiu+val; Flow R cc=True ; Flow J cc=False 0x270c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270c 0x270c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2744 2744 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2745 2745 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2746 2746 ioc_fiubs 0 fiu ; Flow C cc=True 0x2719 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2719 0x2719 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2747 2747 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x270c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270c 0x270c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2748 ; -------------------------------------------------------------------------------------- 2748 ; 0x02cb Declare_Variable Entry 2748 ; -------------------------------------------------------------------------------------- 2748 MACRO_Declare_Variable_Entry: 2748 2748 dispatch_brk_class 4 ; Flow C cc=False 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2748 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 6 2749 2749 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 274a 274a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 val_rand a PASS_B_HIGH 274b 274b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x274f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 274f 0x274f seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 274c 274c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 274d 274d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3279 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 274e 274e fiu_len_fill_lit 58 zero-fill 0x18; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 1c ? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 274f ; -------------------------------------------------------------------------------------- 274f ; Comes from: 274f ; 274b C True from color MACRO_Declare_Variable_Entry 274f ; 2755 C True from color 0x0000 274f ; -------------------------------------------------------------------------------------- 274f 274f seq_br_type a Unconditional Return; Flow R val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2750 ; -------------------------------------------------------------------------------------- 2750 ; 0x02c9 Declare_Variable Family 2750 ; -------------------------------------------------------------------------------------- 2750 MACRO_Declare_Variable_Family: 2750 2750 dispatch_brk_class 4 ; Flow C cc=False 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2750 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 6 2751 2751 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2752 2752 fiu_tivi_src 1 tar_val; Flow C cc=False 0x32ac ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2753 2753 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x2762 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2762 0x2762 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 2754 2754 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3279 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 3279 0x3279 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2755 2755 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x274f seq_br_type 5 Call True seq_branch_adr 274f 0x274f seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 val_rand a PASS_B_HIGH 2756 2756 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x275d seq_br_type 5 Call True seq_branch_adr 275d 0x275d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 2757 2757 fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 2758 2758 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2758 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2758 0x2758 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2759 2759 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x2760 fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2760 0x2760 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 20 TOP - 0x1 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 275a 275a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 275b 275b fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 275c 275c fiu_mem_start 3 start-wr; Flow J 0x2758 seq_br_type 3 Unconditional Branch seq_branch_adr 2758 0x2758 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A val_a_adr 30 VR05:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 275d ; -------------------------------------------------------------------------------------- 275d ; Comes from: 275d ; 2756 C True from color 0x0000 275d ; -------------------------------------------------------------------------------------- 275d 275d fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 275e 275e ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 275f 275f fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf67 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f67 0x0f67 2760 2760 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 02 GP02 2761 2761 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 3b TR06:1b typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2762 2762 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA 2763 2763 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32ac ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2764 2764 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2760 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2760 0x2760 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2765 2765 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2766 ; -------------------------------------------------------------------------------------- 2766 ; 0x02cf Declare_Variable Select 2766 ; -------------------------------------------------------------------------------------- 2766 MACRO_Declare_Variable_Select: 2766 2766 dispatch_brk_class 4 ; Flow J 0x2769 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2766 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2769 0x2769 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 34 TR05:14 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2767 ; -------------------------------------------------------------------------------------- 2767 ; Comes from: 2767 ; 276a C True from color 0x0000 2767 ; -------------------------------------------------------------------------------------- 2767 2767 seq_br_type a Unconditional Return; Flow R typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2768 ; -------------------------------------------------------------------------------------- 2768 ; 0x02ce Declare_Variable Select,Choice_Open 2768 ; -------------------------------------------------------------------------------------- 2768 MACRO_Declare_Variable_Select,Choice_Open: 2768 2768 dispatch_brk_class 4 ; Flow J 0x2769 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2768 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2769 0x2769 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 20 TR06:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2769 2769 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2783 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2783 0x2783 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 1d TOP - 3 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 276a 276a seq_b_timing 1 Latch Condition; Flow C cc=True 0x2767 seq_br_type 5 Call True seq_branch_adr 2767 0x2767 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 276b 276b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x32b2 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32b2 0x32b2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 276c 276c fiu_load_var 1 hold_var; Flow C cc=True 0x32ac fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 276d 276d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 30 VR06:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 276e 276e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 3e TR05:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1 A_PLUS_B val_b_adr 2f VR05:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 276f 276f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2776 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2776 0x2776 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2770 2770 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 2771 2771 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2772 2772 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2773 2773 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_frame 2 2774 2774 ioc_load_wdr 0 ; Flow C cc=True 0x2a84 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2775 2775 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x2770 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2770 0x2770 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2776 2776 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x277e ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 277e 0x277e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2777 2777 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 2778 2778 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2779 2779 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 277a 277a fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 277b 277b fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 36 TR02:16 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 277c 277c fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x2a84 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_random 02 ? typ_a_adr 14 ZEROS typ_b_adr 02 GP02 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 277d 277d fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2777 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2777 0x2777 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 277e 277e fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x2780 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2780 0x2780 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 277f 277f fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2780 2780 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 1 START_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2781 2781 ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2782 2782 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2783 2783 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x32b2 seq_br_type 9 Return False seq_branch_adr 32b2 0x32b2 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2a TR07:0a typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 2784 ; -------------------------------------------------------------------------------------- 2784 ; 0x0271 Execute Discrete,Times 2784 ; -------------------------------------------------------------------------------------- 2784 MACRO_Execute_Discrete,Times: 2784 2784 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2784 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 2785 2785 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2786 0x2786 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 2786 2786 ioc_fiubs 0 fiu ; Flow J cc=True 0x2797 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2797 0x2797 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2787 2787 seq_b_timing 1 Latch Condition; Flow J cc=False 0x278a seq_br_type 0 Branch False seq_branch_adr 278a 0x278a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2788 2788 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2789 2789 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 278a 278a seq_b_timing 1 Latch Condition; Flow J cc=True 0x2790 seq_br_type 1 Branch True seq_branch_adr 2790 0x2790 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 278b 278b seq_b_timing 1 Latch Condition; Flow J cc=True 0x278d seq_br_type 1 Branch True seq_branch_adr 278d 0x278d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 278c 278c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x278f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 278f 0x278f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 278d 278d seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 278e 278e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 278f 278f fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2790 2790 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 2791 2791 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2793 seq_br_type 0 Branch False seq_branch_adr 2793 0x2793 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2792 2792 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2796 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2796 0x2796 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 2793 2793 fiu_load_var 1 hold_var; Flow C cc=True 0x3278 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2794 2794 fiu_load_var 1 hold_var; Flow C cc=False 0x3278 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 2795 2795 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2789 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2796 2796 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2797 2797 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2798 2798 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x279d seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 279d 0x279d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2799 2799 ioc_fiubs 1 val ; Flow J cc=True 0x279e ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 279e 0x279e seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 279a 279a fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 279b 279b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 279c 0x279c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 279c 279c ioc_fiubs 0 fiu ; Flow J 0x2787 seq_br_type 3 Unconditional Branch seq_branch_adr 2787 0x2787 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 279d 279d fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 11 TOP + 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 279e 279e ioc_fiubs 1 val ; Flow J cc=True 0x27af seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27af 0x27af seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 279f 279f ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27a0 27a0 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27a2 seq_br_type 0 Branch False seq_branch_adr 27a2 0x27a2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27a1 27a1 seq_br_type 3 Unconditional Branch; Flow J 0x27af seq_branch_adr 27af 0x27af seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27a2 27a2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27a8 seq_br_type 1 Branch True seq_branch_adr 27a8 0x27a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27a3 27a3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27a5 seq_br_type 1 Branch True seq_branch_adr 27a5 0x27a5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27a4 27a4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27a7 0x27a7 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27a5 27a5 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27a6 27a6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 27a7 27a7 ioc_tvbs 1 typ+fiu; Flow J 0x27af seq_br_type 3 Unconditional Branch seq_branch_adr 27af 0x27af seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27a8 27a8 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27a9 27a9 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27ab seq_br_type 0 Branch False seq_branch_adr 27ab 0x27ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27aa 27aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27ae fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27ae 0x27ae seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27ab 27ab fiu_load_var 1 hold_var; Flow C cc=True 0x3278 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27ac 27ac fiu_load_var 1 hold_var; Flow C cc=False 0x3278 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27ad 27ad fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27af fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27af 0x27af seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27ae 27ae ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27af 27af fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 27b0 ; -------------------------------------------------------------------------------------- 27b0 ; 0x026d Execute Discrete,Exponentiate 27b0 ; -------------------------------------------------------------------------------------- 27b0 MACRO_Execute_Discrete,Exponentiate: 27b0 27b0 dispatch_brk_class 8 ; Flow J cc=False 0x27d1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 27b0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 27d1 0x27d1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 2 27b1 27b1 ioc_fiubs 1 val ; Flow C cc=True 0x27db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 27db 0x27db seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 27b2 27b2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu 27b3 27b3 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27b4 ; Flow J cc=#0x0 0x27b4 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27b4 0x27b4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27b4 27b4 ioc_fiubs 1 val ; Flow J 0x27b6 seq_br_type 3 Unconditional Branch seq_branch_adr 27b6 0x27b6 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 27b5 27b5 fiu_load_var 1 hold_var; Flow J 0x27bd fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 27bd 0x27bd seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27b6 27b6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x27ba fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27ba 0x27ba seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 27b7 27b7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b8 27b8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b9 27b9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27ba 27ba fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27bb ; Flow J cc=#0x0 0x27b4 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 27b4 0x27b4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 27bb 27bb seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 27bc 27bc ioc_fiubs 0 fiu ; Flow J 0x27ba seq_br_type 3 Unconditional Branch seq_branch_adr 27ba 0x27ba 27bd 27bd ioc_fiubs 1 val ; Flow J cc=True 0x27cd seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27cd 0x27cd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27be 27be ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27bf 27bf seq_b_timing 1 Latch Condition; Flow J cc=False 0x27c1 seq_br_type 0 Branch False seq_branch_adr 27c1 0x27c1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27c0 27c0 seq_br_type 3 Unconditional Branch; Flow J 0x27cd seq_branch_adr 27cd 0x27cd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27c1 27c1 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27c7 seq_br_type 1 Branch True seq_branch_adr 27c7 0x27c7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27c2 27c2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27c4 seq_br_type 1 Branch True seq_branch_adr 27c4 0x27c4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27c3 27c3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27c6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27c6 0x27c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27c4 27c4 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27c5 27c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 0 PASS_A 27c6 27c6 ioc_tvbs 1 typ+fiu; Flow J 0x27cd seq_br_type 3 Unconditional Branch seq_branch_adr 27cd 0x27cd seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27c7 27c7 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27c8 27c8 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27ca seq_br_type 0 Branch False seq_branch_adr 27ca 0x27ca seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27c9 27c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27c6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27c6 0x27c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27ca 27ca fiu_load_var 1 hold_var; Flow C cc=True 0x3278 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27cb 27cb fiu_load_var 1 hold_var; Flow C cc=False 0x3278 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27cc 27cc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27cd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27cd 0x27cd seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27cd 27cd ioc_fiubs 2 typ ; Flow J cc=True 0x27b4 seq_br_type 1 Branch True seq_branch_adr 27b4 0x27b4 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 27ce 27ce seq_b_timing 0 Early Condition; Flow J cc=False 0x27d0 seq_br_type 0 Branch False seq_branch_adr 27d0 0x27d0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 27cf 27cf fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27d0 27d0 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27d1 27d1 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27da seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27da 0x27da seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A 27d2 27d2 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27d5 seq_br_type 1 Branch True seq_branch_adr 27d5 0x27d5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand b DIVIDE 27d3 27d3 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27cf seq_br_type 1 Branch True seq_branch_adr 27cf 0x27cf seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27d4 27d4 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 27d5 27d5 ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 27d6 27d6 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 27d7 0x27d7 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 27d7 27d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d8 27d8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d9 27d9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2789 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2789 0x2789 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27da 27da fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 27db 27db fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x27de fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 27de 0x27de seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 27dc 27dc seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 27dd 0x27dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_frame 2 27dd 27dd fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x27e2 fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27e2 0x27e2 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 05 GP05 27de 27de fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27df ; Flow J cc=#0x0 0x27df fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27df 0x27df seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 27df 27df fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2789 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2789 0x2789 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 6 27e0 27e0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 27e1 27e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2789 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2789 0x2789 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 5 27e2 27e2 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27e3 ; Flow J cc=#0x0 0x27e3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27e3 0x27e3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 27e3 27e3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 27e4 27e4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 27e5 27e5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 27e6 27e6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27e7 27e7 <halt> ; Flow R 27e8 ; -------------------------------------------------------------------------------------- 27e8 ; 0x0141 Execute Discrete,Multiply_And_Scale 27e8 ; -------------------------------------------------------------------------------------- 27e8 MACRO_Execute_Discrete,Multiply_And_Scale: 27e8 27e8 dispatch_brk_class 8 ; Flow C cc=False 0x2802 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 27e8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 2802 0x2802 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 27e9 27e9 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x2804 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 2804 0x2804 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 27ea 27ea fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 27eb 27eb fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 27ec 27ec fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 27ed 27ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27ee 27ee seq_br_type 0 Branch False; Flow J cc=False 0x2805 seq_branch_adr 2805 0x2805 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 2b TR02:0b typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27ef 27ef ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 27f0 27f0 seq_b_timing 0 Early Condition; Flow J cc=True 0x27ff seq_br_type 1 Branch True seq_branch_adr 27ff 0x27ff seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 27f1 27f1 ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR11:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 27f2 27f2 seq_b_timing 0 Early Condition; Flow J cc=True 0x27fa seq_br_type 1 Branch True seq_branch_adr 27fa 0x27fa seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 27f3 27f3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27f4 27f4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_b_src 2 Bits 32…47 27f5 27f5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 27f6 27f6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 27f7 27f7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 27f8 27f8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27f9 27f9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 27fa 27fa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27fb 27fb seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27fc 27fc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 27fd 27fd seq_br_type 3 Unconditional Branch; Flow J 0x27ff seq_branch_adr 27ff 0x27ff seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 27fe 27fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3278 seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 27ff 27ff fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27fe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27fe 0x27fe seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 0 PASS_A val_a_adr 02 GP02 2800 2800 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x27af fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27af 0x27af typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 2801 2801 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3278 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3278 0x3278 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2802 2802 seq_br_type 0 Branch False; Flow J cc=False 0x2805 seq_branch_adr 2805 0x2805 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2803 2803 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA 2804 2804 seq_br_type 1 Branch True; Flow J cc=True 0x2803 seq_branch_adr 2803 0x2803 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2805 2805 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2806 ; -------------------------------------------------------------------------------------- 2806 ; 0x0247 Execute Float,Equal 2806 ; -------------------------------------------------------------------------------------- 2806 MACRO_Execute_Float,Equal: 2806 2806 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2806 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2807 2807 <halt> ; Flow R 2808 ; -------------------------------------------------------------------------------------- 2808 ; 0x014e Execute Float,Equal_Zero 2808 ; -------------------------------------------------------------------------------------- 2808 MACRO_Execute_Float,Equal_Zero: 2808 2808 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2808 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2809 2809 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 280a ; -------------------------------------------------------------------------------------- 280a ; 0x0245 Execute Float,Greater 280a ; -------------------------------------------------------------------------------------- 280a MACRO_Execute_Float,Greater: 280a 280a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 280a ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 280b 280b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2809 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2809 0x2809 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 280c ; -------------------------------------------------------------------------------------- 280c ; 0x014c Execute Float,Greater_Zero 280c ; -------------------------------------------------------------------------------------- 280c MACRO_Execute_Float,Greater_Zero: 280c 280c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 280c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 280d 280d <halt> ; Flow R 280e ; -------------------------------------------------------------------------------------- 280e ; 0x0246 Execute Float,Not_Equal 280e ; -------------------------------------------------------------------------------------- 280e MACRO_Execute_Float,Not_Equal: 280e 280e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 280e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 280f 280f <halt> ; Flow R 2810 ; -------------------------------------------------------------------------------------- 2810 ; 0x014d Execute Float,Not_Equal_Zero 2810 ; -------------------------------------------------------------------------------------- 2810 MACRO_Execute_Float,Not_Equal_Zero: 2810 2810 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2810 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2811 2811 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2812 ; -------------------------------------------------------------------------------------- 2812 ; 0x0244 Execute Float,Less 2812 ; -------------------------------------------------------------------------------------- 2812 MACRO_Execute_Float,Less: 2812 2812 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2812 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2813 2813 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2811 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2811 0x2811 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2814 ; -------------------------------------------------------------------------------------- 2814 ; 0x014b Execute Float,Less_Zero 2814 ; -------------------------------------------------------------------------------------- 2814 MACRO_Execute_Float,Less_Zero: 2814 2814 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2814 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2815 2815 <halt> ; Flow R 2816 ; -------------------------------------------------------------------------------------- 2816 ; 0x0243 Execute Float,Greater_Equal 2816 ; -------------------------------------------------------------------------------------- 2816 MACRO_Execute_Float,Greater_Equal: 2816 2816 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2816 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2817 2817 fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2818 0x2818 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2818 2818 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2819 2819 <halt> ; Flow R 281a ; -------------------------------------------------------------------------------------- 281a ; 0x014a Execute Float,Greater_Equal_Zero 281a ; -------------------------------------------------------------------------------------- 281a MACRO_Execute_Float,Greater_Equal_Zero: 281a 281a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 281a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 281b 281b fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 281c ; -------------------------------------------------------------------------------------- 281c ; 0x0242 Execute Float,Less_Equal 281c ; -------------------------------------------------------------------------------------- 281c MACRO_Execute_Float,Less_Equal: 281c 281c dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 281c ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 281d 281d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x281b fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 281b 0x281b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 281e ; -------------------------------------------------------------------------------------- 281e ; 0x0149 Execute Float,Less_Equal_Zero 281e ; -------------------------------------------------------------------------------------- 281e MACRO_Execute_Float,Less_Equal_Zero: 281e 281e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 281e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 281f 281f <halt> ; Flow R 2820 ; -------------------------------------------------------------------------------------- 2820 ; 0x0241 Execute Float,First 2820 ; -------------------------------------------------------------------------------------- 2820 MACRO_Execute_Float,First: 2820 2820 dispatch_brk_class 8 ; Flow J 0x2821 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2820 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_br_type 3 Unconditional Branch seq_branch_adr 2821 0x2821 typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 2821 2821 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2822 ; -------------------------------------------------------------------------------------- 2822 ; 0x0240 Execute Float,Last 2822 ; -------------------------------------------------------------------------------------- 2822 MACRO_Execute_Float,Last: 2822 2822 dispatch_brk_class 8 ; Flow J 0x2821 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2822 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 2821 0x2821 typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 2823 2823 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2824 ; -------------------------------------------------------------------------------------- 2824 ; 0x023f Execute Float,Unary_Minus 2824 ; -------------------------------------------------------------------------------------- 2824 MACRO_Execute_Float,Unary_Minus: 2824 2824 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2824 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2825 2825 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2823 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2823 0x2823 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2826 ; -------------------------------------------------------------------------------------- 2826 ; 0x023e Execute Float,Absolute_Value 2826 ; -------------------------------------------------------------------------------------- 2826 MACRO_Execute_Float,Absolute_Value: 2826 2826 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2826 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2827 2827 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e seq_en_micro 0 seq_random 02 ? 2828 ; -------------------------------------------------------------------------------------- 2828 ; 0x023d Execute Float,Plus 2828 ; -------------------------------------------------------------------------------------- 2828 MACRO_Execute_Float,Plus: 2828 2828 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2828 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2829 2829 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 282a 282a fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x283b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 283b 0x283b typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP 282b 282b fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2836 fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2836 0x2836 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 282c 282c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2844 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2844 0x2844 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 282d 282d fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x282e fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 282e 0x282e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 282e 282e fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2834 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2834 0x2834 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 282f 282f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2843 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2843 0x2843 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2a TR02:0a typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2830 2830 fiu_len_fill_lit 74 zero-fill 0x34 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 05 GP05 2831 2831 fiu_fill_mode_src 0 ; Flow J cc=False 0x2846 fiu_len_fill_lit 73 zero-fill 0x33 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 2846 0x2846 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 2832 2832 fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 2833 2833 fiu_len_fill_lit 73 zero-fill 0x33; Flow R cc=False ; Flow J cc=True 0x2835 fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2835 0x2835 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2834 2834 seq_b_timing 0 Early Condition; Flow J cc=False 0x2840 seq_br_type 0 Branch False seq_branch_adr 2840 0x2840 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2835 2835 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2836 2836 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2844 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2844 0x2844 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2837 2837 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x282e fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 282e 0x282e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2838 ; -------------------------------------------------------------------------------------- 2838 ; 0x023c Execute Float,Minus 2838 ; -------------------------------------------------------------------------------------- 2838 MACRO_Execute_Float,Minus: 2838 2838 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2838 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2839 2839 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 283a 283a fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x282b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 282b 0x282b seq_random 02 ? typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 283b 283b fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2841 fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2841 0x2841 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 283c 283c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2845 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2845 0x2845 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 283d 283d fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x283e fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 283e 0x283e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 283e 283e fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x282f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 282f 0x282f seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 283f 283f seq_b_timing 0 Early Condition; Flow J cc=True 0x2835 seq_br_type 1 Branch True seq_branch_adr 2835 0x2835 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2840 2840 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2841 2841 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2845 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2845 0x2845 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 2 INC_A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2842 2842 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x283e fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 283e 0x283e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2843 2843 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2844 2844 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2845 2845 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2846 2846 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x2843 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 0 Branch False seq_branch_adr 2843 0x2843 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_frame 11 2847 2847 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2835 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2835 0x2835 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2848 ; -------------------------------------------------------------------------------------- 2848 ; 0x023b Execute Float,Times 2848 ; -------------------------------------------------------------------------------------- 2848 MACRO_Execute_Float,Times: 2848 2848 dispatch_brk_class 8 ; Flow J cc=True 0x286f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2848 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 286f 0x286f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2849 2849 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3c TR08:1c typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 284a 284a fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x286f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 286f 0x286f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 2d VR1b:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1b 284b 284b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x285c seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 285c 0x285c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 284c 284c seq_b_timing 0 Early Condition; Flow J cc=True 0x2869 seq_br_type 1 Branch True seq_branch_adr 2869 0x2869 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 284d 284d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 284e 284e seq_b_timing 1 Latch Condition; Flow J cc=True 0x2870 seq_br_type 1 Branch True seq_branch_adr 2870 0x2870 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 284f 284f seq_b_timing 1 Latch Condition; Flow J cc=True 0x2874 seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 2850 2850 seq_br_type 0 Branch False; Flow J cc=False 0x2878 seq_branch_adr 2878 0x2878 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 2851 2851 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2878 seq_br_type 1 Branch True seq_branch_adr 2878 0x2878 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 2852 2852 seq_br_type 7 Unconditional Call; Flow C 0x288e seq_branch_adr 288e 0x288e seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 2853 2853 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2854 2854 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2855 2855 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2856 2856 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2857 2857 fiu_load_var 1 hold_var; Flow J cc=True 0x285a fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 285a 0x285a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2858 2858 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_var 1 hold_var fiu_offs_lit 42 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 2859 2859 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 285a 0x285a seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 285a 285a fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 285b 285b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 285c 285c seq_b_timing 0 Early Condition; Flow J cc=True 0x2863 seq_br_type 1 Branch True seq_branch_adr 2863 0x2863 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 285d 285d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 285e 285e seq_b_timing 1 Latch Condition; Flow J cc=True 0x2870 seq_br_type 1 Branch True seq_branch_adr 2870 0x2870 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 285f 285f seq_b_timing 1 Latch Condition; Flow J cc=True 0x2874 seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 2860 2860 seq_br_type 0 Branch False; Flow J cc=False 0x2878 seq_branch_adr 2878 0x2878 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 2861 2861 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2878 seq_br_type 1 Branch True seq_branch_adr 2878 0x2878 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 2862 2862 seq_br_type 3 Unconditional Branch; Flow J 0x2853 seq_branch_adr 2853 0x2853 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 2863 2863 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2864 2864 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2870 seq_br_type 1 Branch True seq_branch_adr 2870 0x2870 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2865 2865 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2874 seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 2866 2866 seq_br_type 0 Branch False; Flow J cc=False 0x2878 seq_branch_adr 2878 0x2878 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2867 2867 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2878 seq_br_type 1 Branch True seq_branch_adr 2878 0x2878 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2868 2868 seq_br_type 3 Unconditional Branch; Flow J 0x2856 seq_branch_adr 2856 0x2856 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2869 2869 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 286a 286a seq_b_timing 1 Latch Condition; Flow J cc=True 0x2870 seq_br_type 1 Branch True seq_branch_adr 2870 0x2870 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 286b 286b seq_b_timing 1 Latch Condition; Flow J cc=True 0x2874 seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 286c 286c seq_br_type 0 Branch False; Flow J cc=False 0x2878 seq_branch_adr 2878 0x2878 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 286d 286d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2878 seq_br_type 1 Branch True seq_branch_adr 2878 0x2878 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 286e 286e seq_br_type 3 Unconditional Branch; Flow J 0x2853 seq_branch_adr 2853 0x2853 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 286f 286f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2870 2870 fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x286f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 286f 0x286f seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2871 2871 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 2872 2872 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 2873 2873 ioc_tvbs 3 fiu+fiu; Flow J 0x287b seq_br_type 3 Unconditional Branch seq_branch_adr 287b 0x287b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2874 2874 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2875 2875 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 2876 2876 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 2877 2877 ioc_tvbs 3 fiu+fiu; Flow J 0x287b seq_br_type 3 Unconditional Branch seq_branch_adr 287b 0x287b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2878 2878 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_b_adr 02 GP02 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2879 2879 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x287a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 287d 0x287d seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287a 287a fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2887 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2887 0x2887 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 287b 287b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287c 287c seq_br_type 7 Unconditional Call; Flow C 0x2887 seq_branch_adr 2887 0x2887 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 287d 287d seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 287e 287e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287f 287f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2881 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2881 0x2881 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2880 2880 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x2882 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2882 0x2882 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 2881 2881 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 2882 2882 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x3278 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 2883 2883 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x2885 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2885 0x2885 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR09:03 typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2884 2884 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2885 2885 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x286f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 286f 0x286f seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 2886 2886 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2887 ; -------------------------------------------------------------------------------------- 2887 ; Comes from: 2887 ; 28ab C from color MACRO_Execute_Float,Exponentiate 2887 ; -------------------------------------------------------------------------------------- 2887 2887 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 2888 2888 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 2889 2889 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 288a 288a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 288b 288b seq_br_type 7 Unconditional Call; Flow C 0x288e seq_branch_adr 288e 0x288e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 288c 288c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 288d 288d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 288e ; -------------------------------------------------------------------------------------- 288e ; Comes from: 288e ; 2852 C from color MACRO_Execute_Float,Times 288e ; 288b C from color MACRO_Execute_Float,Times 288e ; -------------------------------------------------------------------------------------- 288e 288e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 288f 288f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 2890 2890 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 2891 2891 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 2892 ; -------------------------------------------------------------------------------------- 2892 ; 0x0239 Execute Float,Exponentiate 2892 ; -------------------------------------------------------------------------------------- 2892 MACRO_Execute_Float,Exponentiate: 2892 2892 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2892 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2893 2893 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2897 fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 2897 0x2897 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2894 2894 fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_rand 5 COUNT_ZEROS 2895 2895 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 29 VR05:09 val_frame 5 2896 2896 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2897 2897 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2899 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2899 0x2899 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 2898 2898 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 2899 2899 fiu_load_var 1 hold_var; Flow J 0x289c fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 289c 0x289c typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 289a 289a fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x28aa fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 28aa 0x28aa typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 289b 289b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 289c 289c fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x28aa fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 28aa 0x28aa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 289d 289d fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x289a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 289a 0x289a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 289e 289e fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28a0 fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 28a0 0x28a0 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3b TR11:1b typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 14 ZEROS 289f 289f fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x28a8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 28a8 0x28a8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_c_adr 3b GP04 typ_frame 11 val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 28a0 28a0 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28a8 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 3f TR08:1f typ_b_adr 03 GP03 typ_frame 8 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 28a1 28a1 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x28a4 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28a4 0x28a4 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 28a2 28a2 seq_br_type 0 Branch False; Flow J cc=False 0x28a9 seq_branch_adr 28a9 0x28a9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 10 TOP 28a3 28a3 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28a7 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28a7 0x28a7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 val_a_adr 39 VR12:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 12 28a4 28a4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28a5 0x28a5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a5 28a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 28a6 28a6 seq_br_type 3 Unconditional Branch; Flow J 0x28b0 seq_branch_adr 28b0 MACRO_Execute_Float,Divide val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28a7 28a7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28a9 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 28a9 0x28a9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a8 28a8 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28a9 0x28a9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a9 28a9 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 28aa 28aa fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28ab 28ab ioc_tvbs 2 fiu+val; Flow C 0x2887 seq_br_type 7 Unconditional Call seq_branch_adr 2887 0x2887 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 28ac 28ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a7 seq_br_type 1 Branch True seq_branch_adr 28a7 0x28a7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 28ad 28ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a8 seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28ae 28ae ioc_load_wdr 0 ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 28af 0x28af seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28af 28af ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28b0 ; -------------------------------------------------------------------------------------- 28b0 ; 0x023a Execute Float,Divide 28b0 ; -------------------------------------------------------------------------------------- 28b0 MACRO_Execute_Float,Divide: 28b0 28b0 dispatch_brk_class 8 ; Flow C cc=True 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28b0 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 3 LEFT_I_A val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 28b1 28b1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x28bf fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 28bf 0x28bf seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 28b2 28b2 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 23 VR09:03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 28b3 28b3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28c7 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c7 0x28c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28b4 28b4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28c2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c2 0x28c2 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 28b5 28b5 fiu_len_fill_lit 61 zero-fill 0x21 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b6 28b6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_tivi_src 8 type_var seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 35 TR02:15 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b7 28b7 fiu_fill_mode_src 0 fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b8 28b8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b9 28b9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x28b9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 28b9 0x28b9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28ba 28ba fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28bc fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28bc 0x28bc seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 3f TR08:1f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28bb 28bb fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 0b fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 28bc 28bc ioc_tvbs 2 fiu+val; Flow C cc=True 0x3278 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 28bd 28bd fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3e TR08:1e typ_frame 8 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 28be 28be fiu_len_fill_lit 0b sign-fill 0xb; Flow R cc=True ; Flow J cc=False 0x28c4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28c4 0x28c4 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28bf ; -------------------------------------------------------------------------------------- 28bf ; Comes from: 28bf ; 28b1 C True from color MACRO_Execute_Float,Exponentiate 28bf ; -------------------------------------------------------------------------------------- 28bf 28bf fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 26 VR05:06 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 28c0 28c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 28c1 28c1 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 28c2 28c2 seq_br_type 4 Call False; Flow C cc=False 0x3278 seq_branch_adr 3278 0x3278 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 28c3 28c3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28c4 28c4 fiu_len_fill_lit 7e zero-fill 0x3e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 28c5 28c5 fiu_fill_mode_src 0 ; Flow J cc=False 0x28c3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 28c3 0x28c3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 23 VR09:03 val_frame 9 28c6 28c6 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28c7 28c7 fiu_load_var 1 hold_var; Flow J cc=True 0x28cb fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28cb 0x28cb seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_alu_func 3 LEFT_I_A val_b_adr 39 VR02:19 val_frame 2 val_rand 5 COUNT_ZEROS 28c8 28c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c3 0x28c3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 3 LEFT_I_A val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 28c9 28c9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 28ca 28ca fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x28b4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28b4 0x28b4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 28cb 28cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28c2 seq_br_type 1 Branch True seq_branch_adr 28c2 0x28c2 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 28cc 28cc fiu_len_fill_lit 74 zero-fill 0x34; Flow C cc=True 0x3278 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3278 0x3278 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR08:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 28cd 28cd ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 28ce 28ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x28bd fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 28bd 0x28bd typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 28cf 28cf <halt> ; Flow R 28d0 ; -------------------------------------------------------------------------------------- 28d0 ; 0x0238 Execute Float,Convert 28d0 ; -------------------------------------------------------------------------------------- 28d0 MACRO_Execute_Float,Convert: 28d0 28d0 dispatch_brk_class 4 ; Flow J cc=True 0x28d2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28d0 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28d2 0x28d2 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 28d1 28d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2827 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2827 0x2827 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28d2 28d2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2827 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2827 0x2827 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 28d3 28d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2827 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2827 0x2827 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28d4 ; -------------------------------------------------------------------------------------- 28d4 ; 0x0237 Execute Float,Convert_From_Discrete 28d4 ; -------------------------------------------------------------------------------------- 28d4 MACRO_Execute_Float,Convert_From_Discrete: 28d4 28d4 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28d4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 28d5 28d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28d9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28d9 0x28d9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 28d6 28d6 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 28d7 0x28d7 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR11:19 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 28d7 28d7 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 28d8 28d8 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 28d9 28d9 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_rand 5 COUNT_ZEROS 28da 28da fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 28db 28db fiu_fill_mode_src 0 ; Flow J 0x28d7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 28d7 0x28d7 seq_en_micro 0 val_a_adr 38 VR11:18 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 28dc ; -------------------------------------------------------------------------------------- 28dc ; 0x0236 Execute Float,Truncate_To_Discrete 28dc ; -------------------------------------------------------------------------------------- 28dc MACRO_Execute_Float,Truncate_To_Discrete: 28dc 28dc dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28dc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 28dd 28dd fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28e0 fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28e0 0x28e0 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 28de 28de fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e2 0x28e2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28df 28df fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x28e3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 28e3 0x28e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 37 VR11:17 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 11 28e0 28e0 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e2 0x28e2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28e1 28e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x28eb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 28eb 0x28eb seq_en_micro 0 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 28e2 28e2 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 28e3 0x28e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 28e3 28e3 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 28e4 ; -------------------------------------------------------------------------------------- 28e4 ; 0x0235 Execute Float,Round_To_Discrete 28e4 ; -------------------------------------------------------------------------------------- 28e4 MACRO_Execute_Float,Round_To_Discrete: 28e4 28e4 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28e4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 28e5 28e5 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 28e6 28e6 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e2 0x28e2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_frame 11 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28e7 28e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28ea fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28ea 0x28ea seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 28e8 28e8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28e9 28e9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28e3 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28e3 0x28e3 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 28ea 28ea fiu_len_fill_lit 00 sign-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28eb 28eb fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28e3 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28e3 0x28e3 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 28ec ; -------------------------------------------------------------------------------------- 28ec ; 0x0230 Execute Float,In_Range 28ec ; -------------------------------------------------------------------------------------- 28ec MACRO_Execute_Float,In_Range: 28ec 28ec dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 28ec fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 28ed 28ed fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28f2 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28f2 0x28f2 typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 31 VR02:11 val_frame 2 28ee 28ee fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28f9 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28f9 0x28f9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 28ef 28ef <halt> ; Flow R 28f0 ; -------------------------------------------------------------------------------------- 28f0 ; 0x014f Execute Float,Not_In_Range 28f0 ; -------------------------------------------------------------------------------------- 28f0 MACRO_Execute_Float,Not_In_Range: 28f0 28f0 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 28f0 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 28f1 28f1 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x28ee fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 28ee 0x28ee typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 39 VR02:19 val_frame 2 28f2 28f2 ioc_tvbs 2 fiu+val; Flow J cc=True 0x28f9 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f9 0x28f9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 28f3 28f3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28f9 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28f9 0x28f9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 28f4 ; -------------------------------------------------------------------------------------- 28f4 ; 0x0234 Execute Float,In_Type 28f4 ; -------------------------------------------------------------------------------------- 28f4 MACRO_Execute_Float,In_Type: 28f4 28f4 dispatch_brk_class 8 ; Flow J cc=True 0x28f7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28f4 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 28f5 28f5 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28f9 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28f9 0x28f9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 28f6 ; -------------------------------------------------------------------------------------- 28f6 ; 0x0233 Execute Float,Not_In_Type 28f6 ; -------------------------------------------------------------------------------------- 28f6 MACRO_Execute_Float,Not_In_Type: 28f6 28f6 dispatch_brk_class 8 ; Flow J cc=False 0x28f5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28f6 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg fiu_offs_lit 01 ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28f5 0x28f5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 28f7 28f7 fiu_load_var 1 hold_var; Flow J cc=True 0x28f9 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f9 0x28f9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 28f8 28f8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28f9 0x28f9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 28f9 28f9 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 28fa ; -------------------------------------------------------------------------------------- 28fa ; 0x0232 Execute Float,Check_In_Type 28fa ; -------------------------------------------------------------------------------------- 28fa MACRO_Execute_Float,Check_In_Type: 28fa 28fa dispatch_brk_class 8 ; Flow J cc=True 0x28fc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28fa dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28fc 0x28fc seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 28fb 28fb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2827 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2827 0x2827 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28fc 28fc ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2827 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2827 0x2827 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 28fd 28fd fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2827 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2827 0x2827 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28fe ; -------------------------------------------------------------------------------------- 28fe ; 0x0231 Execute Float,Write_Unchecked 28fe ; -------------------------------------------------------------------------------------- 28fe MACRO_Execute_Float,Write_Unchecked: 28fe 28fe dispatch_brk_class 2 ; Flow C cc=False 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28fe fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 28ff 28ff typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 2900 2900 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3279 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2901 2901 fiu_fill_mode_src 0 ; Flow J cc=False 0x2903 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2903 0x2903 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 2902 2902 fiu_fill_mode_src 0 ; Flow J 0x2906 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2906 0x2906 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2903 2903 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2904 2904 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2905 2905 fiu_load_var 1 hold_var; Flow J 0x2906 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2906 0x2906 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2906 2906 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 2907 2907 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2908 ; -------------------------------------------------------------------------------------- 2908 ; 0x4800-0x4fff Short_Literal slit 2908 ; -------------------------------------------------------------------------------------- 2908 MACRO_Short_Literal_slit: 2908 2908 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2908 fiu_len_fill_lit 0a sign-fill 0xa fiu_mem_start 2 start-rd fiu_offs_lit 75 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2909 2909 fiu_mem_start 2 start-rd; Flow J 0x2911 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2911 0x2911 seq_en_micro 0 seq_random 38 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE 290a ; -------------------------------------------------------------------------------------- 290a ; 0x6000-0x67ff Indirect_Literal Discrete,pcrel,literal 290a ; -------------------------------------------------------------------------------------- 290a MACRO_Indirect_Literal_Discrete,pcrel,literal: 290a 290a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 290a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_random 38 ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 290b 290b fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x2909 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2909 0x2909 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 290c ; -------------------------------------------------------------------------------------- 290c ; 0x5800-0x5fff Indirect_Literal Float,pcrel,dbl 290c ; -------------------------------------------------------------------------------------- 290c MACRO_Indirect_Literal_Float,pcrel,dbl: 290c 290c dispatch_brk_class 8 ; Flow J 0x290b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 290c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 290b 0x290b seq_random 38 ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 290d 290d fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x290f fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290f 0x290f seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 290e ; -------------------------------------------------------------------------------------- 290e ; 0x00a2 Action Push_Discrete_Extended 290e ; -------------------------------------------------------------------------------------- 290e MACRO_Action_Push_Discrete_Extended: 290e 290e dispatch_brk_class 8 ; Flow J 0x290d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 290e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290d 0x290d seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 290f 290f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2911 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2911 0x2911 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 2910 ; -------------------------------------------------------------------------------------- 2910 ; 0x00a1 Action Push_Float_Extended 2910 ; -------------------------------------------------------------------------------------- 2910 MACRO_Action_Push_Float_Extended: 2910 2910 dispatch_brk_class 8 ; Flow J 0x290d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2910 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290d 0x290d seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2911 2911 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x290b seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 290b 0x290b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 2912 2912 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2913 2913 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2914 ; -------------------------------------------------------------------------------------- 2914 ; 0x0093 PushFullAddress InMicrocode,caddr 2914 ; -------------------------------------------------------------------------------------- 2914 MACRO_PushFullAddress_InMicrocode,caddr: 2914 2914 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2914 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2915 2915 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2916 2916 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2917 2917 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2918 ; -------------------------------------------------------------------------------------- 2918 ; 0x5000-0x57ff Indirect_Literal Any,pcrel,literal 2918 ; -------------------------------------------------------------------------------------- 2918 MACRO_Indirect_Literal_Any,pcrel,literal: 2918 2918 dispatch_brk_class 8 ; Flow C 0x2923 dispatch_csa_valid 1 dispatch_uadr 2918 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2923 0x2923 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 2919 2919 fiu_tivi_src c mar_0xc; Flow C 0x2963 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2963 0x2963 seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 291a 291a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 291b 291b <halt> ; Flow R 291c ; -------------------------------------------------------------------------------------- 291c ; 0x00a0 Action Push_Structure_Extended,abs,mark 291c ; -------------------------------------------------------------------------------------- 291c MACRO_Action_Push_Structure_Extended,abs,mark: 291c 291c dispatch_brk_class 8 ; Flow C 0x2923 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 291c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2923 0x2923 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 291d 291d fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 291e 291e fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x291f fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 291a 0x291a seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 291f 291f ioc_fiubs 1 val ; Flow J 0x2963 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2963 0x2963 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 2920 ; -------------------------------------------------------------------------------------- 2920 ; 0x0115 Execute Any,Structure_Clear 2920 ; -------------------------------------------------------------------------------------- 2920 MACRO_Execute_Any,Structure_Clear: 2920 2920 dispatch_brk_class 4 ; Flow C 0x2923 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2920 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2923 0x2923 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 2921 2921 seq_br_type 7 Unconditional Call; Flow C 0x2a2e seq_branch_adr 2a2e 0x2a2e seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2922 2922 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 2923 ; -------------------------------------------------------------------------------------- 2923 ; Comes from: 2923 ; 2918 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2923 ; 2920 C from color MACRO_Execute_Any,Structure_Clear 2923 ; -------------------------------------------------------------------------------------- 2923 2923 seq_b_timing 1 Latch Condition; Flow J cc=True 0x292b seq_br_type 1 Branch True seq_branch_adr 292b 0x292b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP 2924 2924 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x292c fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 292c 0x292c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_latch 1 typ_b_adr 10 TOP typ_frame 8 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2925 2925 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x292a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 292a 0x292a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2926 2926 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2927 2927 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2928 2928 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 03 GP03 2929 2929 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 292a 292a fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x32ab fiu_oreg_src 0 rotator output ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ab 0x32ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 38 ? typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 9 LOAD_MAR_CODE 292b 292b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x292a fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 292a 0x292a typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 292c 292c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 292d 292d ioc_tvbs 2 fiu+val; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 292e 292e fiu_len_fill_lit 4a zero-fill 0xa; Flow C 0x210 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c 292f 292f fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 2930 2930 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2933 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2933 0x2933 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2931 2931 fiu_fill_mode_src 0 ; Flow C cc=False 0x2939 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2939 0x2939 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2932 2932 seq_br_type 3 Unconditional Branch; Flow J 0x2936 seq_branch_adr 2936 0x2936 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2933 2933 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2934 2934 fiu_fill_mode_src 0 ; Flow C cc=False 0x2939 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2939 0x2939 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2935 2935 seq_br_type 3 Unconditional Branch; Flow J 0x2936 seq_branch_adr 2936 0x2936 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2936 2936 fiu_load_oreg 1 hold_oreg; Flow R cc=True fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2937 0x2937 seq_en_micro 0 seq_random 38 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2937 2937 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2938 2938 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2939 ; -------------------------------------------------------------------------------------- 2939 ; Comes from: 2939 ; 2931 C False from color 0x292f 2939 ; 2934 C False from color 0x292f 2939 ; -------------------------------------------------------------------------------------- 2939 2939 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x293b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 293b 0x293b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 293a 293a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 293b 293b fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 293c 293c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 293d 293d <halt> ; Flow R 293e ; -------------------------------------------------------------------------------------- 293e ; 0x0092 Action Push_String_Extended,pse 293e ; -------------------------------------------------------------------------------------- 293e MACRO_Action_Push_String_Extended,pse: 293e 293e dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 293e fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 293f 293f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2943 fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2943 0x2943 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2940 ; -------------------------------------------------------------------------------------- 2940 ; 0x0091 Action Push_String_Extended_Indexed,pse 2940 ; -------------------------------------------------------------------------------------- 2940 MACRO_Action_Push_String_Extended_Indexed,pse: 2940 2940 dispatch_brk_class 4 ; Flow C cc=False 0x326e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2940 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 3d VR02:1d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 2941 2941 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2942 2942 fiu_tivi_src 1 tar_val; Flow J 0x2943 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2943 0x2943 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2943 2943 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame c typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A 2944 2944 fiu_mem_start a start_continue_if_false ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2945 2945 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2946 2946 fiu_len_fill_lit 4f zero-fill 0xf fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2947 2947 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_frame 6 2948 2948 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x294e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 294e 0x294e typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2949 2949 fiu_vmux_sel 1 fill value; Flow J cc=True 0x294c ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 294c 0x294c seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 294a 294a seq_br_type 7 Unconditional Call; Flow C 0x2963 seq_branch_adr 2963 0x2963 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 294b 294b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 294c 294c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x294e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 294e 0x294e typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 294d 294d ioc_load_wdr 0 ; Flow J 0x294b ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 294b 0x294b typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 294e ; -------------------------------------------------------------------------------------- 294e ; Comes from: 294e ; 2948 C from color MACRO_Action_Push_String_Extended,pse 294e ; 294c C from color MACRO_Action_Push_String_Extended,pse 294e ; -------------------------------------------------------------------------------------- 294e 294e fiu_fill_mode_src 0 ; Flow J cc=False 0x2950 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2950 0x2950 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 294f 294f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2950 2950 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2951 2951 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2952 ; -------------------------------------------------------------------------------------- 2952 ; 0x0090 Action Store_String_Extended,pse 2952 ; -------------------------------------------------------------------------------------- 2952 MACRO_Action_Store_String_Extended,pse: 2952 2952 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2952 dispatch_uses_tos 1 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2953 2953 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_frame 2 2954 2954 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2955 2955 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 2956 2956 fiu_mem_start a start_continue_if_false seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2957 2957 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2958 2958 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x295a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 295a 0x295a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2959 2959 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 295a 295a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x295e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 5d fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 295e 0x295e typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 295b 295b fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2962 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2962 0x2962 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 295c 295c fiu_len_fill_lit 7c zero-fill 0x3c; Flow C cc=True 0x2963 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 2963 0x2963 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 295d 295d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3273 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3273 0x3273 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 295e ; -------------------------------------------------------------------------------------- 295e ; Comes from: 295e ; 295a C True from color 0x0000 295e ; -------------------------------------------------------------------------------------- 295e 295e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2960 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2960 0x2960 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 295f 295f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2960 2960 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2961 2961 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2962 ; -------------------------------------------------------------------------------------- 2962 ; Comes from: 2962 ; 295b C True from color 0x0000 2962 ; -------------------------------------------------------------------------------------- 2962 2962 fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2963 ; -------------------------------------------------------------------------------------- 2963 ; Comes from: 2963 ; 2919 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2963 ; 294a C from color MACRO_Action_Push_String_Extended,pse 2963 ; -------------------------------------------------------------------------------------- 2963 2963 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2964 2964 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x296f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 296f 0x296f seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 2965 2965 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x296a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 296a 0x296a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 2966 2966 fiu_fill_mode_src 0 ; Flow J 0x2967 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2967 2967 fiu_fill_mode_src 0 ; Flow J cc=False 0x296c fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 296c 0x296c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2968 2968 fiu_fill_mode_src 0 ; Flow J 0x2969 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2969 0x2969 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2969 2969 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 296a 296a fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 296b 296b fiu_fill_mode_src 0 ; Flow J 0x2967 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 296c 296c fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 296d 296d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 296e 296e fiu_load_var 1 hold_var; Flow J 0x2969 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2969 0x2969 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 296f 296f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2978 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2978 0x2978 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2970 2970 fiu_load_tar 1 hold_tar; Flow J cc=True 0x298b fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 298b 0x298b typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 2971 2971 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2972 2972 fiu_fill_mode_src 0 ; Flow J cc=True 0x297c fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 297c 0x297c seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2973 2973 fiu_mem_start 2 start-rd; Flow J 0x2974 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2974 0x2974 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2974 2974 seq_br_type 3 Unconditional Branch; Flow J 0x2963 seq_branch_adr 2963 0x2963 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 2975 2975 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2976 2976 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2965 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2965 0x2965 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 01 GP01 2977 2977 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2970 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2970 0x2970 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2978 2978 fiu_load_tar 1 hold_tar; Flow J cc=True 0x298e fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 298e 0x298e seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2979 2979 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x297b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 297b 0x297b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 297a 297a seq_br_type 0 Branch False; Flow J cc=False 0x2974 seq_branch_adr 2974 0x2974 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 297b 297b fiu_fill_mode_src 0 ; Flow J 0x297c fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 297c 0x297c typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 297c 297c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2980 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2980 0x2980 typ_mar_cntl 6 INCREMENT_MAR 297d 297d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 297e 297e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 297f 297f fiu_fill_mode_src 0 ; Flow J 0x2969 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2969 0x2969 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2980 2980 fiu_load_tar 1 hold_tar; Flow J cc=False 0x2986 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2986 0x2986 seq_cond_sel 64 OFFSET_REGISTER_???? 2981 2981 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2974 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2974 0x2974 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2982 2982 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2983 2983 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2984 2984 fiu_fill_mode_src 0 ; Flow J 0x2985 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2985 0x2985 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2985 2985 fiu_mem_start 4 continue; Flow J 0x2969 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2969 0x2969 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 2986 2986 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2974 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 2974 0x2974 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2987 2987 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 2988 2988 fiu_fill_mode_src 0 ; Flow J cc=True 0x298a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 298a 0x298a seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2989 2989 fiu_fill_mode_src 0 ; Flow J 0x2985 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2985 0x2985 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 298a 298a fiu_fill_mode_src 0 ; Flow J 0x2985 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2985 0x2985 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 298b 298b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 298c 298c fiu_fill_mode_src 0 ; Flow J cc=True 0x2994 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2994 0x2994 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 298d 298d fiu_load_oreg 1 hold_oreg; Flow J 0x2991 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2991 0x2991 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 298e 298e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 298f 298f seq_b_timing 1 Latch Condition; Flow J cc=True 0x2996 seq_br_type 1 Branch True seq_branch_adr 2996 0x2996 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2990 2990 fiu_fill_mode_src 0 ; Flow J 0x2991 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2991 0x2991 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2991 2991 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2992 2992 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2993 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2993 0x2993 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2993 2993 ioc_load_wdr 0 ; Flow J 0x299b ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 299b 0x299b seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2994 2994 fiu_fill_mode_src 0 ; Flow J cc=True 0x299b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 299b 0x299b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2995 2995 fiu_fill_mode_src 0 ; Flow J 0x2998 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2998 0x2998 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 2996 2996 fiu_fill_mode_src 0 ; Flow J cc=True 0x299b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 299b 0x299b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2997 2997 fiu_fill_mode_src 0 ; Flow J 0x2998 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2998 0x2998 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 2998 2998 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2999 2999 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 299a 299a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2993 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2993 0x2993 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 299b 299b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2975 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2975 0x2975 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 299c 299c fiu_mem_start 4 continue; Flow J cc=False 0x29a8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29a8 0x29a8 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 299d 299d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 299e 299e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a7 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29a7 0x29a7 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 299f 299f fiu_load_oreg 1 hold_oreg; Flow J 0x29a0 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a0 0x29a0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29a0 29a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29a1 29a1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a4 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29a4 0x29a4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a2 29a2 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 29a3 29a3 fiu_mem_start 2 start-rd; Flow C 0x32fe seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe 29a4 29a4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a6 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29a6 0x29a6 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29a5 29a5 fiu_load_oreg 1 hold_oreg; Flow J 0x29a0 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a0 0x29a0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a6 29a6 ioc_load_wdr 0 ; Flow J 0x2975 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2975 0x2975 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a7 29a7 ioc_load_wdr 0 ; Flow J 0x2975 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2975 0x2975 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29a8 29a8 fiu_load_var 1 hold_var; Flow J cc=False 0x29b2 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29b2 0x29b2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29a9 29a9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29aa 29aa fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 29ab 29ab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29af fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29af 0x29af typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29ac 29ac fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a84 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29ad 29ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29ae 29ae fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x29ab fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29ab 0x29ab typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29af 29af fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29b0 29b0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 29b1 29b1 ioc_load_wdr 0 ; Flow J 0x2975 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2975 0x2975 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29b2 29b2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29b3 29b3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29b4 29b4 ioc_load_wdr 0 ; Flow J 0x2975 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2975 0x2975 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29b5 ; -------------------------------------------------------------------------------------- 29b5 ; Comes from: 29b5 ; 10d1 C from color 0x10c1 29b5 ; 12d2 C from color 0x098c 29b5 ; 16f0 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 29b5 ; 17c7 C from color MACRO_Execute_Any,Set_Constraint 29b5 ; 17cf C True from color MACRO_Execute_Any,Set_Constraint 29b5 ; -------------------------------------------------------------------------------------- 29b5 29b5 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29ba fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 29ba 0x29ba seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29b6 29b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2a2e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a2e 0x2a2e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29b7 29b7 seq_br_type 5 Call True; Flow C cc=True 0x2a2e seq_branch_adr 2a2e 0x2a2e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29b8 29b8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29b9 29b9 ioc_fiubs 0 fiu ; Flow J 0x2a2e seq_br_type 3 Unconditional Branch seq_branch_adr 2a2e 0x2a2e val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29ba 29ba fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29bb 29bb fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_en_micro 0 typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 29bc 29bc fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x29c2 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29c2 0x29c2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29bd 29bd fiu_fill_mode_src 0 ; Flow J cc=False 0x29bf fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29bf 0x29bf seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29be 29be fiu_fill_mode_src 0 ; Flow J 0x29c4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c4 0x29c4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29bf 29bf fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29c0 29c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29c1 29c1 fiu_load_var 1 hold_var; Flow J 0x29c4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29c4 0x29c4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29c2 29c2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29c3 29c3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x29c4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c4 0x29c4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29c4 29c4 ioc_load_wdr 0 ; Flow J cc=True 0x29d1 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29d1 0x29d1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 29c5 29c5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29c8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29c8 0x29c8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 29c6 29c6 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 29c7 29c7 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 29c8 29c8 <default> 29c9 29c9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 29ca 29ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator 29cb 29cb fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29cc 29cc fiu_fill_mode_src 0 ; Flow J cc=False 0x29ce fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29ce 0x29ce seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29cd 29cd fiu_fill_mode_src 0 ; Flow J 0x29c4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c4 0x29c4 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29ce 29ce fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29cf 29cf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29d0 29d0 fiu_load_var 1 hold_var; Flow J 0x29c4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29c4 0x29c4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29d1 29d1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 29d2 29d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x29d5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29d5 0x29d5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 29d3 29d3 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2a2e seq_br_type 0 Branch False seq_branch_adr 2a2e 0x2a2e seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29d4 29d4 seq_br_type 3 Unconditional Branch; Flow J 0x29d6 seq_branch_adr 29d6 0x29d6 29d5 29d5 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x2a2e seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a2e 0x2a2e seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29d6 29d6 seq_br_type 5 Call True; Flow C cc=True 0x2a2e seq_branch_adr 2a2e 0x2a2e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 0 PASS_A 29d7 29d7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val typ_b_adr 09 GP09 val_b_adr 09 GP09 29d8 29d8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29d9 29d9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 29da 29da fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x29e0 fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29e0 0x29e0 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29db 29db fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 29dc 29dc fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 29dd 29dd typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29de 29de fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29df 29df fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x29e1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 29e1 0x29e1 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 29e0 29e0 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 29e1 0x29e1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 17 LOOP_COUNTER typ_b_adr 32 TR02:12 typ_frame 2 29e1 29e1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 29e2 29e2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 29e3 29e3 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29e4 29e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x29f1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29f1 0x29f1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e5 29e5 fiu_mem_start 2 start-rd; Flow J cc=False 0x29e8 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29e8 0x29e8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 29e6 29e6 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 29e7 29e7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x29f3 seq_br_type 3 Unconditional Branch seq_branch_adr 29f3 0x29f3 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e8 29e8 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 29e9 29e9 fiu_tivi_src c mar_0xc; Flow J cc=False 0x29f3 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29f3 0x29f3 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29ea 29ea fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29eb 29eb ioc_load_wdr 0 ioc_tvbs 1 typ+fiu val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 29ec 29ec fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 29ed 29ed fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS 29ee 29ee ioc_tvbs 1 typ+fiu; Flow J cc=True 0x29f0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29f0 0x29f0 seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 29ef 29ef seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_mux_sel 2 ALU 29f0 29f0 seq_br_type 3 Unconditional Branch; Flow J 0x29f3 seq_branch_adr 29f3 0x29f3 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29f1 29f1 ioc_tvbs 2 fiu+val; Flow J 0x29f3 seq_br_type 3 Unconditional Branch seq_branch_adr 29f3 0x29f3 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 29f2 29f2 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a04 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a04 0x2a04 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29f3 29f3 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29f8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29f8 0x29f8 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 09 GP09 29f4 29f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x29f2 seq_br_type 0 Branch False seq_branch_adr 29f2 0x29f2 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29f5 29f5 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 29f6 29f6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 29f7 29f7 seq_br_type 3 Unconditional Branch; Flow J 0x29f2 seq_branch_adr 29f2 0x29f2 29f8 29f8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29f9 29f9 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 29fa 0x29fa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 29fa 29fa fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS 29fb 29fb fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 29fc 29fc <default> 29fd 29fd fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 29fe 29fe ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a04 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a04 0x2a04 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29ff 29ff fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2a00 0x2a00 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2a00 2a00 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x29fe seq_br_type 0 Branch False seq_branch_adr 29fe 0x29fe seq_cond_sel 67 REFRESH_MACRO_EVENT 2a01 2a01 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 2a02 2a02 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a03 2a03 seq_br_type 3 Unconditional Branch; Flow J 0x29fe seq_branch_adr 29fe 0x29fe 2a04 ; -------------------------------------------------------------------------------------- 2a04 ; Comes from: 2a04 ; 29f2 C True from color 0x0000 2a04 ; 29fe C True from color 0x0000 2a04 ; -------------------------------------------------------------------------------------- 2a04 2a04 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a05 2a05 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a1b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a1b 0x2a1b typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2a06 2a06 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2a07 2a07 ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a08 2a08 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a09 2a09 seq_br_type 3 Unconditional Branch; Flow J 0x2a0d seq_branch_adr 2a0d 0x2a0d val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a0a 2a0a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a14 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a14 0x2a14 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a0b 2a0b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a0c 2a0c val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a0d 2a0d fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a0e 2a0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2a14 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2a14 0x2a14 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2a0f 2a0f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a1e ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a1e 0x2a1e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2a10 2a10 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2a0a seq_br_type 0 Branch False seq_branch_adr 2a0a 0x2a0a seq_cond_sel 67 REFRESH_MACRO_EVENT 2a11 2a11 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 2a12 2a12 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a13 2a13 seq_br_type 3 Unconditional Branch; Flow J 0x2a0a seq_branch_adr 2a0a 0x2a0a 2a14 ; -------------------------------------------------------------------------------------- 2a14 ; Comes from: 2a14 ; 2a0a C from color 0x2a04 2a14 ; 2a0e C from color 0x2a04 2a14 ; 2a25 C from color 0x2a04 2a14 ; -------------------------------------------------------------------------------------- 2a14 2a14 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a17 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a17 0x2a17 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a15 2a15 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a1a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a1a 0x2a1a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a16 ; -------------------------------------------------------------------------------------- 2a16 ; Comes from: 2a16 ; 2a1d C from color 0x2a04 2a16 ; -------------------------------------------------------------------------------------- 2a16 2a16 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 2a17 2a17 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a18 2a18 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a19 2a19 fiu_load_var 1 hold_var; Flow J cc=False 0x2a16 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a16 0x2a16 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a1a 2a1a ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 2a1b 2a1b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1a PASS_B 2a1c 2a1c ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a1d 2a1d fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x2a16 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a16 0x2a16 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 2a1e 2a1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a28 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a28 0x2a28 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a1f 2a1f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a20 2a20 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2a21 2a21 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a22 2a22 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 2a23 2a23 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2a24 2a24 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a25 2a25 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a14 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a14 0x2a14 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a26 2a26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a22 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a22 0x2a22 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a27 2a27 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a28 2a28 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a2b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a2b 0x2a2b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 2a29 2a29 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a2a 2a2a ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a2b 2a2b fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a2c 2a2c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a2d 2a2d fiu_load_var 1 hold_var; Flow J 0x2a2a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a2a 0x2a2a seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a2e ; -------------------------------------------------------------------------------------- 2a2e ; Comes from: 2a2e ; 10ca C from color 0x10aa 2a2e ; 10e9 C from color 0x10d6 2a2e ; 10fc C from color 0x10d7 2a2e ; 1227 C from color 0x10d6 2a2e ; 1237 C from color 0x1201 2a2e ; 12bb C from color 0x125f 2a2e ; 12e7 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2a2e ; 12f2 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2a2e ; 139d C from color 0x139c 2a2e ; 13bd C from color 0x13bc 2a2e ; 140f C from color 0x140c 2a2e ; 1741 C from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 2a2e ; 2921 C from color MACRO_Execute_Any,Structure_Clear 2a2e ; -------------------------------------------------------------------------------------- 2a2e 2a2e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 2a2f 2a2f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a35 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a35 0x2a35 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2a30 2a30 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2a32 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a32 0x2a32 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a31 2a31 fiu_fill_mode_src 0 ; Flow J 0x2a5d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a5d 0x2a5d typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a32 2a32 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a33 2a33 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a34 2a34 fiu_load_var 1 hold_var; Flow J 0x2a5d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a5d 0x2a5d seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a35 2a35 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2a44 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a44 0x2a44 typ_a_adr 14 ZEROS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a36 2a36 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a42 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a42 0x2a42 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2a37 2a37 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a5d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a5d 0x2a5d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a38 2a38 fiu_load_oreg 1 hold_oreg; Flow J 0x2a39 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a39 0x2a39 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a39 2a39 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a40 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a40 0x2a40 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a3a 2a3a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a41 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2a41 0x2a41 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a3b 2a3b fiu_mem_start 4 continue; Flow J cc=True 0x2a5d fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2a5d 0x2a5d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR04:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2a3c 2a3c fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a3d 2a3d seq_en_micro 0 2a3e 2a3e fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2a5d ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2a5d 0x2a5d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 7 INC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 2a3f 2a3f fiu_mem_start 3 start-wr; Flow J 0x2a2e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2a2e 0x2a2e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a40 2a40 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a3b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2a3b 0x2a3b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a41 2a41 fiu_mem_start 2 start-rd; Flow J 0x2a2e ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a2e 0x2a2e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 0 PASS_A 2a42 2a42 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a43 2a43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a39 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a39 0x2a39 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a44 2a44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a46 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a46 0x2a46 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a45 2a45 fiu_load_oreg 1 hold_oreg; Flow J 0x2a47 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a47 0x2a47 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a46 2a46 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a47 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a47 0x2a47 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a47 2a47 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a49 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a49 0x2a49 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a48 2a48 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a4a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a4a 0x2a4a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a49 2a49 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a4a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a4a 0x2a4a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a4a 2a4a fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a41 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a41 0x2a41 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2a4b 2a4b fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2a3b fiu_mem_start 7 start_wr_if_true fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a3b 0x2a3b seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR06:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 6 2a4c 2a4c fiu_mem_start 3 start-wr; Flow J cc=True 0x2a51 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a51 0x2a51 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 2a4d 2a4d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_alu_func 1c DEC_A val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a4e 2a4e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a3f fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 2a3f 0x2a3f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a4f 2a4f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a50 2a50 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 2a51 2a51 fiu_mem_start 4 continue seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a52 2a52 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a53 2a53 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a54 2a54 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a55 2a55 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a56 2a56 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a57 2a57 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a58 2a58 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a59 2a59 fiu_mem_start 4 continue; Flow J cc=False 0x2a5d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5d 0x2a5d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a5a 2a5a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a5b 2a5b seq_br_type 4 Call False; Flow C cc=False 0x329c seq_branch_adr 329c 0x329c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 34 VR02:14 val_frame 2 2a5c 2a5c fiu_mem_start 3 start-wr; Flow J cc=True 0x2a52 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a52 0x2a52 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a5d 2a5d ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a5e 2a5e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2a62 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a62 0x2a62 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 13 ? typ_a_adr 26 TR05:06 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2a5f 2a5f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a63 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a63 0x2a63 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2a60 2a60 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a62 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a62 0x2a62 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 3e ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2a61 2a61 seq_br_type 3 Unconditional Branch; Flow J 0x2a60 seq_branch_adr 2a60 0x2a60 val_rand 1 INC_LOOP_COUNTER 2a62 2a62 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a64 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2a64 0x2a64 seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2a63 2a63 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 2a64 2a64 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a65 2a65 fiu_mem_start d start_physical_rd; Flow J 0x2a66 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a66 0x2a66 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a66 2a66 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1c TR1d:03 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1c VR1d:03 val_c_mux_sel 2 ALU val_frame 1d 2a67 2a67 fiu_mem_start d start_physical_rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a68 2a68 seq_en_micro 0 typ_a_adr 2b TR04:0b typ_alu_func 7 INC_A typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 2b VR04:0b val_alu_func 1 A_PLUS_B val_b_adr 2a VR04:0a val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a69 2a69 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR1d:02 typ_c_source 0 FIU_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6a 2a6a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR1d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR1d:02 val_c_mux_sel 2 ALU val_frame 1d 2a6b 2a6b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6c 2a6c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2a6d 2a6d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6e 2a6e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 2b VR04:0b val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a6f 2a6f fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a70 2a70 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 0d fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a71 2a71 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a72 2a72 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a73 2a73 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 32 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a74 2a74 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a75 2a75 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a76 2a76 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a77 2a77 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 0f fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a78 2a78 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a79 2a79 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a7a 2a7a fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 8 read and clear rtc ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a7b 2a7b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a7c 2a7c ioc_tvbs 1 typ+fiu; Flow J 0x2a7e seq_br_type 3 Unconditional Branch seq_branch_adr 2a7e 0x2a7e seq_en_micro 0 val_a_adr 35 VR04:15 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0a VR04:15 val_c_mux_sel 2 ALU val_frame 4 2a7d 2a7d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a7e 2a7e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2a7d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a7d 0x2a7d seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a7f 2a7f seq_b_timing 1 Latch Condition; Flow J cc=True 0x2a85 seq_br_type 1 Branch True seq_branch_adr 2a85 0x2a85 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 2a80 2a80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a82 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a82 0x2a82 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a81 2a81 fiu_mem_start 18 acknowledge_refresh; Flow J 0x2a83 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2a83 0x2a83 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2a82 2a82 seq_br_type 3 Unconditional Branch; Flow J 0x2a83 seq_branch_adr 2a83 0x2a83 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2a83 2a83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2a84 ; -------------------------------------------------------------------------------------- 2a84 ; Comes from: 2a84 ; 0245 C from color 0x0245 2a84 ; 0274 C from color 0x0274 2a84 ; 031f C True from color MACRO_Action_Name_Partner 2a84 ; 0568 C True from color 0x0567 2a84 ; 058f C True from color 0x058d 2a84 ; 0596 C from color 0x0573 2a84 ; 05af C True from color 0x05af 2a84 ; 05c8 C True from color 0x05a7 2a84 ; 06b6 C True from color 0x06b6 2a84 ; 06d7 C True from color 0x06d2 2a84 ; 0718 C True from color 0x0717 2a84 ; 07ac C True from color 0x07ab 2a84 ; 07b5 C from color 0x07b5 2a84 ; 07e8 C from color 0x07e8 2a84 ; 0851 C True from color 0x0820 2a84 ; 085f C True from color 0x0820 2a84 ; 0869 C from color 0x0820 2a84 ; 086f C True from color 0x0820 2a84 ; 08ff C from color 0x0127 2a84 ; 090d C True from color 0x0905 2a84 ; 0adb C True from color 0x0ac4 2a84 ; 0b8e C True from color 0x0b85 2a84 ; 0b96 C from color 0x0b95 2a84 ; 0ba9 C from color 0x0b95 2a84 ; 0ce9 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 2a84 ; 0d03 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 2a84 ; 0d6f C True from color 0x0d36 2a84 ; 0d99 C True from color 0x0d94 2a84 ; 0f00 C True from color 0x0efa 2a84 ; 0f92 C from color 0x0efa 2a84 ; 0fca C from color 0x0efa 2a84 ; 0fd4 C True from color 0x0fd2 2a84 ; 0fdb C True from color 0x0fd2 2a84 ; 0feb C from color 0x0fd2 2a84 ; 0ffa C True from color 0x0fd2 2a84 ; 107d C True from color 0x0efa 2a84 ; 1080 C True from color 0x0efa 2a84 ; 108a C True from color 0x0efa 2a84 ; 131b C from color 0x1316 2a84 ; 1328 C True from color 0x1316 2a84 ; 13f7 C from color MACRO_Declare_Variable_Array,With_Constraint 2a84 ; 1418 C True from color 0x1411 2a84 ; 16c7 C True from color 0x16c7 2a84 ; 1716 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a84 ; 1718 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a84 ; 1721 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a84 ; 1866 C from color MACRO_Execute_Vector,Greater_Equal 2a84 ; 194c C from color MACRO_Execute_Vector,Complement 2a84 ; 1c55 C from color 0x1c55 2a84 ; 1c89 C True from color MACRO_Execute_Array,Subarray 2a84 ; 1e9d C True from color MACRO_Declare_Type_Record,Incomplete 2a84 ; 1ebc C True from color MACRO_Complete_Type_Record,By_Renaming 2a84 ; 1eca C True from color MACRO_Complete_Type_Record,By_Renaming 2a84 ; 1fef C True from color MACRO_Complete_Type_Array,By_Constraining 2a84 ; 204c C from color 0x2012 2a84 ; 20f2 C from color 0x2012 2a84 ; 218d C from color MACRO_Declare_Type_Array,Constrained 2a84 ; 2217 C True from color 0x2005 2a84 ; 222b C True from color 0x2228 2a84 ; 2243 C True from color 0x2228 2a84 ; 2258 C from color 0x1b7e 2a84 ; 225e C True from color 0x1b7e 2a84 ; 22a8 C from color 0x22a8 2a84 ; 22b8 C True from color 0x09a8 2a84 ; 22fb C True from color MACRO_Declare_Type_Array,Incomplete 2a84 ; 22fd C True from color MACRO_Declare_Type_Array,Incomplete 2a84 ; 231c C True from color MACRO_Complete_Type_Array,By_Component_Completion 2a84 ; 2380 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a84 ; 2384 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a84 ; 238e C from color 0x238e 2a84 ; 2393 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a84 ; 23ad C from color 0x23ad 2a84 ; 23ef C from color 0x23ef 2a84 ; 243c C from color 0x243c 2a84 ; 2452 C from color 0x2452 2a84 ; 24e0 C from color 0x24da 2a84 ; 24f2 C from color 0x248a 2a84 ; 2510 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a84 ; 251a C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a84 ; 2520 C True from color 0x2520 2a84 ; 2529 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a84 ; 254f C True from color MACRO_Complete_Type_Variant_Record,By_Defining 2a84 ; 259c C True from color MACRO_Complete_Type_Variant_Record,By_Defining 2a84 ; 25dc C from color 0x25dc 2a84 ; 25de C from color 0x25de 2a84 ; 2638 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 2a84 ; 264f C True from color 0x263c 2a84 ; 2654 C True from color 0x263c 2a84 ; 2664 C True from color MACRO_Declare_Type_Variant_Record,Defined 2a84 ; 2690 C True from color 0x2690 2a84 ; 26a9 C True from color MACRO_Declare_Type_Variant_Record,Defined 2a84 ; 2701 C True from color 0x26fc 2a84 ; 2706 C True from color 0x26fc 2a84 ; 2719 C from color 0x2719 2a84 ; 289b C True from color MACRO_Execute_Float,Exponentiate 2a84 ; 28a5 C True from color MACRO_Execute_Float,Exponentiate 2a84 ; 2a11 C from color 0x2a04 2a84 ; 2a23 C True from color 0x2a04 2a84 ; 2ab6 C from color 0x0127 2a84 ; 2d2a C True from color 0x2d21 2a84 ; 2dcf C from color 0x2dcf 2a84 ; 2eef C True from color 0x2ee7 2a84 ; 2f76 C from color 0x2f75 2a84 ; 3358 C from color MACRO_Action_Accept_Activation 2a84 ; 337f C True from color 0x337a 2a84 ; 33dc C True from color 0x0f07 2a84 ; 3426 C True from color 0x0d36 2a84 ; 3431 C from color 0x0d36 2a84 ; 3439 C from color 0x0d36 2a84 ; 343e C from color 0x0d36 2a84 ; 34d4 C True from color 0x34d4 2a84 ; 3691 C True from color 0x05a7 2a84 ; 373b C from color 0x373a 2a84 ; 37e5 C from color 0x37e0 2a84 ; 37f7 C from color 0x37e0 2a84 ; 38a1 C from color 0x2abf 2a84 ; 3b7d C True from color 0x3b4d 2a84 ; 3b92 C from color 0x3b8f 2a84 ; -------------------------------------------------------------------------------------- 2a84 2a84 fiu_mem_start d start_physical_rd; Flow J 0x139 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0139 0x0139 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 2a85 2a85 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a87 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a87 0x2a87 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a86 2a86 fiu_mem_start 18 acknowledge_refresh; Flow J 0x2a88 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2a88 0x2a88 seq_en_micro 0 2a87 2a87 seq_br_type 3 Unconditional Branch; Flow J 0x2a88 seq_branch_adr 2a88 0x2a88 seq_en_micro 0 2a88 2a88 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2a89 2a89 seq_en_micro 0 typ_a_adr 23 TR1d:03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 23 VR1d:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1d 2a8a 2a8a fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 22 VR1d:02 val_alu_func 1a PASS_B val_b_adr 21 VR1d:01 val_frame 1d 2a8b 2a8b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src b type_frame ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 25 TR1d:05 typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_frame 1d val_rand 9 PASS_A_HIGH 2a8c 2a8c fiu_len_fill_lit 72 zero-fill 0x32; Flow J cc=True 0x18c fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018c 0x018c seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a8d 2a8d fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0x2aba fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2aba 0x2aba seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2a8e 2a8e fiu_fill_mode_src 0 ; Flow J 0x2a8f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2a8f 0x2a8f seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2a8f 2a8f fiu_fill_mode_src 0 ; Flow J 0x2a90 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a90 0x2a90 seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2a90 2a90 fiu_mem_start d start_physical_rd seq_en_micro 0 2a91 2a91 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2a94 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a94 0x2a94 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR1d:07 val_c_mux_sel 2 ALU val_frame 1d 2a92 2a92 fiu_mem_start e start_physical_wr; Flow J cc=False 0x2a9c fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2a9c 0x2a9c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a93 2a93 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a94 2a94 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2a9c ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 2a9c 0x2a9c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR1d:0d val_alu_func 19 X_XOR_B val_b_adr 2f VR1d:0f val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a95 2a95 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a96 2a96 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a97 2a97 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a9a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a9a 0x2a9a seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 2a98 2a98 fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=True 0x18d fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018d 0x018d seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d 2a99 2a99 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2a9a 2a9a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 2a9b 2a9b fiu_mem_start e start_physical_wr; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 1d 2a9c 2a9c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 2a VR1d:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2a9d 2a9d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_frame 1d 2a9e 2a9e fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 2a9f 2a9f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS 2aa0 2aa0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2aa1 2aa1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 5d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 14 VR1d:0b val_c_mux_sel 2 ALU val_frame 1d 2aa2 2aa2 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR1d:0d val_c_adr 15 VR1d:0a val_frame 1d 2aa3 2aa3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2aa4 2aa4 fiu_len_fill_lit 48 zero-fill 0x8 fiu_load_tar 1 hold_tar fiu_offs_lit 03 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 25 VR08:05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 2aa5 2aa5 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2d VR12:0d val_frame 12 2aa6 2aa6 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2aa9 seq_br_type 1 Branch True seq_branch_adr 2aa9 0x2aa9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 2aa7 2aa7 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2aa8 2aa8 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2aab fiu_load_var 1 hold_var fiu_offs_lit 1b fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2aab 0x2aab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2aa9 2aa9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2aaa 2aaa ioc_tvbs 2 fiu+val; Flow J 0x2aab seq_br_type 3 Unconditional Branch seq_branch_adr 2aab 0x2aab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2aab 2aab fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2aaf fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2aaf 0x2aaf seq_en_micro 0 typ_a_adr 13 LOOP_REG val_a_adr 2d VR06:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2aac 2aac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 30 VR02:10 val_frame 2 2aad 2aad fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 2aae 2aae ioc_tvbs 3 fiu+fiu; Flow J 0x2ab2 seq_br_type 3 Unconditional Branch seq_branch_adr 2ab2 0x2ab2 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2aaf 2aaf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2ab0 2ab0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 27 TR01:07 typ_frame 1 val_b_adr 27 VR01:07 val_frame 1 2ab1 2ab1 ioc_tvbs 3 fiu+fiu; Flow J 0x2ab2 seq_br_type 3 Unconditional Branch seq_branch_adr 2ab2 0x2ab2 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR01:07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR01:07 val_c_mux_sel 2 ALU val_frame 1 2ab2 2ab2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2c TR1d:0c typ_b_adr 27 TR1d:07 typ_frame 1d 2ab3 2ab3 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 21 TR1d:01 typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_frame 1d typ_rand 5 CHECK_CLASS_B_LIT 2ab4 2ab4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 26 TR1d:06 typ_frame 1d val_a_adr 27 VR1d:07 val_b_adr 26 VR1d:06 val_frame 1d 2ab5 2ab5 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x18e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 018e 0x018e seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 0 PASS_A typ_b_adr 25 TR1d:05 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 2b VR1d:0b val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 1d 2ab6 2ab6 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 0 PASS_A typ_c_adr 16 TR1d:09 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 0 PASS_A val_c_adr 16 VR1d:09 val_c_mux_sel 2 ALU val_frame 1d 2ab7 2ab7 seq_en_micro 0 typ_a_adr 29 TR1d:09 typ_alu_func 0 PASS_A typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 29 VR1d:09 val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_mux_sel 2 ALU val_frame 1d 2ab8 2ab8 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x18e fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 018e 0x018e seq_en_micro 0 val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2ab9 ; -------------------------------------------------------------------------------------- 2ab9 ; Comes from: 2ab9 ; 0189 C True from color 0x0127 2ab9 ; -------------------------------------------------------------------------------------- 2ab9 2ab9 fiu_mem_start 18 acknowledge_refresh; Flow R fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR1d:01 typ_frame 1d val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2aba 2aba fiu_fill_mode_src 0 ; Flow J cc=False 0x2a8f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8f 0x2a8f seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2abb 2abb fiu_fill_mode_src 0 ; Flow J cc=True 0x2a90 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2a90 0x2a90 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 1c DEC_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2abc 2abc seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 2abd 2abd seq_br_type 2 Push (branch address); Flow J 0x2abe seq_branch_adr 01d1 0x01d1 seq_en_micro 0 2abe 2abe fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x8aa fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 08aa 0x08aa seq_en_micro 0 val_c_adr 10 VR1d:0f val_c_source 0 FIU_BUS val_frame 1d 2abf ; -------------------------------------------------------------------------------------- 2abf ; Comes from: 2abf ; 061b C from color 0x0000 2abf ; 067e C from color 0x066a 2abf ; -------------------------------------------------------------------------------------- 2abf 2abf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR11:14 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 02 GP02 2ac0 2ac0 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2ac1 2ac1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2ac5 fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ac5 0x2ac5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ac2 2ac2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2add fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2add 0x2add typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ac3 2ac3 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2ad0 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ad0 0x2ad0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 04 GP04 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 24 VR05:04 val_frame 5 2ac4 2ac4 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_b_adr 04 GP04 2ac5 2ac5 fiu_mem_start 11 start_tag_query; Flow C cc=False 0x20a seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ac6 2ac6 seq_br_type 7 Unconditional Call; Flow C 0x34f4 seq_branch_adr 34f4 0x34f4 seq_en_micro 0 2ac7 2ac7 ioc_tvbs 8 typ+mem; Flow J cc=True 0x2aca seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2aca 0x2aca seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2ac8 2ac8 fiu_mem_start 2 start-rd; Flow C 0x348f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 348f 0x348f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2ac9 2ac9 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2aca 2aca fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2acb 2acb ioc_load_wdr 0 typ_b_adr 20 TR05:00 typ_frame 5 val_b_adr 39 VR02:19 val_frame 2 2acc 2acc fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2acd 2acd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 2ace 2ace fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 2acf 2acf ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2ad0 2ad0 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ad1 2ad1 <default> 2ad2 2ad2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 2ad3 2ad3 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 3e VR06:1e val_frame 6 2ad4 2ad4 fiu_mem_start 3 start-wr; Flow J cc=False 0x2ad8 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2ad8 0x2ad8 val_a_adr 3e VR06:1e val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2ad5 2ad5 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2ad6 2ad6 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ad7 2ad7 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 2ad8 2ad8 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 2ad9 2ad9 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2ada 2ada <default> 2adb 2adb fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2adc 2adc ioc_fiubs 0 fiu ; Flow J 0x2ad6 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2ad6 0x2ad6 val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2add ; -------------------------------------------------------------------------------------- 2add ; Comes from: 2add ; 2ac2 C False from color 0x2abf 2add ; -------------------------------------------------------------------------------------- 2add 2add fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2ade 2ade fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x2ae2 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ae2 0x2ae2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_frame 2 2adf 2adf fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2ae0 2ae0 ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2ae1 2ae1 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2ae3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 2ae3 0x2ae3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2ae2 2ae2 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2ae3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ae3 0x2ae3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ae3 2ae3 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2ae4 2ae4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 2ae5 2ae5 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2ae6 2ae6 ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2ae7 2ae7 seq_br_type a Unconditional Return; Flow R 2ae8 ; -------------------------------------------------------------------------------------- 2ae8 ; 0x03d5 Declare_Type Access,Defined 2ae8 ; -------------------------------------------------------------------------------------- 2ae8 MACRO_Declare_Type_Access,Defined: 2ae8 2ae8 dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2ae8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ae9 2ae9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2aea 2aea fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af8 0x2af8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2aeb 2aeb <halt> ; Flow R 2aec ; -------------------------------------------------------------------------------------- 2aec ; 0x03d6 Declare_Type Access,Defined,Visible 2aec ; -------------------------------------------------------------------------------------- 2aec MACRO_Declare_Type_Access,Defined,Visible: 2aec 2aec dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2aec seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2aed 2aed fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 2aee 2aee fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2aef 2aef fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af8 0x2af8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2af0 ; -------------------------------------------------------------------------------------- 2af0 ; 0x03d3 Declare_Type Access,Defined,Accesses_Protected 2af0 ; -------------------------------------------------------------------------------------- 2af0 MACRO_Declare_Type_Access,Defined,Accesses_Protected: 2af0 2af0 dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2af0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2af1 2af1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2af2 2af2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af8 0x2af8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2af3 2af3 <halt> ; Flow R 2af4 ; -------------------------------------------------------------------------------------- 2af4 ; 0x03d4 Declare_Type Access,Defined,Visible,Accesses_Protected 2af4 ; -------------------------------------------------------------------------------------- 2af4 MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected: 2af4 2af4 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2af4 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2af5 2af5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 2af6 2af6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2af7 2af7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af8 0x2af8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2af8 2af8 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2af9 2af9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b17 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b17 0x2b17 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2afa 2afa fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b05 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b05 0x2b05 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 09 GP09 typ_b_adr 03 GP03 val_b_adr 3a VR02:1a val_frame 2 2afb 2afb fiu_mem_start 4 continue; Flow J cc=True 0x2afd ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2afd 0x2afd seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2afc 2afc fiu_load_var 1 hold_var; Flow J 0x2afe fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2afe 0x2afe seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2afd 2afd fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2afe 2afe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP 2aff 2aff fiu_fill_mode_src 0 ; Flow C 0x34fd fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2b00 2b00 ioc_load_wdr 0 ; Flow C cc=True 0x2b02 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2b02 0x2b02 typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA 2b01 2b01 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b02 ; -------------------------------------------------------------------------------------- 2b02 ; Comes from: 2b02 ; 2b00 C True from color 0x2afb 2b02 ; -------------------------------------------------------------------------------------- 2b02 2b02 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2b03 2b03 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 2b04 2b04 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_b_adr 09 GP09 2b05 ; -------------------------------------------------------------------------------------- 2b05 ; Comes from: 2b05 ; 2afa C #0x0 from color MACRO_Declare_Type_Access,Defined 2b05 ; -------------------------------------------------------------------------------------- 2b05 2b05 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b06 2b06 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b07 2b07 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b08 2b08 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b09 2b09 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0a 2b0a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0b 2b0b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0c 2b0c fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b0d 2b0d fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b0e 2b0e seq_br_type 3 Unconditional Branch; Flow J 0x2b15 seq_branch_adr 2b15 0x2b15 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b0f 2b0f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b10 2b10 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b11 2b11 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b12 2b12 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b16 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b16 0x2b16 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b13 2b13 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b16 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b16 0x2b16 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b14 2b14 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b16 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b16 0x2b16 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b15 2b15 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b16 2b16 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 2b17 2b17 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b1a fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b1a 0x2b1a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 3a VR02:1a val_frame 2 2b18 2b18 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b19 2b19 fiu_load_var 1 hold_var; Flow J 0x2afe fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2afe 0x2afe seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2b1a ; -------------------------------------------------------------------------------------- 2b1a ; Comes from: 2b1a ; 2b17 C #0x0 from color MACRO_Declare_Type_Access,Defined 2b1a ; -------------------------------------------------------------------------------------- 2b1a 2b1a seq_br_type 3 Unconditional Branch; Flow J 0x2b2a seq_branch_adr 2b2a 0x2b2a val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b1b 2b1b fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b1c 2b1c fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b1d 2b1d fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2c fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2c 0x2b2c typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b1e 2b1e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b1f 2b1f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b20 2b20 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b21 2b21 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2c fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2c 0x2b2c typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b22 2b22 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2e 0x2b2e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b23 2b23 seq_br_type 3 Unconditional Branch; Flow J 0x2b2d seq_branch_adr 2b2d 0x2b2d typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b24 2b24 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b25 2b25 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b26 2b26 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b27 2b27 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2f 0x2b2f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b28 2b28 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2f 0x2b2f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b29 2b29 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2f 0x2b2f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b2a 2b2a typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b2b 2b2b fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b2c 2b2c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b2d 2b2d fiu_mem_start 7 start_wr_if_true; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2e 0x2b2e typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b2e 2b2e seq_br_type 3 Unconditional Branch; Flow J 0x2b30 seq_branch_adr 2b30 0x2b30 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b2f 2b2f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2b2c seq_br_type 1 Branch True seq_branch_adr 2b2c 0x2b2c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b30 2b30 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b31 2b31 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b32 2b32 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2b33 2b33 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 2b34 2b34 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b35 2b35 <halt> ; Flow R 2b36 ; -------------------------------------------------------------------------------------- 2b36 ; 0x03ce Declare_Type Access,Incomplete 2b36 ; -------------------------------------------------------------------------------------- 2b36 MACRO_Declare_Type_Access,Incomplete: 2b36 2b36 dispatch_brk_class 4 ; Flow J 0x2b3e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b36 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3e 0x2b3e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b37 2b37 <halt> ; Flow R 2b38 ; -------------------------------------------------------------------------------------- 2b38 ; 0x03cf Declare_Type Access,Incomplete,Visible 2b38 ; -------------------------------------------------------------------------------------- 2b38 MACRO_Declare_Type_Access,Incomplete,Visible: 2b38 2b38 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b38 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b39 2b39 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b3e fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3e 0x2b3e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b3a ; -------------------------------------------------------------------------------------- 2b3a ; 0x03cc Declare_Type Access,Incomplete,Accesses_Protected 2b3a ; -------------------------------------------------------------------------------------- 2b3a MACRO_Declare_Type_Access,Incomplete,Accesses_Protected: 2b3a 2b3a dispatch_brk_class 4 ; Flow J 0x2b3e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b3a fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3e 0x2b3e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b3b 2b3b <halt> ; Flow R 2b3c ; -------------------------------------------------------------------------------------- 2b3c ; 0x03cd Declare_Type Access,Incomplete,Visible,Accesses_Protected 2b3c ; -------------------------------------------------------------------------------------- 2b3c MACRO_Declare_Type_Access,Incomplete,Visible,Accesses_Protected: 2b3c 2b3c dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b3c seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b3d 2b3d fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b3e fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3e 0x2b3e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b3e 2b3e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b3f 2b3f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2b40 2b40 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 2b41 2b41 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2b42 2b42 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b43 2b43 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2b44 2b44 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2b45 2b45 <halt> ; Flow R 2b46 ; -------------------------------------------------------------------------------------- 2b46 ; 0x038e Declare_Type Package,Defined 2b46 ; -------------------------------------------------------------------------------------- 2b46 MACRO_Declare_Type_Package,Defined: 2b46 2b46 dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b46 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 22 VR06:02 val_frame 6 2b47 ; -------------------------------------------------------------------------------------- 2b47 ; Comes from: 2b47 ; 2b61 C from color MACRO_Declare_Type_Task,Incomplete 2b47 ; 2b68 C from color 0x2b51 2b47 ; -------------------------------------------------------------------------------------- 2b47 2b47 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2b48 ; -------------------------------------------------------------------------------------- 2b48 ; 0x038c Declare_Type Package,Defined,Not_Elaborated 2b48 ; -------------------------------------------------------------------------------------- 2b48 MACRO_Declare_Type_Package,Defined,Not_Elaborated: 2b48 2b48 dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b48 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 39 VR02:19 val_frame 2 2b49 2b49 fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False ; Flow J cc=True 0x2b58 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b58 0x2b58 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b4a ; -------------------------------------------------------------------------------------- 2b4a ; 0x038f Declare_Type Package,Defined,Visible 2b4a ; -------------------------------------------------------------------------------------- 2b4a MACRO_Declare_Type_Package,Defined,Visible: 2b4a 2b4a dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 22 VR06:02 val_frame 6 2b4b 2b4b fiu_mem_start 4 continue; Flow J 0x2b4d ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b4d 0x2b4d typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b4c ; -------------------------------------------------------------------------------------- 2b4c ; 0x038d Declare_Type Package,Defined,Visible,Not_Elaborated 2b4c ; -------------------------------------------------------------------------------------- 2b4c MACRO_Declare_Type_Package,Defined,Visible,Not_Elaborated: 2b4c 2b4c dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4c fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 39 VR02:19 val_frame 2 2b4d 2b4d ioc_load_wdr 0 ; Flow J 0x2b4f ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b4f 0x2b4f seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 03 GP03 2b4e ; -------------------------------------------------------------------------------------- 2b4e ; 0x037d Declare_Type Task,Defined 2b4e ; -------------------------------------------------------------------------------------- 2b4e MACRO_Declare_Type_Task,Defined: 2b4e 2b4e dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4e fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 27 VR06:07 val_frame 6 2b4f 2b4f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b50 ; -------------------------------------------------------------------------------------- 2b50 ; 0x037e Declare_Type Task,Defined,Visible 2b50 ; -------------------------------------------------------------------------------------- 2b50 MACRO_Declare_Type_Task,Defined,Visible: 2b50 2b50 dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b50 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 27 VR06:07 val_frame 6 2b51 2b51 ioc_load_wdr 0 ; Flow J 0x2b53 seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 typ_b_adr 01 GP01 val_b_adr 01 GP01 2b52 ; -------------------------------------------------------------------------------------- 2b52 ; 0x037a Declare_Type Task,Defined,Not_Elaborated 2b52 ; -------------------------------------------------------------------------------------- 2b52 MACRO_Declare_Type_Task,Defined,Not_Elaborated: 2b52 2b52 dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b52 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b53 2b53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2b54 ; -------------------------------------------------------------------------------------- 2b54 ; 0x037b Declare_Type Task,Defined,Visible,Not_Elaborated 2b54 ; -------------------------------------------------------------------------------------- 2b54 MACRO_Declare_Type_Task,Defined,Visible,Not_Elaborated: 2b54 2b54 dispatch_brk_class 4 ; Flow J 0x2b55 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b54 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b55 0x2b55 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b55 2b55 seq_br_type 2 Push (branch address); Flow J 0x2b56 seq_branch_adr 3279 0x3279 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 11 2b56 2b56 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b49 fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b49 0x2b49 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b57 2b57 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b58 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b58 0x2b58 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b58 2b58 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 10 TOP 2b59 2b59 fiu_mem_start 4 continue; Flow J 0x2b4b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b4b 0x2b4b typ_a_adr 3e TR06:1e typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR06:09 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b5a ; -------------------------------------------------------------------------------------- 2b5a ; 0x0377 Declare_Type Task,Incomplete 2b5a ; -------------------------------------------------------------------------------------- 2b5a MACRO_Declare_Type_Task,Incomplete: 2b5a 2b5a dispatch_brk_class 4 ; Flow J 0x2b5d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b5a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b5d 0x2b5d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b5b 2b5b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2b5c ; -------------------------------------------------------------------------------------- 2b5c ; 0x0378 Declare_Type Task,Incomplete,Visible 2b5c ; -------------------------------------------------------------------------------------- 2b5c MACRO_Declare_Type_Task,Incomplete,Visible: 2b5c 2b5c dispatch_brk_class 4 ; Flow J 0x2b5d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b5c fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b5d 0x2b5d seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b5d 2b5d ioc_fiubs 1 val ; Flow J 0x2b5e seq_br_type 2 Push (branch address) seq_branch_adr 3279 0x3279 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b5e 2b5e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b60 fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b60 0x2b60 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 2b5f 2b5f fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b61 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b61 0x2b61 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b60 2b60 fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b61 0x2b61 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b61 2b61 fiu_mem_start 3 start-wr; Flow C 0x2b47 fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2b47 0x2b47 typ_a_adr 32 TR02:12 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b62 2b62 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b63 2b63 ioc_load_wdr 0 ; Flow J 0x2b5b ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b5b 0x2b5b seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b64 ; -------------------------------------------------------------------------------------- 2b64 ; 0x0374 Complete_Type Task,By_Renaming 2b64 ; -------------------------------------------------------------------------------------- 2b64 MACRO_Complete_Type_Task,By_Renaming: 2b64 2b64 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b64 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2b65 2b65 fiu_mem_start 4 continue ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b66 2b66 fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR 2b67 2b67 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b68 2b68 fiu_mem_start 3 start-wr; Flow C 0x2b47 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2b47 0x2b47 seq_random 02 ? typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 2b69 2b69 fiu_mem_start 4 continue; Flow J 0x2b51 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b51 0x2b51 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 2b6a ; -------------------------------------------------------------------------------------- 2b6a ; 0x009c Action Load_Dynamic 2b6a ; -------------------------------------------------------------------------------------- 2b6a MACRO_Action_Load_Dynamic: 2b6a 2b6a dispatch_brk_class 8 ; Flow C 0x2c70 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b6a seq_br_type 7 Unconditional Call seq_branch_adr 2c70 0x2c70 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2b6b 2b6b fiu_mem_start 2 start-rd 2b6c ; -------------------------------------------------------------------------------------- 2b6c ; 0xe000-0xffff Load llvl,ldelta 2b6c ; -------------------------------------------------------------------------------------- 2b6c MACRO_Load_llvl,ldelta: 2b6c 2b6c dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2b6c 2b6d 2b6d fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b6e 2b6e fiu_load_var 1 hold_var; Flow J cc=True 0x2b6f ; Flow J cc=#0x0 0x2b70 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2b70 0x2b70 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 6 2b6f 2b6f fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b78 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b78 0x2b78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b70 2b70 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b71 2b71 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 2b72 2b72 seq_br_type 3 Unconditional Branch; Flow J 0x2b79 seq_branch_adr 2b79 0x2b79 2b73 2b73 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b74 2b74 fiu_mem_start 6 start_rd_if_false; Flow J 0x2b7a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2b7a 0x2b7a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2b75 2b75 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b78 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b78 0x2b78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b76 2b76 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b78 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b78 0x2b78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b77 2b77 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 2b78 2b78 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2b79 2b79 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b7a 2b7a ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2b82 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b82 0x2b82 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2b7b 2b7b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2b7c 2b7c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2b7e fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2b7e 0x2b7e seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR05:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 2b7d 2b7d fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2b80 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2b80 0x2b80 seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b7e 2b7e fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2b7f 2b7f fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2b80 0x2b80 seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b80 2b80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b81 0x2b81 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2b81 2b81 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b82 2b82 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b83 0x2b83 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b83 2b83 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2b84 ; -------------------------------------------------------------------------------------- 2b84 ; 0x00d8 Load_Top At_Offset_0 2b84 ; -------------------------------------------------------------------------------------- 2b84 MACRO_Load_Top_At_Offset_0: 2b84 2b84 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b84 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b85 2b85 <halt> ; Flow R 2b86 ; -------------------------------------------------------------------------------------- 2b86 ; 0x00d9 Load_Top At_Offset_1 2b86 ; -------------------------------------------------------------------------------------- 2b86 MACRO_Load_Top_At_Offset_1: 2b86 2b86 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b86 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b87 2b87 <halt> ; Flow R 2b88 ; -------------------------------------------------------------------------------------- 2b88 ; 0x00da Load_Top At_Offset_2 2b88 ; -------------------------------------------------------------------------------------- 2b88 MACRO_Load_Top_At_Offset_2: 2b88 2b88 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b88 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b89 2b89 <halt> ; Flow R 2b8a ; -------------------------------------------------------------------------------------- 2b8a ; 0x00db Load_Top At_Offset_3 2b8a ; -------------------------------------------------------------------------------------- 2b8a MACRO_Load_Top_At_Offset_3: 2b8a 2b8a dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2b8a fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1d TOP - 3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8b 2b8b <halt> ; Flow R 2b8c ; -------------------------------------------------------------------------------------- 2b8c ; 0x00dc Load_Top At_Offset_4 2b8c ; -------------------------------------------------------------------------------------- 2b8c MACRO_Load_Top_At_Offset_4: 2b8c 2b8c dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2b8c fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1c TOP - 4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1c TOP - 4 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8d 2b8d <halt> ; Flow R 2b8e ; -------------------------------------------------------------------------------------- 2b8e ; 0x00dd Load_Top At_Offset_5 2b8e ; -------------------------------------------------------------------------------------- 2b8e MACRO_Load_Top_At_Offset_5: 2b8e 2b8e dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 2b8e fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1b TOP - 5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1b TOP - 5 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8f 2b8f <halt> ; Flow R 2b90 ; -------------------------------------------------------------------------------------- 2b90 ; 0x00de Load_Top At_Offset_6 2b90 ; -------------------------------------------------------------------------------------- 2b90 MACRO_Load_Top_At_Offset_6: 2b90 2b90 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6e dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2b90 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1a TOP - 6 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1a TOP - 6 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b91 2b91 <halt> ; Flow R 2b92 ; -------------------------------------------------------------------------------------- 2b92 ; 0x00e0 Load_Encached eon 2b92 ; -------------------------------------------------------------------------------------- 2b92 MACRO_Load_Encached_eon: 2b92 2b92 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b92 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR0b:00 typ_alu_func 15 NOT_B typ_b_adr 20 TR0b:00 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 20 VR0b:00 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b93 2b93 <halt> ; Flow R 2b94 ; -------------------------------------------------------------------------------------- 2b94 ; 0x00e1 Load_Encached eon 2b94 ; -------------------------------------------------------------------------------------- 2b94 MACRO_Load_Encached_eon: 2b94 2b94 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b94 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR0b:01 typ_alu_func 15 NOT_B typ_b_adr 21 TR0b:01 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 21 VR0b:01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b95 2b95 <halt> ; Flow R 2b96 ; -------------------------------------------------------------------------------------- 2b96 ; 0x00e2 Load_Encached eon 2b96 ; -------------------------------------------------------------------------------------- 2b96 MACRO_Load_Encached_eon: 2b96 2b96 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b96 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 22 TR0b:02 typ_alu_func 15 NOT_B typ_b_adr 22 TR0b:02 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 22 VR0b:02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b97 2b97 <halt> ; Flow R 2b98 ; -------------------------------------------------------------------------------------- 2b98 ; 0x00e3 Load_Encached eon 2b98 ; -------------------------------------------------------------------------------------- 2b98 MACRO_Load_Encached_eon: 2b98 2b98 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b98 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 23 TR0b:03 typ_alu_func 15 NOT_B typ_b_adr 23 TR0b:03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 23 VR0b:03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b99 2b99 <halt> ; Flow R 2b9a ; -------------------------------------------------------------------------------------- 2b9a ; 0x00e4 Load_Encached eon 2b9a ; -------------------------------------------------------------------------------------- 2b9a MACRO_Load_Encached_eon: 2b9a 2b9a dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9a fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 24 TR0b:04 typ_alu_func 15 NOT_B typ_b_adr 24 TR0b:04 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 24 VR0b:04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9b 2b9b <halt> ; Flow R 2b9c ; -------------------------------------------------------------------------------------- 2b9c ; 0x00e5 Load_Encached eon 2b9c ; -------------------------------------------------------------------------------------- 2b9c MACRO_Load_Encached_eon: 2b9c 2b9c dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 25 TR0b:05 typ_alu_func 15 NOT_B typ_b_adr 25 TR0b:05 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 25 VR0b:05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9d 2b9d <halt> ; Flow R 2b9e ; -------------------------------------------------------------------------------------- 2b9e ; 0x00e6 Load_Encached eon 2b9e ; -------------------------------------------------------------------------------------- 2b9e MACRO_Load_Encached_eon: 2b9e 2b9e dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9e fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 26 TR0b:06 typ_alu_func 15 NOT_B typ_b_adr 26 TR0b:06 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 26 VR0b:06 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9f 2b9f <halt> ; Flow R 2ba0 ; -------------------------------------------------------------------------------------- 2ba0 ; 0x00e7 Load_Encached eon 2ba0 ; -------------------------------------------------------------------------------------- 2ba0 MACRO_Load_Encached_eon: 2ba0 2ba0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 27 TR0b:07 typ_alu_func 15 NOT_B typ_b_adr 27 TR0b:07 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 27 VR0b:07 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba1 2ba1 <halt> ; Flow R 2ba2 ; -------------------------------------------------------------------------------------- 2ba2 ; 0x00e8 Load_Encached eon 2ba2 ; -------------------------------------------------------------------------------------- 2ba2 MACRO_Load_Encached_eon: 2ba2 2ba2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR0b:08 typ_alu_func 15 NOT_B typ_b_adr 28 TR0b:08 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 28 VR0b:08 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba3 2ba3 <halt> ; Flow R 2ba4 ; -------------------------------------------------------------------------------------- 2ba4 ; 0x00e9 Load_Encached eon 2ba4 ; -------------------------------------------------------------------------------------- 2ba4 MACRO_Load_Encached_eon: 2ba4 2ba4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 29 TR0b:09 typ_alu_func 15 NOT_B typ_b_adr 29 TR0b:09 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 29 VR0b:09 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba5 2ba5 <halt> ; Flow R 2ba6 ; -------------------------------------------------------------------------------------- 2ba6 ; 0x00ea Load_Encached eon 2ba6 ; -------------------------------------------------------------------------------------- 2ba6 MACRO_Load_Encached_eon: 2ba6 2ba6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR0b:0a typ_alu_func 15 NOT_B typ_b_adr 2a TR0b:0a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2a VR0b:0a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba7 2ba7 <halt> ; Flow R 2ba8 ; -------------------------------------------------------------------------------------- 2ba8 ; 0x00eb Load_Encached eon 2ba8 ; -------------------------------------------------------------------------------------- 2ba8 MACRO_Load_Encached_eon: 2ba8 2ba8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2b TR0b:0b typ_alu_func 15 NOT_B typ_b_adr 2b TR0b:0b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2b VR0b:0b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba9 2ba9 <halt> ; Flow R 2baa ; -------------------------------------------------------------------------------------- 2baa ; 0x00ec Load_Encached eon 2baa ; -------------------------------------------------------------------------------------- 2baa MACRO_Load_Encached_eon: 2baa 2baa dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2baa fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2c TR0b:0c typ_alu_func 15 NOT_B typ_b_adr 2c TR0b:0c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2c VR0b:0c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bab 2bab <halt> ; Flow R 2bac ; -------------------------------------------------------------------------------------- 2bac ; 0x00ed Load_Encached eon 2bac ; -------------------------------------------------------------------------------------- 2bac MACRO_Load_Encached_eon: 2bac 2bac dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bac fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR0b:0d typ_alu_func 15 NOT_B typ_b_adr 2d TR0b:0d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2d VR0b:0d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bad 2bad <halt> ; Flow R 2bae ; -------------------------------------------------------------------------------------- 2bae ; 0x00ee Load_Encached eon 2bae ; -------------------------------------------------------------------------------------- 2bae MACRO_Load_Encached_eon: 2bae 2bae dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bae fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2e TR0b:0e typ_alu_func 15 NOT_B typ_b_adr 2e TR0b:0e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR0b:0e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2baf 2baf <halt> ; Flow R 2bb0 ; -------------------------------------------------------------------------------------- 2bb0 ; 0x00ef Load_Encached eon 2bb0 ; -------------------------------------------------------------------------------------- 2bb0 MACRO_Load_Encached_eon: 2bb0 2bb0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2f TR0b:0f typ_alu_func 15 NOT_B typ_b_adr 2f TR0b:0f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR0b:0f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb1 2bb1 <halt> ; Flow R 2bb2 ; -------------------------------------------------------------------------------------- 2bb2 ; 0x00f0 Load_Encached eon 2bb2 ; -------------------------------------------------------------------------------------- 2bb2 MACRO_Load_Encached_eon: 2bb2 2bb2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 30 TR0b:10 typ_alu_func 15 NOT_B typ_b_adr 30 TR0b:10 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR0b:10 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb3 2bb3 <halt> ; Flow R 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 ; 0x00f1 Load_Encached eon 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 MACRO_Load_Encached_eon: 2bb4 2bb4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 31 TR0b:11 typ_alu_func 15 NOT_B typ_b_adr 31 TR0b:11 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 31 VR0b:11 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb5 2bb5 <halt> ; Flow R 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 ; 0x00f2 Load_Encached eon 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 MACRO_Load_Encached_eon: 2bb6 2bb6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 32 TR0b:12 typ_alu_func 15 NOT_B typ_b_adr 32 TR0b:12 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 32 VR0b:12 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb7 2bb7 <halt> ; Flow R 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 ; 0x00f3 Load_Encached eon 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 MACRO_Load_Encached_eon: 2bb8 2bb8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 33 TR0b:13 typ_alu_func 15 NOT_B typ_b_adr 33 TR0b:13 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 33 VR0b:13 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb9 2bb9 <halt> ; Flow R 2bba ; -------------------------------------------------------------------------------------- 2bba ; 0x00f4 Load_Encached eon 2bba ; -------------------------------------------------------------------------------------- 2bba MACRO_Load_Encached_eon: 2bba 2bba dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bba fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 34 TR0b:14 typ_alu_func 15 NOT_B typ_b_adr 34 TR0b:14 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 34 VR0b:14 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbb 2bbb <halt> ; Flow R 2bbc ; -------------------------------------------------------------------------------------- 2bbc ; 0x00f5 Load_Encached eon 2bbc ; -------------------------------------------------------------------------------------- 2bbc MACRO_Load_Encached_eon: 2bbc 2bbc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 35 TR0b:15 typ_alu_func 15 NOT_B typ_b_adr 35 TR0b:15 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 35 VR0b:15 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbd 2bbd <halt> ; Flow R 2bbe ; -------------------------------------------------------------------------------------- 2bbe ; 0x00f6 Load_Encached eon 2bbe ; -------------------------------------------------------------------------------------- 2bbe MACRO_Load_Encached_eon: 2bbe 2bbe dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR0b:16 typ_alu_func 15 NOT_B typ_b_adr 36 TR0b:16 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 36 VR0b:16 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbf 2bbf <halt> ; Flow R 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 ; 0x00f7 Load_Encached eon 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 MACRO_Load_Encached_eon: 2bc0 2bc0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR0b:17 typ_alu_func 15 NOT_B typ_b_adr 37 TR0b:17 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR0b:17 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc1 2bc1 <halt> ; Flow R 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 ; 0x00f8 Load_Encached eon 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 MACRO_Load_Encached_eon: 2bc2 2bc2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR0b:18 typ_alu_func 15 NOT_B typ_b_adr 38 TR0b:18 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR0b:18 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc3 2bc3 <halt> ; Flow R 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 ; 0x00f9 Load_Encached eon 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 MACRO_Load_Encached_eon: 2bc4 2bc4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR0b:19 typ_alu_func 15 NOT_B typ_b_adr 39 TR0b:19 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR0b:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc5 2bc5 <halt> ; Flow R 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 ; 0x00fa Load_Encached eon 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 MACRO_Load_Encached_eon: 2bc6 2bc6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3a TR0b:1a typ_alu_func 15 NOT_B typ_b_adr 3a TR0b:1a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3a VR0b:1a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc7 2bc7 <halt> ; Flow R 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 ; 0x00fb Load_Encached eon 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 MACRO_Load_Encached_eon: 2bc8 2bc8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3b TR0b:1b typ_alu_func 15 NOT_B typ_b_adr 3b TR0b:1b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR0b:1b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc9 2bc9 <halt> ; Flow R 2bca ; -------------------------------------------------------------------------------------- 2bca ; 0x00fc Load_Encached eon 2bca ; -------------------------------------------------------------------------------------- 2bca MACRO_Load_Encached_eon: 2bca 2bca dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bca fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3c TR0b:1c typ_alu_func 15 NOT_B typ_b_adr 3c TR0b:1c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3c VR0b:1c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcb 2bcb <halt> ; Flow R 2bcc ; -------------------------------------------------------------------------------------- 2bcc ; 0x00fd Load_Encached eon 2bcc ; -------------------------------------------------------------------------------------- 2bcc MACRO_Load_Encached_eon: 2bcc 2bcc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bcc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR0b:1d typ_alu_func 15 NOT_B typ_b_adr 3d TR0b:1d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3d VR0b:1d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcd 2bcd <halt> ; Flow R 2bce ; -------------------------------------------------------------------------------------- 2bce ; 0x00fe Load_Encached eon 2bce ; -------------------------------------------------------------------------------------- 2bce MACRO_Load_Encached_eon: 2bce 2bce dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bd1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bce fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR0b:1e typ_alu_func 15 NOT_B typ_b_adr 3e TR0b:1e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3e VR0b:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcf 2bcf <halt> ; Flow R 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 ; 0x00ff Load_Encached eon 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 MACRO_Load_Encached_eon: 2bd0 2bd0 dispatch_brk_class 4 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bd1 0x2bd1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3f TR0b:1f typ_alu_func 15 NOT_B typ_b_adr 3f TR0b:1f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR0b:1f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd1 2bd1 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2bd2 ; -------------------------------------------------------------------------------------- 2bd2 ; 0x1b00-0x1bff Execute Package,Field_Read,fieldnum 2bd2 ; -------------------------------------------------------------------------------------- 2bd2 MACRO_Execute_Package,Field_Read,fieldnum: 2bd2 2bd2 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2bd2 dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2bd3 2bd3 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_random 17 force type bus receivers ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2bd4 0x2bd4 seq_cond_sel 79 IOC.PFR seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bd4 2bd4 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2bdf seq_br_type 0 Branch False seq_branch_adr 2bdf 0x2bdf seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2bd5 2bd5 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2b7a ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2b7a 0x2b7a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2bd6 2bd6 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2b82 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 2b82 0x2b82 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 0 PASS_A 2bd7 2bd7 seq_br_type 1 Branch True; Flow J cc=True 0x2b6f seq_branch_adr 2b6f 0x2b6f seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 2bd8 2bd8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 2bd9 2bd9 <halt> ; Flow R 2bda ; -------------------------------------------------------------------------------------- 2bda ; 0x0098 Execute Package,Field_Read_Dynamic 2bda ; -------------------------------------------------------------------------------------- 2bda MACRO_Execute_Package,Field_Read_Dynamic: 2bda 2bda dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2bda fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2bdb 2bdb fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2bdc 2bdc ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2bdd 2bdd fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bde 0x2bde seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bde 2bde ioc_tvbs 2 fiu+val; Flow J 0x2bd5 seq_br_type 3 Unconditional Branch seq_branch_adr 2bd5 0x2bd5 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2bdf 2bdf fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32aa ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2be0 2be0 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2be1 2be1 seq_br_type 4 Call False; Flow C cc=False 0x326e seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR1b:0d val_frame 1b 2be2 2be2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be6 seq_br_type 1 Branch True seq_branch_adr 2be6 0x2be6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 1f TOP - 1 typ_frame 1 val_a_adr 26 VR12:06 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 12 2be3 2be3 ioc_fiubs 1 val ; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 2be4 2be4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be8 seq_br_type 1 Branch True seq_branch_adr 2be8 0x2be8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 10 NOT_A val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 2be5 2be5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2be6 2be6 ioc_fiubs 1 val ; Flow J cc=False 0x2be4 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2be4 0x2be4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1b val_a_adr 17 LOOP_COUNTER 2be7 2be7 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2be8 2be8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326e seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2be9 2be9 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 2bea ; -------------------------------------------------------------------------------------- 2bea ; 0x009a Action Call_Dynamic 2bea ; -------------------------------------------------------------------------------------- 2bea MACRO_Action_Call_Dynamic: 2bea 2bea dispatch_brk_class 6 ; Flow C 0x2c70 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2bea seq_br_type 7 Unconditional Call seq_branch_adr 2c70 0x2c70 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2beb 2beb fiu_mem_start 2 start-rd; Flow J cc=True 0x2bf4 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2bf4 MACRO_Call_llvl,ldelta 2bec ; -------------------------------------------------------------------------------------- 2bec ; 0x8200-0x9fff Call llvl,ldelta 2bec ; -------------------------------------------------------------------------------------- 2bec MACRO_Call_llvl,ldelta: 2bec 2bec dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2bec fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2bed 2bed fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2bef fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2bef 0x2bef seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 50 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2bee 2bee fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c07 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c07 0x2c07 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bef 2bef fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c3a ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c3a 0x2c3a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A 2bf0 2bf0 seq_br_type 2 Push (branch address); Flow J 0x2bf1 seq_branch_adr 2c07 0x2c07 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2bf1 2bf1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c3f 0x2c3f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf2 2bf2 fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c37 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c37 0x2c37 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bf3 2bf3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2bf4 ; -------------------------------------------------------------------------------------- 2bf4 ; 0x8000-0x81ff Call llvl,ldelta 2bf4 ; -------------------------------------------------------------------------------------- 2bf4 MACRO_Call_llvl,ldelta: 2bf4 2bf4 dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2bf4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 14 ZEROS typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2bf5 2bf5 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf6 2bf6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 37 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2bf7 2bf7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2c37 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c37 0x2c37 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf8 2bf8 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c07 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c07 0x2c07 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bf9 2bf9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2bf3 seq_br_type 3 Unconditional Branch seq_branch_adr 2bf3 0x2bf3 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2bfa ; -------------------------------------------------------------------------------------- 2bfa ; 0x1800-0x18ff Execute Package,Field_Execute,fieldnum 2bfa ; -------------------------------------------------------------------------------------- 2bfa MACRO_Execute_Package,Field_Execute,fieldnum: 2bfa 2bfa dispatch_brk_class 6 ; Flow J cc=True 0x3b98 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2bfa dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3b98 0x3b98 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 0a ? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 18 NOT_A_AND_B val_b_adr 22 VR11:02 val_frame 11 2bfb 2bfb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2bfd fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2bfd 0x2bfd seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 4a Load_current_lex+? typ_a_adr 20 TR16:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2bfc 2bfc fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c07 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c07 0x2c07 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bfd 2bfd seq_br_type 0 Branch False; Flow J cc=False 0x2c02 seq_branch_adr 2c02 0x2c02 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 val_c_adr 3e GP01 2bfe 2bfe fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c3b ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c3b 0x2c3b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 2bff 2bff seq_br_type 2 Push (branch address); Flow J 0x2c00 seq_branch_adr 2c07 0x2c07 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2c00 2c00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c3f 0x2c3f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c01 2c01 fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c37 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c37 0x2c37 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c02 2c02 seq_br_type 1 Branch True; Flow J cc=True 0x2c3b seq_branch_adr 2c3b 0x2c3b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_frame 10 2c03 2c03 ioc_load_wdr 0 ; Flow J 0x2c3b seq_br_type 3 Unconditional Branch seq_branch_adr 2c3b 0x2c3b typ_b_adr 29 TR05:09 typ_frame 5 val_b_adr 01 GP01 2c04 ; -------------------------------------------------------------------------------------- 2c04 ; 0x0096 Execute Package,Field_Execute_Dynamic 2c04 ; -------------------------------------------------------------------------------------- 2c04 MACRO_Execute_Package,Field_Execute_Dynamic: 2c04 2c04 dispatch_brk_class 6 ; Flow C cc=False 0x32ae dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c04 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c05 2c05 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a7 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2c06 2c06 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2bfb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2bfb 0x2bfb seq_int_reads 5 RESOLVE RAM seq_random 0a ? 2c07 2c07 ioc_fiubs 0 fiu ; Flow J cc=False 0x2c09 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c09 0x2c09 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 2d Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c08 2c08 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x2bf3 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bf3 0x2bf3 seq_cond_sel 4f SEQ.uE_field_number_error seq_random 54 Load_save_offset+Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c09 2c09 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2c29 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2c29 0x2c29 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c0a ; -------------------------------------------------------------------------------------- 2c0a ; 0x1c00-0x1cff Execute_Immediate Run_Utility,uimmediate 2c0a ; -------------------------------------------------------------------------------------- 2c0a MACRO_Execute_Immediate_Run_Utility,uimmediate: 2c0a 2c0a dispatch_brk_class 6 ; Flow C cc=True 0x32a7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_uadr 2c0a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2c0b 2c0b fiu_tivi_src 4 fiu_var; Flow J cc=False 0x32a7 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c0c 2c0c fiu_load_tar 1 hold_tar; Flow J cc=True 0x2c25 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c25 0x2c25 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 2d TR1b:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 2c0d 2c0d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4c Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 2c0e 2c0e fiu_load_tar 1 hold_tar; Flow J cc=False 0x2c1d fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c1d 0x2c1d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2c0f 2c0f fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c10 2c10 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c1a fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c1a 0x2c1a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c11 2c11 ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c12 2c12 fiu_load_var 1 hold_var; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2c13 0x2c13 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c13 2c13 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2c14 2c14 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 2c15 2c15 fiu_len_fill_lit 4c zero-fill 0xc; Flow R cc=False ; Flow J cc=True 0x32fe fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 32fe 0x32fe seq_random 04 Load_save_offset+? typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 21 TOP - 0x2 val_c_source 0 FIU_BUS 2c16 ; -------------------------------------------------------------------------------------- 2c16 ; 0x0127 Execute Any,Run_Initialization_Utility 2c16 ; -------------------------------------------------------------------------------------- 2c16 MACRO_Execute_Any,Run_Initialization_Utility: 2c16 2c16 dispatch_brk_class 6 ; Flow C cc=True 0x32a7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2c16 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c17 2c17 seq_br_type 0 Branch False; Flow J cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 2c18 2c18 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2c19 0x2c19 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR05:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 2c19 2c19 fiu_mem_start 2 start-rd; Flow J 0x2c0b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c0b 0x2c0b typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 2c1a 2c1a ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c1b 2c1b fiu_load_var 1 hold_var; Flow C cc=True 0x2c13 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c13 0x2c13 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c1c 2c1c fiu_mem_start 2 start-rd; Flow J 0x2c29 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c29 0x2c29 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2c1d 2c1d fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c1e 2c1e ioc_fiubs 0 fiu typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c1f 2c1f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2c20 2c20 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 10 TOP typ_c_adr 3d GP02 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c21 2c21 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 1d TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2c22 2c22 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2c23 2c23 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2c13 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c13 0x2c13 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c24 2c24 fiu_mem_start 2 start-rd; Flow J 0x2c29 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c29 0x2c29 seq_random 15 ? typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE 2c25 2c25 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 2c26 0x2c26 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL 2c26 2c26 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2c27 2c27 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2c28 2c28 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c29 2c29 seq_br_type 3 Unconditional Branch; Flow J 0x2bf9 seq_branch_adr 2bf9 0x2bf9 2c2a ; -------------------------------------------------------------------------------------- 2c2a ; 0x00c5 Action Set_Block_Start 2c2a ; -------------------------------------------------------------------------------------- 2c2a MACRO_Action_Set_Block_Start: 2c2a 2c2a dispatch_brk_class 8 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2c2a ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c2b 2c2b fiu_len_fill_lit 4e zero-fill 0xe fiu_load_mdr 1 hold_mdr fiu_offs_lit 54 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2c2c 2c2c fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c2d fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2bf9 0x2bf9 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2c2d 2c2d fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_random 16 ? typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_c_adr 1d VR02:02 val_c_source 0 FIU_BUS val_frame 2 2c2e 2c2e fiu_mem_start 2 start-rd; Flow J 0x32fe ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe seq_random 02 ? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2c2f ; -------------------------------------------------------------------------------------- 2c2f ; Comes from: 2c2f ; 2c37 C from color 0x0000 2c2f ; 2c3b C from color 0x0000 2c2f ; 2c40 C from color 0x0000 2c2f ; -------------------------------------------------------------------------------------- 2c2f 2c2f fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2c30 2c30 ioc_fiubs 1 val seq_random 41 Load_control_pred+? val_a_adr 3e VR02:1e val_frame 2 2c31 2c31 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 2c32 2c32 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3e ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c33 2c33 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_random 6c Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2c34 2c34 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 2c35 2c35 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c36 2c36 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2c37 2c37 fiu_load_var 1 hold_var; Flow C 0x2c2f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2f 0x2c2f seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c38 2c38 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c39 2c39 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2c3a 2c3a seq_br_type 3 Unconditional Branch; Flow J 0x2c37 seq_branch_adr 2c37 0x2c37 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c3b 2c3b fiu_load_var 1 hold_var; Flow C 0x2c2f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2f 0x2c2f seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c3c 2c3c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c3d 2c3d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279 seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_frame 2 2c3e 2c3e seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 2c3f 2c3f ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2c40 2c40 fiu_load_var 1 hold_var; Flow C 0x2c2f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2f 0x2c2f seq_en_micro 0 seq_random 0a ? val_a_adr 3e VR02:1e val_frame 2 2c41 2c41 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 2c42 2c42 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_b_adr 16 CSA/VAL_BUS 2c43 2c43 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? val_a_adr 05 GP05 2c44 2c44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c45 2c45 <halt> ; Flow R 2c46 ; -------------------------------------------------------------------------------------- 2c46 ; 0x1d00-0x1dff Execute_Immediate Reference_Lex_1,uimmediate 2c46 ; -------------------------------------------------------------------------------------- 2c46 MACRO_Execute_Immediate_Reference_Lex_1,uimmediate: 2c46 2c46 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2c46 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME 2c47 2c47 fiu_mem_start 2 start-rd; Flow J 0x2c4a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c4a 0x2c4a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2c48 ; -------------------------------------------------------------------------------------- 2c48 ; 0x0099 Action Reference_Dynamic 2c48 ; -------------------------------------------------------------------------------------- 2c48 MACRO_Action_Reference_Dynamic: 2c48 2c48 dispatch_brk_class 4 ; Flow C 0x2c70 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c48 seq_br_type 7 Unconditional Call seq_branch_adr 2c70 0x2c70 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2c49 2c49 fiu_mem_start 2 start-rd; Flow J cc=True 0x2c58 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c58 MACRO_Reference_zdelta 2c4a 2c4a fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 32 TR05:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2c4b 2c4b fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4c 0x2c4c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 1c ? typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c4c 2c4c fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4d 0x2c4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2c4d 2c4d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x2c4f seq_br_type f Unconditional Case Call seq_branch_adr 2c4f 0x2c4f seq_en_micro 0 2c4e 2c4e seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2c4f ; -------------------------------------------------------------------------------------- 2c4f ; Comes from: 2c4f ; 2c4d C #0x0 from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2c4f ; -------------------------------------------------------------------------------------- 2c4f 2c4f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c50 2c50 seq_br_type a Unconditional Return; Flow R 2c51 2c51 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c52 2c52 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c53 2c53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c54 2c54 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2c4e ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4e 0x2c4e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL 2c55 2c55 seq_br_type a Unconditional Return; Flow R 2c56 2c56 seq_br_type a Unconditional Return; Flow R 2c57 2c57 <halt> ; Flow R 2c58 ; -------------------------------------------------------------------------------------- 2c58 ; 0xa000-0xa1ff Reference zdelta 2c58 ; -------------------------------------------------------------------------------------- 2c58 MACRO_Reference_zdelta: 2c58 2c58 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2c58 2c59 2c59 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c5a 0x2c5a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 1c ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c5a 2c5a seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 2c5b 2c5b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2c5c ; -------------------------------------------------------------------------------------- 2c5c ; 0x1900-0x19ff Execute Package,Field_Reference,fieldnum 2c5c ; -------------------------------------------------------------------------------------- 2c5c MACRO_Execute_Package,Field_Reference,fieldnum: 2c5c 2c5c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2c5c dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c5d 2c5d fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c5e 2c5e fiu_len_fill_lit 01 sign-fill 0x1; Flow J cc=True 0x2c5f ; Flow J cc=#0x0 0x2c60 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2c60 0x2c60 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c5f 2c5f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c60 2c60 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c61 2c61 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c62 2c62 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c63 2c63 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 32 TR05:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c64 2c64 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c65 2c65 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c66 2c66 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c68 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c67 2c67 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c68 2c68 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2c69 2c69 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2c6a 0x2c6a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2c6a 2c6a seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c6b 2c6b <halt> ; Flow R 2c6c ; -------------------------------------------------------------------------------------- 2c6c ; 0x0095 Execute Package,Field_Reference_Dynamic 2c6c ; -------------------------------------------------------------------------------------- 2c6c MACRO_Execute_Package,Field_Reference_Dynamic: 2c6c 2c6c dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c6c fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2c6d 2c6d fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c6e 2c6e fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 1f TOP - 1 val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c6f 2c6f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2c5e fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2c5e 0x2c5e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c70 ; -------------------------------------------------------------------------------------- 2c70 ; Comes from: 2c70 ; 1c9a C from color 0x0000 2c70 ; 2b6a C from color 0x0000 2c70 ; 2bea C from color 0x0000 2c70 ; 2c48 C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2c70 ; -------------------------------------------------------------------------------------- 2c70 2c70 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x2c76 fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2c76 0x2c76 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c71 2c71 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ae fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2c72 2c72 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x2c75 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2c75 0x2c75 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 2c73 2c73 val_rand 2 DEC_LOOP_COUNTER 2c74 2c74 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2c73 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2c73 0x2c73 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2c75 2c75 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2c76 2c76 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32ae fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2c77 2c77 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c75 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2c75 0x2c75 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c78 2c78 ioc_adrbs 1 val ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 0 PASS_A 2c79 2c79 <halt> ; Flow R 2c7a ; -------------------------------------------------------------------------------------- 2c7a ; 0x1100-0x11ff Execute Select,Member_Write,fieldnum 2c7a ; -------------------------------------------------------------------------------------- 2c7a MACRO_Execute_Select,Member_Write,fieldnum: 2c7a 2c7a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2c7a fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 2c7b 2c7b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2c8e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c8e 0x2c8e seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2c7c 2c7c fiu_mem_start 2 start-rd; Flow C cc=False 0x32ae ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c7d 2c7d seq_br_type 4 Call False; Flow C cc=False 0x3276 seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR06:16 val_frame 6 2c7e 2c7e fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=False 0x2c86 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c86 0x2c86 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2c7f 2c7f fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 2c80 2c80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3276 fiu_offs_lit 07 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c81 2c81 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS 2c82 2c82 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2c83 2c83 fiu_mem_start 3 start-wr; Flow C cc=False 0x3276 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c84 2c84 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 2c85 2c85 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c86 ; -------------------------------------------------------------------------------------- 2c86 ; Comes from: 2c86 ; 2c7e C False from color MACRO_Execute_Select,Member_Write,fieldnum 2c86 ; -------------------------------------------------------------------------------------- 2c86 2c86 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL 2c87 2c87 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 2c88 2c88 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c89 2c89 fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x3276 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c8a 2c8a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 19 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2c8b 2c8b fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2c8c 2c8c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2c8d 0x2c8d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2c8d 2c8d seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 2c8e 2c8e fiu_mem_start 2 start-rd; Flow C cc=False 0x32ae ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c8f 2c8f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2c7e seq_br_type 0 Branch False seq_branch_adr 2c7e 0x2c7e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 2c90 2c90 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 2c91 2c91 <halt> ; Flow R 2c92 ; -------------------------------------------------------------------------------------- 2c92 ; 0x1000-0x10ff Execute Select,Guard_Write,fieldnum 2c92 ; -------------------------------------------------------------------------------------- 2c92 MACRO_Execute_Select,Guard_Write,fieldnum: 2c92 2c92 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2c92 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2c93 2c93 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2c94 2c94 fiu_mem_start 2 start-rd; Flow C cc=False 0x32ae ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ae 0x32ae seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c95 2c95 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2c99 seq_br_type 1 Branch True seq_branch_adr 2c99 0x2c99 typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2c96 2c96 fiu_mem_start 7 start_wr_if_true ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 3a TR06:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c97 2c97 ioc_load_wdr 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2c98 2c98 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c99 2c99 fiu_mem_start 3 start-wr; Flow J 0x2c97 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2c97 0x2c97 typ_a_adr 3a TR06:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c9a ; -------------------------------------------------------------------------------------- 2c9a ; 0x013d Execute Select,Timed_Duration_Write 2c9a ; -------------------------------------------------------------------------------------- 2c9a MACRO_Execute_Select,Timed_Duration_Write: 2c9a 2c9a dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2c9a fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2c9b 2c9b ioc_fiubs 2 typ ; Flow C cc=False 0x32b2 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32b2 0x32b2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c9c 2c9c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_b_adr 3a TR07:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B 2c9d 2c9d ioc_load_wdr 0 ; Flow J cc=True 0x2c9f ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c9f 0x2c9f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_frame 7 val_a_adr 25 VR07:05 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_frame 7 2c9e 2c9e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c9f 2c9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ae seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 2 PUSH_CSA typ_frame 7 2ca0 2ca0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326e seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 1a PASS_B val_b_adr 10 TOP 2ca1 2ca1 fiu_mem_start 3 start-wr; Flow J 0x2c9d ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c9d 0x2c9d typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 2ca2 ; -------------------------------------------------------------------------------------- 2ca2 ; 0x013e Execute Select,Timed_Guard_Write 2ca2 ; -------------------------------------------------------------------------------------- 2ca2 MACRO_Execute_Select,Timed_Guard_Write: 2ca2 2ca2 dispatch_brk_class 8 ; Flow C cc=False 0x32b2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ca2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32b2 0x32b2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ca3 2ca3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2ca4 2ca4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2ca5 2ca5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2ca6 ; -------------------------------------------------------------------------------------- 2ca6 ; 0x013c Execute Select,Terminate_Guard_Write 2ca6 ; -------------------------------------------------------------------------------------- 2ca6 MACRO_Execute_Select,Terminate_Guard_Write: 2ca6 2ca6 dispatch_brk_class 8 ; Flow C cc=False 0x32b2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ca6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32b2 0x32b2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ca7 2ca7 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2ca8 2ca8 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2ca9 2ca9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2caa ; -------------------------------------------------------------------------------------- 2caa ; 0x029f Declare_Subprogram For_Call,subp 2caa ; -------------------------------------------------------------------------------------- 2caa MACRO_Declare_Subprogram_For_Call,subp: 2caa 2caa dispatch_brk_class 4 ; Flow J 0x2cab dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2caa fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cab 2cab fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cac ; -------------------------------------------------------------------------------------- 2cac ; 0x029e Declare_Subprogram For_Call,Unelaborated,subp 2cac ; -------------------------------------------------------------------------------------- 2cac MACRO_Declare_Subprogram_For_Call,Unelaborated,subp: 2cac 2cac dispatch_brk_class 4 ; Flow J 0x2cad dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cac fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cad 2cad fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cae ; -------------------------------------------------------------------------------------- 2cae ; 0x029d Declare_Subprogram For_Outer_Call,subp 2cae ; -------------------------------------------------------------------------------------- 2cae MACRO_Declare_Subprogram_For_Outer_Call,subp: 2cae 2cae dispatch_brk_class 4 ; Flow J 0x2caf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2caf 2caf fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR07:10 val_frame 7 2cb0 ; -------------------------------------------------------------------------------------- 2cb0 ; 0x029c Declare_Subprogram For_Outer_Call,Visible,subp 2cb0 ; -------------------------------------------------------------------------------------- 2cb0 MACRO_Declare_Subprogram_For_Outer_Call,Visible,subp: 2cb0 2cb0 dispatch_brk_class 4 ; Flow J 0x2cb1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cb0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cb1 2cb1 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR07:0b val_frame 7 2cb2 ; -------------------------------------------------------------------------------------- 2cb2 ; 0x029b Declare_Subprogram For_Outer_Call,Unelaborated,subp 2cb2 ; -------------------------------------------------------------------------------------- 2cb2 MACRO_Declare_Subprogram_For_Outer_Call,Unelaborated,subp: 2cb2 2cb2 dispatch_brk_class 4 ; Flow J 0x2cb3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cb2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cb3 2cb3 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_frame 5 2cb4 ; -------------------------------------------------------------------------------------- 2cb4 ; 0x029a Declare_Subprogram For_Outer_Call,Visible,Unelaborated,subp 2cb4 ; -------------------------------------------------------------------------------------- 2cb4 MACRO_Declare_Subprogram_For_Outer_Call,Visible,Unelaborated,subp: 2cb4 2cb4 dispatch_brk_class 4 ; Flow J 0x2cb5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cb4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cb5 2cb5 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb9 0x2cb9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR07:0a val_frame 7 2cb6 2cb6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2cb7 0x2cb7 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cb7 2cb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ac seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cb8 2cb8 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 2cb9 2cb9 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE 2cba 2cba ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2cbb 2cbb <halt> ; Flow R 2cbc ; -------------------------------------------------------------------------------------- 2cbc ; 0x0299 Declare_Subprogram For_Accept,subp 2cbc ; -------------------------------------------------------------------------------------- 2cbc MACRO_Declare_Subprogram_For_Accept,subp: 2cbc 2cbc dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cbc fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 2cbd 2cbd fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x32ac fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 2cbe 2cbe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2cbf 2cbf fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cc0 ; -------------------------------------------------------------------------------------- 2cc0 ; 0x02ab Declare_Subprogram For_Call,With_Address 2cc0 ; -------------------------------------------------------------------------------------- 2cc0 MACRO_Declare_Subprogram_For_Call,With_Address: 2cc0 2cc0 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc1 2cc1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccd 0x2ccd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 ; 0x02aa Declare_Subprogram For_Call,Visible,With_Address 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 MACRO_Declare_Subprogram_For_Call,Visible,With_Address: 2cc2 2cc2 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc3 2cc3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccc 0x2ccc seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc4 ; -------------------------------------------------------------------------------------- 2cc4 ; 0x02a9 Declare_Subprogram For_Call,Unelaborated,With_Address 2cc4 ; -------------------------------------------------------------------------------------- 2cc4 MACRO_Declare_Subprogram_For_Call,Unelaborated,With_Address: 2cc4 2cc4 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc5 2cc5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccd 0x2ccd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc6 ; -------------------------------------------------------------------------------------- 2cc6 ; 0x02a8 Declare_Subprogram For_Call,Visible,Unelaborated,With_Address 2cc6 ; -------------------------------------------------------------------------------------- 2cc6 MACRO_Declare_Subprogram_For_Call,Visible,Unelaborated,With_Address: 2cc6 2cc6 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc7 2cc7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccc 0x2ccc seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2a TR05:0a typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc8 ; -------------------------------------------------------------------------------------- 2cc8 ; 0x02a5 Declare_Subprogram For_Outer_Call,With_Address 2cc8 ; -------------------------------------------------------------------------------------- 2cc8 MACRO_Declare_Subprogram_For_Outer_Call,With_Address: 2cc8 2cc8 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc8 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2cc9 2cc9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccd 0x2ccd seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2cca ; -------------------------------------------------------------------------------------- 2cca ; 0x02a4 Declare_Subprogram For_Outer_Call,Visible,With_Address 2cca ; -------------------------------------------------------------------------------------- 2cca MACRO_Declare_Subprogram_For_Outer_Call,Visible,With_Address: 2cca 2cca dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cca fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2ccb 2ccb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccc 0x2ccc seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2ccc 2ccc seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2ccd 2ccd fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2cce 0x2cce seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cce 2cce seq_br_type 3 Unconditional Branch; Flow J 0x32ac seq_branch_adr 32ac 0x32ac typ_csa_cntl 3 POP_CSA 2ccf 2ccf <halt> ; Flow R 2cd0 ; -------------------------------------------------------------------------------------- 2cd0 ; 0x02a2 Declare_Subprogram For_Accept,With_Address 2cd0 ; -------------------------------------------------------------------------------------- 2cd0 MACRO_Declare_Subprogram_For_Accept,With_Address: 2cd0 2cd0 dispatch_brk_class 4 ; Flow J cc=True 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2cd0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cd1 2cd1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ac fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cd2 2cd2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd3 2cd3 fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cd4 ; -------------------------------------------------------------------------------------- 2cd4 ; 0x02a0 Declare_Subprogram Null_Subprogram 2cd4 ; -------------------------------------------------------------------------------------- 2cd4 MACRO_Declare_Subprogram_Null_Subprogram: 2cd4 2cd4 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cd4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 38 TR06:18 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2cd5 2cd5 <halt> ; Flow R 2cd6 ; -------------------------------------------------------------------------------------- 2cd6 ; 0x00c7 Action Elaborate_Subprogram 2cd6 ; -------------------------------------------------------------------------------------- 2cd6 MACRO_Action_Elaborate_Subprogram: 2cd6 2cd6 dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cd6 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 2cd7 2cd7 fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd8 2cd8 ioc_load_wdr 0 seq_random 02 ? 2cd9 2cd9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2cda ; -------------------------------------------------------------------------------------- 2cda ; 0x00c6 Action Check_Subprogram_Elaborated 2cda ; -------------------------------------------------------------------------------------- 2cda MACRO_Action_Check_Subprogram_Elaborated: 2cda 2cda dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cda fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 2cdb 2cdb seq_br_type 2 Push (branch address); Flow J 0x2cdc seq_branch_adr 3279 0x3279 2cdc 2cdc fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2cdd 0x2cdd seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 2cdd 2cdd seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2cde 2cde fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2cdf 2cdf fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ce0 2ce0 ioc_load_wdr 0 ; Flow J 0x2d18 seq_br_type 3 Unconditional Branch seq_branch_adr 2d18 0x2d18 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2ce1 ; -------------------------------------------------------------------------------------- 2ce1 ; Comes from: 2ce1 ; 2cf7 C from color 0x2cf6 2ce1 ; -------------------------------------------------------------------------------------- 2ce1 2ce1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2ce2 2ce2 ioc_tvbs 5 seq+seq; Flow J cc=False 0x2cf4 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2cf4 0x2cf4 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 2ce3 2ce3 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2ce4 2ce4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2ce7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ce7 0x2ce7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f 2ce5 2ce5 fiu_mem_start 2 start-rd; Flow C 0x2cef ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cef 0x2cef seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 2ce6 2ce6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 2ce7 2ce7 fiu_mem_start 2 start-rd; Flow C 0x2ce6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ce6 0x2ce6 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2ce8 2ce8 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2a84 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 2ce9 2ce9 fiu_mem_start 2 start-rd; Flow C 0x2cef ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cef 0x2cef seq_en_micro 0 typ_a_adr 25 TR12:05 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 2cea 2cea fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2ce5 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ce5 0x2ce5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 2ceb 2ceb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 2cec 2cec seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2ce5 seq_br_type 0 Branch False seq_branch_adr 2ce5 0x2ce5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 2ced 2ced ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 2 INC_A_PLUS_B typ_b_adr 34 TR12:14 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f 2cee 2cee fiu_mem_start 2 start-rd; Flow J 0x2ce6 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2ce6 0x2ce6 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2cef 2cef seq_en_micro 0 2cf0 2cf0 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2cf1 0x2cf1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2cf1 2cf1 seq_en_micro 0 seq_random 06 Pop_stack+? 2cf2 2cf2 seq_br_type 7 Unconditional Call; Flow C 0x2cf4 seq_branch_adr 2cf4 0x2cf4 seq_en_micro 0 2cf3 2cf3 seq_br_type 3 Unconditional Branch; Flow J 0x2ce3 seq_branch_adr 2ce3 0x2ce3 val_c_adr 30 GP0f 2cf4 ; -------------------------------------------------------------------------------------- 2cf4 ; Comes from: 2cf4 ; 2cde C from color ML_break_class 2cf4 ; 2cfb C from color 0x2cfb 2cf4 ; 2cfd C from color 0x2cfd 2cf4 ; 2d00 C from color 0x2d00 2cf4 ; 2d01 C from color 0x2d00 2cf4 ; 2d03 C from color 0x2cf6 2cf4 ; 2d10 C from color ML_break_class 2cf4 ; 2d14 C from color 0x2d13 2cf4 ; 2d3f C from color ML_break_class 2cf4 ; 2d43 C from color ML_break_class 2cf4 ; 2d46 C from color 0x2d45 2cf4 ; -------------------------------------------------------------------------------------- 2cf4 2cf4 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2cf5 0x2cf5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 2cf5 ; -------------------------------------------------------------------------------------- 2cf5 ; Comes from: 2cf5 ; 2d06 C True from color ML_break_class 2cf5 ; 2d09 C True from color ML_break_class 2cf5 ; -------------------------------------------------------------------------------------- 2cf5 2cf5 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32b5 seq_branch_adr 32b5 0x32b5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2cf6 2cf6 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_b_adr 1f TOP - 1 2cf7 2cf7 fiu_mem_start 2 start-rd; Flow C 0x2ce1 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2cf8 2cf8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d33 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d33 0x2d33 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2cf9 2cf9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 25 TR00:05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2cfa 2cfa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 24 TR00:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2cfb 2cfb fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2cfc 2cfc fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 2cfd 2cfd fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2cfe 2cfe fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2cff 2cff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2d00 2d00 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 9 val_rand a PASS_B_HIGH 2d01 2d01 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d02 2d02 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2d03 2d03 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2d04 2d04 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d33 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d33 0x2d33 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d05 2d05 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_frame 4 val_rand a PASS_B_HIGH 2d06 2d06 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2cf5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2cf5 0x2cf5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d07 2d07 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d17 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d17 0x2d17 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d08 2d08 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 15 NOT_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d09 2d09 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2cf5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2cf5 0x2cf5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d0a 2d0a fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 16 CSA/VAL_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 16 CSA/VAL_BUS 2d0b 2d0b fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2d0c 2d0c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2d0d 2d0d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x2d0f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d0f 0x2d0f typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 2d0e 2d0e ioc_tvbs 3 fiu+fiu; Flow J 0x2d18 seq_br_type 3 Unconditional Branch seq_branch_adr 2d18 0x2d18 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2d0f 2d0f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2d17 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d17 0x2d17 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d10 2d10 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 32 VR05:12 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2d11 2d11 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d12 2d12 ioc_load_wdr 0 ; Flow J 0x2d18 seq_br_type 3 Unconditional Branch seq_branch_adr 2d18 0x2d18 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 2d13 2d13 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 37 VR05:17 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 5 2d14 2d14 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2cf4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_b_adr 24 VR11:04 val_frame 11 2d15 2d15 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2d16 2d16 fiu_mem_start 3 start-wr; Flow C cc=True 0x32ad ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ad 0x32ad seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 28 TR06:08 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2d17 2d17 ioc_load_wdr 0 ; Flow J 0x2d18 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d18 0x2d18 2d18 2d18 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2d19 2d19 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d1a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2d1f 0x2d1f seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 2d1a 2d1a ioc_tvbs 2 fiu+val; Flow J cc=False 0x2d1d seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d1d 0x2d1d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2d1b 2d1b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2cf5 seq_br_type 9 Return False seq_branch_adr 2cf5 0x2cf5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d1c 2d1c seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 2d1d 2d1d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2d1c ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d1c 0x2d1c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2d1e 2d1e seq_br_type 7 Unconditional Call; Flow C 0x2ce1 seq_branch_adr 2ce1 0x2ce1 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2d1f 2d1f fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d1d fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2d1d 0x2d1d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 2d20 2d20 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d21 2d21 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d22 2d22 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2d2b fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2d2b 0x2d2b seq_cond_sel 08 VAL.ALU_CARRY(late) typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_frame 2 2d23 2d23 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d2b ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d2b 0x2d2b seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR07:03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2d24 2d24 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d25 2d25 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2d26 2d26 ioc_fiubs 0 fiu ; Flow J cc=False 0x2d2c ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d2c 0x2d2c seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 6 A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2d27 2d27 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d2c ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d2c 0x2d2c typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 2d28 2d28 fiu_vmux_sel 1 fill value; Flow J 0x2d25 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d25 0x2d25 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d29 2d29 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d2a 2d2a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d2b 2d2b fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2d29 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 10 fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d29 0x2d29 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 2d2c 2d2c fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 30 TR00:10 typ_alu_func 0 PASS_A typ_c_adr 0f TR00:10 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 2d2d 2d2d <halt> ; Flow R 2d2e ; -------------------------------------------------------------------------------------- 2d2e ; 0x006b Action Query_Break_Address 2d2e ; -------------------------------------------------------------------------------------- 2d2e MACRO_Action_Query_Break_Address: 2d2e 2d2e dispatch_brk_class 0 ; Flow C 0x2d35 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d2e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d35 0x2d35 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d2f 2d2f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1d 2d30 ; -------------------------------------------------------------------------------------- 2d30 ; 0x006d Action Query_Break_Cause 2d30 ; -------------------------------------------------------------------------------------- 2d30 MACRO_Action_Query_Break_Cause: 2d30 2d30 dispatch_brk_class 0 ; Flow J 0x2d31 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d30 fiu_len_fill_lit 42 zero-fill 0x2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 7d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d31 0x2d31 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d31 2d31 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d32 2d32 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d33 2d33 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d34 ; -------------------------------------------------------------------------------------- 2d34 ; 0x006c Action Query_Break_Mask 2d34 ; -------------------------------------------------------------------------------------- 2d34 MACRO_Action_Query_Break_Mask: 2d34 2d34 dispatch_brk_class 0 ; Flow J 0x2d31 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d34 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d31 0x2d31 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d35 ; -------------------------------------------------------------------------------------- 2d35 ; Comes from: 2d35 ; 2d2e C from color MACRO_Action_Query_Break_Address 2d35 ; 2d36 C from color ML_break_class 2d35 ; -------------------------------------------------------------------------------------- 2d35 2d35 ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ab 0x32ab seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d36 ; -------------------------------------------------------------------------------------- 2d36 ; 0x006a Action Alter_Break_Mask 2d36 ; -------------------------------------------------------------------------------------- 2d36 MACRO_Action_Alter_Break_Mask: 2d36 2d36 dispatch_brk_class 0 ; Flow C 0x2d35 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2d36 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d35 0x2d35 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d37 2d37 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 2d38 2d38 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d17 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d17 0x2d17 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d39 2d39 <halt> ; Flow R 2d3a ; -------------------------------------------------------------------------------------- 2d3a ; 0x006f Action Break_Unconditional 2d3a ; -------------------------------------------------------------------------------------- 2d3a MACRO_Action_Break_Unconditional: 2d3a 2d3a dispatch_brk_class 0 dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2d3a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 3e VR03:1e val_frame 3 2d3b 2d3b fiu_load_tar 1 hold_tar; Flow J 0x14a fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d3c 2d3c fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d3d 2d3d ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 16 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d3e 2d3e ioc_tvbs 2 fiu+val; Flow J cc=True 0x2d4a seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d4a 0x2d4a typ_a_adr 2e TR06:0e typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 2d3f 2d3f fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 28 TR06:08 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d40 2d40 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2d49 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d49 0x2d49 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d41 2d41 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_en_micro 0 2d42 2d42 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2d3b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d3b 0x2d3b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2d43 2d43 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d44 2d44 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2d45 2d45 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d46 2d46 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d47 2d47 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d48 2d48 ioc_load_wdr 0 ; Flow J 0x2d3b seq_br_type 3 Unconditional Branch seq_branch_adr 2d3b 0x2d3b seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d49 2d49 seq_br_type 0 Branch False; Flow J cc=False 0x2dbc seq_branch_adr 2dbc 0x2dbc seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 16 val_b_adr 39 VR02:19 val_frame 2 2d4a 2d4a fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 0a ? typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 30 VR02:10 val_frame 2 2d4b 2d4b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 34 VR02:14 val_frame 2 2d4c 2d4c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 02 ? 2d4d 2d4d seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2d4e 2d4e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 03 GP03 2d4f 2d4f fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2d50 2d50 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 3 seq_random 25 Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d51 2d51 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d53 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d53 0x2d53 seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2d52 2d52 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d53 seq_br_type 3 Unconditional Branch seq_branch_adr 2d53 0x2d53 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2d53 2d53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2d54 2d54 seq_br_type 3 Unconditional Branch; Flow J 0x2dbc seq_branch_adr 2dbc 0x2dbc seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 39 VR02:19 val_frame 2 2d55 ; -------------------------------------------------------------------------------------- 2d55 ; Comes from: 2d55 ; 0148 C True from color ML_break_class 2d55 ; -------------------------------------------------------------------------------------- 2d55 2d55 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION 2d56 2d56 ioc_tvbs 5 seq+seq; Flow J cc=True 0x2d57 ; Flow J cc=#0x0 0x2d57 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2d57 0x2d57 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d57 2d57 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2d58 2d58 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d59 2d59 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5a 2d5a ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5b 2d5b ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5c 2d5c ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5d 2d5d ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5e 2d5e ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5f 2d5f ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d60 2d60 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d61 2d61 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d62 2d62 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d63 2d63 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d64 2d64 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d65 2d65 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d66 2d66 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 2d67 2d67 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 38 TR00:18 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 38 VR00:18 2d68 2d68 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 37 TR00:17 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 37 VR00:17 2d69 2d69 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 36 TR00:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 36 VR00:16 2d6a 2d6a fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR00:15 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 35 VR00:15 2d6b 2d6b fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 34 TR00:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 34 VR00:14 2d6c 2d6c fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 33 TR00:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 33 VR00:13 2d6d 2d6d fiu_tivi_src 4 fiu_var; Flow J cc=True 0x2d70 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d70 0x2d70 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR00:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 32 VR00:12 2d6e 2d6e fiu_tivi_src 4 fiu_var; Flow J cc=False 0x2dbc ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2dbc 0x2dbc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 31 TR00:11 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 31 VR00:11 val_c_adr 3b GP04 2d6f 2d6f seq_br_type 3 Unconditional Branch; Flow J 0x14a seq_branch_adr 014a 0x014a seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 04 GP04 2d70 2d70 seq_br_type 3 Unconditional Branch; Flow J 0x2d6f seq_branch_adr 2d6f 0x2d6f seq_en_micro 0 val_c_adr 3b GP04 2d71 2d71 <halt> ; Flow R 2d72 ; -------------------------------------------------------------------------------------- 2d72 ; 0x006e Action Exit_Break 2d72 ; -------------------------------------------------------------------------------------- 2d72 MACRO_Action_Exit_Break: 2d72 2d72 dispatch_brk_class 0 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2d72 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2d73 2d73 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_mar_cntl e LOAD_MAR_CONTROL 2d74 2d74 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d75 2d75 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d76 2d76 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2d77 2d77 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d78 2d78 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_lex_adr 2 seq_random 0b ? typ_a_adr 14 ZEROS val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2d79 2d79 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 2d7a 2d7a ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2d7b 2d7b seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_b_adr 01 GP01 2d7c 2d7c fiu_mem_start 2 start-rd; Flow J 0x2ddc seq_br_type 3 Unconditional Branch seq_branch_adr 2ddc MACRO_Exit_Subprogram_topoffset,>R seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 14 Load_save_offset+? 2d7d ; -------------------------------------------------------------------------------------- 2d7d ; Comes from: 2d7d ; 2d9e C from color MACRO_Action_Query_Frame 2d7d ; 2dae C from color ML_break_class 2d7d ; -------------------------------------------------------------------------------------- 2d7d 2d7d ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 3a VR02:1a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d7e 2d7e fiu_load_tar 1 hold_tar; Flow J cc=True 0x2d82 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d82 0x2d82 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 5 RESOLVE RAM typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 2d7f 2d7f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ce1 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2d80 2d80 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2d8f seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d8f 0x2d8f seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2d81 2d81 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d82 2d82 fiu_mem_start 2 start-rd; Flow C 0x2cf4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf4 0x2cf4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2d83 2d83 seq_br_type 1 Branch True; Flow J cc=True 0x2d86 seq_branch_adr 2d86 0x2d86 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2d84 2d84 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2d85 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 2d8f 0x2d8f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d85 2d85 fiu_mem_start 2 start-rd; Flow J 0x2ce1 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2ce1 0x2ce1 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2d86 2d86 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d87 2d87 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d88 2d88 fiu_mem_start 2 start-rd; Flow C 0x2ce1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 2d89 2d89 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2d8a 2d8a fiu_mem_start 2 start-rd; Flow C 0x2ce1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2d8b 2d8b ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d8c 2d8c fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2d8d 2d8d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 2d8e 2d8e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d8f 2d8f fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d94 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2d94 0x2d94 seq_cond_sel 56 SEQ.LATCHED_COND typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d90 2d90 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2d81 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d81 0x2d81 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3e VR02:1e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2d91 2d91 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2d92 2d92 fiu_mem_start 2 start-rd; Flow C 0x2ce1 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d93 2d93 seq_br_type 3 Unconditional Branch; Flow J 0x2d8f seq_branch_adr 2d8f 0x2d8f seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2d94 2d94 fiu_len_fill_lit 13 sign-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand a PASS_B_HIGH 2d95 2d95 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2d81 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d81 0x2d81 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2d96 2d96 seq_br_type 7 Unconditional Call; Flow C 0x2ce1 seq_branch_adr 2ce1 0x2ce1 seq_en_micro 0 2d97 2d97 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ce1 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2d98 2d98 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2d9b seq_br_type 0 Branch False seq_branch_adr 2d9b 0x2d9b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d99 2d99 fiu_mem_start 2 start-rd; Flow C 0x2ce1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ce1 0x2ce1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_frame 4 2d9a 2d9a ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2d9b 0x2d9b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d9b 2d9b seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d9c ; -------------------------------------------------------------------------------------- 2d9c ; Comes from: 2d9c ; 2da0 C from color MACRO_Action_Query_Frame 2d9c ; 2dc1 C from color 0x2dbf 2d9c ; 2dc5 C from color 0x2dbf 2d9c ; -------------------------------------------------------------------------------------- 2d9c 2d9c seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 2d9d 2d9d <halt> ; Flow R 2d9e ; -------------------------------------------------------------------------------------- 2d9e ; 0x0069 Action Query_Frame 2d9e ; -------------------------------------------------------------------------------------- 2d9e MACRO_Action_Query_Frame: 2d9e 2d9e dispatch_brk_class 0 ; Flow C 0x2d7d dispatch_csa_free 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2d9e seq_br_type 7 Unconditional Call seq_branch_adr 2d7d 0x2d7d 2d9f 2d9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2da7 seq_br_type 1 Branch True seq_branch_adr 2da7 0x2da7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2da0 2da0 ioc_fiubs 1 val ; Flow C 0x2d9c seq_br_type 7 Unconditional Call seq_branch_adr 2d9c 0x2d9c typ_a_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 2da1 2da1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2da8 seq_br_type 0 Branch False seq_branch_adr 2da8 0x2da8 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2da2 2da2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2da3 2da3 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 11 2da4 2da4 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR07:00 val_alu_func 1e A_AND_B val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 7 2da5 2da5 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 28 VR07:08 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU val_frame 7 2da6 2da6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU val_frame 6 2da7 2da7 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2da8 2da8 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2da9 2da9 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2daa 2daa typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2dab 2dab typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 2dac 2dac fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 2dad 2dad <halt> ; Flow R 2dae ; -------------------------------------------------------------------------------------- 2dae ; 0x0068 Action Establish_Frame 2dae ; -------------------------------------------------------------------------------------- 2dae MACRO_Action_Establish_Frame: 2dae 2dae dispatch_brk_class 0 ; Flow C 0x2d7d dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2dae seq_br_type 7 Unconditional Call seq_branch_adr 2d7d 0x2d7d 2daf 2daf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2dbd seq_br_type 1 Branch True seq_branch_adr 2dbd 0x2dbd seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2db0 2db0 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2db1 2db1 typ_a_adr 29 TR05:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2db2 2db2 val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2db3 2db3 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 2db4 2db4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 2 INC_A_PLUS_B val_b_adr 07 GP07 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2db5 2db5 seq_en_micro 0 seq_random 02 ? typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2db6 2db6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2db7 2db7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 06 GP06 2db8 2db8 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2db9 2db9 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 2d Load_ibuff+? typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2dba 2dba fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dbc fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2dbc 0x2dbc seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2dbb 2dbb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dbc seq_br_type 3 Unconditional Branch seq_branch_adr 2dbc 0x2dbc seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2dbc 2dbc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2dbd 2dbd seq_random 02 ? typ_csa_cntl 3 POP_CSA 2dbe 2dbe seq_br_type 3 Unconditional Branch; Flow J 0x2d18 seq_branch_adr 2d18 0x2d18 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2dbf 2dbf ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2dc0 2dc0 ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP 2dc1 2dc1 ioc_fiubs 2 typ ; Flow C 0x2d9c seq_br_type 7 Unconditional Call seq_branch_adr 2d9c 0x2d9c typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 2dc2 2dc2 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dcd ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dcd 0x2dcd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 2dc3 2dc3 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2dc4 2dc4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2dd2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2dd2 0x2dd2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2dc5 2dc5 seq_br_type 7 Unconditional Call; Flow C 0x2d9c seq_branch_adr 2d9c 0x2d9c 2dc6 2dc6 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dcd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dcd 0x2dcd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 2dc7 2dc7 ioc_fiubs 1 val ; Flow J cc=True 0x2dcd seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dcd 0x2dcd seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_rand 9 PASS_A_HIGH 2dc8 2dc8 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dcd fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dcd 0x2dcd seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2dc9 2dc9 fiu_mem_start 2 start-rd; Flow C 0x336d ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 336d 0x336d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2dca 2dca fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2dce ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dce 0x2dce seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 07 GP07 typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dcb 2dcb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2dcf seq_br_type 5 Call True seq_branch_adr 2dcf 0x2dcf seq_cond_sel 67 REFRESH_MACRO_EVENT 2dcc 2dcc fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dc9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2dc9 0x2dc9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 2dcd 2dcd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2dce 2dce fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 20 VR07:00 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 2dcf ; -------------------------------------------------------------------------------------- 2dcf ; Comes from: 2dcf ; 2dcb C True from color 0x2dbf 2dcf ; -------------------------------------------------------------------------------------- 2dcf 2dcf seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2dd0 2dd0 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dd1 2dd1 seq_br_type a Unconditional Return; Flow R 2dd2 2dd2 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2dd3 2dd3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2dc9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2dc9 0x2dc9 typ_b_adr 08 GP08 2dd4 2dd4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2dd5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2dd5 0x2dd5 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 2dd5 2dd5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2dd8 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2dd8 0x2dd8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 2dd6 2dd6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 2dd7 2dd7 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x2dda fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2dda 0x2dda seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2dd8 2dd8 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2dd9 2dd9 fiu_fill_mode_src 0 ; Flow J 0x2dd7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2dd7 0x2dd7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2dda 2dda fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32c5 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32c5 0x32c5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2ddb 2ddb <halt> ; Flow R 2ddc ; -------------------------------------------------------------------------------------- 2ddc ; 0x4500-0x45ff Exit_Subprogram topoffset,>R 2ddc ; -------------------------------------------------------------------------------------- 2ddc MACRO_Exit_Subprogram_topoffset,>R: 2ddc 2ddc dispatch_brk_class 6 ; Flow J cc=False 0x2f4c dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2ddc fiu_mem_start 9 start_continue_if_true fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4c 0x2f4c seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2ddd 2ddd ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2dde 2dde fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2de2 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2de2 0x2de2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2ddf 2ddf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2de7 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de7 0x2de7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2de0 2de0 ioc_fiubs 2 typ ; Flow J cc=False 0x2de5 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2de5 0x2de5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2de1 2de1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER 2de2 2de2 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2de3 2de3 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2de9 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de9 0x2de9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2de4 2de4 ioc_fiubs 0 fiu ; Flow J 0x2e83 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2de5 2de5 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2de6 2de6 fiu_tivi_src 4 fiu_var; Flow J 0x2e86 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2e86 0x2e86 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR02:19 val_b_adr 39 VR02:19 val_frame 2 2de7 2de7 fiu_load_var 1 hold_var; Flow C 0x2ded fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2ded 0x2ded seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2de8 2de8 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 2de9 2de9 seq_br_type 7 Unconditional Call; Flow C 0x2ded seq_branch_adr 2ded 0x2ded seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2dea 2dea ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2deb 2deb fiu_load_tar 1 hold_tar; Flow J 0x2dec fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32af 0x32af seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2dec 2dec seq_br_type 3 Unconditional Branch; Flow J 0x2e83 seq_branch_adr 2e83 0x2e83 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2ded 2ded ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2dee 2dee fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2def 2def fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2df7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2df7 0x2df7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2df0 2df0 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2df1 2df1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2df2 2df2 seq_b_timing 0 Early Condition; Flow J cc=False 0x2df2 seq_br_type 0 Branch False seq_branch_adr 2df2 0x2df2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA val_rand 2 DEC_LOOP_COUNTER 2df3 2df3 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2df4 2df4 ioc_fiubs 2 typ ; Flow C 0x32fe seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 0c TR18:13 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 18 2df5 2df5 ioc_tvbs 5 seq+seq; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2df6 0x2df6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 2df6 2df6 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_c_lit 0 typ_frame 1f 2df7 2df7 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 2df8 2df8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2df9 2df9 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2dfa 2dfa ioc_adrbs 2 typ ; Flow J cc=True 0x2df3 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2df3 0x2df3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2dfb 2dfb seq_br_type 3 Unconditional Branch; Flow J 0x2df2 seq_branch_adr 2df2 0x2df2 seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 2dfc ; -------------------------------------------------------------------------------------- 2dfc ; 0x00cc Action Pop_Block 2dfc ; -------------------------------------------------------------------------------------- 2dfc MACRO_Action_Pop_Block: 2dfc 2dfc dispatch_brk_class 6 ; Flow J cc=False 0x2f4c dispatch_csa_valid 0 dispatch_ignore 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2dfc fiu_mem_start 9 start_continue_if_true ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4c 0x2f4c seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 2dfd 2dfd ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2dfe 2dfe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e01 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e01 0x2e01 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2dff 2dff fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 2e00 2e00 ioc_fiubs 2 typ ; Flow J 0x2de1 seq_br_type 3 Unconditional Branch seq_branch_adr 2de1 0x2de1 seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e01 2e01 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2e02 2e02 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2e03 2e03 ioc_fiubs 2 typ ; Flow J 0x2e83 seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? 2e04 ; -------------------------------------------------------------------------------------- 2e04 ; 0x4300-0x43ff Exit_Subprogram From_Utility,>R,topoffset 2e04 ; -------------------------------------------------------------------------------------- 2e04 MACRO_Exit_Subprogram_From_Utility,>R,topoffset: 2e04 2e04 dispatch_brk_class 6 ; Flow C cc=False 0x32af dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2e04 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e05 2e05 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2e0a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e0a 0x2e0a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e06 2e06 ioc_adrbs 3 seq ; Flow J 0x2e07 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2de1 0x2de1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_a_adr 14 ZEROS typ_csa_cntl 1 START_POP_DOWN val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e07 2e07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e10 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e10 0x2e10 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e08 2e08 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2de7 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de7 0x2de7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2e09 2e09 ioc_fiubs 2 typ ; Flow R cc=True ; Flow J cc=False 0x2de5 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 2de5 0x2de5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? 2e0a 2e0a fiu_mem_start 2 start-rd; Flow J 0x2e0b ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2de1 0x2de1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e0b 2e0b typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e0c 2e0c fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2e0d 2e0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2e7f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7f 0x2e7f seq_random 02 ? typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_b_adr 02 GP02 2e0e 2e0e ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_csa_cntl 1 START_POP_DOWN 2e0f 2e0f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e08 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2e08 0x2e08 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_b_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 02 GP02 2e10 2e10 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e11 2e11 fiu_load_var 1 hold_var; Flow J cc=True 0x2de7 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de7 0x2de7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 2e12 2e12 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e13 2e13 fiu_tivi_src 2 tar_fiu; Flow J 0x2e83 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 2e14 ; -------------------------------------------------------------------------------------- 2e14 ; 0x4400-0x44ff Exit_Subprogram With_Result,>R,topoffset 2e14 ; -------------------------------------------------------------------------------------- 2e14 MACRO_Exit_Subprogram_With_Result,>R,topoffset: 2e14 2e14 dispatch_brk_class 6 ; Flow J cc=False 0x2f4f dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e14 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4f 0x2f4f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e15 2e15 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x2f8c fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2f8c 0x2f8c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e16 2e16 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e1b fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e1b 0x2e1b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e17 2e17 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e35 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e35 0x2e35 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e18 2e18 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e2f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e2f 0x2e2f seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e19 2e19 ioc_fiubs 2 typ ; Flow J cc=False 0x2e3a ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e3a 0x2e3a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e1a 2e1a fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e1b 2e1b fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e26 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e26 0x2e26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e1c 2e1c seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e1d 2e1d seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e1e 2e1e seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e1f 2e1f fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e26 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e26 0x2e26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e20 2e20 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e21 2e21 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2e23 seq_br_type 1 Branch True seq_branch_adr 2e23 0x2e23 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e22 2e22 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e23 2e23 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e26 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e26 0x2e26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 03 GP03 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e24 ; -------------------------------------------------------------------------------------- 2e24 ; 0x00ca Action Exit_Nullary_Function,>R 2e24 ; -------------------------------------------------------------------------------------- 2e24 MACRO_Action_Exit_Nullary_Function,>R: 2e24 2e24 dispatch_brk_class 6 ; Flow J cc=False 0x2f4f dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2e24 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4f 0x2f4f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e25 2e25 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e16 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e16 0x2e16 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_c_adr 3e GP01 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2e26 2e26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e2c fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e2c 0x2e2c seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e27 2e27 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e28 2e28 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e29 2e29 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f 2e2a 2e2a seq_br_type 7 Unconditional Call; Flow C 0x2ded seq_branch_adr 2ded 0x2ded seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e2b 2e2b seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 2e2c 2e2c fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e2d 2e2d fiu_load_var 1 hold_var; Flow J 0x2e2e fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2dea 0x2dea seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 2e2e 2e2e seq_br_type 3 Unconditional Branch; Flow J 0x2ded seq_branch_adr 2ded 0x2ded seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e2f 2e2f ioc_fiubs 2 typ ; Flow J cc=False 0x2e31 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e31 0x2e31 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e30 2e30 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e34 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e34 0x2e34 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e31 2e31 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e32 2e32 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e34 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e34 0x2e34 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 15 ? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e33 2e33 seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e34 2e34 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e35 2e35 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e36 2e36 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e38 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 2e38 0x2e38 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 2e37 2e37 ioc_fiubs 2 typ ; Flow J 0x2e83 seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e38 2e38 ioc_fiubs 2 typ ; Flow C 0x2e83 seq_br_type 7 Unconditional Call seq_branch_adr 2e83 0x2e83 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e39 2e39 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e34 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e34 0x2e34 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e3a 2e3a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e3b 2e3b seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 03 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e3c ; -------------------------------------------------------------------------------------- 2e3c ; 0x00cb Action Pop_Block_With_Result 2e3c ; -------------------------------------------------------------------------------------- 2e3c MACRO_Action_Pop_Block_With_Result: 2e3c 2e3c dispatch_brk_class 6 ; Flow J cc=False 0x2f4f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2e3c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4f 0x2f4f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 2b ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e3d 2e3d seq_random 14 Load_save_offset+? typ_c_adr 3e GP01 val_c_adr 3c GP03 2e3e 2e3e fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e3f 2e3f fiu_mem_start 4 continue; Flow J cc=True 0x2e40 ; Flow J cc=#0x0 0x2e40 ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2e40 0x2e40 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 62 ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e40 2e40 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e48 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e48 0x2e48 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e41 2e41 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e42 2e42 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e43 2e43 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e44 2e44 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e48 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e48 0x2e48 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e45 2e45 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e46 2e46 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e47 2e47 seq_br_type 3 Unconditional Branch; Flow J 0x2e4f seq_branch_adr 2e4f 0x2e4f 2e48 2e48 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e52 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e52 0x2e52 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e49 2e49 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e4c fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e4c 0x2e4c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e4a 2e4a ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e4b 2e4b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e4c 2e4c ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e4d 2e4d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e4e 0x2e4e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e4e 2e4e seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e4f 2e4f ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2e50 2e50 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 2e51 2e51 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 seq_int_reads 0 TYP VAL BUS seq_random 4f ? typ_b_adr 05 GP05 val_b_adr 05 GP05 2e52 2e52 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e53 2e53 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e4c ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2e4c 0x2e4c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e54 2e54 ioc_fiubs 2 typ ; Flow J 0x2e83 seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e55 2e55 <halt> ; Flow R 2e56 ; -------------------------------------------------------------------------------------- 2e56 ; 0x4200-0x42ff Exit_Subprogram From_Utility,With_Result,>R,topoffset 2e56 ; -------------------------------------------------------------------------------------- 2e56 MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset: 2e56 2e56 dispatch_brk_class 6 ; Flow C cc=False 0x32af dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e56 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e57 2e57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2f8e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2f8e 0x2f8e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame b typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e58 2e58 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2e7a fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e7a 0x2e7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2e59 2e59 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e5b fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e5b 0x2e5b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e5a 2e5a seq_br_type 3 Unconditional Branch; Flow J 0x2e26 seq_branch_adr 2e26 0x2e26 seq_en_micro 0 2e5b ; -------------------------------------------------------------------------------------- 2e5b ; Comes from: 2e5b ; 2e59 C #0x0 from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2e5b ; -------------------------------------------------------------------------------------- 2e5b 2e5b ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e63 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e63 0x2e63 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e5c 2e5c seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e5d 2e5d ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e68 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e68 0x2e68 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e5e 2e5e seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e5f 2e5f ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e63 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e63 0x2e63 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e60 2e60 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e61 2e61 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e62 2e62 seq_br_type 3 Unconditional Branch; Flow J 0x2e88 seq_branch_adr 2e88 0x2e88 2e63 2e63 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e65 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e65 0x2e65 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e64 2e64 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e19 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e19 0x2e19 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e65 2e65 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e66 2e66 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 2e67 2e67 seq_br_type 3 Unconditional Branch; Flow J 0x2e83 seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2e68 2e68 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e6e fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e6e 0x2e6e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e69 2e69 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_latch 1 seq_random 57 Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e6a 2e6a ioc_fiubs 2 typ ; Flow J cc=False 0x2e76 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e76 0x2e76 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e6b 2e6b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2e6c 0x2e6c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 2e6c 2e6c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2e6d 0x2e6d seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2e6d 2e6d seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e6e 2e6e ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e6f 2e6f ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e70 2e70 fiu_load_var 1 hold_var; Flow J cc=True 0x2e72 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e72 0x2e72 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS 2e71 2e71 seq_br_type 3 Unconditional Branch; Flow J 0x2e83 seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e72 2e72 ioc_tvbs 1 typ+fiu; Flow J 0x2e83 seq_br_type 3 Unconditional Branch seq_branch_adr 2e83 0x2e83 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2e73 2e73 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 2e74 2e74 ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e75 2e75 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 2e76 2e76 seq_br_type 2 Push (branch address); Flow J 0x2e77 seq_branch_adr 2e73 0x2e73 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2e77 2e77 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e79 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e79 0x2e79 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e78 2e78 seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e79 2e79 fiu_tivi_src 2 tar_fiu; Flow J 0x2e86 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e86 0x2e86 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2e7a 2e7a fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e7b 2e7b typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 2e7c 2e7c fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2e7d 2e7d fiu_load_var 1 hold_var; Flow C cc=False 0x2e7f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7f 0x2e7f seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2e7e 2e7e fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e59 fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e59 0x2e59 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e7f ; -------------------------------------------------------------------------------------- 2e7f ; Comes from: 2e7f ; 2e0d C False from color 0x0000 2e7f ; 2e7d C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2e7f ; 2f0a C False from color 0x2f06 2e7f ; -------------------------------------------------------------------------------------- 2e7f 2e7f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e80 2e80 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e81 2e81 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e82 2e82 ioc_load_wdr 0 ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_b_adr 03 GP03 2e83 2e83 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e84 2e84 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e85 2e85 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e86 2e86 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e87 0x2e87 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2e87 2e87 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2e88 2e88 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2e89 2e89 ioc_adrbs 2 typ ; Flow J 0x2e8a seq_br_type 2 Push (branch address) seq_branch_adr 32a8 0x32a8 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2e8a 2e8a ioc_fiubs 2 typ ; Flow J 0x2f98 seq_br_type 3 Unconditional Branch seq_branch_adr 2f98 0x2f98 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 2e8b 2e8b <halt> ; Flow R 2e8c ; -------------------------------------------------------------------------------------- 2e8c ; 0x0100 Execute Exception,Raise,>R 2e8c ; -------------------------------------------------------------------------------------- 2e8c MACRO_Execute_Exception,Raise,>R: 2e8c 2e8c dispatch_brk_class 8 ; Flow J cc=False 0x2ec0 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e8c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2ec0 0x2ec0 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e8d 2e8d fiu_mem_start 2 start-rd; Flow J cc=True 0x2eac ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2eac 0x2eac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2e8e 2e8e fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e8f 2e8f ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e90 2e90 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2ea4 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea4 0x2ea4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e91 2e91 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2e92 2e92 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e93 2e93 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ea9 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea9 0x2ea9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e94 2e94 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2ea2 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea2 0x2ea2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2e95 2e95 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2e96 2e96 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ea2 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea2 0x2ea2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e97 2e97 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2ea2 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ea2 0x2ea2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 2e98 2e98 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2e99 2e99 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e9b ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e9b 0x2e9b seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2e9a 2e9a seq_br_type 3 Unconditional Branch; Flow J 0x2e9c seq_branch_adr 2e9c 0x2e9c val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2e9b 2e9b seq_br_type 3 Unconditional Branch; Flow J 0x2e9c seq_branch_adr 2e9c 0x2e9c val_a_adr 27 VR05:07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2e9c 2e9c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2e9d 2e9d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 03 GP03 2e9e 2e9e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e9f 2e9f ioc_tvbs 3 fiu+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 2ea0 2ea0 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2ea1 0x2ea1 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ea1 2ea1 seq_br_type 3 Unconditional Branch; Flow J 0x2e85 seq_branch_adr 2e85 0x2e85 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 59 ? val_b_adr 04 GP04 2ea2 2ea2 seq_br_type 2 Push (branch address); Flow J 0x2ea3 seq_branch_adr 2e9a 0x2e9a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ea3 2ea3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2e9b fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e9b 0x2e9b seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ea4 2ea4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2ea5 2ea5 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ea6 2ea6 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ea7 2ea7 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ea8 2ea8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e93 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2e93 0x2e93 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2ea9 2ea9 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eaa 2eaa fiu_mem_start 2 start-rd; Flow J cc=True 0x2e92 seq_br_type 1 Branch True seq_branch_adr 2e92 0x2e92 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_rand 0 NO_OP 2eab 2eab seq_br_type 3 Unconditional Branch; Flow J 0x2ea2 seq_branch_adr 2ea2 0x2ea2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eac 2eac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 2ead 2ead fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 01 GP01 2eae 2eae fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2eaf fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2eaf 0x2eaf seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 03 ? typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2eaf ; -------------------------------------------------------------------------------------- 2eaf ; Comes from: 2eaf ; 2eae C #0x0 from color 0x0000 2eaf ; -------------------------------------------------------------------------------------- 2eaf 2eaf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2eb3 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2eb0 2eb0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2eb8 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb8 0x2eb8 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2eb1 2eb1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2ebd seq_br_type 3 Unconditional Branch seq_branch_adr 2ebd 0x2ebd seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2eb2 2eb2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eb3 2eb3 fiu_load_var 1 hold_var; Flow C cc=True 0x2eb7 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2eb7 0x2eb7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 28 TR12:08 typ_frame 12 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 2eb4 2eb4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2eb6 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2eb6 0x2eb6 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eb5 2eb5 ioc_fiubs 0 fiu ; Flow C 0x3919 seq_br_type 7 Unconditional Call seq_branch_adr 3919 0x3919 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 26 VR05:06 val_frame 5 2eb6 2eb6 ioc_fiubs 0 fiu ; Flow C 0x3919 seq_br_type 7 Unconditional Call seq_branch_adr 3919 0x3919 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 27 VR05:07 val_frame 5 2eb7 2eb7 seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 9 2eb8 2eb8 fiu_mem_start 4 continue typ_a_adr 31 TR08:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR 2eb9 2eb9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eba 2eba ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2ebc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ebc 0x2ebc typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2ebb 2ebb seq_br_type 7 Unconditional Call; Flow C 0x395d seq_branch_adr 395d 0x395d seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 26 VR05:06 val_frame 5 2ebc 2ebc seq_br_type 7 Unconditional Call; Flow C 0x395d seq_branch_adr 395d 0x395d seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 27 VR05:07 val_frame 5 2ebd 2ebd seq_b_timing 1 Latch Condition; Flow J cc=True 0x2ebf seq_br_type 1 Branch True seq_branch_adr 2ebf 0x2ebf 2ebe 2ebe seq_br_type 3 Unconditional Branch; Flow J 0x2e87 seq_branch_adr 2e87 0x2e87 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 26 VR05:06 val_frame 5 2ebf 2ebf seq_br_type 3 Unconditional Branch; Flow J 0x2e87 seq_branch_adr 2e87 0x2e87 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 27 VR05:07 val_frame 5 2ec0 2ec0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ee7 seq_br_type 5 Call True seq_branch_adr 2ee7 0x2ee7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ec1 2ec1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2eac seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2eac 0x2eac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2ec2 2ec2 fiu_load_var 1 hold_var; Flow J cc=True 0x2f03 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f03 0x2f03 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2ec3 2ec3 ioc_load_wdr 0 ; Flow J cc=False 0x2f4c ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2f4c 0x2f4c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2ec4 2ec4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f62 seq_br_type 1 Branch True seq_branch_adr 2f62 0x2f62 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 38 GP07 typ_frame 2 2ec5 2ec5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2ec6 2ec6 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR09:11 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 9 2ec7 2ec7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2ec8 2ec8 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 2ec9 2ec9 fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 38 GP07 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eca 2eca fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2ecb 2ecb fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2edd fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2edd 0x2edd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ecc 2ecc fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ecd 2ecd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ece 2ece fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x2ee2 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2ee2 0x2ee2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ecf 2ecf fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2eda fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2eda 0x2eda seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2ed0 2ed0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2eda seq_br_type 1 Branch True seq_branch_adr 2eda 0x2eda typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2ed1 2ed1 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2edb fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2edb 0x2edb seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ed2 2ed2 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2edb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2edb 0x2edb seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2ed3 2ed3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 30 TR09:10 typ_csa_cntl 1 START_POP_DOWN typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ed4 2ed4 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 37 GP08 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 07 GP07 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2ed5 2ed5 fiu_mem_start 2 start-rd; Flow J cc=True 0x2ed7 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ed7 0x2ed7 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2ed6 2ed6 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2ed8 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2ed8 0x2ed8 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 26 VR05:06 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2ed7 2ed7 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2ed8 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2ed8 0x2ed8 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 27 VR05:07 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2ed8 2ed8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 2ed9 2ed9 ioc_adrbs 1 val ; Flow J 0x2f0c ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f0c 0x2f0c seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 2eda 2eda seq_br_type 3 Unconditional Branch; Flow J 0x2edb seq_branch_adr 2edb 0x2edb typ_c_adr 1d TR02:02 typ_frame 2 2edb 2edb fiu_load_var 1 hold_var; Flow J 0x2edc fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2ed6 0x2ed6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 30 TR09:10 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2edc 2edc fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2ed7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ed7 0x2ed7 seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2edd 2edd fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2ede 2ede ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2edf 2edf fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ee0 2ee0 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ee1 2ee1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ece fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2ece 0x2ece val_b_adr 22 VR02:02 val_frame 2 2ee2 2ee2 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2ee3 2ee3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ee5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 2ee5 0x2ee5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_b_adr 22 VR02:02 val_frame 2 2ee4 2ee4 fiu_mem_start 2 start-rd; Flow J 0x2ecd seq_br_type 3 Unconditional Branch seq_branch_adr 2ecd 0x2ecd seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 2ee5 2ee5 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 2ee6 2ee6 ioc_tvbs 1 typ+fiu; Flow J 0x2edb seq_br_type 3 Unconditional Branch seq_branch_adr 2edb 0x2edb seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_c_adr 1d TR02:02 typ_frame 2 2ee7 ; -------------------------------------------------------------------------------------- 2ee7 ; Comes from: 2ee7 ; 2ec0 C True from color 0x0000 2ee7 ; -------------------------------------------------------------------------------------- 2ee7 2ee7 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2ee8 2ee8 fiu_mem_start 2 start-rd; Flow C 0x3347 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3347 0x3347 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2ee9 2ee9 fiu_load_var 1 hold_var; Flow J cc=True 0x2eea ; Flow J cc=#0x0 0x2eeb fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 2eeb 0x2eeb seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2eea 2eea fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2eeb 2eeb seq_br_type 3 Unconditional Branch; Flow J 0x2ef3 seq_branch_adr 2ef3 0x2ef3 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2eec 2eec seq_br_type 3 Unconditional Branch; Flow J 0x2ef3 seq_branch_adr 2ef3 0x2ef3 typ_a_adr 14 ZEROS typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2eed 2eed seq_br_type 3 Unconditional Branch; Flow J 0x2eef seq_branch_adr 2eef 0x2eef seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2eee 2eee seq_br_type 3 Unconditional Branch; Flow J 0x2eef seq_branch_adr 2eef 0x2eef seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2eef 2eef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 2ef0 2ef0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2eea seq_br_type 1 Branch True seq_branch_adr 2eea 0x2eea 2ef1 2ef1 seq_br_type 2 Push (branch address); Flow J 0x2ef2 seq_branch_adr 2ee9 0x2ee9 2ef2 2ef2 fiu_load_oreg 1 hold_oreg; Flow J 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 335c 0x335c seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 2ef3 2ef3 fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2ef4 2ef4 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f02 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f02 0x2f02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2ef5 2ef5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR09:13 val_frame 9 2ef6 2ef6 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2f02 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f02 0x2f02 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 2ef7 2ef7 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2f02 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f02 0x2f02 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR05:01 val_frame 5 2ef8 2ef8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f02 seq_br_type 1 Branch True seq_branch_adr 2f02 0x2f02 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR08:05 typ_frame 8 2ef9 2ef9 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x2eff ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2eff 0x2eff typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2efa 2efa ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2efb 2efb seq_br_type 2 Push (branch address); Flow J 0x2efc seq_branch_adr 0282 0x0282 2efc 2efc fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 5 val_rand a PASS_B_HIGH 2efd 2efd ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 2e TR02:0e typ_frame 2 2efe 2efe seq_br_type 3 Unconditional Branch; Flow J 0x2eef seq_branch_adr 2eef 0x2eef seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2eff 2eff fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 2f TR11:0f typ_frame 11 2f00 2f00 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2f01 2f01 ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f02 2f02 seq_br_type 3 Unconditional Branch; Flow J 0x2eef seq_branch_adr 2eef 0x2eef seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f03 2f03 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2f06 seq_br_type 5 Call True seq_branch_adr 2f06 0x2f06 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 2f04 2f04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL 2f05 2f05 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2e8f fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2e8f 0x2e8f seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f06 ; -------------------------------------------------------------------------------------- 2f06 ; Comes from: 2f06 ; 2f03 C True from color 0x0000 2f06 ; -------------------------------------------------------------------------------------- 2f06 2f06 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f07 2f07 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f08 2f08 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f09 2f09 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2f0a 2f0a fiu_load_var 1 hold_var; Flow C cc=False 0x2e7f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7f 0x2e7f seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2f0b 2f0b seq_br_type a Unconditional Return; Flow R 2f0c 2f0c ioc_fiubs 1 val ; Flow J cc=True 0x2f0e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f0e 0x2f0e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f0d 2f0d fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2f0e 2f0e fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f0f 2f0f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 36 TR02:16 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 2f10 2f10 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2f40 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f40 0x2f40 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f11 2f11 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3e GP01 2f12 2f12 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f13 fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 2 Push (branch address) seq_branch_adr 2e85 0x2e85 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2f13 2f13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f37 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f37 0x2f37 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f14 2f14 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2f15 2f15 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1f typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 2f16 2f16 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2f17 2f17 ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 2f18 2f18 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2f49 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f49 0x2f49 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f19 2f19 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2f2b fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f2b 0x2f2b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f1a 2f1a fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f1b 2f1b ioc_adrbs 1 val ; Flow J cc=False 0x2f2b seq_br_type 0 Branch False seq_branch_adr 2f2b 0x2f2b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f1c 2f1c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f2b fiu_load_mdr 1 hold_mdr fiu_offs_lit 44 fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f2b 0x2f2b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f1d 2f1d fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x32fe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 01 GP01 2f1e 2f1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f1f 2f1f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2f30 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f30 0x2f30 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f20 2f20 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f21 2f21 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f22 2f22 seq_br_type 1 Branch True; Flow J cc=True 0x2f45 seq_branch_adr 2f45 0x2f45 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 2f23 2f23 <default> 2f24 2f24 seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2f25 2f25 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 2f26 2f26 ioc_adrbs 2 typ ; Flow C 0x6b7 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f27 2f27 fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f28 2f28 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2f29 0x2f29 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f29 2f29 seq_br_type 7 Unconditional Call; Flow C 0x33bc seq_branch_adr 33bc 0x33bc 2f2a 2f2a fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f2b 2f2b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f2c 2f2c fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 01 GP01 2f2d 2f2d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f2e 2f2e fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2f20 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2f20 0x2f20 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f2f 2f2f seq_br_type 3 Unconditional Branch; Flow J 0x2f30 seq_branch_adr 2f30 0x2f30 2f30 2f30 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 20 TR08:00 typ_c_adr 39 GP06 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 39 GP06 val_frame 4 val_rand 9 PASS_A_HIGH 2f31 2f31 ioc_load_wdr 0 ; Flow J cc=True 0x2f34 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f34 0x2f34 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2f32 2f32 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f36 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f36 0x2f36 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 37 TR06:17 typ_frame 6 val_a_adr 2e VR06:0e val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f33 2f33 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f36 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f36 0x2f36 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f34 2f34 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f36 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f36 0x2f36 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 23 VR06:03 val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f35 2f35 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f36 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f36 0x2f36 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f36 2f36 ioc_fiubs 1 val ; Flow J 0x2f21 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f21 0x2f21 typ_b_adr 06 GP06 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f37 2f37 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 01 GP01 typ_c_adr 30 GP0f 2f38 2f38 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2f3c ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f3c 0x2f3c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 2f39 2f39 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f3a 2f3a fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2f45 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2f45 0x2f45 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f3b 2f3b ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f3c 2f3c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 2f3d 2f3d fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f3e 2f3e fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f3f 2f3f ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f40 2f40 fiu_load_var 1 hold_var fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f41 2f41 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2f42 0x2f42 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2f42 2f42 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 2f43 2f43 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f44 2f44 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f11 fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f11 0x2f11 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f45 ; -------------------------------------------------------------------------------------- 2f45 ; Comes from: 2f45 ; 2f3a C True from color 0x2ec9 2f45 ; -------------------------------------------------------------------------------------- 2f45 2f45 fiu_mem_start 2 start-rd; Flow C 0x34ae ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ae 0x34ae typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 11 val_rand a PASS_B_HIGH 2f46 2f46 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 2f47 2f47 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f48 2f48 ioc_load_wdr 0 ; Flow J 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2f49 2f49 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f4a 2f4a fiu_mem_start 2 start-rd; Flow J cc=True 0x2f17 seq_br_type 1 Branch True seq_branch_adr 2f17 0x2f17 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f4b 2f4b ioc_fiubs 2 typ ; Flow J 0x2f2b seq_br_type 3 Unconditional Branch seq_branch_adr 2f2b 0x2f2b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f4c 2f4c fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2f4d fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f66 0x2f66 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f4d 2f4d fiu_mem_start 2 start-rd; Flow J cc=True 0x336b ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 336b 0x336b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f4e 2f4e seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 2f4f 2f4f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2f50 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f66 0x2f66 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f50 2f50 fiu_mem_start 2 start-rd; Flow J cc=True 0x336b ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 336b 0x336b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f51 2f51 seq_br_type 4 Call False; Flow C cc=False 0x32af seq_branch_adr 32af 0x32af seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2f52 2f52 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f53 2f53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT 2f54 2f54 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2f66 seq_br_type 0 Branch False seq_branch_adr 2f66 0x2f66 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 10 TOP 2f55 2f55 seq_br_type 3 Unconditional Branch; Flow J 0x2f66 seq_branch_adr 2f66 0x2f66 2f56 2f56 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f57 2f57 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f5f seq_br_type 1 Branch True seq_branch_adr 2f5f 0x2f5f seq_cond_sel 67 REFRESH_MACRO_EVENT 2f58 2f58 fiu_mem_start 2 start-rd; Flow J cc=True 0x2f5d ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f5d 0x2f5d seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_frame 9 val_rand 9 PASS_A_HIGH 2f59 2f59 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f5a 2f5a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand 9 PASS_A_HIGH 2f5b 2f5b ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 2f5c 2f5c seq_b_timing 1 Latch Condition; Flow J cc=False 0x2f56 seq_br_type 0 Branch False seq_branch_adr 2f56 0x2f56 2f5d 2f5d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2f5e 2f5e seq_br_type 3 Unconditional Branch; Flow J 0x2f66 seq_branch_adr 2f66 0x2f66 2f5f 2f5f seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f60 2f60 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2f61 2f61 seq_br_type 3 Unconditional Branch; Flow J 0x2f58 seq_branch_adr 2f58 0x2f58 2f62 2f62 seq_br_type 2 Push (branch address); Flow J 0x2f63 seq_branch_adr 2f66 0x2f66 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 2f63 2f63 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x336b ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 336b 0x336b seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f64 2f64 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2f65 2f65 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f66 2f66 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2f6b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f6b 0x2f6b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2f67 2f67 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 2f68 2f68 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2f69 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 2f65 0x2f65 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 2f69 2f69 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f6a fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f6a 2f6a ioc_tvbs 1 typ+fiu; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f6b 2f6b fiu_mem_start 2 start-rd; Flow C 0x3347 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3347 0x3347 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f6c 2f6c fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2f72 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2f72 0x2f72 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f6d 2f6d ioc_fiubs 2 typ ; Flow J 0x2f6e seq_br_type 3 Unconditional Branch seq_branch_adr 2f6e 0x2f6e val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f6e 2f6e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f7b fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f7b 0x2f7b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 2f6f 2f6f fiu_load_oreg 1 hold_oreg; Flow C 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335c 0x335c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 2f70 2f70 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2f72 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2f72 0x2f72 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f71 2f71 ioc_fiubs 2 typ ; Flow J 0x2f6e seq_br_type 3 Unconditional Branch seq_branch_adr 2f6e 0x2f6e val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f72 2f72 seq_br_type 3 Unconditional Branch; Flow J 0x2f78 seq_branch_adr 2f78 0x2f78 2f73 2f73 seq_br_type 3 Unconditional Branch; Flow J 0x2f78 seq_branch_adr 2f78 0x2f78 2f74 2f74 fiu_mem_start 2 start-rd; Flow J 0x3457 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3457 0x3457 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2f75 2f75 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2f7e fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2f7e 0x2f7e seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2f76 2f76 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 2f77 2f77 seq_br_type 3 Unconditional Branch; Flow J 0x2f7e seq_branch_adr 2f7e 0x2f7e 2f78 2f78 seq_br_type 2 Push (branch address); Flow J 0x2f79 seq_branch_adr 2f6e 0x2f6e 2f79 2f79 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 2f7a 2f7a ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f7b 2f7b fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2f7c 2f7c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2f7d 2f7d ioc_load_wdr 0 ; Flow J 0x2e87 seq_br_type 3 Unconditional Branch seq_branch_adr 2e87 0x2e87 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2f7e 2f7e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f7f 2f7f ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f80 2f80 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f81 2f81 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2f82 2f82 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f8b seq_br_type 1 Branch True seq_branch_adr 2f8b 0x2f8b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 2f83 2f83 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 2f84 2f84 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2f86 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2f86 0x2f86 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2f85 2f85 fiu_fill_mode_src 0 ; Flow J 0x2f88 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f88 0x2f88 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f86 2f86 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2f87 2f87 fiu_fill_mode_src 0 ; Flow J 0x2f88 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f88 0x2f88 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f88 2f88 ioc_fiubs 2 typ ; Flow J 0x2f89 seq_br_type 2 Push (branch address) seq_branch_adr 2f82 0x2f82 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f89 2f89 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 2f8a 2f8a ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f8b 2f8b seq_br_type 3 Unconditional Branch; Flow J 0x2f6e seq_branch_adr 2f6e 0x2f6e typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2f8c 2f8c fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2f8d 2f8d fiu_mem_start 5 start_rd_if_true; Flow R cc=True ; Flow J cc=False 0x32af ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 32af 0x32af seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f8e ; -------------------------------------------------------------------------------------- 2f8e ; Comes from: 2f8e ; 2e57 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2f8e ; -------------------------------------------------------------------------------------- 2f8e 2f8e fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2f8f 2f8f seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32af seq_br_type 8 Return True seq_branch_adr 32af 0x32af seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 2f90 ; -------------------------------------------------------------------------------------- 2f90 ; 0x4100-0x41ff End_Rendezvous >R,parmcnt 2f90 ; -------------------------------------------------------------------------------------- 2f90 MACRO_End_Rendezvous_>R,parmcnt: 2f90 2f90 dispatch_brk_class 5 ; Flow C 0x337f dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 2f90 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f seq_int_reads 5 RESOLVE RAM typ_a_adr 2f TR05:0f typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 2e VR05:0e val_frame 5 2f91 2f91 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2f92 2f92 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f62 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f62 0x2f62 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 2f93 2f93 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x2f96 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f96 0x2f96 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2f94 2f94 ioc_fiubs 2 typ ; Flow C cc=False 0x32af ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 2f95 2f95 ioc_adrbs 1 val ; Flow J 0x3732 seq_br_type 3 Unconditional Branch seq_branch_adr 3732 0x3732 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f96 2f96 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x32af seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2f97 2f97 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2f98 2f98 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? 2f99 2f99 seq_random 6a ? 2f9a 2f9a seq_lex_adr 3 seq_random 6a ? 2f9b 2f9b seq_br_type a Unconditional Return; Flow R seq_lex_adr 2 seq_random 0b ? 2f9c ; -------------------------------------------------------------------------------------- 2f9c ; 0x027f Execute Discrete,Equal 2f9c ; -------------------------------------------------------------------------------------- 2f9c MACRO_Execute_Discrete,Equal: 2f9c 2f9c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2f9c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2f9d 2f9d <halt> ; Flow R 2f9e ; -------------------------------------------------------------------------------------- 2f9e ; 0x0f00-0x0fff Execute_Immediate Equal,uimmediate 2f9e ; -------------------------------------------------------------------------------------- 2f9e MACRO_Execute_Immediate_Equal,uimmediate: 2f9e 2f9e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2f9e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2f9f 2f9f <halt> ; Flow R 2fa0 ; -------------------------------------------------------------------------------------- 2fa0 ; 0x027e Execute Discrete,Not_Equal 2fa0 ; -------------------------------------------------------------------------------------- 2fa0 MACRO_Execute_Discrete,Not_Equal: 2fa0 2fa0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa0 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa1 2fa1 <halt> ; Flow R 2fa2 ; -------------------------------------------------------------------------------------- 2fa2 ; 0x0e00-0x0eff Execute_Immediate Not_Equal,uimmediate 2fa2 ; -------------------------------------------------------------------------------------- 2fa2 MACRO_Execute_Immediate_Not_Equal,uimmediate: 2fa2 2fa2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fa2 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fa3 2fa3 <halt> ; Flow R 2fa4 ; -------------------------------------------------------------------------------------- 2fa4 ; 0x027d Execute Discrete,Greater 2fa4 ; -------------------------------------------------------------------------------------- 2fa4 MACRO_Execute_Discrete,Greater: 2fa4 2fa4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa4 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa5 2fa5 <halt> ; Flow R 2fa6 ; -------------------------------------------------------------------------------------- 2fa6 ; 0x027c Execute Discrete,Less 2fa6 ; -------------------------------------------------------------------------------------- 2fa6 MACRO_Execute_Discrete,Less: 2fa6 2fa6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa7 2fa7 <halt> ; Flow R 2fa8 ; -------------------------------------------------------------------------------------- 2fa8 ; 0x0d00-0x0dff Execute_Immediate Less,uimmediate 2fa8 ; -------------------------------------------------------------------------------------- 2fa8 MACRO_Execute_Immediate_Less,uimmediate: 2fa8 2fa8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fa8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fa9 2fa9 <halt> ; Flow R 2faa ; -------------------------------------------------------------------------------------- 2faa ; 0x027b Execute Discrete,Greater_Equal 2faa ; -------------------------------------------------------------------------------------- 2faa MACRO_Execute_Discrete,Greater_Equal: 2faa 2faa dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2faa fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fab 2fab <halt> ; Flow R 2fac ; -------------------------------------------------------------------------------------- 2fac ; 0x0c00-0x0cff Execute_Immediate Greater_Equal,uimmediate 2fac ; -------------------------------------------------------------------------------------- 2fac MACRO_Execute_Immediate_Greater_Equal,uimmediate: 2fac 2fac dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 2fac ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fad 2fad fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fae ; -------------------------------------------------------------------------------------- 2fae ; 0x027a Execute Discrete,Less_Equal 2fae ; -------------------------------------------------------------------------------------- 2fae MACRO_Execute_Discrete,Less_Equal: 2fae 2fae dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fae fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2faf 2faf <halt> ; Flow R 2fb0 ; -------------------------------------------------------------------------------------- 2fb0 ; 0x0279 Execute Discrete,And 2fb0 ; -------------------------------------------------------------------------------------- 2fb0 MACRO_Execute_Discrete,And: 2fb0 2fb0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fb0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fb1 2fb1 <halt> ; Flow R 2fb2 ; -------------------------------------------------------------------------------------- 2fb2 ; 0x0278 Execute Discrete,Or 2fb2 ; -------------------------------------------------------------------------------------- 2fb2 MACRO_Execute_Discrete,Or: 2fb2 2fb2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fb2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fb3 2fb3 <halt> ; Flow R 2fb4 ; -------------------------------------------------------------------------------------- 2fb4 ; 0x0277 Execute Discrete,Xor 2fb4 ; -------------------------------------------------------------------------------------- 2fb4 MACRO_Execute_Discrete,Xor: 2fb4 2fb4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fb4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fb5 2fb5 <halt> ; Flow R 2fb6 ; -------------------------------------------------------------------------------------- 2fb6 ; 0x0276 Execute Discrete,Complement 2fb6 ; -------------------------------------------------------------------------------------- 2fb6 MACRO_Execute_Discrete,Complement: 2fb6 2fb6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fb6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 10 NOT_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fb7 2fb7 <halt> ; Flow R 2fb8 ; -------------------------------------------------------------------------------------- 2fb8 ; 0x0275 Execute Discrete,Unary_Minus 2fb8 ; -------------------------------------------------------------------------------------- 2fb8 MACRO_Execute_Discrete,Unary_Minus: 2fb8 2fb8 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fb8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fb9 0x2fb9 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fb9 2fb9 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 2fba ; -------------------------------------------------------------------------------------- 2fba ; 0x0274 Execute Discrete,Absolute_Value 2fba ; -------------------------------------------------------------------------------------- 2fba MACRO_Execute_Discrete,Absolute_Value: 2fba 2fba dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fba seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 2fbb 2fbb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fb9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fb9 0x2fb9 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fbc ; -------------------------------------------------------------------------------------- 2fbc ; 0x0273 Execute Discrete,Plus 2fbc ; -------------------------------------------------------------------------------------- 2fbc MACRO_Execute_Discrete,Plus: 2fbc 2fbc dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fbd 0x2fbd seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fbd 2fbd seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 2fbe ; -------------------------------------------------------------------------------------- 2fbe ; 0x0a00-0x0a7f Execute_Immediate Plus,s8 2fbe ; -------------------------------------------------------------------------------------- 2fbe MACRO_Execute_Immediate_Plus,s8: 2fbe 2fbe dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2fbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fbf 0x2fbf seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fbf 2fbf seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 ; 0x0272 Execute Discrete,Minus 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 MACRO_Execute_Discrete,Minus: 2fc0 2fc0 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fc1 0x2fc1 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fc1 2fc1 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 2fc2 ; -------------------------------------------------------------------------------------- 2fc2 ; 0x0a80-0x0aff Execute_Immediate Plus,s8 2fc2 ; -------------------------------------------------------------------------------------- 2fc2 MACRO_Execute_Immediate_Plus,s8: 2fc2 2fc2 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2fc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fc3 0x2fc3 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 30 VR02:10 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fc3 2fc3 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 2fc4 ; -------------------------------------------------------------------------------------- 2fc4 ; 0x026c Execute Discrete,Minimum 2fc4 ; -------------------------------------------------------------------------------------- 2fc4 MACRO_Execute_Discrete,Minimum: 2fc4 2fc4 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fc4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2fc5 2fc5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fc6 ; -------------------------------------------------------------------------------------- 2fc6 ; 0x026b Execute Discrete,Maximum 2fc6 ; -------------------------------------------------------------------------------------- 2fc6 MACRO_Execute_Discrete,Maximum: 2fc6 2fc6 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fc6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2fc7 2fc7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fc8 ; -------------------------------------------------------------------------------------- 2fc8 ; 0x026a Execute Discrete,First 2fc8 ; -------------------------------------------------------------------------------------- 2fc8 MACRO_Execute_Discrete,First: 2fc8 2fc8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fc8 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fc9 2fc9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fca ; -------------------------------------------------------------------------------------- 2fca ; 0x0269 Execute Discrete,Last 2fca ; -------------------------------------------------------------------------------------- 2fca MACRO_Execute_Discrete,Last: 2fca 2fca dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fca dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fcb 2fcb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fcc ; -------------------------------------------------------------------------------------- 2fcc ; 0x0268 Execute Discrete,Successor 2fcc ; -------------------------------------------------------------------------------------- 2fcc MACRO_Execute_Discrete,Successor: 2fcc 2fcc dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fcc fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2fcd 2fcd ioc_fiubs 1 val ; Flow C cc=True 0x326e ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fce 2fce fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fcf 0x2fcf seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fcf 2fcf fiu_mem_start 2 start-rd; Flow J 0x2fd0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2fd0 0x2fd0 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2fd0 2fd0 <default> 2fd1 2fd1 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2fd2 2fd2 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2fd3 2fd3 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e seq_en_micro 0 seq_random 02 ? 2fd4 ; -------------------------------------------------------------------------------------- 2fd4 ; 0x0267 Execute Discrete,Predecessor 2fd4 ; -------------------------------------------------------------------------------------- 2fd4 MACRO_Execute_Discrete,Predecessor: 2fd4 2fd4 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fd4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2fd5 2fd5 ioc_fiubs 1 val ; Flow C cc=True 0x326e ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fd6 2fd6 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fd7 0x2fd7 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fd7 2fd7 fiu_mem_start 2 start-rd; Flow J 0x2fd0 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2fd0 0x2fd0 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 ; 0x0b00-0x0bff Execute_Immediate Case_Compare,uimmediate 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 MACRO_Execute_Immediate_Case_Compare,uimmediate: 2fd8 2fd8 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_uadr 2fd8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fd9 2fd9 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fda ; -------------------------------------------------------------------------------------- 2fda ; 0x0249 Execute Discrete,Case_In_Range 2fda ; -------------------------------------------------------------------------------------- 2fda MACRO_Execute_Discrete,Case_In_Range: 2fda 2fda dispatch_brk_class 8 ; Flow J cc=True 0x2fd9 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fda seq_br_type 1 Branch True seq_branch_adr 2fd9 0x2fd9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fdb 2fdb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fdc ; -------------------------------------------------------------------------------------- 2fdc ; 0x0266 Execute Discrete,Bounds 2fdc ; -------------------------------------------------------------------------------------- 2fdc MACRO_Execute_Discrete,Bounds: 2fdc 2fdc dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fdc dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fdd 2fdd ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2fde 2fde fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fdf 2fdf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 ; 0x0265 Execute Discrete,Reverse_Bounds 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 MACRO_Execute_Discrete,Reverse_Bounds: 2fe0 2fe0 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fe0 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fe1 2fe1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2fdf seq_br_type 3 Unconditional Branch seq_branch_adr 2fdf 0x2fdf seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 ; 0x0264 Execute Discrete,Below_Bound 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 MACRO_Execute_Discrete,Below_Bound: 2fe2 2fe2 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe2 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fe3 0x2fe3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2fe3 2fe3 seq_br_type 3 Unconditional Branch; Flow J 0x2fe5 seq_branch_adr 2fe5 0x2fe5 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 ; 0x0263 Execute Discrete,Above_Bound 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 MACRO_Execute_Discrete,Above_Bound: 2fe4 2fe4 dispatch_brk_class 8 ; Flow R cc=True ; Flow J cc=False 0x2fe3 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe4 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fe3 0x2fe3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2fe5 2fe5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 ; 0x0262 Execute Discrete,In_Range 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 MACRO_Execute_Discrete,In_Range: 2fe6 2fe6 dispatch_brk_class 8 ; Flow J cc=True 0x2faa dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fe6 seq_br_type 1 Branch True seq_branch_adr 2faa MACRO_Execute_Discrete,Greater_Equal seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fe7 2fe7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 ; 0x0261 Execute Discrete,Not_In_Range 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 MACRO_Execute_Discrete,Not_In_Range: 2fe8 2fe8 dispatch_brk_class 8 ; Flow J cc=True 0x2fa6 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fe8 seq_br_type 1 Branch True seq_branch_adr 2fa6 MACRO_Execute_Discrete,Less seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fe9 2fe9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2fea ; -------------------------------------------------------------------------------------- 2fea ; 0x0260 Execute Discrete,In_Type 2fea ; -------------------------------------------------------------------------------------- 2fea MACRO_Execute_Discrete,In_Type: 2fea 2fea dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fea dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_frame 2 2feb 2feb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fed fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fed 0x2fed seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 2fec ; -------------------------------------------------------------------------------------- 2fec ; 0x025f Execute Discrete,Not_In_Type 2fec ; -------------------------------------------------------------------------------------- 2fec MACRO_Execute_Discrete,Not_In_Type: 2fec 2fec dispatch_brk_class 8 ; Flow J 0x2feb dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fec dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2feb 0x2feb typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2fed 2fed fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2fee ; -------------------------------------------------------------------------------------- 2fee ; 0x025e Execute Discrete,Convert 2fee ; -------------------------------------------------------------------------------------- 2fee MACRO_Execute_Discrete,Convert: 2fee 2fee dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fee dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2fef 2fef fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ff0 0x2ff0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff0 2ff0 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2ff1 2ff1 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2ff2 2ff2 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326e seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff3 2ff3 seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 2ff4 ; -------------------------------------------------------------------------------------- 2ff4 ; 0x025d Execute Discrete,Bounds_Check 2ff4 ; -------------------------------------------------------------------------------------- 2ff4 MACRO_Execute_Discrete,Bounds_Check: 2ff4 2ff4 dispatch_brk_class 8 ; Flow J 0x2ff5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff4 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2ff7 0x2ff7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2ff5 2ff5 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ff6 0x2ff6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff6 2ff6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fd3 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2fd3 0x2fd3 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 2ff7 2ff7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 ; 0x025c Execute Discrete,ReverseBounds_Check 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 MACRO_Execute_Discrete,ReverseBounds_Check: 2ff8 2ff8 dispatch_brk_class 8 ; Flow J 0x2ff9 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff8 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2ff7 0x2ff7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 2ff9 2ff9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2ff6 seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ff6 0x2ff6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ffa ; -------------------------------------------------------------------------------------- 2ffa ; 0x025b Execute Discrete,Check_In_Type 2ffa ; -------------------------------------------------------------------------------------- 2ffa MACRO_Execute_Discrete,Check_In_Type: 2ffa 2ffa dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ffa dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 2ffb 2ffb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2ff0 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ff0 0x2ff0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ffc ; -------------------------------------------------------------------------------------- 2ffc ; 0x0248 Execute Discrete,Check_In_Integer 2ffc ; -------------------------------------------------------------------------------------- 2ffc MACRO_Execute_Discrete,Check_In_Integer: 2ffc 2ffc dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2ffc fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 2ffd 0x2ffd seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 2ffd 2ffd fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3278 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3278 0x3278 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 2ffe ; -------------------------------------------------------------------------------------- 2ffe ; 0x025a Execute Discrete,Write_Unchecked 2ffe ; -------------------------------------------------------------------------------------- 2ffe MACRO_Execute_Discrete,Write_Unchecked: 2ffe 2ffe dispatch_brk_class 2 ; Flow C cc=False 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ffe fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2fff 2fff typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 3000 3000 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3279 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3001 3001 fiu_fill_mode_src 0 ; Flow J cc=False 0x3003 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3003 0x3003 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 3002 3002 fiu_fill_mode_src 0 ; Flow J 0x3006 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3006 0x3006 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3003 3003 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3004 3004 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3005 3005 fiu_load_var 1 hold_var; Flow J 0x3006 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3006 0x3006 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3006 3006 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 3007 3007 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3008 ; -------------------------------------------------------------------------------------- 3008 ; 0x0259 Execute Discrete,Test_And_Set_Previous 3008 ; -------------------------------------------------------------------------------------- 3008 MACRO_Execute_Discrete,Test_And_Set_Previous: 3008 3008 dispatch_brk_class 8 ; Flow J cc=True 0x3011 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3008 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3011 0x3011 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 3009 3009 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 300a 300a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 300b 300b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 300c 300c fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 300d 300d fiu_load_var 1 hold_var; Flow J cc=True 0x300f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 300f 0x300f typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 300e 300e fiu_mem_start 3 start-wr; Flow J cc=True 0x300f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300f 0x300f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 300f 300f ioc_load_wdr 0 ; Flow J 0x3025 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3025 0x3025 seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 3010 ; -------------------------------------------------------------------------------------- 3010 ; 0x0258 Execute Discrete,Test_And_Set_Next 3010 ; -------------------------------------------------------------------------------------- 3010 MACRO_Execute_Discrete,Test_And_Set_Next: 3010 3010 dispatch_brk_class 8 ; Flow J cc=False 0x3009 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3010 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 3009 0x3009 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 3011 3011 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3012 3012 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3279 fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 3013 3013 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3014 3014 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3019 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3019 0x3019 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3015 3015 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3016 3016 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x300f seq_br_type 1 Branch True seq_branch_adr 300f 0x300f seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3017 3017 fiu_fill_mode_src 0 ; Flow J cc=True 0x300f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300f 0x300f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3018 3018 fiu_fill_mode_src 0 ; Flow J 0x300f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 300f 0x300f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3019 3019 fiu_load_var 1 hold_var; Flow J cc=True 0x301f fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 301f 0x301f seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 301a 301a seq_br_type 7 Unconditional Call; Flow C 0x3077 seq_branch_adr 3077 0x3077 301b 301b <default> 301c 301c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 301d 301d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 301e 301e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 301f 301f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3020 3020 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3021 3021 fiu_fill_mode_src 0 ; Flow J cc=True 0x300f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300f 0x300f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3022 3022 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first 3023 3023 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3024 3024 fiu_load_var 1 hold_var; Flow J 0x300f fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 300f 0x300f seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3025 3025 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3026 ; -------------------------------------------------------------------------------------- 3026 ; 0x0256 Execute Discrete,Instruction_Read 3026 ; -------------------------------------------------------------------------------------- 3026 MACRO_Execute_Discrete,Instruction_Read: 3026 3026 dispatch_brk_class 8 ; Flow C 0x32fe dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3026 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_frame 6 3027 3027 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3028 ; -------------------------------------------------------------------------------------- 3028 ; 0x0255 Execute Discrete,Partial_Plus 3028 ; -------------------------------------------------------------------------------------- 3028 MACRO_Execute_Discrete,Partial_Plus: 3028 3028 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3028 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 3029 3029 seq_b_timing 1 Latch Condition; Flow J cc=True 0x302b seq_br_type 1 Branch True seq_branch_adr 302b 0x302b typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 302a 302a seq_br_type 3 Unconditional Branch; Flow J 0x302c seq_branch_adr 302c 0x302c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 302b 302b seq_br_type 3 Unconditional Branch; Flow J 0x302c seq_branch_adr 302c 0x302c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 302c 302c seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 302d 302d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 302e ; -------------------------------------------------------------------------------------- 302e ; 0x0254 Execute Discrete,Partial_Minus 302e ; -------------------------------------------------------------------------------------- 302e MACRO_Execute_Discrete,Partial_Minus: 302e 302e dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 302e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 302f 302f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3031 seq_br_type 1 Branch True seq_branch_adr 3031 0x3031 typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 3030 3030 seq_br_type 3 Unconditional Branch; Flow J 0x302c seq_branch_adr 302c 0x302c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3031 3031 seq_br_type 3 Unconditional Branch; Flow J 0x302c seq_branch_adr 302c 0x302c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3032 ; -------------------------------------------------------------------------------------- 3032 ; 0x0253 Execute Discrete,Binary_Scale 3032 ; -------------------------------------------------------------------------------------- 3032 MACRO_Execute_Discrete,Binary_Scale: 3032 3032 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3032 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3033 3033 fiu_tivi_src 6 fiu_fiu; Flow J cc=True 0x3038 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3038 0x3038 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3034 3034 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3035 0x3035 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 3035 3035 ioc_tvbs 2 fiu+val; Flow J cc=False 0x3037 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3037 0x3037 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_rand 5 COUNT_ZEROS 3036 3036 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3037 0x3037 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3037 3037 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2fb9 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2fb9 0x2fb9 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 3038 3038 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3039 0x3039 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR11:12 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 11 3039 3039 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x303b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 303b 0x303b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 02 ? val_alu_func 6 A_MINUS_B val_b_adr 32 VR11:12 val_frame 11 303a 303a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 303b 303b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 303c ; -------------------------------------------------------------------------------------- 303c ; 0x09c0-0x09ff Execute_Immediate Binary_Scale,limitedneg 303c ; -------------------------------------------------------------------------------------- 303c MACRO_Execute_Immediate_Binary_Scale,limitedneg: 303c 303c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 303c fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR02:10 val_frame 2 val_rand 6 IMMEDIATE_OP 303d 303d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 303e 0x303e seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 303e 303e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value 303f 303f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 3040 ; -------------------------------------------------------------------------------------- 3040 ; 0x0900-0x093f Execute_Immediate Binary_Scale,limitedpos 3040 ; -------------------------------------------------------------------------------------- 3040 MACRO_Execute_Immediate_Binary_Scale,limitedpos: 3040 3040 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 3040 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 3041 3041 fiu_tivi_src 6 fiu_fiu; Flow J cc=False 0x3035 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3035 0x3035 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3042 3042 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x3035 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3035 0x3035 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3043 3043 <halt> ; Flow R 3044 ; -------------------------------------------------------------------------------------- 3044 ; 0x0252 Execute Discrete,Arithmetic_Shift 3044 ; -------------------------------------------------------------------------------------- 3044 MACRO_Execute_Discrete,Arithmetic_Shift: 3044 3044 dispatch_brk_class 8 ; Flow J cc=True 0x3047 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3044 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3047 0x3047 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3045 3045 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 39 VR02:19 val_frame 2 3046 3046 fiu_len_fill_lit 7e zero-fill 0x3e; Flow R cc=True ; Flow J cc=False 0x2fd3 fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3047 3047 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3048 ; -------------------------------------------------------------------------------------- 3048 ; 0x0251 Execute Discrete,Logical_Shift 3048 ; -------------------------------------------------------------------------------------- 3048 MACRO_Execute_Discrete,Logical_Shift: 3048 3048 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3048 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3049 3049 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 304a ; -------------------------------------------------------------------------------------- 304a ; 0x0940-0x097f Execute_Immediate Logical_Shift,limitedneg 304a ; 0x0980-0x09bf Execute_Immediate Logical_Shift,limitedpos 304a ; -------------------------------------------------------------------------------------- 304a MACRO_Execute_Immediate_Logical_Shift,limitedneg: 304a MACRO_Execute_Immediate_Logical_Shift,limitedpos: 304a 304a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 304a fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 304b 304b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 304c ; -------------------------------------------------------------------------------------- 304c ; 0x0250 Execute Discrete,Rotate 304c ; -------------------------------------------------------------------------------------- 304c MACRO_Execute_Discrete,Rotate: 304c 304c dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 304c fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 304d 304d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 304e ; -------------------------------------------------------------------------------------- 304e ; 0x024f Execute Discrete,Insert_Bits 304e ; -------------------------------------------------------------------------------------- 304e MACRO_Execute_Discrete,Insert_Bits: 304e 304e dispatch_brk_class 8 ; Flow C cc=True 0x326e dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 304e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 304f 304f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x326e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3050 3050 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 3051 3051 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd3 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3052 ; -------------------------------------------------------------------------------------- 3052 ; 0x024e Execute Discrete,Extract_Bits 3052 ; -------------------------------------------------------------------------------------- 3052 MACRO_Execute_Discrete,Extract_Bits: 3052 3052 dispatch_brk_class 8 ; Flow J cc=True 0x3056 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3052 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3056 0x3056 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3053 3053 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x326e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3054 3054 fiu_fill_mode_src 0 ; Flow C cc=True 0x326e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3055 3055 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2fd3 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd3 0x2fd3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3056 3056 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x3054 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3054 0x3054 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3057 3057 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e seq_en_micro 0 seq_random 02 ? 3058 ; -------------------------------------------------------------------------------------- 3058 ; 0x024d Execute Discrete,Count_Nonzero_Bits 3058 ; -------------------------------------------------------------------------------------- 3058 MACRO_Execute_Discrete,Count_Nonzero_Bits: 3058 3058 dispatch_brk_class 8 ; Flow J cc=True 0x306d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3058 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 306d 0x306d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3059 3059 fiu_len_fill_lit 7d zero-fill 0x3d fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER 305a 305a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 305b 305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 305c 305c fiu_fill_mode_src 0 ; Flow J cc=True 0x305d ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_mux_sel 2 ALU 305d 305d fiu_fill_mode_src 0 ; Flow J cc=True 0x305e ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3e VR03:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 val_rand 2 DEC_LOOP_COUNTER 305e 305e fiu_fill_mode_src 0 ; Flow J cc=True 0x305f ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 305f 305f fiu_fill_mode_src 0 ; Flow J cc=True 0x3060 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3060 3060 fiu_fill_mode_src 0 ; Flow J cc=True 0x3061 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3061 3061 fiu_fill_mode_src 0 ; Flow J cc=True 0x3062 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3062 3062 fiu_fill_mode_src 0 ; Flow J cc=True 0x3063 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3063 3063 fiu_fill_mode_src 0 ; Flow J cc=True 0x3064 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3064 3064 fiu_fill_mode_src 0 ; Flow J cc=True 0x3065 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3065 3065 fiu_fill_mode_src 0 ; Flow J cc=True 0x3066 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3066 3066 fiu_fill_mode_src 0 ; Flow J cc=True 0x3067 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3067 3067 fiu_fill_mode_src 0 ; Flow J cc=True 0x3068 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3068 3068 fiu_fill_mode_src 0 ; Flow J cc=True 0x3069 ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3069 3069 fiu_fill_mode_src 0 ; Flow J cc=True 0x306a ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306a 306a fiu_fill_mode_src 0 ; Flow J cc=True 0x306b ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306b 306b fiu_fill_mode_src 0 ; Flow J cc=True 0x306c ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306c 306c fiu_fill_mode_src 0 ; Flow J cc=True 0x306d ; Flow J cc=#0x0 0x305d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305d 0x305d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306d 306d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 306e ; -------------------------------------------------------------------------------------- 306e ; 0x024c Execute Discrete,Count_Leading_Zeros 306e ; -------------------------------------------------------------------------------------- 306e MACRO_Execute_Discrete,Count_Leading_Zeros: 306e 306e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 306e typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 306f 306f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 3070 ; -------------------------------------------------------------------------------------- 3070 ; 0x024b Execute Discrete,Count_Trailing_Zeros 3070 ; -------------------------------------------------------------------------------------- 3070 MACRO_Execute_Discrete,Count_Trailing_Zeros: 3070 3070 dispatch_brk_class 8 ; Flow J cc=True 0x3073 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3070 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3073 0x3073 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3071 3071 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_rand 5 COUNT_ZEROS 3072 3072 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3073 3073 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 3074 ; -------------------------------------------------------------------------------------- 3074 ; 0x024a Execute Discrete,Is_Unsigned 3074 ; -------------------------------------------------------------------------------------- 3074 MACRO_Execute_Discrete,Is_Unsigned: 3074 3074 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3074 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_b_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 3075 3075 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3076 3076 fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3077 ; -------------------------------------------------------------------------------------- 3077 ; Comes from: 3077 ; 0888 C False from color 0x0000 3077 ; 088c C False from color 0x0000 3077 ; 0969 C False from color MACRO_0966_QQUnknown_InMicrocode 3077 ; 0975 C False from color 0x0000 3077 ; 09da C False from color MACRO_Execute_Any,Size 3077 ; 09e3 C False from color 0x09e1 3077 ; 09f0 C False from color MACRO_Execute_Any,Size 3077 ; 0b21 C False from color 0x0000 3077 ; 0c25 C False from color MACRO_Execute_Heap_Access,Element_Type 3077 ; 0c63 C False from color 0x0000 3077 ; 0c95 C False from color 0x0000 3077 ; 0cb1 C False from color MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head 3077 ; 0cdc C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3077 ; 0ce3 C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3077 ; 0cfc C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3077 ; 0d00 C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3077 ; 0d0b C False from color MACRO_Execute_Vector,Hash 3077 ; 0d1d C False from color MACRO_Execute_Vector,Hash 3077 ; 0d1f C False from color MACRO_Execute_Vector,Hash 3077 ; 0d26 C False from color MACRO_Execute_Vector,Hash 3077 ; 0d2d C False from color 0x0000 3077 ; 134d C False from color 0x0000 3077 ; 1352 C False from color 0x1350 3077 ; 1369 C False from color 0x0000 3077 ; 1441 C False from color 0x09ac 3077 ; 1443 C False from color 0x09ac 3077 ; 1455 C False from color 0x09ac 3077 ; 1457 C False from color 0x09ac 3077 ; 146c C False from color 0x0000 3077 ; 1470 C False from color 0x0000 3077 ; 147f C False from color MACRO_Execute_Matrix,Length 3077 ; 148c C False from color 0x1486 3077 ; 1495 C False from color 0x1486 3077 ; 14dd C False from color 0x14d7 3077 ; 14e0 C False from color 0x14d7 3077 ; 1523 C False from color 0x0000 3077 ; 1535 C False from color 0x1531 3077 ; 1542 C False from color 0x1531 3077 ; 1571 C False from color 0x1569 3077 ; 1574 C False from color 0x1569 3077 ; 1576 C False from color 0x1569 3077 ; 15df C False from color 0x0000 3077 ; 15f4 C False from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 3077 ; 1602 C False from color 0x0000 3077 ; 1605 C False from color 0x0000 3077 ; 160c C False from color 0x0000 3077 ; 162c C False from color 0x0000 3077 ; 1637 C False from color 0x0000 3077 ; 163e C False from color 0x0000 3077 ; 1643 C False from color 0x0000 3077 ; 1650 C False from color 0x0000 3077 ; 165c C False from color 0x0000 3077 ; 1662 C False from color 0x0000 3077 ; 1667 C False from color 0x0000 3077 ; 1671 C False from color 0x0000 3077 ; 16ab C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 3077 ; 16cb C False from color 0x16c7 3077 ; 16dc C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3077 ; 16e4 C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3077 ; 16ec C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3077 ; 16ff C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3077 ; 175c C False from color MACRO_Execute_Variant_Record,Read_Variant 3077 ; 17cd C False from color MACRO_Execute_Any,Set_Constraint 3077 ; 17d8 C False from color MACRO_Execute_Record,Field_Read,fieldnum 3077 ; 1821 C False from color 0x09ab 3077 ; 182d C False from color 0x09ab 3077 ; 1846 C False from color MACRO_Execute_Vector,Greater_Equal 3077 ; 1850 C False from color MACRO_Execute_Vector,Greater_Equal 3077 ; 185b C False from color MACRO_Execute_Vector,Greater_Equal 3077 ; 1864 C False from color MACRO_Execute_Vector,Greater_Equal 3077 ; 186b C False from color MACRO_Execute_Vector,First 3077 ; 1872 C False from color MACRO_Execute_Vector,First 3077 ; 1884 C False from color MACRO_Execute_Vector,First 3077 ; 1890 C False from color MACRO_Execute_Vector,Reverse_Bounds 3077 ; 189f C False from color MACRO_Execute_Vector,Reverse_Bounds 3077 ; 18ac C False from color MACRO_Execute_Vector,Field_Read 3077 ; 18bc C False from color MACRO_Execute_Vector,Field_Read 3077 ; 18d5 C False from color 0x0000 3077 ; 18f0 C False from color MACRO_Execute_Vector,Field_Reference 3077 ; 18fe C False from color MACRO_Execute_Vector,And 3077 ; 1907 C False from color MACRO_Execute_Vector,And 3077 ; 1919 C False from color MACRO_Execute_Vector,And 3077 ; 1933 C False from color 0x0000 3077 ; 1935 C False from color 0x0000 3077 ; 1940 C False from color MACRO_Execute_Vector,Complement 3077 ; 1955 C False from color MACRO_Execute_Vector,Complement 3077 ; 195f C False from color MACRO_Execute_Vector,Complement 3077 ; 1982 C False from color MACRO_Execute_Vector,Slice_Read 3077 ; 19aa C False from color MACRO_Execute_Vector,Slice_Write 3077 ; 19b3 C False from color MACRO_Execute_Vector,Slice_Write 3077 ; 19cd C False from color 0x19ca 3077 ; 19d5 C False from color MACRO_Execute_Vector,Catenate 3077 ; 19e0 C False from color MACRO_Execute_Vector,Catenate 3077 ; 19ff C False from color MACRO_Execute_Vector,Catenate 3077 ; 1a2c C False from color 0x0000 3077 ; 1a4c C False from color 0x0000 3077 ; 1a55 C False from color 0x1a4f 3077 ; 1a68 C False from color 0x1a65 3077 ; 1aaa C False from color 0x1aa7 3077 ; 1ae5 C False from color MACRO_Execute_Access,Element_Type 3077 ; 1b53 C False from color 0x09a8 3077 ; 1b5d C False from color 0x1b5a 3077 ; 1b8a C False from color 0x1b80 3077 ; 1b90 C False from color 0x1b80 3077 ; 1c28 C False from color 0x1c27 3077 ; 1c61 C False from color 0x0000 3077 ; 1c65 C False from color 0x0000 3077 ; 1c6e C False from color MACRO_Execute_Array,Field_Read 3077 ; 1dfb C False from color 0x0000 3077 ; 1e06 C False from color 0x0000 3077 ; 1e1c C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e20 C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e26 C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e2a C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e3c C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e3f C False from color MACRO_Execute_Matrix,Structure_Write 3077 ; 1e72 C False from color 0x0000 3077 ; 1ef5 C False from color 0x0000 3077 ; 228a C False from color 0x2282 3077 ; 22a5 C False from color 0x0000 3077 ; 22ba C False from color 0x09a8 3077 ; 22c0 C False from color 0x09a8 3077 ; 22c5 C False from color 0x0000 3077 ; 245c C False from color 0x0000 3077 ; 246a C False from color 0x0000 3077 ; 2472 C False from color 0x0000 3077 ; 24b4 C False from color 0x248a 3077 ; 24c1 C False from color 0x248a 3077 ; 24dd C False from color 0x24da 3077 ; 24f0 C False from color 0x248a 3077 ; 24fa C False from color 0x248a 3077 ; 2501 C False from color 0x248a 3077 ; 2703 C False from color 0x26fc 3077 ; 2705 C False from color 0x26fc 3077 ; 2933 C False from color 0x292f 3077 ; 293b C False from color 0x2939 3077 ; 2960 C False from color 0x295e 3077 ; 2b7e C False from color 0x0000 3077 ; 2dd8 C False from color 0x0000 3077 ; 301a C from color MACRO_Execute_Discrete,Test_And_Set_Previous 3077 ; 35f1 C False from color 0x0000 3077 ; 35fc C False from color 0x0000 3077 ; 3602 C False from color 0x3600 3077 ; -------------------------------------------------------------------------------------- 3077 3077 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3078 0x3078 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3078 3078 fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3079 3079 fiu_load_var 1 hold_var; Flow J 0x3076 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3076 0x3076 307a 307a fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 307b ; -------------------------------------------------------------------------------------- 307b ; Comes from: 307b ; 0791 C False from color 0x0767 307b ; 0ab2 C False from color 0x0000 307b ; 0c15 C False from color 0x0c07 307b ; 0c9d C False from color 0x0000 307b ; 0ca6 C False from color 0x0000 307b ; 0d38 C False from color 0x0d36 307b ; 1152 C False from color 0x110f 307b ; 12ec C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 307b ; 1324 C False from color 0x1316 307b ; 137f C False from color MACRO_Declare_Variable_Array,With_Constraint 307b ; 13c2 C False from color MACRO_Declare_Variable_Array,With_Constraint 307b ; 13d7 C False from color MACRO_Declare_Variable_Array,With_Constraint 307b ; 13e3 C False from color MACRO_Declare_Variable_Array,With_Constraint 307b ; 1409 C False from color MACRO_Declare_Variable_Array,With_Constraint 307b ; 1428 C False from color 0x1411 307b ; 1433 C False from color 0x1411 307b ; 172a C False from color 0x1727 307b ; 1ad5 C False from color 0x0000 307b ; 1d68 C False from color 0x0000 307b ; 1d7d C False from color 0x1d2a 307b ; 1d9b C False from color 0x1d2a 307b ; 1da3 C False from color 0x1d2a 307b ; 1ef7 C False from color 0x0000 307b ; 2903 C False from color MACRO_Execute_Float,Write_Unchecked 307b ; 296c C False from color 0x0000 307b ; 29bf C False from color 0x0000 307b ; 29ce C False from color 0x0000 307b ; 2a17 C False from color 0x2a14 307b ; 2a2b C False from color 0x2a04 307b ; 2a32 C False from color 0x0000 307b ; 3003 C False from color MACRO_Execute_Discrete,Write_Unchecked 307b ; 35a8 C False from color 0x35a3 307b ; 392e C False from color 0x062d 307b ; -------------------------------------------------------------------------------------- 307b 307b fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x307f ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 307f 0x307f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl 1 RESTORE_RDR val_c_adr 30 GP0f 307c 307c fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x3080 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 3080 0x3080 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 307d 307d ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 307e 307e ioc_adrbs 1 val ; Flow R cc=True ; Flow J cc=False 0x3080 seq_br_type 8 Return True seq_branch_adr 3080 0x3080 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 307f 307f fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 3080 3080 fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A val_b_adr 0f GP0f 3081 3081 fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3082 3082 fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe 3083 3083 fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3084 3084 fiu_fill_mode_src 0 ; Flow J 0x307a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 307a 0x307a 3085 3085 <halt> ; Flow R 3086 ; -------------------------------------------------------------------------------------- 3086 ; 0x03e6 Declare_Type Float,Defined,Visible 3086 ; -------------------------------------------------------------------------------------- 3086 MACRO_Declare_Type_Float,Defined,Visible: 3086 3086 dispatch_brk_class 4 ; Flow C 0x3089 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3086 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3089 0x3089 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3087 3087 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32aa ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 36 TR08:16 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 3088 3088 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 3089 ; -------------------------------------------------------------------------------------- 3089 ; Comes from: 3089 ; 3086 C from color MACRO_Declare_Type_Float,Defined,Visible 3089 ; 308c C from color MACRO_Declare_Type_Float,Defined,Visible 3089 ; -------------------------------------------------------------------------------------- 3089 3089 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_frame 1c val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 308a 308a fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_alu_func 1 A_PLUS_B val_b_adr 29 VR09:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 308b 308b fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 308c ; -------------------------------------------------------------------------------------- 308c ; 0x03e5 Declare_Type Float,Defined 308c ; -------------------------------------------------------------------------------------- 308c MACRO_Declare_Type_Float,Defined: 308c 308c dispatch_brk_class 4 ; Flow C 0x3089 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 308c fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3089 0x3089 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 308d 308d fiu_tivi_src 4 fiu_var; Flow J 0x3088 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3088 0x3088 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 31 TR02:11 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 308e ; -------------------------------------------------------------------------------------- 308e ; Comes from: 308e ; 309a C from color 0x0000 308e ; -------------------------------------------------------------------------------------- 308e 308e fiu_load_tar 1 hold_tar; Flow C 0x3092 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3092 0x3092 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_rand 8 SPARE_0x08 308f 308f ioc_tvbs 2 fiu+val; Flow J cc=False 0x3093 seq_br_type 0 Branch False seq_branch_adr 3093 0x3093 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 3090 ; -------------------------------------------------------------------------------------- 3090 ; Comes from: 3090 ; 3092 C from color 0x3092 3090 ; -------------------------------------------------------------------------------------- 3090 3090 fiu_mem_start 3 start-wr; Flow J cc=False 0x3097 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3097 0x3097 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3091 3091 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x3094 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3094 0x3094 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3092 ; -------------------------------------------------------------------------------------- 3092 ; Comes from: 3092 ; 308e C from color 0x308e 3092 ; -------------------------------------------------------------------------------------- 3092 3092 ioc_tvbs 2 fiu+val; Flow C 0x3090 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3090 0x3090 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 3093 3093 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 3094 3094 fiu_mem_start 3 start-wr; Flow J cc=False 0x3096 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3096 0x3096 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3095 3095 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326e seq_br_type 8 Return True seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 3096 3096 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326e seq_br_type 8 Return True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 3097 3097 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x3094 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3094 0x3094 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3098 ; -------------------------------------------------------------------------------------- 3098 ; Comes from: 3098 ; 309c C from color MACRO_Declare_Type_Float,Constrained,Visible 3098 ; 30a0 C from color 0x309f 3098 ; -------------------------------------------------------------------------------------- 3098 3098 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3099 3099 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 309a 309a ioc_tvbs c mem+mem+csa+dummy; Flow C 0x308e seq_br_type 7 Unconditional Call seq_branch_adr 308e 0x308e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 309b 309b fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x3279 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3279 0x3279 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 309c ; -------------------------------------------------------------------------------------- 309c ; 0x03e4 Declare_Type Float,Constrained,Visible 309c ; -------------------------------------------------------------------------------------- 309c MACRO_Declare_Type_Float,Constrained,Visible: 309c 309c dispatch_brk_class 4 ; Flow C 0x3098 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 309c fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3098 0x3098 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 309d 309d fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32aa ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 309e 309e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR08:18 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 309f 309f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR05:1d typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 30a0 ; -------------------------------------------------------------------------------------- 30a0 ; 0x03e3 Declare_Type Float,Constrained 30a0 ; -------------------------------------------------------------------------------------- 30a0 MACRO_Declare_Type_Float,Constrained: 30a0 30a0 dispatch_brk_class 4 ; Flow C 0x3098 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30a0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3098 0x3098 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30a1 30a1 fiu_tivi_src 4 fiu_var; Flow J 0x309f ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 309f 0x309f seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30a2 ; -------------------------------------------------------------------------------------- 30a2 ; 0x03e1 Declare_Type Float,Incomplete,Visible 30a2 ; -------------------------------------------------------------------------------------- 30a2 MACRO_Declare_Type_Float,Incomplete,Visible: 30a2 30a2 dispatch_brk_class 4 ; Flow C 0x30a5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30a2 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30a5 0x30a5 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30a3 30a3 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32aa ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3a TR08:1a typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30a4 30a4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30a5 ; -------------------------------------------------------------------------------------- 30a5 ; Comes from: 30a5 ; 30a2 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30a5 ; 30a8 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30a5 ; -------------------------------------------------------------------------------------- 30a5 30a5 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30a6 30a6 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 2a VR09:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 30a7 30a7 fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 30a8 ; -------------------------------------------------------------------------------------- 30a8 ; 0x03e0 Declare_Type Float,Incomplete 30a8 ; -------------------------------------------------------------------------------------- 30a8 MACRO_Declare_Type_Float,Incomplete: 30a8 30a8 dispatch_brk_class 4 ; Flow C 0x30a5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30a8 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30a5 0x30a5 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30a9 30a9 fiu_tivi_src 4 fiu_var; Flow J 0x30a4 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30a4 0x30a4 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3b TR08:1b typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30aa ; -------------------------------------------------------------------------------------- 30aa ; 0x03de Complete_Type Float,By_Defining 30aa ; -------------------------------------------------------------------------------------- 30aa MACRO_Complete_Type_Float,By_Defining: 30aa 30aa dispatch_brk_class 4 ; Flow C cc=True 0x32a7 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30aa fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30ab 30ab seq_br_type 2 Push (branch address); Flow J 0x30ac seq_branch_adr 32a9 0x32a9 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_frame 8 typ_rand 8 SPARE_0x08 30ac 30ac fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x30bf fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 30bf 0x30bf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 30ad 30ad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 30ae ; -------------------------------------------------------------------------------------- 30ae ; 0x03dd Complete_Type Float,By_Renaming 30ae ; -------------------------------------------------------------------------------------- 30ae MACRO_Complete_Type_Float,By_Renaming: 30ae 30ae dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30af 30af fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 30b0 30b0 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30b1 30b1 fiu_load_var 1 hold_var; Flow C cc=True 0x3279 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30b2 30b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30b3 30b3 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR06:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 30b4 30b4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 30b5 30b5 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x3279 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 30b6 30b6 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert typ_mar_cntl 6 INCREMENT_MAR 30b7 30b7 fiu_mem_start 4 continue; Flow J 0x30c1 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 30c1 0x30c1 typ_mar_cntl 6 INCREMENT_MAR 30b8 ; -------------------------------------------------------------------------------------- 30b8 ; 0x03dc Complete_Type Float,By_Constraining 30b8 ; -------------------------------------------------------------------------------------- 30b8 MACRO_Complete_Type_Float,By_Constraining: 30b8 30b8 dispatch_brk_class 4 ; Flow C 0x32fe dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30b8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1d TOP - 3 val_b_adr 1e TOP - 2 30b9 30b9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 30ba 30ba fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30bb 30bb fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32a9 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR 30bc 30bc fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x30c2 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 30c2 0x30c2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30bd 30bd ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 30be 30be fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3279 0x3279 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30bf 30bf fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 21 TR06:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30c0 30c0 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 30c1 30c1 ioc_load_wdr 0 ; Flow J 0x30ad seq_br_type 3 Unconditional Branch seq_branch_adr 30ad 0x30ad typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 30c2 ; -------------------------------------------------------------------------------------- 30c2 ; Comes from: 30c2 ; 30bc C from color MACRO_Complete_Type_Float,By_Defining 30c2 ; -------------------------------------------------------------------------------------- 30c2 30c2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x30c6 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c6 0x30c6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30c3 30c3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30c7 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 30c7 0x30c7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30c4 30c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x30cb fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30cb 0x30cb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30c5 30c5 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30c8 seq_branch_adr 30c8 0x30c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 30c6 30c6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30c4 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30c4 0x30c4 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30c7 30c7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 30c8 30c8 fiu_mem_start 2 start-rd; Flow J cc=False 0x30ca ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30ca 0x30ca seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30c9 30c9 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x326e seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 30ca 30ca seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x326e seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 30cb 30cb seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30c8 seq_branch_adr 30c8 0x30c8 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 30cc ; -------------------------------------------------------------------------------------- 30cc ; 0x03d9 Declare_Variable Float,Visible 30cc ; -------------------------------------------------------------------------------------- 30cc MACRO_Declare_Variable_Float,Visible: 30cc 30cc dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30cc seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 30cd 30cd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR08:16 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30ce ; -------------------------------------------------------------------------------------- 30ce ; 0x03da Declare_Variable Float 30ce ; -------------------------------------------------------------------------------------- 30ce MACRO_Declare_Variable_Float: 30ce 30ce dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30ce fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR09:17 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30cf 30cf <halt> ; Flow R 30d0 ; -------------------------------------------------------------------------------------- 30d0 ; 0x03d8 Declare_Variable Float,Duplicate 30d0 ; -------------------------------------------------------------------------------------- 30d0 MACRO_Declare_Variable_Float,Duplicate: 30d0 30d0 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30d0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 30d1 30d1 <halt> ; Flow R 30d2 ; -------------------------------------------------------------------------------------- 30d2 ; 0x02bf Declare_Variable Float,With_Value,With_Constraint 30d2 ; -------------------------------------------------------------------------------------- 30d2 MACRO_Declare_Variable_Float,With_Value,With_Constraint: 30d2 30d2 dispatch_brk_class 4 ; Flow J cc=True 0x30d8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 30d2 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 30d8 0x30d8 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30d3 30d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x326e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30d4 ; -------------------------------------------------------------------------------------- 30d4 ; 0x03df Declare_Variable Float,With_Value 30d4 ; -------------------------------------------------------------------------------------- 30d4 MACRO_Declare_Variable_Float,With_Value: 30d4 30d4 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30d4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 30d5 0x30d5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 30d5 30d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 30d6 ; -------------------------------------------------------------------------------------- 30d6 ; 0x02be Declare_Variable Float,Visible,With_Value,With_Constraint 30d6 ; -------------------------------------------------------------------------------------- 30d6 MACRO_Declare_Variable_Float,Visible,With_Value,With_Constraint: 30d6 30d6 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 30d6 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 30d7 30d7 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30d3 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30d3 0x30d3 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30d8 30d8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326e 0x326e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 30d9 30d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x326e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 326e 0x326e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30da ; -------------------------------------------------------------------------------------- 30da ; 0x03db Declare_Variable Float,Visible,With_Value 30da ; -------------------------------------------------------------------------------------- 30da MACRO_Declare_Variable_Float,Visible,With_Value: 30da 30da dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30da fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 30db 30db fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 30dc ; -------------------------------------------------------------------------------------- 30dc ; Comes from: 30dc ; 30ea C from color 0x30e5 30dc ; 30ee C from color 0x30e5 30dc ; 30f2 C from color 0x30e5 30dc ; 30f4 C from color 0x30e5 30dc ; -------------------------------------------------------------------------------------- 30dc 30dc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x30e1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30e1 0x30e1 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 typ_a_adr 35 TR02:15 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 30dd 30dd fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x30e3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30e3 0x30e3 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_b_adr 10 TOP 30de 30de fiu_tivi_src c mar_0xc; Flow J cc=False 0x30e0 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30e0 0x30e0 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 30df 30df val_alu_func 15 NOT_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 30e0 30e0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1c val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30e1 30e1 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_b_adr 10 TOP 30e2 30e2 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 30e3 30e3 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30e4 30e4 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 30e5 30e5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32aa fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 30e6 30e6 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30e7 30e7 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32a9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30e8 30e8 seq_br_type 4 Call False; Flow C cc=False 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 30e9 30e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 30ea ; -------------------------------------------------------------------------------------- 30ea ; 0x03fe Declare_Type Discrete,Defined,Visible 30ea ; -------------------------------------------------------------------------------------- 30ea MACRO_Declare_Type_Discrete,Defined,Visible: 30ea 30ea dispatch_brk_class 4 ; Flow C 0x30dc dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30ea fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30dc 0x30dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30eb 30eb fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30ec 30ec fiu_mem_start 4 continue; Flow C cc=False 0x32aa fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 30ed 30ed fiu_tivi_src 4 fiu_var; Flow J 0x30e9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e9 0x30e9 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30ee ; -------------------------------------------------------------------------------------- 30ee ; 0x03fd Declare_Type Discrete,Defined 30ee ; -------------------------------------------------------------------------------------- 30ee MACRO_Declare_Type_Discrete,Defined: 30ee 30ee dispatch_brk_class 4 ; Flow C 0x30dc dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30ee fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30dc 0x30dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30ef 30ef fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30f0 30f0 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 30f1 30f1 fiu_tivi_src 4 fiu_var; Flow J 0x30e9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e9 0x30e9 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30f2 ; -------------------------------------------------------------------------------------- 30f2 ; 0x03fb Declare_Type Discrete,Defined,Visible,With_Size 30f2 ; -------------------------------------------------------------------------------------- 30f2 MACRO_Declare_Type_Discrete,Defined,Visible,With_Size: 30f2 30f2 dispatch_brk_class 4 ; Flow C 0x30dc dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30f2 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30dc 0x30dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30f3 30f3 ioc_tvbs 1 typ+fiu; Flow J 0x30e5 seq_br_type 3 Unconditional Branch seq_branch_adr 30e5 0x30e5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30f4 ; -------------------------------------------------------------------------------------- 30f4 ; 0x03fa Declare_Type Discrete,Defined,With_Size 30f4 ; -------------------------------------------------------------------------------------- 30f4 MACRO_Declare_Type_Discrete,Defined,With_Size: 30f4 30f4 dispatch_brk_class 4 ; Flow C 0x30dc dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30f4 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30dc 0x30dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30f5 30f5 ioc_tvbs 1 typ+fiu; Flow J 0x30e5 seq_br_type 3 Unconditional Branch seq_branch_adr 30e5 0x30e5 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30f6 ; -------------------------------------------------------------------------------------- 30f6 ; 0x03f9 Declare_Type Discrete,Constrained,Visible 30f6 ; -------------------------------------------------------------------------------------- 30f6 MACRO_Declare_Type_Discrete,Constrained,Visible: 30f6 30f6 dispatch_brk_class 4 ; Flow J 0x30f7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30f6 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 30f7 30f7 fiu_mem_start 4 continue; Flow J cc=False 0x30fd ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30fd 0x30fd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 30f8 30f8 fiu_mem_start 4 continue; Flow J cc=True 0x30fb ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 30fb 0x30fb seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30f9 30f9 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 30fa 30fa fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x310a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 310a 0x310a seq_en_micro 0 typ_a_adr 26 TR06:06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30fb 30fb ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 30fc 30fc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x310a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 310a 0x310a seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30fd 30fd ioc_fiubs 1 val ; Flow R cc=False ; Flow J cc=True 0x3106 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 3106 0x3106 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30fe ; -------------------------------------------------------------------------------------- 30fe ; 0x03f8 Declare_Type Discrete,Constrained 30fe ; -------------------------------------------------------------------------------------- 30fe MACRO_Declare_Type_Discrete,Constrained: 30fe 30fe dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30fe fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 30ff 30ff fiu_mem_start 4 continue; Flow J cc=False 0x3105 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3105 0x3105 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3100 3100 fiu_mem_start 4 continue; Flow J cc=True 0x3103 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3103 0x3103 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3101 3101 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3102 3102 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x310a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 310a 0x310a seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3103 3103 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3104 3104 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x310a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 310a 0x310a seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3105 3105 ioc_load_wdr 0 ; Flow J 0x3106 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3106 0x3106 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3106 3106 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3107 3107 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3108 3108 fiu_mem_start 4 continue; Flow J cc=False 0x310c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 310c 0x310c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3109 3109 seq_br_type 3 Unconditional Branch; Flow J 0x3278 seq_branch_adr 3278 0x3278 310a 310a fiu_load_tar 1 hold_tar; Flow C cc=False 0x326e fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 310b 310b fiu_mem_start 4 continue; Flow C cc=False 0x326e ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 310c 310c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 310d 310d fiu_load_oreg 1 hold_oreg fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 310e 310e fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 310f ; -------------------------------------------------------------------------------------- 310f ; Comes from: 310f ; 311e C from color MACRO_Declare_Type_InMicrocode,Discrete 310f ; 3124 C from color MACRO_Declare_Type_InMicrocode,Discrete 310f ; -------------------------------------------------------------------------------------- 310f 310f fiu_mem_start 4 continue; Flow J cc=False 0x3117 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3117 0x3117 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3110 3110 fiu_mem_start 4 continue; Flow J cc=True 0x3113 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3113 0x3113 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3111 3111 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3112 3112 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3115 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3115 0x3115 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3113 3113 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3114 3114 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3115 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3115 0x3115 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3115 3115 fiu_load_tar 1 hold_tar; Flow C cc=False 0x326e fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3116 3116 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326e ioc_tvbs 3 fiu+fiu seq_br_type 8 Return True seq_branch_adr 326e 0x326e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3117 3117 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3118 3118 fiu_mem_start 2 start-rd; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3119 3119 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3278 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3278 0x3278 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 311a 311a fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x3278 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3278 0x3278 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 311b 311b <halt> ; Flow R 311c ; -------------------------------------------------------------------------------------- 311c ; 0x03fc Declare_Type InMicrocode,Discrete 311c ; -------------------------------------------------------------------------------------- 311c MACRO_Declare_Type_InMicrocode,Discrete: 311c 311c dispatch_brk_class 0 ; Flow C cc=False 0x32ac dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 311c fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 311d 311d ioc_fiubs 1 val ; Flow C cc=False 0x32aa ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 311e 311e fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x310f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 310f 0x310f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 311f 311f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3120 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3120 0x3120 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 3120 3120 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x32a9 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3121 3121 fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 3122 ; -------------------------------------------------------------------------------------- 3122 ; 0x03f7 Declare_Type InMicrocode,Discrete 3122 ; -------------------------------------------------------------------------------------- 3122 MACRO_Declare_Type_InMicrocode,Discrete: 3122 3122 dispatch_brk_class 0 ; Flow C cc=False 0x32ac dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3122 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 3123 3123 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3124 3124 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x310f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 310f 0x310f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 3125 3125 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3120 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3120 0x3120 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 3126 3126 fiu_mem_start 4 continue; Flow J 0x3129 seq_br_type 3 Unconditional Branch seq_branch_adr 3129 0x3129 typ_a_adr 24 TR09:04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 3127 3127 <halt> ; Flow R 3128 ; -------------------------------------------------------------------------------------- 3128 ; 0x03f5 Declare_Variable Discrete,Incomplete 3128 ; -------------------------------------------------------------------------------------- 3128 MACRO_Declare_Variable_Discrete,Incomplete: 3128 3128 dispatch_brk_class 4 ; Flow J 0x312b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3128 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312b 0x312b seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3129 3129 fiu_mem_start 4 continue; Flow J 0x312d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 312d 0x312d seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 312a ; -------------------------------------------------------------------------------------- 312a ; 0x03f2 Declare_Variable Discrete,Incomplete,Unsigned 312a ; -------------------------------------------------------------------------------------- 312a MACRO_Declare_Variable_Discrete,Incomplete,Unsigned: 312a 312a dispatch_brk_class 4 ; Flow J 0x312b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 312a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312b 0x312b seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 312b 312b fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3126 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3126 0x3126 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 312c ; -------------------------------------------------------------------------------------- 312c ; 0x03f6 Declare_Variable Discrete,Incomplete,Visible 312c ; -------------------------------------------------------------------------------------- 312c MACRO_Declare_Variable_Discrete,Incomplete,Visible: 312c 312c dispatch_brk_class 4 ; Flow J 0x312f dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 312c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312f 0x312f seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 312d 312d fiu_tivi_src 4 fiu_var; Flow J 0x30e9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e9 0x30e9 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_b_adr 30 VR02:10 val_frame 2 312e ; -------------------------------------------------------------------------------------- 312e ; 0x03f3 Declare_Variable Discrete,Incomplete,Visible,Unsigned 312e ; -------------------------------------------------------------------------------------- 312e MACRO_Declare_Variable_Discrete,Incomplete,Visible,Unsigned: 312e 312e dispatch_brk_class 4 ; Flow J 0x312f dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 312e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312f 0x312f seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 312f 312f fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3130 3130 fiu_mem_start 4 continue; Flow J 0x3131 seq_br_type 2 Push (branch address) seq_branch_adr 32aa 0x32aa typ_a_adr 21 TR08:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 3131 3131 fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x312d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 9 Return False seq_branch_adr 312d 0x312d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 3132 ; -------------------------------------------------------------------------------------- 3132 ; 0x03ef Complete_Type Discrete,By_Defining 3132 ; -------------------------------------------------------------------------------------- 3132 MACRO_Complete_Type_Discrete,By_Defining: 3132 3132 dispatch_brk_class 4 ; Flow J 0x3133 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3132 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32a7 0x32a7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3133 3133 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3139 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3139 0x3139 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 5 COUNT_ZEROS 3134 3134 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x313a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 313a 0x313a seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 1f TOP - 1 val_a_adr 15 ZERO_COUNTER val_b_adr 1f TOP - 1 3135 3135 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3137 seq_br_type 0 Branch False seq_branch_adr 3137 0x3137 val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 3136 3136 val_alu_func 15 NOT_B val_b_adr 1d TOP - 3 val_rand 5 COUNT_ZEROS 3137 3137 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3138 3138 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x313b ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 313b 0x313b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3139 3139 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x313b ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 313b 0x313b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 28 VR06:08 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 313a 313a fiu_mem_start 2 start-rd; Flow C cc=True 0x32a7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 2a VR06:0a val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 313b 313b ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_rand 8 SPARE_0x08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 313c 313c fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x32a9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 313d 313d fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 24 TR09:04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR 313e 313e fiu_mem_start 4 continue; Flow J 0x313f ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 313f 0x313f typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 313f 313f fiu_tivi_src 4 fiu_var; Flow J 0x3165 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3165 0x3165 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3140 ; -------------------------------------------------------------------------------------- 3140 ; 0x03ee Complete_Type Discrete,By_Renaming 3140 ; -------------------------------------------------------------------------------------- 3140 MACRO_Complete_Type_Discrete,By_Renaming: 3140 3140 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3140 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3141 3141 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3142 3142 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 3143 3143 fiu_load_var 1 hold_var; Flow C cc=True 0x3279 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3144 3144 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3145 3145 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3146 3146 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B 3147 3147 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 02 GP02 typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 3148 3148 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x3279 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 3149 3149 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 314a 314a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 314b 314b ioc_load_wdr 0 ; Flow J 0x3165 seq_br_type 3 Unconditional Branch seq_branch_adr 3165 0x3165 typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 314c ; -------------------------------------------------------------------------------------- 314c ; 0x03ed Complete_Type Discrete,By_Constraining 314c ; -------------------------------------------------------------------------------------- 314c MACRO_Complete_Type_Discrete,By_Constraining: 314c 314c dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 314c fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 314d 314d fiu_load_tar 1 hold_tar; Flow J cc=True 0x315a fiu_tivi_src 8 type_var ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 315a 0x315a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 314e 314e fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 314f 314f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3152 seq_br_type 1 Branch True seq_branch_adr 3152 0x3152 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3150 3150 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3153 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3153 0x3153 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3151 3151 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3154 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3154 0x3154 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3152 3152 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 01 GP01 val_rand 5 COUNT_ZEROS 3153 3153 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3154 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3154 0x3154 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3154 3154 fiu_mem_start 4 continue; Flow C cc=False 0x32a9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1d TOP - 3 3155 3155 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3279 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS 3156 3156 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3157 3157 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3158 3158 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3159 3159 fiu_mem_start 4 continue; Flow J 0x313f ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 313f 0x313f typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 315a 315a fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 315b 315b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 315c 315c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 315d 315d fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 28 VR06:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 315e 315e ioc_fiubs 1 val ; Flow J 0x315f ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3157 0x3157 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 315f 315f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3279 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 3160 3160 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3278 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3278 0x3278 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3161 3161 <halt> ; Flow R 3162 ; -------------------------------------------------------------------------------------- 3162 ; 0x03ea Declare_Variable Discrete,Visible 3162 ; -------------------------------------------------------------------------------------- 3162 MACRO_Declare_Variable_Discrete,Visible: 3162 3162 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3162 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3163 3163 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3164 ; -------------------------------------------------------------------------------------- 3164 ; 0x03eb Declare_Variable Discrete 3164 ; -------------------------------------------------------------------------------------- 3164 MACRO_Declare_Variable_Discrete: 3164 3164 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3164 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3165 3165 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3166 ; -------------------------------------------------------------------------------------- 3166 ; 0x03e9 Declare_Variable Discrete,Duplicate 3166 ; -------------------------------------------------------------------------------------- 3166 MACRO_Declare_Variable_Discrete,Duplicate: 3166 3166 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3166 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3167 ; -------------------------------------------------------------------------------------- 3167 ; Comes from: 3167 ; 3178 C from color MACRO_Execute_Immediate_Set_Value,uimmediate 3167 ; -------------------------------------------------------------------------------------- 3167 3167 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3168 ; -------------------------------------------------------------------------------------- 3168 ; 0x0600-0x06ff Execute_Immediate Set_Value_Unchecked,uimmediate 3168 ; -------------------------------------------------------------------------------------- 3168 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 3168 3168 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_uadr 3168 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 3169 ; -------------------------------------------------------------------------------------- 3169 ; Comes from: 3169 ; 316a C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 3169 ; -------------------------------------------------------------------------------------- 3169 3169 seq_br_type a Unconditional Return; Flow R typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 316a ; -------------------------------------------------------------------------------------- 316a ; 0x0700-0x07ff Execute_Immediate Set_Value,uimmediate 316a ; -------------------------------------------------------------------------------------- 316a MACRO_Execute_Immediate_Set_Value,uimmediate: 316a 316a dispatch_brk_class 4 ; Flow C cc=True 0x3169 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 316a dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3169 0x3169 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 316b 316b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316c 0x316c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 316c 316c fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 316d 316d fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3279 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 316e 316e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326e seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 316f 316f seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 3170 ; -------------------------------------------------------------------------------------- 3170 ; 0x0400-0x04ff Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 3170 ; -------------------------------------------------------------------------------------- 3170 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 3170 3170 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_uadr 3170 ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 3171 3171 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 3172 ; -------------------------------------------------------------------------------------- 3172 ; 0x0500-0x05ff Execute_Immediate Set_Value_Visible,uimmediate 3172 ; -------------------------------------------------------------------------------------- 3172 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 3172 3172 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3172 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 3173 3173 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3179 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3179 0x3179 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 3174 ; -------------------------------------------------------------------------------------- 3174 ; 0x03ec Declare_Variable Discrete,With_Value,With_Constraint 3174 ; -------------------------------------------------------------------------------------- 3174 MACRO_Declare_Variable_Discrete,With_Value,With_Constraint: 3174 3174 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3174 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3175 3175 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x316c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316c 0x316c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3176 ; -------------------------------------------------------------------------------------- 3176 ; 0x03f1 Declare_Variable Discrete,With_Value 3176 ; -------------------------------------------------------------------------------------- 3176 MACRO_Declare_Variable_Discrete,With_Value: 3176 3176 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3176 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3177 0x3177 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 3177 3177 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 3178 ; -------------------------------------------------------------------------------------- 3178 ; 0x03e8 Declare_Variable Discrete,Visible,With_Value,With_Constraint 3178 ; -------------------------------------------------------------------------------------- 3178 MACRO_Declare_Variable_Discrete,Visible,With_Value,With_Constraint: 3178 3178 dispatch_brk_class 4 ; Flow C 0x3167 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3178 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3167 0x3167 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3179 3179 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x316c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316c 0x316c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 317a ; -------------------------------------------------------------------------------------- 317a ; 0x03f0 Declare_Variable Discrete,Visible,With_Value 317a ; -------------------------------------------------------------------------------------- 317a MACRO_Declare_Variable_Discrete,Visible,With_Value: 317a 317a dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 317a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 317b 317b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 317c ; -------------------------------------------------------------------------------------- 317c ; 0x03ad Declare_Type Heap_Access,Defined 317c ; -------------------------------------------------------------------------------------- 317c MACRO_Declare_Type_Heap_Access,Defined: 317c 317c dispatch_brk_class 4 ; Flow J cc=False 0x3181 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 317c fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3181 0x3181 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 317d 317d seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 317e ; -------------------------------------------------------------------------------------- 317e ; 0x03ae Declare_Type Heap_Access,Defined,Visible 317e ; -------------------------------------------------------------------------------------- 317e MACRO_Declare_Type_Heap_Access,Defined,Visible: 317e 317e dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 317e seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 317f 317f fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3181 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3181 0x3181 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3a VR07:1a val_frame 7 3180 3180 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 3181 3181 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 29 VR06:09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 3182 3182 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c 3183 3183 ioc_adrbs 2 typ ; Flow C cc=#0x0 0x318a seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 318a 0x318a seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 3184 3184 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 38 TR11:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3185 3185 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 10 TOP 3186 3186 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 3187 3187 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 39 VR02:19 val_frame 2 3188 3188 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 3189 3189 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 318a ; -------------------------------------------------------------------------------------- 318a ; Comes from: 318a ; 3183 C #0x0 from color MACRO_Declare_Type_Heap_Access,Defined 318a ; -------------------------------------------------------------------------------------- 318a 318a seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x3190 seq_br_type 9 Return False seq_branch_adr 3190 0x3190 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318b 318b seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x3190 seq_br_type 9 Return False seq_branch_adr 3190 0x3190 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318c 318c seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x3190 seq_br_type 9 Return False seq_branch_adr 3190 0x3190 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318d 318d seq_br_type 3 Unconditional Branch; Flow J 0x318e seq_branch_adr 318e 0x318e typ_c_adr 3b GP04 318e 318e seq_br_type 4 Call False; Flow C cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 318f 318f seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 3190 0x3190 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 3190 3190 seq_br_type a Unconditional Return; Flow R typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 3191 3191 <halt> ; Flow R 3192 ; -------------------------------------------------------------------------------------- 3192 ; 0x03a8 Declare_Type Heap_Access,Incomplete 3192 ; -------------------------------------------------------------------------------------- 3192 MACRO_Declare_Type_Heap_Access,Incomplete: 3192 3192 dispatch_brk_class 4 ; Flow J 0x3193 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3192 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3193 0x3193 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3193 3193 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x31a0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 31a0 0x31a0 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR06:09 val_frame 6 3194 ; -------------------------------------------------------------------------------------- 3194 ; 0x03a9 Declare_Type Heap_Access,Incomplete,Visible 3194 ; -------------------------------------------------------------------------------------- 3194 MACRO_Declare_Type_Heap_Access,Incomplete,Visible: 3194 3194 dispatch_brk_class 4 ; Flow J cc=True 0x3193 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3194 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3193 0x3193 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3195 3195 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 3196 ; -------------------------------------------------------------------------------------- 3196 ; 0x03a5 Declare_Type Heap_Access,Incomplete,Values_Relative 3196 ; -------------------------------------------------------------------------------------- 3196 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative: 3196 3196 dispatch_brk_class 4 ; Flow J 0x3197 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3196 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3197 0x3197 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3197 3197 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x31a0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 31a0 0x31a0 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR11:11 val_frame 11 3198 ; -------------------------------------------------------------------------------------- 3198 ; 0x03a6 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative 3198 ; -------------------------------------------------------------------------------------- 3198 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative: 3198 3198 dispatch_brk_class 4 ; Flow J cc=True 0x3197 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3198 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3197 0x3197 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3199 3199 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 319a ; -------------------------------------------------------------------------------------- 319a ; 0x03a4 Declare_Type Heap_Access,Incomplete,Values_Relative,With_Size 319a ; -------------------------------------------------------------------------------------- 319a MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative,With_Size: 319a 319a dispatch_brk_class 4 ; Flow J 0x319b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 319a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 319b 0x319b typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 319b 319b fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 319c 319c fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x31a0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_br_type 1 Branch True seq_branch_adr 31a0 0x31a0 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 319d 319d seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 319e ; -------------------------------------------------------------------------------------- 319e ; 0x03a7 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative,With_Size 319e ; -------------------------------------------------------------------------------------- 319e MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative,With_Size: 319e 319e dispatch_brk_class 4 ; Flow J cc=True 0x319b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 319e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 319b 0x319b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 319f 319f seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 31a0 31a0 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 3b TR02:1b typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 31a1 31a1 fiu_mem_start 4 continue ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 31a2 31a2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 2c TR07:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 31a3 31a3 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 31a4 31a4 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 31a5 31a5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 31a6 ; -------------------------------------------------------------------------------------- 31a6 ; Comes from: 31a6 ; 31b0 C False from color 0x0000 31a6 ; 31c4 C False from color 0x0000 31a6 ; 31d9 C False from color MACRO_Execute_Discrete,Remainder 31a6 ; 31e7 C False from color MACRO_Execute_Discrete,Remainder 31a6 ; 31f8 C False from color MACRO_Execute_Discrete,Remainder 31a6 ; 3204 C False from color MACRO_Execute_Discrete,Remainder 31a6 ; -------------------------------------------------------------------------------------- 31a6 31a6 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x31a6 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31a7 31a7 <halt> ; Flow R 31a8 ; -------------------------------------------------------------------------------------- 31a8 ; 0x0270 Execute Discrete,Divide 31a8 ; -------------------------------------------------------------------------------------- 31a8 MACRO_Execute_Discrete,Divide: 31a8 31a8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31a8 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31a9 31a9 fiu_load_var 1 hold_var; Flow J cc=True 0x31b8 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31b8 0x31b8 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31aa 31aa fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31b3 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31b3 0x31b3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31ab 31ab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31ad fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31ad 0x31ad seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31ac 31ac fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 31ad 31ad ioc_fiubs 1 val ; Flow J cc=False 0x31b0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31b0 0x31b0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31ae 31ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31af 31af fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31b0 31b0 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31a6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31b1 31b1 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31b2 31b2 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31b3 31b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b4 31b4 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31b5 31b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31ad fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31ad 0x31ad seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31b6 31b6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 31b7 31b7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 30 VR02:10 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 31b8 31b8 fiu_vmux_sel 1 fill value; Flow J cc=True 0x31bc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31bc 0x31bc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b9 31b9 fiu_load_var 1 hold_var; Flow J cc=True 0x31b4 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31b4 0x31b4 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ba 31ba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31bb 31bb fiu_load_oreg 1 hold_oreg; Flow J 0x31ab fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 31ab 0x31ab seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31bc 31bc fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 31bd 0x31bd seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31bd 31bd seq_br_type 7 Unconditional Call; Flow C 0x3278 seq_branch_adr 3278 0x3278 seq_en_micro 0 seq_random 02 ? 31be ; -------------------------------------------------------------------------------------- 31be ; 0x0140 Execute Discrete,Divide_And_Scale 31be ; -------------------------------------------------------------------------------------- 31be MACRO_Execute_Discrete,Divide_And_Scale: 31be 31be dispatch_brk_class 8 ; Flow C cc=False 0x31c7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 31be fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 31c7 0x31c7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31bf 31bf fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31c9 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 31c9 0x31c9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31c0 31c0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 31c1 31c1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER 31c2 31c2 ioc_fiubs 0 fiu ; Flow J cc=True 0x31cb seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31cb 0x31cb seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 31c3 31c3 fiu_load_var 1 hold_var; Flow J cc=True 0x31cf fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31cf 0x31cf seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_frame 2 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 31c4 31c4 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31a6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31c5 31c5 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31ce fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31ce 0x31ce seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 31c6 31c6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3278 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3278 0x3278 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31c7 ; -------------------------------------------------------------------------------------- 31c7 ; Comes from: 31c7 ; 31be C False from color 0x0000 31c7 ; -------------------------------------------------------------------------------------- 31c7 31c7 seq_br_type 4 Call False; Flow C cc=False 0x3277 seq_branch_adr 3277 0x3277 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31c8 31c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA val_b_adr 01 GP01 31c9 ; -------------------------------------------------------------------------------------- 31c9 ; Comes from: 31c9 ; 31bf C False from color 0x0000 31c9 ; -------------------------------------------------------------------------------------- 31c9 31c9 seq_br_type 1 Branch True; Flow J cc=True 0x31c8 seq_branch_adr 31c8 0x31c8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ca 31ca fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31cb 31cb fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 31cc 31cc fiu_fill_mode_src 0 ; Flow J cc=True 0x31cf fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31cf 0x31cf seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 31cd 31cd fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31c6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31c6 0x31c6 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 31ce 31ce fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3278 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3278 0x3278 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31cf 31cf fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3278 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3278 0x3278 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31d0 ; -------------------------------------------------------------------------------------- 31d0 ; 0x026f Execute Discrete,Remainder 31d0 ; -------------------------------------------------------------------------------------- 31d0 MACRO_Execute_Discrete,Remainder: 31d0 31d0 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31d0 ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d1 31d1 fiu_load_var 1 hold_var; Flow J cc=False 0x31df fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31df 0x31df seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d2 31d2 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31d5 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d5 0x31d5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31d3 31d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d4 31d4 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31d5 31d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31d8 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d8 0x31d8 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31d6 31d6 seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 31d7 31d7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31d8 31d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x31de seq_br_type 1 Branch True seq_branch_adr 31de 0x31de seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31d9 31d9 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31da 31da ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31db 31db fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31dd fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31dd 0x31dd seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31dc 31dc fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 31dd 31dd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31de 31de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31df 31df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x320a seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e0 31e0 fiu_load_var 1 hold_var; Flow J cc=True 0x31e2 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e2 0x31e2 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e1 31e1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e2 31e2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31e3 31e3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31e6 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e6 0x31e6 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31e4 31e4 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 31e5 0x31e5 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 31e5 31e5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 31e6 31e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x31ec seq_br_type 1 Branch True seq_branch_adr 31ec 0x31ec seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31e7 31e7 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31e8 31e8 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31e9 31e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31eb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31eb 0x31eb seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31ea 31ea fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 31eb 31eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ec 31ec val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31ed 31ed fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ee ; -------------------------------------------------------------------------------------- 31ee ; 0x026e Execute Discrete,Modulo 31ee ; -------------------------------------------------------------------------------------- 31ee MACRO_Execute_Discrete,Modulo: 31ee 31ee dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31ee ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ef 31ef fiu_load_var 1 hold_var; Flow J cc=False 0x31fd fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31fd 0x31fd seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31f0 31f0 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31d5 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d5 0x31d5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31f1 31f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31f2 31f2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31f3 31f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31f7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31f7 0x31f7 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31f4 31f4 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 31f5 31f5 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 31f6 0x31f6 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31f6 31f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 31f7 31f7 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31f8 31f8 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31f9 31f9 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x320a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31fa 31fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31fc fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31fc 0x31fc seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31fb 31fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x320a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 31fc 31fc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31fd 31fd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x320a seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31fe 31fe fiu_load_var 1 hold_var; Flow J cc=False 0x31e1 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31e1 0x31e1 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ff 31ff fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3200 3200 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3203 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3203 0x3203 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 3201 3201 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3202 0x3202 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3202 3202 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 3203 3203 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3209 seq_br_type 1 Branch True seq_branch_adr 3209 0x3209 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3204 3204 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a6 0x31a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 3205 3205 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x320a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 3206 3206 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3208 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3208 0x3208 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3207 3207 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x320a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 320a 0x320a seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 3208 3208 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3209 3209 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 320a 320a fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 320b 0x320b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 320b 320b seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 seq_random 02 ? 320c ; -------------------------------------------------------------------------------------- 320c ; 0x7800-0x7fff Jump pcrel,>J 320c ; -------------------------------------------------------------------------------------- 320c MACRO_Jump_pcrel,>J: 320c 320c dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 320c 320d 320d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x321c seq_br_type 3 Unconditional Branch seq_branch_adr 321c 0x321c seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? 320e ; -------------------------------------------------------------------------------------- 320e ; 0x7000-0x77ff Jump_Nonzero pcrel,>JC 320e ; -------------------------------------------------------------------------------------- 320e MACRO_Jump_Nonzero_pcrel,>JC: 320e 320e dispatch_brk_class 1 ; Flow J 0x3211 dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 320e seq_br_type 3 Unconditional Branch seq_branch_adr 3211 0x3211 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 320f 320f <halt> ; Flow R 3210 ; -------------------------------------------------------------------------------------- 3210 ; 0x6800-0x6fff Jump_Zero pcrel,>JC 3210 ; -------------------------------------------------------------------------------------- 3210 MACRO_Jump_Zero_pcrel,>JC: 3210 3210 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 3210 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 3211 3211 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3212 0x3212 seq_int_reads 0 TYP VAL BUS seq_random 40 Load_ibuff+Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3212 3212 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3213 0x3213 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 3213 3213 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3214 ; -------------------------------------------------------------------------------------- 3214 ; 0x4600-0x47ff Jump_Case case_max 3214 ; -------------------------------------------------------------------------------------- 3214 MACRO_Jump_Case_case_max: 3214 3214 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_uadr 3214 fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3d VR02:1d val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 3215 3215 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3216 3216 fiu_tivi_src c mar_0xc; Flow J cc=False 0x321b ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 321b 0x321b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3217 3217 ioc_tvbs 1 typ+fiu; Flow C 0x326f seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 2 PUSH_CSA 3218 ; -------------------------------------------------------------------------------------- 3218 ; 0x00a7 Action Jump_Extended,abs,>J 3218 ; -------------------------------------------------------------------------------------- 3218 MACRO_Action_Jump_Extended,abs,>J: 3218 3218 dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3218 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3219 3219 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 321a 321a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? 321b 321b ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 321c 321c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 321d 321d <halt> ; Flow R 321e ; -------------------------------------------------------------------------------------- 321e ; 0x00a5 Action Jump_Nonzero_Extended,abs,>JC 321e ; -------------------------------------------------------------------------------------- 321e MACRO_Action_Jump_Nonzero_Extended,abs,>JC: 321e 321e dispatch_brk_class 1 ; Flow J 0x3221 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 321e fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3221 0x3221 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 321f 321f <halt> ; Flow R 3220 ; -------------------------------------------------------------------------------------- 3220 ; 0x00a6 Action Jump_Zero_Extended,abs,>JC 3220 ; -------------------------------------------------------------------------------------- 3220 MACRO_Action_Jump_Zero_Extended,abs,>JC: 3220 3220 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3220 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 3221 3221 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3219 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3219 0x3219 seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3222 3222 seq_br_type 1 Branch True; Flow J cc=True 0x321b seq_branch_adr 321b 0x321b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 16 ? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 3223 3223 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3224 ; -------------------------------------------------------------------------------------- 3224 ; 0x009f Action Jump_Dynamic 3224 ; -------------------------------------------------------------------------------------- 3224 MACRO_Action_Jump_Dynamic: 3224 3224 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3224 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 3225 3225 fiu_tivi_src c mar_0xc; Flow J 0x321b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 321b 0x321b seq_int_reads 0 TYP VAL BUS seq_random 59 ? 3226 ; -------------------------------------------------------------------------------------- 3226 ; 0x009d Action Jump_Nonzero_Dynamic 3226 ; -------------------------------------------------------------------------------------- 3226 MACRO_Action_Jump_Nonzero_Dynamic: 3226 3226 dispatch_brk_class 1 ; Flow J cc=False 0x322b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3226 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 322b 0x322b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3227 3227 fiu_tivi_src c mar_0xc; Flow J cc=True 0x321b ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 321b 0x321b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 3228 3228 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3229 3229 <halt> ; Flow R 322a ; -------------------------------------------------------------------------------------- 322a ; 0x009e Action Jump_Zero_Dynamic 322a ; -------------------------------------------------------------------------------------- 322a MACRO_Action_Jump_Zero_Dynamic: 322a 322a dispatch_brk_class 1 ; Flow J cc=True 0x3227 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 322a fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3227 0x3227 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 322b 322b fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3228 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3228 0x3228 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 322c ; -------------------------------------------------------------------------------------- 322c ; 0x3e00-0x3fff Loop_Increasing pcrelneg,>JC 322c ; -------------------------------------------------------------------------------------- 322c MACRO_Loop_Increasing_pcrelneg,>JC: 322c 322c dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 322c fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 322d 322d fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x322f fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 322f 0x322f seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 322e 322e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 322f 322f fiu_tivi_src c mar_0xc; Flow J 0x321b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 321b 0x321b seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 3230 ; -------------------------------------------------------------------------------------- 3230 ; 0x3600-0x37ff Loop_Decreasing pcrelneg,>JC 3230 ; -------------------------------------------------------------------------------------- 3230 MACRO_Loop_Decreasing_pcrelneg,>JC: 3230 3230 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 3230 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3231 3231 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3233 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3233 0x3233 seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 3232 3232 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3233 3233 fiu_tivi_src c mar_0xc; Flow J 0x321b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 321b 0x321b seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 3234 ; -------------------------------------------------------------------------------------- 3234 ; 0x00a4 Action Loop_Increasing_Extended,abs,>JC 3234 ; -------------------------------------------------------------------------------------- 3234 MACRO_Action_Loop_Increasing_Extended,abs,>JC: 3234 3234 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3234 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3235 3235 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3236 3236 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 3237 3237 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x322f fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 322f 0x322f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 3238 3238 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3239 3239 <halt> ; Flow R 323a ; -------------------------------------------------------------------------------------- 323a ; 0x00a3 Action Loop_Decreasing_Extended,abs,>JC 323a ; -------------------------------------------------------------------------------------- 323a MACRO_Action_Loop_Decreasing_Extended,abs,>JC: 323a 323a dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 323a ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 323b 323b fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 323c 323c fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 323d 323d fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3233 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3233 0x3233 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 323e 323e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 323f ; -------------------------------------------------------------------------------------- 323f ; Comes from: 323f ; 0a81 C from color 0x0a76 323f ; 0a95 C from color 0x0a8a 323f ; 0aa8 C from color 0x0a9e 323f ; 120b C from color 0x10c1 323f ; 120f C from color 0x10d6 323f ; 122c C from color 0x1201 323f ; 1439 C from color 0x09ac 323f ; 14f1 C from color 0x14f1 323f ; 169e C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 323f ; 1745 C from color 0x09ae 323f ; 17a3 C from color 0x0a32 323f ; 17b1 C from color 0x0a7c 323f ; 17b5 C from color 0x0a90 323f ; 17b9 C from color MACRO_Execute_Variant_Record,Check_In_Type 323f ; 17bf C from color 0x0aa4 323f ; 1817 C from color 0x1817 323f ; 181b C from color 0x09ab 323f ; 19bc C from color 0x19b9 323f ; 1ac3 C from color 0x0aa1 323f ; 1b45 C from color 0x09a8 323f ; 1bd3 C from color 0x0aa0 323f ; 1db3 C from color 0x1d39 323f ; 1e42 C False from color MACRO_Execute_Matrix,Structure_Write 323f ; 1e46 C False from color MACRO_Execute_Matrix,Structure_Write 323f ; 1e7b C from color 0x1e7b 323f ; 239e C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 323f ; 23b2 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 323f ; 248a C from color 0x248a 323f ; 2494 C from color 0x248a 323f ; -------------------------------------------------------------------------------------- 323f 323f seq_en_micro 0 typ_c_adr 36 GP09 3240 3240 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3279 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3241 3241 ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3242 0x3242 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3242 3242 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3243 3243 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3244 ; -------------------------------------------------------------------------------------- 3244 ; Comes from: 3244 ; 0503 C from color 0x04fa 3244 ; 1f75 C from color 0x1f6b 3244 ; 2202 C from color 0x21f8 3244 ; -------------------------------------------------------------------------------------- 3244 3244 seq_en_micro 0 typ_c_adr 36 GP09 3245 3245 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3249 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3249 0x3249 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3246 3246 ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3247 0x3247 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3247 3247 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3249 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3249 0x3249 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3248 3248 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3249 3249 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3279 seq_br_type 9 Return False seq_branch_adr 3279 0x3279 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0c GP0c 324a ; -------------------------------------------------------------------------------------- 324a ; 0x0001-0x0006 Illegal - 324a ; 0x0009-0x000f Illegal - 324a ; -------------------------------------------------------------------------------------- 324a MACRO_Illegal_-: 324a 324a dispatch_brk_class f ; Flow C 0x32ad dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 324a seq_br_type 7 Unconditional Call seq_branch_adr 32ad 0x32ad 324b 324b <halt> ; Flow R 324c ; -------------------------------------------------------------------------------------- 324c ; 0x0007 Action Break_Optional 324c ; -------------------------------------------------------------------------------------- 324c MACRO_Action_Break_Optional: 324c 324c dispatch_brk_class 7 ; Flow R dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 324c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 324d 324d <halt> ; Flow R 324e ; -------------------------------------------------------------------------------------- 324e ; 0x0107 Execute Exception,Get_Name 324e ; -------------------------------------------------------------------------------------- 324e MACRO_Execute_Exception,Get_Name: 324e 324e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 324e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 1c ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 324f 324f <halt> ; Flow R 3250 ; -------------------------------------------------------------------------------------- 3250 ; 0x0106 Execute Exception,Address 3250 ; -------------------------------------------------------------------------------------- 3250 MACRO_Execute_Exception,Address: 3250 3250 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3250 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3251 3251 fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value val_alu_func 1e A_AND_B val_b_adr 37 VR0d:17 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame d 3252 3252 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3253 3253 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3255 seq_br_type 1 Branch True seq_branch_adr 3255 0x3255 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3254 3254 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 3255 3255 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3256 ; -------------------------------------------------------------------------------------- 3256 ; 0x010e Execute Exception,Is_Constraint_Error 3256 ; -------------------------------------------------------------------------------------- 3256 MACRO_Execute_Exception,Is_Constraint_Error: 3256 3256 dispatch_brk_class 8 ; Flow J 0x3257 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3256 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3254 0x3254 typ_alu_func 1a PASS_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2d VR1b:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 1b 3257 3257 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3253 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3253 0x3253 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2c VR08:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3258 ; -------------------------------------------------------------------------------------- 3258 ; 0x010d Execute Exception,Is_Numeric_Error 3258 ; -------------------------------------------------------------------------------------- 3258 MACRO_Execute_Exception,Is_Numeric_Error: 3258 3258 dispatch_brk_class 8 ; Flow J 0x3259 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3258 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3254 0x3254 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 35 VR08:15 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 3259 3259 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3253 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3253 0x3253 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2d VR08:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325a ; -------------------------------------------------------------------------------------- 325a ; 0x010c Execute Exception,Is_Program_Error 325a ; -------------------------------------------------------------------------------------- 325a MACRO_Execute_Exception,Is_Program_Error: 325a 325a dispatch_brk_class 8 ; Flow J 0x325b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3254 0x3254 typ_alu_func 1a PASS_B typ_b_adr 30 TR11:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 325b 325b ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3253 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3253 0x3253 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2e VR08:0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325c ; -------------------------------------------------------------------------------------- 325c ; 0x010b Execute Exception,Is_Storage_Error 325c ; -------------------------------------------------------------------------------------- 325c MACRO_Execute_Exception,Is_Storage_Error: 325c 325c dispatch_brk_class 8 ; Flow J 0x325d dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3254 0x3254 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 36 VR08:16 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 325d 325d ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3253 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3253 0x3253 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2f VR08:0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325e ; -------------------------------------------------------------------------------------- 325e ; 0x010a Execute Exception,Is_Tasking_Error 325e ; -------------------------------------------------------------------------------------- 325e MACRO_Execute_Exception,Is_Tasking_Error: 325e 325e dispatch_brk_class 8 ; Flow J 0x325f dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3254 0x3254 typ_alu_func 1a PASS_B typ_b_adr 2d TR08:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 37 VR08:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 325f 325f ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3253 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3253 0x3253 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 30 VR08:10 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3260 ; -------------------------------------------------------------------------------------- 3260 ; 0x0109 Execute Exception,Is_Instruction_Error 3260 ; -------------------------------------------------------------------------------------- 3260 MACRO_Execute_Exception,Is_Instruction_Error: 3260 3260 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3260 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 3261 3261 ioc_fiubs 0 fiu ; Flow J 0x3253 seq_br_type 3 Unconditional Branch seq_branch_adr 3253 0x3253 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3262 ; -------------------------------------------------------------------------------------- 3262 ; 0x010f Execute Exception,Equal 3262 ; -------------------------------------------------------------------------------------- 3262 MACRO_Execute_Exception,Equal: 3262 3262 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3262 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 3263 3263 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 3264 ; -------------------------------------------------------------------------------------- 3264 ; 0x0257 Execute Discrete,Raise,>R 3264 ; -------------------------------------------------------------------------------------- 3264 MACRO_Execute_Discrete,Raise,>R: 3264 3264 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3264 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 3265 3265 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3266 3266 seq_br_type 7 Unconditional Call; Flow C 0x32c6 seq_branch_adr 32c6 0x32c6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 3267 3267 <halt> ; Flow R 3268 ; -------------------------------------------------------------------------------------- 3268 ; 0x0800-0x08ff Execute_Immediate Raise,uimmediate,>R 3268 ; -------------------------------------------------------------------------------------- 3268 MACRO_Execute_Immediate_Raise,uimmediate,>R: 3268 3268 dispatch_brk_class 1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 3268 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3269 3269 ioc_fiubs 1 val ; Flow C 0x32c6 seq_br_type 7 Unconditional Call seq_branch_adr 32c6 0x32c6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 326a ; -------------------------------------------------------------------------------------- 326a ; Comes from: 326a ; 3982 C from color 0x3976 326a ; -------------------------------------------------------------------------------------- 326a 326a fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 326b 326b ioc_fiubs 1 val ; Flow J 0x32c6 seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 326c ; -------------------------------------------------------------------------------------- 326c ; Comes from: 326c ; 0342 C from color MACRO_Action_Increase_Priority 326c ; 1d31 C from color 0x1d31 326c ; 1d33 C from color 0x1d33 326c ; -------------------------------------------------------------------------------------- 326c 326c fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR09:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 326d 326d fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 326e ; -------------------------------------------------------------------------------------- 326e ; Comes from: 326e ; 0328 C True from color MACRO_Action_Set_Priority 326e ; 090a C True from color 0x0905 326e ; 0e43 C False from color 0x0d36 326e ; 0e45 C False from color 0x0d36 326e ; 0e5b C True from color 0x0e5b 326e ; 0ee5 C True from color 0x0ee5 326e ; 112f C False from color 0x110f 326e ; 113a C False from color 0x110f 326e ; 113d C True from color 0x110f 326e ; 1d76 C from color 0x1d2a 326e ; 1d86 C True from color 0x1d2a 326e ; 1d87 C from color 0x1d2a 326e ; 2377 C True from color 0x2371 326e ; 2419 C True from color 0x2415 326e ; 2827 C from color 0x0a2b 326e ; 2940 C False from color MACRO_Action_Push_String_Extended,pse 326e ; 2ca0 C True from color MACRO_Execute_Select,Timed_Duration_Write 326e ; 2fcd C True from color MACRO_Execute_Any,Convert 326e ; 2fd3 C from color MACRO_Execute_Any,Convert 326e ; 2fd5 C True from color MACRO_Execute_Any,Convert 326e ; 2ff2 C False from color MACRO_Execute_Any,Convert 326e ; 304e C True from color MACRO_Execute_Any,Convert 326e ; 304f C True from color MACRO_Execute_Any,Convert 326e ; 3053 C True from color MACRO_Execute_Any,Convert 326e ; 3054 C True from color MACRO_Execute_Any,Convert 326e ; 3057 C from color MACRO_Execute_Any,Convert 326e ; 316e C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 326e ; 35d6 C False from color 0x35c7 326e ; 35db C False from color 0x35db 326e ; -------------------------------------------------------------------------------------- 326e 326e fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 326f ; -------------------------------------------------------------------------------------- 326f ; Comes from: 326f ; 3217 C from color MACRO_Execute_Discrete,Remainder 326f ; -------------------------------------------------------------------------------------- 326f 326f fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 3270 3270 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3271 ; -------------------------------------------------------------------------------------- 3271 ; Comes from: 3271 ; 0c20 C True from color MACRO_Execute_Heap_Access,Element_Type 3271 ; 0c30 C True from color MACRO_Execute_Heap_Access,All_Reference 3271 ; 1ae0 C True from color MACRO_Execute_Access,Element_Type 3271 ; 1af0 C True from color MACRO_Execute_Access,All_Reference 3271 ; -------------------------------------------------------------------------------------- 3271 3271 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 3272 ; -------------------------------------------------------------------------------------- 3272 ; Comes from: 3272 ; 0508 C from color 0x04fa 3272 ; 0c4e C from color 0x0a35 3272 ; 1147 C False from color 0x110f 3272 ; 1175 C True from color 0x111d 3272 ; 1179 C from color 0x111d 3272 ; 117c C True from color 0x111d 3272 ; 117d C True from color 0x111d 3272 ; 1195 C False from color 0x111d 3272 ; 11ba C from color 0x111d 3272 ; 11bf C False from color 0x111d 3272 ; 11c9 C False from color 0x111d 3272 ; 1214 C False from color 0x10d6 3272 ; 1218 C from color 0x10d6 3272 ; 1239 C True from color 0x1201 3272 ; 127c C False from color 0x10d6 3272 ; 12a7 C True from color 0x125f 3272 ; 12a8 C True from color 0x125f 3272 ; 1383 C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 1384 C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 13a9 C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 13aa C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 13ce C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 13cf C False from color MACRO_Declare_Variable_Array,With_Constraint 3272 ; 1419 C True from color 0x1411 3272 ; 141c C True from color 0x1411 3272 ; 142b C True from color 0x1411 3272 ; 14bb C from color 0x0aa2 3272 ; 1536 C True from color 0x1531 3272 ; 153d C True from color 0x1531 3272 ; 1546 C True from color 0x1531 3272 ; 154e C True from color 0x1531 3272 ; 15e9 C True from color MACRO_Execute_Matrix,Subarray 3272 ; 15ec C True from color MACRO_Execute_Matrix,Subarray 3272 ; 16b4 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 3272 ; 1713 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3272 ; 1714 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3272 ; 18b2 C True from color MACRO_Execute_Vector,Field_Read 3272 ; 18bb C from color MACRO_Execute_Vector,Field_Read 3272 ; 18c0 C True from color MACRO_Execute_Vector,Field_Read 3272 ; 18c2 C True from color MACRO_Execute_Vector,Field_Read 3272 ; 18e4 C from color MACRO_Execute_Vector,Field_Reference 3272 ; 18ee C False from color MACRO_Execute_Vector,Field_Reference 3272 ; 18f4 C False from color MACRO_Execute_Vector,Field_Reference 3272 ; 196d C False from color MACRO_Execute_Vector,Slice_Read 3272 ; 196e C True from color MACRO_Execute_Vector,Slice_Read 3272 ; 199c C False from color MACRO_Execute_Vector,Slice_Write 3272 ; 199d C True from color MACRO_Execute_Vector,Slice_Write 3272 ; 19ea C True from color MACRO_Execute_Vector,Catenate 3272 ; 1a5d C True from color 0x0a2f 3272 ; 1a9f C from color 0x0a2f 3272 ; 1abc C from color 0x0aa1 3272 ; 1abe C False from color 0x0aa1 3272 ; 1ac2 C from color 0x0aa1 3272 ; 1b0d C from color 0x0a33 3272 ; 1bc8 C from color 0x0aa0 3272 ; 1bcb C from color 0x0aa0 3272 ; 1bcf C from color 0x0aa0 3272 ; 1bd2 C from color 0x0aa0 3272 ; 1c8b C True from color MACRO_Execute_Array,Subarray 3272 ; 1d92 C from color 0x1d2a 3272 ; 1f7a C from color 0x1f6b 3272 ; 1f90 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1f94 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1faf C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1fb3 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1fb8 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1fc5 C False from color 0x1fc5 3272 ; 1ff2 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 1ff3 C True from color MACRO_Complete_Type_Array,By_Constraining 3272 ; 214b C True from color MACRO_Declare_Type_Array,Constrained 3272 ; 214f C True from color MACRO_Declare_Type_Array,Constrained 3272 ; 2154 C True from color MACRO_Declare_Type_Array,Constrained 3272 ; 2161 C True from color 0x2161 3272 ; 2191 C True from color MACRO_Declare_Type_Array,Constrained 3272 ; 2192 C True from color MACRO_Declare_Type_Array,Constrained 3272 ; 2207 C from color 0x21f8 3272 ; -------------------------------------------------------------------------------------- 3272 3272 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3273 ; -------------------------------------------------------------------------------------- 3273 ; Comes from: 3273 ; 190f C True from color MACRO_Execute_Vector,And 3273 ; 19a2 C True from color MACRO_Execute_Vector,Slice_Write 3273 ; 19b1 C True from color MACRO_Execute_Vector,Slice_Write 3273 ; 19b5 C True from color MACRO_Execute_Vector,Slice_Write 3273 ; 19c5 C True from color MACRO_Execute_Vector,Slice_Reference 3273 ; 19c7 C True from color MACRO_Execute_Vector,Slice_Reference 3273 ; 1e47 C False from color MACRO_Execute_Matrix,Structure_Write 3273 ; 1e48 C False from color MACRO_Execute_Matrix,Structure_Write 3273 ; -------------------------------------------------------------------------------------- 3273 3273 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3274 ; -------------------------------------------------------------------------------------- 3274 ; Comes from: 3274 ; 0c4d C True from color 0x0a35 3274 ; 116e C from color 0x116b 3274 ; 1320 C True from color 0x1316 3274 ; 17a1 C False from color 0x0a32 3274 ; 17bc C from color MACRO_Execute_Variant_Record,Check_In_Type 3274 ; 17c1 C True from color 0x0aa4 3274 ; 1b0c C True from color 0x0a33 3274 ; 1d91 C True from color 0x1d2a 3274 ; 24f8 C from color 0x248a 3274 ; -------------------------------------------------------------------------------------- 3274 3274 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3275 ; -------------------------------------------------------------------------------------- 3275 ; Comes from: 3275 ; 1146 C True from color 0x110f 3275 ; 12e0 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3275 ; 12e2 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3275 ; -------------------------------------------------------------------------------------- 3275 3275 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR05:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3276 ; -------------------------------------------------------------------------------------- 3276 ; Comes from: 3276 ; 2c7d C False from color MACRO_Execute_Select,Member_Write,fieldnum 3276 ; 2c80 C True from color MACRO_Execute_Select,Member_Write,fieldnum 3276 ; 2c83 C False from color 0x2c82 3276 ; 2c89 C True from color MACRO_Execute_Select,Member_Write,fieldnum 3276 ; 2c8d C from color MACRO_Execute_Select,Member_Write,fieldnum 3276 ; 2c90 C from color MACRO_Execute_Select,Member_Write,fieldnum 3276 ; 3825 C True from color 0x3803 3276 ; -------------------------------------------------------------------------------------- 3276 3276 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3277 ; -------------------------------------------------------------------------------------- 3277 ; Comes from: 3277 ; 28b0 C True from color MACRO_Execute_Float,Exponentiate 3277 ; 31c7 C False from color 0x31c7 3277 ; 31d3 C True from color MACRO_Execute_Discrete,Remainder 3277 ; 31e1 C True from color MACRO_Execute_Discrete,Remainder 3277 ; 31f1 C True from color MACRO_Execute_Discrete,Remainder 3277 ; 320b C from color MACRO_Execute_Discrete,Remainder 3277 ; -------------------------------------------------------------------------------------- 3277 3277 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3278 ; -------------------------------------------------------------------------------------- 3278 ; Comes from: 3278 ; 1130 C from color 0x110f 3278 ; 113b C from color 0x110f 3278 ; 113c C True from color 0x110f 3278 ; 113e C from color 0x110f 3278 ; 201c C False from color 0x2012 3278 ; 201d C False from color 0x2012 3278 ; 2037 C False from color 0x2012 3278 ; 2038 C False from color 0x2012 3278 ; 204f C False from color 0x2012 3278 ; 2050 C False from color 0x2012 3278 ; 208a C False from color 0x2012 3278 ; 208b C False from color 0x2012 3278 ; 20c0 C False from color 0x2012 3278 ; 20c1 C False from color 0x2012 3278 ; 20d5 C False from color 0x2012 3278 ; 20f5 C False from color 0x2012 3278 ; 20f6 C False from color 0x2012 3278 ; 27e5 C False from color 0x27e5 3278 ; 2832 C True from color 0x0a2b 3278 ; 2882 C True from color MACRO_Execute_Float,Times 3278 ; 28a9 C from color MACRO_Execute_Float,Exponentiate 3278 ; 28bc C True from color MACRO_Execute_Float,Exponentiate 3278 ; 28bd C True from color MACRO_Execute_Float,Exponentiate 3278 ; 28c2 C False from color MACRO_Execute_Float,Exponentiate 3278 ; 28cc C True from color MACRO_Execute_Float,Exponentiate 3278 ; 28e3 C from color MACRO_Execute_Float,Truncate_To_Discrete 3278 ; 2fb9 C from color MACRO_Execute_Discrete,Unary_Minus 3278 ; 2fbd C from color MACRO_Execute_Discrete,Plus 3278 ; 2fbf C from color MACRO_Execute_Discrete,Plus 3278 ; 2fc1 C from color MACRO_Execute_Discrete,Plus 3278 ; 2fc3 C from color MACRO_Execute_Discrete,Plus 3278 ; 2ff3 C from color MACRO_Execute_Any,Convert 3278 ; 316f C from color MACRO_Execute_Immediate_Set_Value,uimmediate 3278 ; -------------------------------------------------------------------------------------- 3278 3278 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR07:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3279 ; -------------------------------------------------------------------------------------- 3279 ; Comes from: 3279 ; 0221 C False from color MACRO_Action_Accept_Activation 3279 ; 0224 C False from color MACRO_Action_Accept_Activation 3279 ; 09d0 C from color MACRO_Execute_Any,Size 3279 ; 09d4 C from color MACRO_Execute_Any,Size 3279 ; 09e5 C True from color MACRO_Execute_Any,Size 3279 ; 0a18 C True from color MACRO_Execute_Any,Make_Root_Type 3279 ; 0a1d C True from color MACRO_Execute_Any,Make_Root_Type 3279 ; 0a6e C True from color 0x0a50 3279 ; 0c12 C True from color 0x0c07 3279 ; 109f C from color 0x1099 3279 ; 10a6 C from color 0x1099 3279 ; 119d C True from color 0x119a 3279 ; 11cc C True from color 0x111d 3279 ; 12cc C True from color 0x098c 3279 ; 12da C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3279 ; 1312 C True from color MACRO_Declare_Variable_Variant_Record,Duplicate 3279 ; 1394 C True from color MACRO_Declare_Variable_Array,With_Constraint 3279 ; 13b7 C True from color MACRO_Declare_Variable_Array,With_Constraint 3279 ; 1436 C False from color MACRO_Declare_Variable_Array,With_Constraint 3279 ; 144b C True from color 0x09ac 3279 ; 145f C True from color 0x09ac 3279 ; 17ac C True from color 0x17ab 3279 ; 17ae C True from color 0x17ab 3279 ; 17ea C from color MACRO_Execute_Record,Field_Type,fieldnum 3279 ; 17ee C from color MACRO_Execute_Record,Field_Type_Dynamic 3279 ; 180b C True from color 0x0a31 3279 ; 180d C True from color 0x0a31 3279 ; 1827 C True from color 0x09ab 3279 ; 1833 C True from color 0x09ab 3279 ; 19da C True from color MACRO_Execute_Vector,Catenate 3279 ; 1a5e C True from color 0x0a2f 3279 ; 1a76 C True from color 0x0a2f 3279 ; 1a78 C True from color 0x0a2f 3279 ; 1a8c C True from color 0x0a2f 3279 ; 1b50 C True from color 0x09a8 3279 ; 1b61 C True from color 0x09a8 3279 ; 1b63 C True from color 0x09a8 3279 ; 1c2e C True from color 0x1c27 3279 ; 1e94 C False from color MACRO_Declare_Type_Record,Defined 3279 ; 1e96 C False from color MACRO_Declare_Type_Record,Defined 3279 ; 1ea2 C False from color MACRO_Declare_Type_Record,Incomplete 3279 ; 1ea6 C True from color MACRO_Complete_Type_Record,By_Defining 3279 ; 1eb4 C True from color MACRO_Complete_Type_Record,By_Renaming 3279 ; 1eb9 C True from color MACRO_Complete_Type_Record,By_Renaming 3279 ; 1ee9 C True from color MACRO_Declare_Variable_Record,Duplicate 3279 ; 1f54 C False from color MACRO_Declare_Type_Access,Constrained 3279 ; 1f58 C False from color MACRO_Declare_Type_Access,Constrained 3279 ; 1f5d C True from color MACRO_Declare_Type_Access,Constrained 3279 ; 1f85 C from color MACRO_Complete_Type_Array,By_Constraining 3279 ; 1f9b C from color 0x1f99 3279 ; 1f9f C from color 0x1f9e 3279 ; 200f C True from color MACRO_Complete_Type_Array,By_Defining 3279 ; 209c C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 3279 ; 20a4 C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 3279 ; 20ce C True from color 0x2012 3279 ; 2114 C False from color MACRO_Declare_Type_Array,Defined,Visible 3279 ; 2118 C from color 0x2012 3279 ; 211d C from color 0x2012 3279 ; 211e C False from color 0x2012 3279 ; 2122 C from color 0x2012 3279 ; 2137 C from color 0x2135 3279 ; 213b C from color 0x213a 3279 ; 21b0 C False from color MACRO_Declare_Type_Array,Constrained 3279 ; 21b2 C False from color MACRO_Declare_Type_Array,Constrained 3279 ; 21b8 C False from color MACRO_Declare_Type_Array,Constrained 3279 ; 21ba C False from color MACRO_Declare_Type_Array,Constrained 3279 ; 21da C True from color 0x2005 3279 ; 21ea C True from color 0x2005 3279 ; 220c C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 3279 ; 220e C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 3279 ; 2216 C from color 0x2005 3279 ; 2306 C False from color MACRO_Declare_Type_Array,Incomplete 3279 ; 230a C False from color MACRO_Declare_Type_Array,Incomplete 3279 ; 2315 C True from color MACRO_Complete_Type_Array,By_Component_Completion 3279 ; 2333 C True from color MACRO_Complete_Type_Array,By_Renaming 3279 ; 2335 C True from color MACRO_Complete_Type_Array,By_Renaming 3279 ; 239d C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3279 ; 23c6 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3279 ; 23c8 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3279 ; 23f2 C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 3279 ; 23f7 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 3279 ; 2504 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3279 ; 2519 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3279 ; 2522 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3279 ; 2531 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 3279 ; 25e8 C from color 0x25e1 3279 ; 262d C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 3279 ; 2632 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 3279 ; 263c C False from color 0x263c 3279 ; 2653 C True from color 0x263c 3279 ; 26e3 C from color 0x26e2 3279 ; 2749 C False from color MACRO_Declare_Variable_Entry 3279 ; 274d C False from color MACRO_Declare_Variable_Entry 3279 ; 2900 C True from color MACRO_Execute_Float,Write_Unchecked 3279 ; 2cb8 C from color MACRO_Declare_Subprogram_For_Call,subp 3279 ; 2fd1 C True from color MACRO_Execute_Any,Convert 3279 ; 2ff1 C True from color MACRO_Execute_Any,Convert 3279 ; 3000 C True from color MACRO_Execute_Discrete,Write_Unchecked 3279 ; 3012 C True from color MACRO_Execute_Discrete,Test_And_Set_Previous 3279 ; 30b1 C True from color MACRO_Complete_Type_Float,By_Defining 3279 ; 30b5 C True from color MACRO_Complete_Type_Float,By_Defining 3279 ; 30bd C True from color MACRO_Complete_Type_Float,By_Defining 3279 ; 30be C True from color MACRO_Complete_Type_Float,By_Defining 3279 ; 316d C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 3279 ; -------------------------------------------------------------------------------------- 3279 3279 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR08:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 327a 327a fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR05:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 327b 327b fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR06:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 327c ; -------------------------------------------------------------------------------------- 327c ; Comes from: 327c ; 0f23 C True from color 0x0efa 327c ; -------------------------------------------------------------------------------------- 327c 327c fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 05 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 327d 327d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3772 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 0 Branch False seq_branch_adr 3772 0x3772 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 20 VR0d:00 val_frame d 327e 327e ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 327f 327f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3281 seq_br_type 1 Branch True seq_branch_adr 3281 0x3281 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 3b TR05:1b typ_frame 5 3280 3280 seq_br_type 3 Unconditional Branch; Flow J 0x327f seq_branch_adr 327f 0x327f seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand 0 NO_OP 3281 3281 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 3282 3282 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 3283 3283 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3284 3284 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 14 ZEROS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 3285 3285 ioc_tvbs 2 fiu+val; Flow J cc=True 0x328c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 328c 0x328c seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3286 3286 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3287 3287 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6a ? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 2a TR08:0a typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 8 typ_rand 6 CHECK_CLASS_A_??_B 3288 3288 ioc_fiubs 2 typ ; Flow J cc=True 0x328e seq_br_type 1 Branch True seq_branch_adr 328e 0x328e seq_cond_sel 20 TYP.ALU_CARRY(late) seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 3289 3289 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 328a 328a ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 328b 328b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x32f1 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f1 0x32f1 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 328c 328c ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 3e TR09:1e typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 9 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 328d 328d seq_br_type 3 Unconditional Branch; Flow J 0x32c8 seq_branch_adr 32c8 0x32c8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_csa_cntl 7 FINISH_POP_DOWN 328e 328e fiu_load_tar 1 hold_tar; Flow C cc=False 0x3298 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3298 0x3298 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 328f 328f fiu_mem_start 4 continue ioc_tvbs 2 fiu+val seq_random 0a ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 3290 3290 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3291 3291 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3292 3292 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 3293 3293 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3294 3294 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3295 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 328e 0x328e seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 3295 3295 ioc_fiubs 2 typ ; Flow J cc=True 0x328c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 328c 0x328c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 0f Load_control_top+? typ_a_adr 02 GP02 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3296 3296 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3289 seq_br_type 0 Branch False seq_branch_adr 3289 0x3289 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 val_b_adr 03 GP03 3297 3297 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 3298 ; -------------------------------------------------------------------------------------- 3298 ; Comes from: 3298 ; 328e C False from color 0x0000 3298 ; -------------------------------------------------------------------------------------- 3298 3298 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3299 3299 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 329a 329a seq_br_type 3 Unconditional Branch; Flow J 0x3281 seq_branch_adr 3281 0x3281 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 329b ; -------------------------------------------------------------------------------------- 329b ; Comes from: 329b ; 0f33 C True from color 0x0efa 329b ; 2044 C True from color 0x2012 329b ; 20ea C True from color 0x2012 329b ; -------------------------------------------------------------------------------------- 329b 329b fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR06:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 329c ; -------------------------------------------------------------------------------------- 329c ; Comes from: 329c ; 0f46 C True from color 0x0efa 329c ; 12cb C False from color 0x098c 329c ; 12d1 C from color 0x098c 329c ; 12d9 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 329c ; 12e6 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 329c ; 1311 C False from color MACRO_Declare_Variable_Variant_Record,Duplicate 329c ; 1393 C from color MACRO_Declare_Variable_Array,With_Constraint 329c ; 139a C False from color 0x1399 329c ; 13e8 C from color MACRO_Declare_Variable_Array,With_Constraint 329c ; 13ec C False from color MACRO_Declare_Variable_Array,With_Constraint 329c ; 13f5 C False from color MACRO_Declare_Variable_Array,With_Constraint 329c ; 1408 C from color MACRO_Declare_Variable_Array,With_Constraint 329c ; 140e C from color 0x140c 329c ; 17ad C from color 0x17ab 329c ; 180c C from color 0x0a31 329c ; 196c C False from color MACRO_Execute_Vector,Slice_Read 329c ; 1979 C from color MACRO_Execute_Vector,Slice_Read 329c ; 197d C False from color MACRO_Execute_Vector,Slice_Read 329c ; 1987 C False from color MACRO_Execute_Vector,Slice_Read 329c ; 1a61 C False from color 0x0a2f 329c ; 1a7b C False from color 0x0a2f 329c ; 1a7d C False from color 0x0a2f 329c ; 1a93 C False from color 0x0a2f 329c ; 1c36 C False from color 0x1c27 329c ; 1c37 C False from color 0x1c27 329c ; 1eea C False from color MACRO_Declare_Variable_Record,Duplicate 329c ; 272e C True from color 0x26fc 329c ; 2739 C True from color 0x26fc 329c ; -------------------------------------------------------------------------------------- 329c 329c fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR06:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 329d 329d fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR07:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 329e ; -------------------------------------------------------------------------------------- 329e ; Comes from: 329e ; 0f3c C from color 0x0efa 329e ; -------------------------------------------------------------------------------------- 329e 329e fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR07:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 329f 329f fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR07:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 32a0 ; -------------------------------------------------------------------------------------- 32a0 ; Comes from: 32a0 ; 3599 C False from color 0x3599 32a0 ; -------------------------------------------------------------------------------------- 32a0 32a0 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR09:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a1 32a1 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR13:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 32a2 ; -------------------------------------------------------------------------------------- 32a2 ; Comes from: 32a2 ; 10d4 C from color 0x10d4 32a2 ; 11c2 C False from color 0x111d 32a2 ; 11cd C False from color 0x111d 32a2 ; 1232 C False from color 0x1201 32a2 ; 12d0 C True from color 0x098c 32a2 ; 12e5 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a2 ; 138c C from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13d6 C from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 1407 C True from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 140d C True from color 0x140c 32a2 ; -------------------------------------------------------------------------------------- 32a2 32a2 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a3 32a3 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR08:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32a4 ; -------------------------------------------------------------------------------------- 32a4 ; Comes from: 32a4 ; 0215 C True from color MACRO_Action_Accept_Activation 32a4 ; 0217 C True from color MACRO_Action_Accept_Activation 32a4 ; 022c C True from color MACRO_Action_Signal_Activated 32a4 ; 0230 C from color MACRO_Action_Signal_Activated 32a4 ; 394a C True from color 0x0913 32a4 ; 3956 C True from color 0x06b6 32a4 ; 3968 C False from color 0x03fa 32a4 ; -------------------------------------------------------------------------------------- 32a4 32a4 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a5 32a5 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR09:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a6 32a6 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a7 ; -------------------------------------------------------------------------------------- 32a7 ; Comes from: 32a7 ; 01a9 C from color UE_CLASS 32a7 ; 054f C True from color MACRO_Action_Pop_Auxiliary 32a7 ; 055a C False from color MACRO_Action_Pop_Auxiliary_Range 32a7 ; 090c C True from color 0x0905 32a7 ; 0917 C True from color 0x0917 32a7 ; 0950 C True from color MACRO_Execute_Module,Is_Callable 32a7 ; 095e C True from color MACRO_Execute_Module,Is_Callable 32a7 ; 096d C from color MACRO_0966_QQUnknown_InMicrocode 32a7 ; 0983 C from color MACRO_Declare_Variable_Any 32a7 ; 0993 C from color MACRO_Declare_Variable_Any,Visible 32a7 ; 09a5 C from color MACRO_Execute_Any,Equal 32a7 ; 09a8 C from color 0x09a8 32a7 ; 09a9 C from color 0x09a8 32a7 ; 09b5 C from color MACRO_Execute_Any,Not_Equal 32a7 ; 09b8 C from color 0x09a8 32a7 ; 09b9 C from color 0x09a8 32a7 ; 09ca C True from color MACRO_Execute_Any,Address_Of_Type 32a7 ; 09cd C True from color MACRO_Execute_Any,Size 32a7 ; 09f8 C True from color MACRO_Execute_Any,Change_Utility 32a7 ; 09fa C False from color MACRO_Execute_Any,Change_Utility 32a7 ; 09fc C True from color MACRO_Execute_Any,Change_Utility 32a7 ; 0a03 C from color MACRO_Execute_Any,Make_Visible 32a7 ; 0a05 C from color MACRO_Execute_Any,Make_Visible 32a7 ; 0a0a C from color MACRO_Execute_Any,Make_Visible 32a7 ; 0a16 C True from color MACRO_Execute_Any,Make_Root_Type 32a7 ; 0a17 C False from color MACRO_Execute_Any,Make_Root_Type 32a7 ; 0a1f C from color 0x0a1f 32a7 ; 0a22 C True from color MACRO_Execute_Any,Is_Value 32a7 ; 0a24 C True from color MACRO_Execute_Any,Is_Scalar 32a7 ; 0a29 C from color MACRO_Execute_Any,Convert 32a7 ; 0a3b C from color MACRO_Execute_Any,Convert 32a7 ; 0a4d C True from color MACRO_Execute_Any,Convert_Unchecked 32a7 ; 0a51 C from color 0x0a50 32a7 ; 0a5e C True from color 0x0a50 32a7 ; 0a73 C from color 0x0a50 32a7 ; 0a87 C from color 0x0a50 32a7 ; 0a9b C from color MACRO_Execute_Any,Convert 32a7 ; 0ab8 C True from color MACRO_Execute_Any,Structure_Query 32a7 ; 0c0f C False from color 0x0c07 32a7 ; 0c10 C False from color 0x0c07 32a7 ; 0e47 C False from color 0x0d36 32a7 ; 0e48 C False from color 0x0d36 32a7 ; 0e6f C False from color 0x0d36 32a7 ; 0e70 C False from color 0x0d36 32a7 ; 12c8 C False from color 0x098c 32a7 ; 12d4 C False from color 0x098c 32a7 ; 12d6 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a7 ; 130c C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a7 ; 130e C False from color MACRO_Declare_Variable_Variant_Record,Duplicate 32a7 ; 17d2 C from color MACRO_Execute_Any,Set_Constraint 32a7 ; 1e83 C True from color MACRO_Declare_Type_Record,Defined 32a7 ; 1ea5 C True from color MACRO_Complete_Type_Record,By_Defining 32a7 ; 1ee6 C False from color MACRO_Declare_Variable_Record,Duplicate 32a7 ; 200b C True from color MACRO_Complete_Type_Array,By_Defining 32a7 ; 2010 C True from color MACRO_Complete_Type_Array,By_Defining 32a7 ; 2026 C True from color 0x2012 32a7 ; 205d C True from color 0x2012 32a7 ; 206c C True from color MACRO_Declare_Type_Array,Defined_Incomplete 32a7 ; 2094 C True from color 0x2012 32a7 ; 209d C True from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 32a7 ; 20a0 C True from color 0x209f 32a7 ; 20a5 C True from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 32a7 ; 20cc C True from color MACRO_Declare_Type_Array,Defined 32a7 ; 20e0 C True from color 0x2012 32a7 ; 2103 C True from color 0x2012 32a7 ; 2106 C True from color 0x2012 32a7 ; 2115 C True from color MACRO_Declare_Type_Array,Defined,Visible 32a7 ; 211a C True from color MACRO_Declare_Type_Array,Defined,Bounds_With_Object 32a7 ; 211f C True from color 0x2012 32a7 ; 21c1 C True from color 0x2005 32a7 ; 21c2 C True from color 0x2005 32a7 ; 230c C True from color MACRO_Complete_Type_Array,By_Component_Completion 32a7 ; 232f C True from color MACRO_Complete_Type_Array,By_Renaming 32a7 ; 2538 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a7 ; 2575 C False from color MACRO_Complete_Type_Variant_Record,By_Defining 32a7 ; 2576 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a7 ; 2640 C True from color 0x263c 32a7 ; 2646 C True from color 0x263c 32a7 ; 26bb C True from color 0x26b8 32a7 ; 26e0 C True from color 0x26b8 32a7 ; 28fe C False from color MACRO_Execute_Float,Write_Unchecked 32a7 ; 2ae8 C True from color MACRO_Declare_Type_Access,Defined 32a7 ; 2aed C True from color MACRO_Declare_Type_Access,Defined 32a7 ; 2af0 C True from color MACRO_Declare_Type_Access,Defined 32a7 ; 2af5 C True from color MACRO_Declare_Type_Access,Defined 32a7 ; 2afe C True from color 0x2afb 32a7 ; 2b31 C True from color 0x2b1d 32a7 ; 2c4e C from color 0x2c4e 32a7 ; 2c5b C from color 0x2c5b 32a7 ; 2c5f C from color 0x2c5b 32a7 ; 2c67 C from color 0x2c5b 32a7 ; 2c6c C True from color 0x2c5b 32a7 ; 2cd6 C True from color MACRO_Action_Elaborate_Subprogram 32a7 ; 2cda C True from color MACRO_Action_Check_Subprogram_Elaborated 32a7 ; 2d13 C True from color 0x2d13 32a7 ; 2ffe C False from color MACRO_Execute_Discrete,Write_Unchecked 32a7 ; 3089 C True from color 0x3089 32a7 ; 30aa C True from color MACRO_Complete_Type_Float,By_Defining 32a7 ; 317d C from color MACRO_Declare_Type_Heap_Access,Defined 32a7 ; 3180 C from color MACRO_Declare_Type_Heap_Access,Defined 32a7 ; 3185 C True from color 0x3184 32a7 ; 3213 C from color MACRO_Execute_Discrete,Remainder 32a7 ; 3223 C from color MACRO_Execute_Discrete,Remainder 32a7 ; 3228 C from color MACRO_Execute_Discrete,Remainder 32a7 ; -------------------------------------------------------------------------------------- 32a7 32a7 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32a8 32a8 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32a9 ; -------------------------------------------------------------------------------------- 32a9 ; Comes from: 32a9 ; 04bb C from color 0x04bb 32a9 ; 0501 C False from color 0x04fa 32a9 ; 0515 C from color 0x0515 32a9 ; 09f9 C False from color MACRO_Execute_Any,Change_Utility 32a9 ; 09fb C False from color MACRO_Execute_Any,Change_Utility 32a9 ; 0c1f C from color MACRO_Execute_Heap_Access,Element_Type 32a9 ; 0c3b C from color 0x0a7e 32a9 ; 0cf2 C True from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32a9 ; 109d C True from color 0x1099 32a9 ; 10a4 C True from color 0x1099 32a9 ; 10cc C False from color 0x10c1 32a9 ; 115c C True from color 0x1117 32a9 ; 1162 C True from color 0x1118 32a9 ; 1172 C True from color 0x111c 32a9 ; 11b5 C True from color 0x111d 32a9 ; 11e6 C from color 0x11e6 32a9 ; 11ea C from color 0x11ea 32a9 ; 11ee C from color 0x11ee 32a9 ; 11f2 C from color 0x11f2 32a9 ; 11f3 C from color 0x11f2 32a9 ; 11f4 C from color 0x11f2 32a9 ; 11f5 C from color 0x11f2 32a9 ; 11f6 C from color 0x11f2 32a9 ; 11fa C from color 0x10c1 32a9 ; 11fb C from color 0x10c1 32a9 ; 1207 C True from color 0x10c1 32a9 ; 1209 C True from color 0x10c1 32a9 ; 120a C False from color 0x10c1 32a9 ; 1251 C from color 0x1250 32a9 ; 1252 C from color 0x1250 32a9 ; 1253 C from color 0x1250 32a9 ; 1254 C from color 0x1250 32a9 ; 12dc C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a9 ; 1481 C True from color MACRO_Execute_Matrix,Length 32a9 ; 1497 C True from color 0x1486 32a9 ; 15e7 C True from color MACRO_Execute_Matrix,Subarray 32a9 ; 15ea C True from color MACRO_Execute_Matrix,Subarray 32a9 ; 1697 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32a9 ; 16d1 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32a9 ; 16df C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32a9 ; 16f7 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a9 ; 16f8 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a9 ; 16f9 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a9 ; 16fa C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a9 ; 1702 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a9 ; 172e C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 172f C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 1731 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 1732 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 1738 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 173a C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a9 ; 175f C from color MACRO_Execute_Variant_Record,Read_Variant 32a9 ; 1772 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a9 ; 1773 C False from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a9 ; 1774 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a9 ; 1775 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a9 ; 177e C True from color MACRO_Execute_Variant_Record,Reference_Makes_Copy 32a9 ; 1785 C True from color MACRO_Execute_Variant_Record,Structure_Query 32a9 ; 1786 C True from color MACRO_Execute_Variant_Record,Structure_Query 32a9 ; 179a C True from color MACRO_Execute_Variant_Record,Component_Offset 32a9 ; 1801 C True from color 0x0a31 32a9 ; 1adf C from color MACRO_Execute_Access,Element_Type 32a9 ; 1afb C from color 0x0a7d 32a9 ; 1b82 C True from color 0x1b80 32a9 ; 1b8d C False from color 0x1b80 32a9 ; 1c81 C True from color MACRO_Execute_Array,Subarray 32a9 ; 1c82 C True from color MACRO_Execute_Array,Subarray 32a9 ; 1c83 C False from color MACRO_Execute_Array,Subarray 32a9 ; 1e84 C True from color MACRO_Declare_Type_Record,Defined 32a9 ; 1e9b C True from color MACRO_Declare_Type_Record,Incomplete 32a9 ; 1ea8 C True from color MACRO_Complete_Type_Record,By_Defining 32a9 ; 1eb7 C True from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1eba C True from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1ec4 C from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1f5f C True from color MACRO_Declare_Type_Access,Constrained 32a9 ; 1f73 C False from color 0x1f6b 32a9 ; 1f80 C True from color MACRO_Complete_Type_Array,By_Constraining 32a9 ; 1f8a C from color MACRO_Complete_Type_Array,By_Constraining 32a9 ; 200a C True from color MACRO_Complete_Type_Array,By_Defining 32a9 ; 2042 C True from color 0x2012 32a9 ; 2081 C from color 0x2012 32a9 ; 2083 C from color 0x2012 32a9 ; 20ba C from color 0x2012 32a9 ; 20bc C from color 0x2012 32a9 ; 20e8 C True from color 0x2012 32a9 ; 21be C False from color 0x2005 32a9 ; 21cd C False from color 0x21c9 32a9 ; 21d4 C False from color 0x2005 32a9 ; 21e4 C False from color 0x2005 32a9 ; 21ec C True from color 0x2005 32a9 ; 2200 C True from color 0x21f8 32a9 ; 2213 C from color 0x2005 32a9 ; 22f3 C True from color MACRO_Declare_Type_Array,Incomplete 32a9 ; 22f5 C True from color MACRO_Declare_Type_Array,Incomplete 32a9 ; 2313 C from color MACRO_Complete_Type_Array,By_Component_Completion 32a9 ; 232e C True from color MACRO_Complete_Type_Array,By_Renaming 32a9 ; 2338 C True from color MACRO_Complete_Type_Array,By_Renaming 32a9 ; 234c C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 234d C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 2351 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 2352 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23b1 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23c3 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23c7 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23f8 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32a9 ; 248e C True from color 0x248a 32a9 ; 2490 C True from color 0x248a 32a9 ; 2498 C True from color 0x248a 32a9 ; 2534 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a9 ; 2536 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a9 ; 25b5 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 25b6 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 262f C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 2630 C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 2634 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 263d C True from color 0x263c 32a9 ; 2644 C True from color 0x263c 32a9 ; 26ec C True from color 0x26e5 32a9 ; 2ae9 C False from color MACRO_Declare_Type_Access,Defined 32a9 ; 2aee C False from color MACRO_Declare_Type_Access,Defined 32a9 ; 2af1 C False from color MACRO_Declare_Type_Access,Defined 32a9 ; 2af6 C False from color MACRO_Declare_Type_Access,Defined 32a9 ; 2af8 C True from color MACRO_Declare_Type_Access,Defined 32a9 ; 2b3e C False from color MACRO_Declare_Type_Access,Incomplete 32a9 ; 2b3f C True from color MACRO_Declare_Type_Access,Incomplete 32a9 ; 30b3 C False from color MACRO_Complete_Type_Float,By_Defining 32a9 ; 30bb C False from color MACRO_Complete_Type_Float,By_Defining 32a9 ; 30e7 C False from color 0x30e5 32a9 ; 3120 C False from color MACRO_Declare_Type_InMicrocode,Discrete 32a9 ; 318e C False from color 0x318a 32a9 ; 319b C True from color MACRO_Declare_Type_Heap_Access,Incomplete 32a9 ; 319d C from color MACRO_Declare_Type_Heap_Access,Incomplete 32a9 ; -------------------------------------------------------------------------------------- 32a9 32a9 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR08:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32aa ; -------------------------------------------------------------------------------------- 32aa ; Comes from: 32aa ; 099d C False from color 0x099d 32aa ; 099f C False from color 0x099f 32aa ; 0a00 C False from color MACRO_Execute_Any,Make_Visible 32aa ; 1090 C False from color MACRO_Declare_Variable_Access,Visible 32aa ; 1096 C False from color MACRO_Declare_Variable_Heap_Access,Visible 32aa ; 109b C False from color 0x1099 32aa ; 10a2 C False from color 0x1099 32aa ; 12c9 C False from color 0x098c 32aa ; 12d7 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32aa ; 2aec C False from color MACRO_Declare_Type_Access,Defined 32aa ; 2af4 C False from color MACRO_Declare_Type_Access,Defined 32aa ; 2b38 C False from color MACRO_Declare_Type_Access,Incomplete 32aa ; 2b3c C False from color MACRO_Declare_Type_Access,Incomplete 32aa ; 2c6a C from color 0x2c5b 32aa ; 3087 C False from color MACRO_Declare_Type_Float,Defined,Visible 32aa ; 309d C False from color MACRO_Declare_Type_Float,Constrained,Visible 32aa ; 30a3 C False from color MACRO_Declare_Type_Float,Incomplete,Visible 32aa ; 30cc C False from color 0x0995 32aa ; 30da C False from color MACRO_Declare_Variable_Float,Visible,With_Value 32aa ; 30e5 C False from color 0x30e5 32aa ; 30ec C False from color 0x30e5 32aa ; 311d C False from color MACRO_Declare_Type_InMicrocode,Discrete 32aa ; 3162 C False from color MACRO_Declare_Variable_Any,Visible 32aa ; 3170 C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 32aa ; 3172 C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 32aa ; 317a C False from color MACRO_Declare_Variable_Discrete,Visible,With_Value 32aa ; 317e C False from color MACRO_Declare_Type_Heap_Access,Defined 32aa ; 3195 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32aa ; 3199 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32aa ; 319f C from color MACRO_Declare_Type_Heap_Access,Incomplete 32aa ; -------------------------------------------------------------------------------------- 32aa 32aa fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR08:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32ab ; -------------------------------------------------------------------------------------- 32ab ; Comes from: 32ab ; 0a4e C from color MACRO_Execute_Any,Convert_Unchecked 32ab ; 0a6c C False from color 0x0a50 32ab ; 0a6f C from color 0x0a50 32ab ; 1112 C from color 0x1112 32ab ; 169a C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ab ; 1762 C False from color MACRO_Execute_Variant_Record,Indirects_Appended 32ab ; 1763 C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32ab ; 17f7 C True from color MACRO_Execute_Record,Structure_Write 32ab ; 17f8 C True from color MACRO_Execute_Record,Structure_Write 32ab ; 19b9 C True from color 0x19b9 32ab ; 19bb C from color 0x19b9 32ab ; 1d2e C from color 0x1d2e 32ab ; 1d2f C from color 0x1d2e 32ab ; 1d3e C from color 0x1d3e 32ab ; 1d4c C from color 0x1d4c 32ab ; 1eab C False from color MACRO_Complete_Type_Record,By_Defining 32ab ; 1eb8 C False from color MACRO_Complete_Type_Record,By_Renaming 32ab ; 1f7e C True from color MACRO_Complete_Type_Array,By_Constraining 32ab ; 1f83 C True from color MACRO_Complete_Type_Array,By_Constraining 32ab ; 2008 C True from color MACRO_Complete_Type_Array,By_Defining 32ab ; 200e C True from color MACRO_Complete_Type_Array,By_Defining 32ab ; 21bd C True from color 0x2005 32ab ; 21d3 C True from color 0x2005 32ab ; 21e3 C True from color 0x2005 32ab ; 220a C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32ab ; 2215 C True from color 0x2005 32ab ; 232c C True from color MACRO_Complete_Type_Array,By_Renaming 32ab ; 2332 C True from color MACRO_Complete_Type_Array,By_Renaming 32ab ; 23c0 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ab ; 23c5 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ab ; 2532 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2535 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2633 C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32ab ; 2d31 C True from color 0x2cf6 32ab ; -------------------------------------------------------------------------------------- 32ab 32ab fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR08:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32ac ; -------------------------------------------------------------------------------------- 32ac ; Comes from: 32ac ; 0907 C False from color 0x0905 32ac ; 10ab C from color 0x10aa 32ac ; 10af C from color 0x10aa 32ac ; 10b3 C from color 0x10aa 32ac ; 10b7 C from color 0x10aa 32ac ; 10e1 C False from color 0x10d6 32ac ; 1180 C False from color 0x111d 32ac ; 118b C from color 0x111d 32ac ; 1215 C False from color 0x10d6 32ac ; 1219 C False from color 0x10d6 32ac ; 121c C False from color 0x10d6 32ac ; 1244 C from color 0x1244 32ac ; 1248 C from color 0x1248 32ac ; 124c C from color 0x124c 32ac ; 1250 C from color 0x1250 32ac ; 128c C False from color 0x10d6 32ac ; 129e C False from color 0x125f 32ac ; 12a2 C False from color 0x125f 32ac ; 12a5 C False from color 0x125f 32ac ; 12c5 C False from color 0x12c5 32ac ; 1376 C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 137a C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 13a1 C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 13a5 C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 13c8 C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 13cc C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 13fd C False from color MACRO_Declare_Variable_Array,With_Constraint 32ac ; 1415 C False from color 0x1411 32ac ; 1710 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32ac ; 171d C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32ac ; 1972 C False from color MACRO_Execute_Vector,Slice_Read 32ac ; 197a C False from color MACRO_Execute_Vector,Slice_Read 32ac ; 1986 C False from color MACRO_Execute_Vector,Slice_Read 32ac ; 198b C False from color MACRO_Execute_Vector,Slice_Read 32ac ; 1992 C False from color MACRO_Execute_Vector,Slice_Read 32ac ; 19e5 C False from color MACRO_Execute_Vector,Catenate 32ac ; 19f8 C False from color MACRO_Execute_Vector,Catenate 32ac ; 1a07 C True from color MACRO_Execute_Vector,Catenate 32ac ; 1a7f C False from color 0x0a2f 32ac ; 1a86 C True from color 0x0a2f 32ac ; 1a88 C False from color 0x0a2f 32ac ; 20bd C True from color 0x2012 32ac ; 222c C False from color 0x2228 32ac ; 2238 C False from color 0x2228 32ac ; 224a C False from color 0x2228 32ac ; 224b C False from color 0x2228 32ac ; 2748 C False from color MACRO_Declare_Variable_Entry 32ac ; 2a0d C False from color 0x2a04 32ac ; 2a24 C False from color 0x2a04 32ac ; 2cb7 C True from color MACRO_Declare_Subprogram_For_Call,subp 32ac ; 2cbd C True from color MACRO_Declare_Subprogram_For_Accept,subp 32ac ; 30e8 C False from color 0x30e5 32ac ; 311c C False from color MACRO_Declare_Type_InMicrocode,Discrete 32ac ; 3122 C False from color MACRO_Declare_Type_InMicrocode,Discrete 32ac ; 3b1d C True from color 0x36eb 32ac ; 3b1f C True from color 0x36eb 32ac ; -------------------------------------------------------------------------------------- 32ac 32ac fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 37 VR12:17 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32ad ; -------------------------------------------------------------------------------------- 32ad ; Comes from: 32ad ; 01f8 C from color MACRO_01f8_QQUnknown_InMicrocode 32ad ; 2357 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ad ; 239a C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ad ; 23a1 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ad ; 23fd C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32ad ; 2422 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32ad ; 2508 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 2509 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 250a C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 250b C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 250c C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 2525 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 2526 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 2527 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ad ; 2533 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 2539 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 254d C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 254e C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 255f C True from color 0x255e 32ad ; 2577 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 2578 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 257a C False from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 2599 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 259a C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 259b C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 259d C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 259e C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 25a0 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ad ; 264c C True from color 0x263c 32ad ; 2662 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 2663 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 266d C True from color 0x266c 32ad ; 26a6 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 26a7 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 26a8 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 26aa C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 26ab C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 26ad C True from color MACRO_Declare_Type_Variant_Record,Defined 32ad ; 2d16 C True from color ML_break_class 32ad ; 324a C from color MACRO_Illegal_- 32ad ; -------------------------------------------------------------------------------------- 32ad 32ad fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR08:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32ae ; -------------------------------------------------------------------------------------- 32ae ; Comes from: 32ae ; 0fa3 C True from color 0x0efa 32ae ; 0fb0 C True from color 0x0efa 32ae ; 0fb5 C True from color 0x0efa 32ae ; 15f7 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 32ae ; 164a C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 32ae ; 164c C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 32ae ; 169b C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16a1 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16a6 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16d4 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; 16e7 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; 16f6 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32ae ; 1767 C from color MACRO_Execute_Variant_Record,Indirects_Appended 32ae ; 176a C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32ae ; 176e C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32ae ; 1798 C False from color MACRO_Execute_Variant_Record,Component_Offset 32ae ; 179c C from color MACRO_Execute_Variant_Record,Component_Offset 32ae ; 17c9 C from color MACRO_Execute_Any,Set_Constraint 32ae ; 17d4 C True from color MACRO_Execute_Record,Field_Read,fieldnum 32ae ; 17e4 C True from color MACRO_Execute_Record,Field_Reference,fieldnum 32ae ; 17f1 C True from color 0x09ad 32ae ; 17fc C from color MACRO_Execute_Record,Structure_Write 32ae ; 17fe C False from color 0x0a31 32ae ; 1803 C from color 0x0a31 32ae ; 1811 C True from color 0x1811 32ae ; 1812 C True from color 0x1811 32ae ; 1815 C from color 0x1811 32ae ; 1964 C True from color MACRO_Execute_Vector,Slice_Read 32ae ; 19b7 C True from color MACRO_Execute_Vector,Slice_Write 32ae ; 19c2 C True from color MACRO_Execute_Vector,Slice_Reference 32ae ; 24e6 C False from color 0x248a 32ae ; 2a63 C True from color ML_Resolve Reference 32ae ; 2c6d C True from color 0x2c5b 32ae ; 2c71 C False from color 0x2c70 32ae ; 2c76 C True from color 0x2c70 32ae ; 2c7c C False from color MACRO_Execute_Select,Member_Write,fieldnum 32ae ; 2c8e C False from color MACRO_Execute_Select,Member_Write,fieldnum 32ae ; 2c94 C False from color MACRO_Execute_Select,Guard_Write,fieldnum 32ae ; 2c9f C True from color MACRO_Execute_Select,Timed_Duration_Write 32ae ; 35ae C True from color 0x35ac 32ae ; 35b0 C from color 0x35ac 32ae ; 37d5 C True from color MACRO_Execute_Entry,Count 32ae ; 37db C True from color MACRO_Execute_Family,Count 32ae ; 38b3 C True from color 0x38b0 32ae ; -------------------------------------------------------------------------------------- 32ae 32ae fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR11:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32af ; -------------------------------------------------------------------------------------- 32af ; Comes from: 32af ; 019a C from color UE_CHK_EXIT 32af ; 01e2 C from color UE_NEW_PAK 32af ; 2e56 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 32af ; -------------------------------------------------------------------------------------- 32af 32af fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR11:0e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32b0 ; -------------------------------------------------------------------------------------- 32b0 ; Comes from: 32b0 ; 01a2 C from color UE_FIELD_ERROR 32b0 ; 1699 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 169c C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16b6 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16bc C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16bd C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16c1 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16c3 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32b0 ; 16d3 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32b0 ; 16d8 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32b0 ; 16d9 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32b0 ; 16e0 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32b0 ; -------------------------------------------------------------------------------------- 32b0 32b0 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR11:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32b1 ; -------------------------------------------------------------------------------------- 32b1 ; Comes from: 32b1 ; 0c58 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32b1 ; 0c59 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32b1 ; 1156 C False from color 0x1156 32b1 ; 1dae C False from color 0x1dae 32b1 ; 35bb C from color 0x35b4 32b1 ; 35c0 C False from color 0x35bd 32b1 ; 35c2 C False from color 0x35bd 32b1 ; 35c3 C True from color 0x35bd 32b1 ; 35c7 C False from color 0x35c7 32b1 ; 35c8 C True from color 0x35c7 32b1 ; 35c9 C False from color 0x35c7 32b1 ; 35cf C from color 0x35c7 32b1 ; 35d0 C False from color 0x35c7 32b1 ; 35d1 C True from color 0x35c7 32b1 ; 35d2 C False from color 0x35c7 32b1 ; 35d5 C from color 0x35c7 32b1 ; -------------------------------------------------------------------------------------- 32b1 32b1 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR11:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32b2 ; -------------------------------------------------------------------------------------- 32b2 ; Comes from: 32b2 ; 03ab C True from color 0x0398 32b2 ; 2c9b C False from color MACRO_Execute_Select,Timed_Duration_Write 32b2 ; 2ca2 C False from color MACRO_Execute_Select,Timed_Guard_Write 32b2 ; 2ca6 C False from color MACRO_Execute_Select,Terminate_Guard_Write 32b2 ; -------------------------------------------------------------------------------------- 32b2 32b2 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR05:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32b3 32b3 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 32b4 32b4 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR09:10 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32b5 32b5 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR12:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32b6 ; -------------------------------------------------------------------------------------- 32b6 ; Comes from: 32b6 ; 0f56 C from color 0x0efa 32b6 ; 0fa9 C False from color 0x0efa 32b6 ; 0fae C from color 0x0efa 32b6 ; -------------------------------------------------------------------------------------- 32b6 32b6 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR18:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 32b7 32b7 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR18:10 typ_c_mux_sel 0 ALU typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0f VR18:10 val_c_mux_sel 2 ALU val_frame 18 32b8 32b8 ioc_adrbs 1 val ; Flow C 0x349d ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 32b9 32b9 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x32bd fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32bd 0x32bd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 27 ? val_a_adr 22 VR02:02 val_frame 2 32ba 32ba ioc_adrbs 1 val ; Flow C 0x349d ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32bb 32bb fiu_tivi_src 1 tar_val; Flow J cc=False 0x32be ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 32be 0x32be seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32bc 32bc seq_br_type 3 Unconditional Branch; Flow J 0x32c6 seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 32bd 32bd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32be 32be fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR07:18 typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 32bf 32bf fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 14 ZEROS val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 32c0 32c0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 02 GP02 32c1 32c1 seq_br_type 3 Unconditional Branch; Flow J 0x32e3 seq_branch_adr 32e3 0x32e3 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32c2 ; -------------------------------------------------------------------------------------- 32c2 ; Comes from: 32c2 ; 0f7f C False from color 0x0efa 32c2 ; -------------------------------------------------------------------------------------- 32c2 32c2 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR12:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32c3 ; -------------------------------------------------------------------------------------- 32c3 ; Comes from: 32c3 ; 1f50 C from color 0x1f4e 32c3 ; -------------------------------------------------------------------------------------- 32c3 32c3 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 32c4 32c4 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR12:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32c5 ; -------------------------------------------------------------------------------------- 32c5 ; Comes from: 32c5 ; 097c C from color MACRO_Execute_Module,Is_Callable 32c5 ; 0b71 C False from color 0x0b70 32c5 ; 0ceb C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32c5 ; 0d06 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32c5 ; 0e7c C False from color 0x0e7a 32c5 ; 0e7d C True from color 0x0e7a 32c5 ; 0e7f C False from color 0x0e7a 32c5 ; -------------------------------------------------------------------------------------- 32c5 32c5 fiu_tivi_src 1 tar_val; Flow J 0x32c6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 39 VR09:19 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32c6 ; -------------------------------------------------------------------------------------- 32c6 ; Comes from: 32c6 ; 3266 C from color MACRO_Execute_Discrete,Raise,>R 32c6 ; -------------------------------------------------------------------------------------- 32c6 32c6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 32c7 32c7 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x32c9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c9 0x32c9 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32c8 32c8 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32c9 32c9 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 32ca 32ca fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32cb 32cb fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32cc 32cc fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x32dc fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 32cd 32cd fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 32ce 32ce fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x32e3 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32e3 0x32e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_lex_adr 2 seq_random 0b ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 32cf 32cf fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x32e3 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32e3 0x32e3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 32d0 32d0 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x32e3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32e3 0x32e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 32d1 32d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32e3 seq_br_type 1 Branch True seq_branch_adr 32e3 0x32e3 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 3e TR11:1e typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_frame 11 val_a_adr 38 VR02:18 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_frame 2 32d2 32d2 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 32d3 32d3 ioc_fiubs 2 typ ; Flow J cc=True 0x32da seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32da 0x32da seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 06 GP06 val_alu_func 0 PASS_A 32d4 32d4 seq_en_micro 0 32d5 32d5 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x32d8 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32d8 0x32d8 seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 32d6 32d6 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f9 0x32f9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 32d7 32d7 seq_br_type 3 Unconditional Branch; Flow J 0x32f1 seq_branch_adr 32f1 0x32f1 32d8 32d8 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f9 0x32f9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 32d9 32d9 seq_br_type 3 Unconditional Branch; Flow J 0x32f1 seq_branch_adr 32f1 0x32f1 32da 32da seq_en_micro 0 32db 32db fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x32ea fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32ea 0x32ea seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 32dc 32dc seq_br_type 3 Unconditional Branch; Flow J 0x32e3 seq_branch_adr 32e3 0x32e3 seq_lex_adr 3 seq_random 6a ? val_c_adr 39 GP06 val_c_mux_sel 2 ALU 32dd 32dd seq_en_micro 0 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 32de 32de fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32df 32df ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 32e0 32e0 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_frame 2 32e1 32e1 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32e2 32e2 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x32ce fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 32ce 0x32ce seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 32e3 32e3 fiu_load_tar 1 hold_tar; Flow J cc=True 0x32e9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32e9 0x32e9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 32e4 32e4 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x32e7 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32e7 0x32e7 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32e5 32e5 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f9 0x32f9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 32e6 32e6 seq_br_type 3 Unconditional Branch; Flow J 0x32f1 seq_branch_adr 32f1 0x32f1 32e7 32e7 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f9 0x32f9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 32e8 32e8 seq_br_type 3 Unconditional Branch; Flow J 0x32f1 seq_branch_adr 32f1 0x32f1 32e9 32e9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32ea 32ea fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f9 0x32f9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 32eb 32eb seq_br_type 3 Unconditional Branch; Flow J 0x32f1 seq_branch_adr 32f1 0x32f1 32ec ; -------------------------------------------------------------------------------------- 32ec ; 0x0101 Execute Exception,Reraise,>R 32ec ; -------------------------------------------------------------------------------------- 32ec MACRO_Execute_Exception,Reraise,>R: 32ec 32ec dispatch_brk_class 8 ; Flow J cc=True 0x32dd dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 32ec fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dd 0x32dd seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_alu_func 13 ONES val_c_adr 39 GP06 val_c_mux_sel 2 ALU 32ed 32ed seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_frame 8 32ee 32ee fiu_mem_start 2 start-rd; Flow J cc=True 0x32f0 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32f0 0x32f0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 32ef 32ef ioc_fiubs 2 typ ; Flow J 0x32f1 seq_br_type 3 Unconditional Branch seq_branch_adr 32f1 0x32f1 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 28 VR05:08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 32f0 32f0 ioc_fiubs 2 typ ; Flow J 0x32f1 seq_br_type 3 Unconditional Branch seq_branch_adr 32f1 0x32f1 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 29 VR05:09 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 32f1 32f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x32f4 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 32f4 0x32f4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 32f2 32f2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 32f3 32f3 ioc_tvbs 1 typ+fiu; Flow J 0x32f8 seq_br_type 3 Unconditional Branch seq_branch_adr 32f8 0x32f8 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 32f4 32f4 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 32f5 32f5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_random 15 ? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 32f6 32f6 ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 6e Load_break_mask+? 32f7 32f7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32f8 seq_br_type 3 Unconditional Branch seq_branch_adr 32f8 0x32f8 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 32f8 32f8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 32f9 ; -------------------------------------------------------------------------------------- 32f9 ; Comes from: 32f9 ; 32d6 C True from color 0x0000 32f9 ; 32d8 C True from color 0x0000 32f9 ; 32e5 C True from color 0x0000 32f9 ; 32e7 C True from color 0x0000 32f9 ; 32ea C True from color 0x0000 32f9 ; -------------------------------------------------------------------------------------- 32f9 32f9 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 32fa 32fa typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 32fb 32fb fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL 32fc 32fc ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 32fd 32fd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 32fe ; -------------------------------------------------------------------------------------- 32fe ; Comes from: 32fe ; 0222 C from color MACRO_Action_Accept_Activation 32fe ; 0223 C from color MACRO_Action_Accept_Activation 32fe ; 026f C from color MACRO_Action_Accept_Activation 32fe ; 031a C from color MACRO_Action_Name_Partner 32fe ; 03d5 C from color 0x03d4 32fe ; 0402 C from color 0x03f0 32fe ; 067f C from color 0x066a 32fe ; 068a C from color 0x066a 32fe ; 090f C from color 0x0905 32fe ; 0911 C from color 0x0905 32fe ; 0913 C from color 0x0913 32fe ; 0961 C from color MACRO_Execute_Module,Is_Callable 32fe ; 0977 C from color MACRO_Execute_Module,Is_Callable 32fe ; 0a5a C from color 0x0a50 32fe ; 0cec C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32fe ; 0d0e C from color MACRO_Execute_Vector,Hash 32fe ; 1177 C from color 0x111d 32fe ; 1319 C from color 0x1316 32fe ; 144c C from color 0x09ac 32fe ; 1460 C from color 0x09ac 32fe ; 1484 C from color MACRO_Execute_Matrix,Length 32fe ; 1499 C from color 0x1486 32fe ; 14c2 C from color 0x0aa2 32fe ; 14c3 C from color 0x0aa2 32fe ; 14c7 C from color 0x0aa2 32fe ; 14c8 C from color 0x0aa2 32fe ; 14cf C from color 0x0aa2 32fe ; 14d4 C from color 0x0aa2 32fe ; 1752 C from color MACRO_Execute_Variant_Record,Is_Constrained_Object 32fe ; 1799 C from color MACRO_Execute_Variant_Record,Component_Offset 32fe ; 181d C from color 0x09ab 32fe ; 1829 C from color 0x09ab 32fe ; 1a82 C from color 0x0a2f 32fe ; 1b0b C from color 0x0a33 32fe ; 1b0f C from color 0x0a33 32fe ; 1b41 C from color MACRO_1b40_QQUnknown_InMicrocode 32fe ; 1c87 C from color MACRO_Execute_Array,Subarray 32fe ; 1d75 C from color 0x1d2a 32fe ; 1d90 C from color 0x1d2a 32fe ; 1e13 C from color MACRO_Execute_Matrix,Structure_Write 32fe ; 1e2f C from color MACRO_Execute_Matrix,Structure_Write 32fe ; 1ebe C from color MACRO_Complete_Type_Record,By_Renaming 32fe ; 220d C from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32fe ; 231b C from color MACRO_Complete_Type_Array,By_Component_Completion 32fe ; 238b C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fe ; 239f C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fe ; 23d4 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fe ; 2417 C from color 0x2415 32fe ; 2418 C from color 0x2415 32fe ; 241e C from color 0x2415 32fe ; 244f C from color 0x240b 32fe ; 2518 C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32fe ; 2530 C from color MACRO_Complete_Type_Variant_Record,By_Defining 32fe ; 2557 C from color 0x2555 32fe ; 2559 C from color 0x2555 32fe ; 255b C from color 0x2555 32fe ; 262c C from color MACRO_Complete_Type_Variant_Record,By_Renaming 32fe ; 2639 C from color MACRO_Complete_Type_Variant_Record,By_Renaming 32fe ; 2652 C from color 0x263c 32fe ; 267a C from color 0x2678 32fe ; 267c C from color 0x2678 32fe ; 267e C from color 0x2678 32fe ; 26f2 C from color 0x26e5 32fe ; 2b02 C from color 0x2b02 32fe ; 2cb9 C from color MACRO_Declare_Subprogram_For_Call,subp 32fe ; 2e7f C from color 0x2e7f 32fe ; 2f1d C from color 0x06b6 32fe ; 2f46 C from color 0x06b6 32fe ; 2ff0 C from color MACRO_Execute_Any,Convert 32fe ; 3009 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fe ; 300a C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fe ; 300b C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fe ; 3026 C from color MACRO_Execute_Discrete,Instruction_Read 32fe ; 3076 C from color 0x3076 32fe ; 3078 C from color 0x3076 32fe ; 307a C from color 0x307a 32fe ; 3080 C from color 0x307a 32fe ; 3081 C from color 0x307a 32fe ; 3082 C from color 0x307a 32fe ; 3083 C from color 0x307a 32fe ; 30b2 C from color MACRO_Complete_Type_Float,By_Defining 32fe ; 30b8 C from color MACRO_Complete_Type_Float,By_Defining 32fe ; 316c C from color MACRO_Execute_Immediate_Set_Value,uimmediate 32fe ; 35b1 C from color 0x35ac 32fe ; 35ce C from color 0x35c7 32fe ; 35d7 C from color 0x35c7 32fe ; 35dc C from color 0x35db 32fe ; 379b C from color 0x3797 32fe ; 3807 C from color 0x3802 32fe ; 38b7 C from color 0x38b7 32fe ; 38d8 C from color 0x38cc 32fe ; 3916 C from color 0x3910 32fe ; 3935 C from color 0x062d 32fe ; 39b3 C from color 0x39b2 32fe ; 3a21 C from color 0x03fa 32fe ; 3a3b C from color 0x3a3b 32fe ; -------------------------------------------------------------------------------------- 32fe 32fe seq_br_type a Unconditional Return; Flow R 32ff ; -------------------------------------------------------------------------------------- 32ff ; Comes from: 32ff ; 0754 C from color 0x0203 32ff ; 0ed2 C from color 0x0000 32ff ; 32b6 C from color 0x0000 32ff ; 32e1 C from color 0x0000 32ff ; 32f4 C from color 0x0000 32ff ; 3ab0 C from color 0x0000 32ff ; -------------------------------------------------------------------------------------- 32ff 32ff seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3300 3300 fiu_tivi_src c mar_0xc; Flow J 0x3305 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3305 0x3305 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3301 ; -------------------------------------------------------------------------------------- 3301 ; Comes from: 3301 ; 0b4b C from color 0x0000 3301 ; -------------------------------------------------------------------------------------- 3301 3301 fiu_tivi_src c mar_0xc; Flow J 0x3302 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3305 0x3305 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3302 3302 fiu_mem_start 7 start_wr_if_true; Flow R cc=False fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 3303 0x3303 seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3303 3303 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 3304 3304 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3305 3305 fiu_mem_start 2 start-rd; Flow J 0x3306 ioc_adrbs 3 seq seq_br_type 2 Push (branch address) seq_branch_adr 3311 0x3311 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 26 TR11:06 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 3306 3306 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3367 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3367 0x3367 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3307 3307 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3336 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3336 0x3336 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3308 3308 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 3309 3309 fiu_mem_start 2 start-rd; Flow J 0x330a fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3315 0x3315 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 27 TR11:07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 330a 330a fiu_tivi_src c mar_0xc; Flow J cc=True 0x3367 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3367 0x3367 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 330b 330b fiu_load_tar 1 hold_tar; Flow J cc=False 0x3336 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3336 0x3336 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 330c 330c seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 330d 330d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x330e fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3318 0x3318 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 28 TR11:08 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 330e 330e fiu_tivi_src c mar_0xc; Flow J cc=True 0x3367 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3367 0x3367 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 330f 330f fiu_load_tar 1 hold_tar; Flow J cc=False 0x3336 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3336 0x3336 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3310 3310 seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 3311 3311 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3323 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3323 0x3323 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3312 3312 ioc_adrbs 1 val ; Flow J cc=True 0x3314 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3314 0x3314 typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3313 3313 seq_b_timing 0 Early Condition; Flow J cc=True 0x3314 ; Flow J cc=#0x0 0x331b seq_br_type b Case False seq_branch_adr 331b 0x331b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3314 3314 seq_b_timing 0 Early Condition; Flow J cc=True 0x3315 ; Flow J cc=#0x0 0x331b seq_br_type b Case False seq_branch_adr 331b 0x331b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3315 3315 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3326 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3326 0x3326 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3316 3316 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3317 3317 seq_b_timing 0 Early Condition; Flow J cc=True 0x3318 ; Flow J cc=#0x0 0x331b seq_br_type b Case False seq_branch_adr 331b 0x331b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3318 3318 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3328 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3328 0x3328 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3319 3319 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 331a 331a seq_b_timing 0 Early Condition; Flow J cc=True 0x331b ; Flow J cc=#0x0 0x331b seq_br_type b Case False seq_branch_adr 331b 0x331b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 331b 331b seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 331c 331c fiu_mem_start 3 start-wr; Flow J 0x331f ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 331f 0x331f seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 331d 331d fiu_mem_start 3 start-wr; Flow J 0x3320 seq_br_type 3 Unconditional Branch seq_branch_adr 3320 0x3320 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 331e 331e seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 331f 331f ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 3320 3320 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 07 GP07 val_a_adr 0f GP0f val_b_adr 05 GP05 3321 3321 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3322 3322 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3323 3323 fiu_mem_start 2 start-rd; Flow J cc=True 0x3325 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3325 0x3325 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3324 3324 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3325 ; Flow J cc=#0x0 0x332a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 332a 0x332a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 3325 3325 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3326 ; Flow J cc=#0x0 0x332a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 332a 0x332a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2b TR11:0b typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3326 3326 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3327 3327 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3328 ; Flow J cc=#0x0 0x332a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 332a 0x332a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR11:0c typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3328 3328 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3329 3329 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x332a ; Flow J cc=#0x0 0x332a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 332a 0x332a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR11:0d typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 332a 332a fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x3330 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3330 0x3330 typ_a_adr 04 GP04 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 332b 332b fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x332e fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 332c 332c fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3333 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3333 0x3333 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 332d 332d seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 332e 332e fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_c_adr 3b GP04 332f 332f ioc_load_wdr 0 ; Flow J 0x3331 seq_br_type 3 Unconditional Branch seq_branch_adr 3331 0x3331 seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 3330 3330 ioc_load_wdr 0 ; Flow J 0x3331 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3331 0x3331 seq_en_micro 0 val_b_adr 04 GP04 3331 3331 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3332 3332 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 07 GP07 val_b_adr 05 GP05 3333 3333 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 val_b_adr 05 GP05 3334 3334 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3335 3335 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3336 3336 ioc_adrbs 2 typ ; Flow J cc=True 0x3339 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3339 0x3339 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3337 3337 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3338 3338 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x333b fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 333b 0x333b seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 07 GP07 val_b_adr 07 GP07 3339 3339 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 333a 333a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x333b fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 333b 0x333b seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 29 TR11:09 typ_frame 11 val_b_adr 07 GP07 333b 333b fiu_len_fill_lit 4c zero-fill 0xc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 333c 333c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 3c TR02:1c typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 333d 333d ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 333e 333e seq_br_type a Unconditional Return; Flow R 333f ; -------------------------------------------------------------------------------------- 333f ; Comes from: 333f ; 0236 C from color 0x0000 333f ; -------------------------------------------------------------------------------------- 333f 333f fiu_tivi_src c mar_0xc; Flow C 0x3366 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3366 0x3366 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3340 3340 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x334a fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 334a 0x334a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3341 3341 fiu_load_oreg 1 hold_oreg; Flow J 0x334a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 334a 0x334a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 3342 3342 fiu_mem_start 4 continue; Flow J 0x3343 seq_br_type 2 Push (branch address) seq_branch_adr 3348 0x3348 typ_mar_cntl 6 INCREMENT_MAR 3343 3343 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3344 3344 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3370 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3370 0x3370 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 3345 3345 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 3346 3346 seq_br_type a Unconditional Return; Flow R 3347 ; -------------------------------------------------------------------------------------- 3347 ; Comes from: 3347 ; 024e C from color 0x0000 3347 ; 02c0 C from color 0x0000 3347 ; 2f6b C from color 0x0000 3347 ; 3874 C from color 0x0000 3347 ; -------------------------------------------------------------------------------------- 3347 3347 fiu_tivi_src c mar_0xc; Flow C 0x3366 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3366 0x3366 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3348 3348 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x335c fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 335c 0x335c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3349 3349 fiu_load_oreg 1 hold_oreg; Flow J 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 335c 0x335c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 334a ; -------------------------------------------------------------------------------------- 334a ; Comes from: 334a ; 0239 C False from color 0x0000 334a ; 0251 C False from color 0x0000 334a ; -------------------------------------------------------------------------------------- 334a 334a fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 334b 334b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 334c 334c ioc_fiubs 0 fiu ; Flow J cc=True 0x334d ; Flow J cc=#0x0 0x3352 seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3352 0x3352 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 334d 334d seq_b_timing 0 Early Condition; Flow J cc=True 0x334e ; Flow J cc=#0x0 0x334e seq_br_type b Case False seq_branch_adr 334e 0x334e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 334e 334e seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 334f 334f fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3350 3350 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x334f fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 334f 0x334f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3351 3351 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3352 3352 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3356 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3356 0x3356 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 3353 3353 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x335b fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 335b 0x335b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3354 3354 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x335a fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 335a 0x335a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3355 3355 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3356 3356 fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3357 0x3357 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3357 3357 fiu_mem_start 2 start-rd; Flow J cc=False 0x334a ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 334a 0x334a seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3358 3358 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3359 3359 fiu_mem_start 2 start-rd; Flow J 0x334a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 334a 0x334a seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 335a 335a fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 335b 0x335b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 335b 335b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3356 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3356 0x3356 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 335c ; -------------------------------------------------------------------------------------- 335c ; Comes from: 335c ; 02c4 C from color 0x0000 335c ; 063a C from color 0x0000 335c ; 2f6f C from color 0x0000 335c ; 3878 C from color 0x0000 335c ; -------------------------------------------------------------------------------------- 335c 335c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 335d 335d fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 335e 335e seq_b_timing 0 Early Condition; Flow J cc=True 0x335f ; Flow J cc=#0x0 0x335f seq_br_type b Case False seq_branch_adr 335f 0x335f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 335f 335f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3363 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3363 0x3363 seq_en_micro 0 typ_a_adr 2e TR11:0e typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 3360 3360 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x3365 fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3365 0x3365 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3361 3361 fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3a fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3362 3362 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3363 3363 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False fiu_load_oreg 1 hold_oreg fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3364 0x3364 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3364 3364 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3365 3365 fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3366 ; -------------------------------------------------------------------------------------- 3366 ; Comes from: 3366 ; 333f C from color MACRO_Action_Accept_Activation 3366 ; 3347 C from color 0x2ee7 3366 ; -------------------------------------------------------------------------------------- 3366 3366 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3368 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3368 0x3368 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3367 3367 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x3279 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3368 3368 ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3369 3369 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 336a 336a ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 336b ; -------------------------------------------------------------------------------------- 336b ; Comes from: 336b ; 2ee7 C from color 0x2ee7 336b ; 3938 C from color 0x03fa 336b ; -------------------------------------------------------------------------------------- 336b 336b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 336c 336c fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3370 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3370 0x3370 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 336d ; -------------------------------------------------------------------------------------- 336d ; Comes from: 336d ; 2dc9 C from color 0x2dbf 336d ; -------------------------------------------------------------------------------------- 336d 336d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 336e 336e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 336f 336f fiu_tivi_src c mar_0xc; Flow J 0x3370 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3370 0x3370 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 3370 3370 ioc_fiubs 2 typ typ_a_adr 06 GP06 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3371 3371 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3372 3372 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3373 ; -------------------------------------------------------------------------------------- 3373 ; Comes from: 3373 ; 033e C from color 0x033e 3373 ; 2f24 C from color 0x06b6 3373 ; 3942 C from color 0x0913 3373 ; 397e C from color 0x3976 3373 ; 3a6e C from color 0x3a6e 3373 ; -------------------------------------------------------------------------------------- 3373 3373 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3382 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3382 0x3382 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3374 3374 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a84 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3375 3375 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 3376 3376 fiu_len_fill_lit 6f zero-fill 0x2f; Flow C cc=True 0x3381 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 3381 0x3381 seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 3377 3377 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x338c fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 338c 0x338c seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_frame 2 3378 3378 fiu_len_fill_lit 6b zero-fill 0x2b; Flow J cc=True 0x337e fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 337e 0x337e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3379 3379 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 337a 337a fiu_mem_start 3 start-wr; Flow J cc=True 0x337c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 337c 0x337c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 337b 337b fiu_mem_start 4 continue; Flow J cc=False 0x337b ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 337b 0x337b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 337c 337c ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 337d 337d seq_br_type a Unconditional Return; Flow R 337e 337e ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 337f ; -------------------------------------------------------------------------------------- 337f ; Comes from: 337f ; 022a C from color MACRO_Action_Signal_Activated 337f ; 0233 C from color 0x0000 337f ; 0249 C from color 0x0000 337f ; 0278 C from color 0x0000 337f ; 036d C from color 0x0000 337f ; 055f C from color 0x0000 337f ; 069b C from color 0x0698 337f ; 0756 C from color 0x0203 337f ; 0adf C from color 0x0adf 337f ; 2f90 C from color 0x0000 337f ; 37bc C from color 0x0000 337f ; 382c C from color 0x0000 337f ; 3838 C from color 0x0000 337f ; 3854 C from color 0x0000 337f ; 38e6 C from color 0x0000 337f ; 39e0 C from color 0x0000 337f ; 3a3e C from color 0x0000 337f ; 3a42 C from color 0x0000 337f ; 3aef C from color 0x0000 337f ; 3afd C from color 0x0000 337f ; 3b0b C from color 0x0000 337f ; 3b1a C from color MACRO_3b16_QQUnknown_InMicrocode 337f ; 3b29 C from color 0x0000 337f ; 3b37 C from color 0x0000 337f ; -------------------------------------------------------------------------------------- 337f 337f fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3380 3380 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x337a fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 337a 0x337a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 3381 ; -------------------------------------------------------------------------------------- 3381 ; Comes from: 3381 ; 3376 C True from color 0x0000 3381 ; -------------------------------------------------------------------------------------- 3381 3381 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3651 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3651 0x3651 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3c VR12:1c val_frame 12 3382 3382 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3383 3383 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3384 3384 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 3385 3385 ioc_load_wdr 0 ; Flow J 0x3386 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3386 0x3386 seq_en_micro 0 typ_b_adr 0e GP0e 3386 3386 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3374 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3374 0x3374 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3387 3387 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3388 3388 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3389 3389 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 338a 338a ioc_load_wdr 0 ; Flow J 0x338b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 338b 0x338b seq_en_micro 0 typ_b_adr 0e GP0e 338b 338b fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3391 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3391 0x3391 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 338c 338c fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 338d 338d fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 338e 338e fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 338f 338f ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x337a seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 337a 0x337a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 24 VR02:04 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3390 3390 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3387 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3387 0x3387 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3391 3391 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a84 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3392 3392 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 3393 3393 fiu_len_fill_lit 6f zero-fill 0x2f; Flow J 0x3377 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3377 0x3377 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 3394 ; -------------------------------------------------------------------------------------- 3394 ; Comes from: 3394 ; 0877 C from color 0x0821 3394 ; 2f27 C from color 0x06b6 3394 ; 371e C from color 0x371d 3394 ; 3980 C from color 0x3976 3394 ; -------------------------------------------------------------------------------------- 3394 3394 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x33a8 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33a8 0x33a8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 04 TR02:1b typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_c_adr 03 VR02:1c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3395 3395 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_random 6 load slice timer ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 42 Load_current_lex+Load_control_pred+? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3396 3396 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3397 3397 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 3398 3398 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x33aa ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 33aa 0x33aa seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3399 3399 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x33a5 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33a5 0x33a5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 339a 339a fiu_load_var 1 hold_var; Flow J cc=False 0x33b4 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b4 0x33b4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 339b 339b fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 28 LOOP_COUNTER typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 339c 339c fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x33b4 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b4 0x33b4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 339d 339d fiu_mem_start 2 start-rd; Flow J cc=False 0x33a0 ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33a0 0x33a0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 6 339e 339e ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 339f 339f ioc_random c enable slice timer; Flow R cc=True ; Flow J cc=False 0x33b8 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 33b8 0x33b8 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 33a0 33a0 ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 33a1 33a1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33b8 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b8 0x33b8 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 33a2 33a2 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 33a3 33a3 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33a4 33a4 ioc_random c enable slice timer; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33a5 33a5 ioc_adrbs 3 seq ; Flow J 0x33a6 seq_br_type 2 Push (branch address) seq_branch_adr 07e9 0x07e9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 1a TR02:05 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_c_adr 1a VR02:05 val_frame 2 33a6 33a6 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 33a7 33a7 ioc_random c enable slice timer; Flow R seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 33a8 33a8 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 33a9 33a9 fiu_mem_start 2 start-rd; Flow J 0x3394 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3394 0x3394 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 33aa ; -------------------------------------------------------------------------------------- 33aa ; Comes from: 33aa ; 3398 C True from color 0x3397 33aa ; -------------------------------------------------------------------------------------- 33aa 33aa fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 33ab 0x33ab seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33ab 33ab ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 39 VR02:19 val_frame 2 33ac 33ac fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x33af fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33af 0x33af seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 33ad 33ad fiu_mem_start 2 start-rd; Flow R cc=True ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 33ae 0x33ae seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c val_a_adr 31 VR05:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 33ae 33ae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33af 33af ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33b0 33b0 fiu_mem_start 3 start-wr seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 0c GP0c typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 18 NOT_A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 33b1 33b1 ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0c GP0c val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0c GP0c val_frame 9 33b2 33b2 fiu_mem_start 6 start_rd_if_false; Flow R cc=False ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 33b3 0x33b3 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33b3 33b3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33b4 33b4 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 33b5 33b5 seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 33b6 33b6 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 31 ? val_a_adr 0f GP0f 33b7 33b7 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 31 ? typ_b_adr 3b TR02:1b typ_frame 2 33b8 33b8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33b9 33b9 fiu_mem_start 4 continue seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 33ba 33ba ioc_adrbs 3 seq ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33bb 33bb ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33bc ; -------------------------------------------------------------------------------------- 33bc ; Comes from: 33bc ; 0738 C from color 0x0738 33bc ; 2f29 C from color 0x06b6 33bc ; 3981 C True from color 0x3976 33bc ; -------------------------------------------------------------------------------------- 33bc 33bc fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 40 SEQ.macro_restartable seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33bd 33bd seq_en_micro 0 33be 33be fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33c5 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33c5 0x33c5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 33bf 33bf seq_en_micro 0 33c0 33c0 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33c2 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33c2 0x33c2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 33c1 33c1 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3394 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 3394 0x3394 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33c2 33c2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 33c3 33c3 seq_en_micro 0 33c4 33c4 seq_br_type 3 Unconditional Branch; Flow J 0x33bc seq_branch_adr 33bc 0x33bc 33c5 33c5 ioc_adrbs 3 seq ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33c6 33c6 ioc_fiubs 2 typ ; Flow J cc=True 0x33bc seq_br_type 1 Branch True seq_branch_adr 33bc 0x33bc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 33c7 33c7 seq_br_type 3 Unconditional Branch; Flow J 0x33bc seq_branch_adr 33bc 0x33bc seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 0f GP0f 33c8 ; -------------------------------------------------------------------------------------- 33c8 ; Comes from: 33c8 ; 33e3 C from color 0x0000 33c8 ; 33e7 C from color 0x0000 33c8 ; 3402 C from color 0x22cd 33c8 ; 341a C from color 0x0000 33c8 ; 341e C from color 0x0000 33c8 ; -------------------------------------------------------------------------------------- 33c8 33c8 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 33c9 ; -------------------------------------------------------------------------------------- 33c9 ; Comes from: 33c9 ; 0d40 C from color 0x0000 33c9 ; 0d53 C from color 0x0000 33c9 ; 0d85 C from color 0x0000 33c9 ; 0dab C from color 0x0da1 33c9 ; 0dba C from color 0x0db3 33c9 ; 33e9 C from color 0x0000 33c9 ; 33eb C from color 0x0000 33c9 ; 340b C from color 0x22cd 33c9 ; 3420 C from color 0x0000 33c9 ; 34bb C from color 0x0000 33c9 ; 34cb C from color 0x0000 33c9 ; -------------------------------------------------------------------------------------- 33c9 33c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert ioc_tvbs 3 fiu+fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 33ca 33ca fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 33cb 33cb ioc_tvbs 2 fiu+val; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 30 VR12:10 val_alu_func 18 NOT_A_AND_B val_b_adr 0b GP0b val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33cc 33cc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0b GP0b val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 33cd 33cd fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 25 VR05:05 val_frame 5 33ce 33ce seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 33cf 33cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x33d9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33d9 0x33d9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33d0 33d0 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 33d1 33d1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0c GP0c typ_frame d typ_mar_cntl b LOAD_MAR_DATA 33d2 33d2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 33d3 33d3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 33d4 33d4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 33d5 33d5 fiu_load_tar 1 hold_tar; Flow C 0x34fc fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34fc 0x34fc seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0c GP0c typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_b_adr 0c GP0c 33d6 33d6 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33d7 33d7 fiu_mem_start 10 start_physical_tag_wr; Flow J 0x33d8 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 33d8 33d8 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34cd fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34cd 0x34cd seq_en_micro 0 val_b_adr 0b GP0b 33d9 33d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0xfd2 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 33da 33da fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x33ca fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 33ca 0x33ca seq_en_micro 0 val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 33db 33db seq_b_timing 0 Early Condition; Flow C cc=True 0x104e seq_br_type 5 Call True seq_branch_adr 104e 0x104e seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 33dc 33dc fiu_load_tar 1 hold_tar; Flow C cc=True 0x2a84 fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 0b GP0b val_frame d 33dd 33dd fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 33de 0x33de seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 23 VR0d:03 val_frame d 33de ; -------------------------------------------------------------------------------------- 33de ; Comes from: 33de ; 33f5 C from color 0x0000 33de ; 3450 C from color 0x02c9 33de ; 346b C from color 0x0000 33de ; 3472 C from color 0x3472 33de ; 3493 C from color 0x0d36 33de ; 34d5 C from color 0x34d4 33de ; 34de C from color 0x34de 33de ; -------------------------------------------------------------------------------------- 33de 33de seq_br_type a Unconditional Return; Flow R seq_en_micro 0 33df ; -------------------------------------------------------------------------------------- 33df ; Comes from: 33df ; 33e1 C from color 0x0000 33df ; 3401 C from color 0x22cd 33df ; 3418 C from color 0x0000 33df ; -------------------------------------------------------------------------------------- 33df 33df seq_en_micro 0 33e0 33e0 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 33e1 33e1 seq_br_type 7 Unconditional Call; Flow C 0x33df seq_branch_adr 33df 0x33df typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 33e2 33e2 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 33e3 33e3 fiu_mem_start 2 start-rd; Flow C 0x33c8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c8 0x33c8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33e4 33e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x33e1 seq_br_type 0 Branch False seq_branch_adr 33e1 0x33e1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 33e5 33e5 fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 33e6 33e6 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33e7 33e7 fiu_mem_start 2 start-rd; Flow C 0x33c8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c8 0x33c8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33e8 33e8 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 33e9 33e9 ioc_adrbs 1 val ; Flow C 0x33c9 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33c9 0x33c9 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 33ea 33ea fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x33e2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33e2 0x33e2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 33eb 33eb ioc_adrbs 1 val ; Flow C 0x33c9 seq_br_type 7 Unconditional Call seq_branch_adr 33c9 0x33c9 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 33ec 33ec fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x33f9 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33f9 0x33f9 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 33ed 33ed fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3a VR1b:1a val_frame 1b 33ee 33ee fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 3b TR1b:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR1b:1b val_frame 1b 33ef 33ef fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 28 TR05:08 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 33f0 33f0 fiu_mem_start 4 continue; Flow J cc=False 0x33f0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33f0 0x33f0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT 33f1 33f1 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x33f4 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33f4 0x33f4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 33f2 33f2 fiu_mem_start 3 start-wr; Flow J cc=True 0x33f0 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 33f0 0x33f0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 33f3 33f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 33f4 33f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x33f8 seq_br_type 1 Branch True seq_branch_adr 33f8 0x33f8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 33f5 33f5 fiu_mem_start 2 start-rd; Flow C 0x33de ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 33f6 33f6 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 33f7 33f7 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 val_b_adr 0f GP0f 33f8 33f8 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 21 TR0d:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 33f9 33f9 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 33fa 33fa seq_br_type 7 Unconditional Call; Flow C 0x34fb seq_branch_adr 34fb 0x34fb seq_en_micro 0 33fb 33fb ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33fc 33fc fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 33fd 33fd fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34da fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34da 0x34da seq_en_micro 0 val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 33fe 33fe ioc_adrbs 1 val ; Flow C 0x104e seq_br_type 7 Unconditional Call seq_branch_adr 104e 0x104e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 33ff 33ff fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 3400 3400 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x33e2 fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 33e2 0x33e2 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3401 3401 seq_br_type 7 Unconditional Call; Flow C 0x33df seq_branch_adr 33df 0x33df typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3402 3402 fiu_mem_start 2 start-rd; Flow C 0x33c8 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33c8 0x33c8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_source 0 FIU_BUS val_frame d val_rand a PASS_B_HIGH 3403 3403 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3401 seq_br_type 0 Branch False seq_branch_adr 3401 0x3401 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 3404 3404 fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 3405 3405 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3406 3406 fiu_mem_start 11 start_tag_query; Flow C 0x34f3 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3407 3407 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x340b fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 340b 0x340b seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3408 3408 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=False 0x340a fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 340a 0x340a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0d GP0d typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3409 3409 ioc_load_wdr 0 ; Flow J 0x340a seq_br_type 3 Unconditional Branch seq_branch_adr 340a 0x340a seq_en_micro 0 val_b_adr 0d GP0d 340a 340a fiu_mem_start 2 start-rd; Flow J 0x340e fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 340e 0x340e seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 340b 340b seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 340c 340c fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3402 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3402 0x3402 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 340d 340d fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 340e 340e fiu_mem_start 4 continue ioc_fiubs 0 fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d 340f 340f fiu_load_var 1 hold_var; Flow J cc=False 0x3416 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3416 0x3416 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3410 3410 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3411 3411 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 7 3412 3412 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 3413 3413 fiu_mem_start 9 start_continue_if_true; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 1 typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR12:14 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 12 3414 3414 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3415 3415 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_b_adr 22 VR0d:02 val_frame d 3416 3416 fiu_mem_start 11 start_tag_query; Flow C 0x3495 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3495 0x3495 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3417 3417 fiu_len_fill_reg_ctl 2 ; Flow J 0x3402 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3402 0x3402 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3418 3418 seq_br_type 7 Unconditional Call; Flow C 0x33df seq_branch_adr 33df 0x33df typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3419 3419 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 341a 341a fiu_mem_start 2 start-rd; Flow C 0x33c8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c8 0x33c8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 341b 341b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3418 seq_br_type 0 Branch False seq_branch_adr 3418 0x3418 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 341c 341c fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 341d 341d ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 341e 341e fiu_mem_start 2 start-rd; Flow C 0x33c8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c8 0x33c8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 341f 341f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 3420 3420 ioc_adrbs 1 val ; Flow C 0x33c9 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33c9 0x33c9 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3421 3421 fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3419 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3419 0x3419 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3422 3422 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR07:17 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3423 3423 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3424 3424 fiu_mem_start 4 continue; Flow J cc=False 0x3424 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3424 0x3424 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3425 3425 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x2a84 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3426 ; -------------------------------------------------------------------------------------- 3426 ; Comes from: 3426 ; 3459 C from color 0x02c9 3426 ; 3482 C from color 0x0f07 3426 ; 3488 C from color 0x0f07 3426 ; 348b C from color 0x0f07 3426 ; -------------------------------------------------------------------------------------- 3426 3426 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2a84 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR02:13 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3427 3427 fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR02:13 val_alu_func 18 NOT_A_AND_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3428 3428 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3429 0x3429 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3429 3429 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3436 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3436 0x3436 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3b VR12:1b val_frame 12 342a 342a seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 342b 342b fiu_tivi_src 1 tar_val; Flow J cc=False 0x3430 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3430 0x3430 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 342c 342c fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x342f fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 342f 0x342f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 342d 342d fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x342f ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 342f 0x342f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 342e 342e ioc_load_wdr 0 ; Flow J 0x3430 seq_br_type 3 Unconditional Branch seq_branch_adr 3430 0x3430 seq_en_micro 0 val_b_adr 0f GP0f 342f 342f ioc_load_wdr 0 ; Flow C 0x34da seq_br_type 7 Unconditional Call seq_branch_adr 34da 0x34da seq_en_micro 0 val_b_adr 0f GP0f 3430 3430 fiu_mem_start 11 start_tag_query; Flow J cc=False 0x3433 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3433 0x3433 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 4 RESTORE_MAR val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 3431 3431 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 3432 3432 fiu_mem_start 11 start_tag_query seq_en_micro 0 3433 3433 seq_br_type 1 Branch True; Flow J cc=True 0x342a seq_branch_adr 342a 0x342a seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d 3434 3434 fiu_tivi_src 2 tar_fiu; Flow R cc=True ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3435 0x3435 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3435 3435 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3436 3436 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 3f TR06:1f typ_frame 6 val_a_adr 2c VR0d:0c val_b_adr 16 CSA/VAL_BUS val_frame d val_rand c START_MULTIPLY 3437 3437 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3449 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3449 0x3449 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3438 3438 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x343b seq_br_type 0 Branch False seq_branch_adr 343b 0x343b seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3439 3439 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 343a 343a fiu_mem_start 14 start_name_query; Flow J 0x3438 seq_br_type 3 Unconditional Branch seq_branch_adr 3438 0x3438 seq_en_micro 0 343b 343b fiu_tivi_src 3 tar_frame; Flow J cc=False 0x3449 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3449 0x3449 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 4 343c 343c fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR05:11 typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 343d 343d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3440 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3440 0x3440 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS 343e 343e seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 343f 343f fiu_mem_start f start_physical_tag_rd; Flow J 0x343d seq_br_type 3 Unconditional Branch seq_branch_adr 343d 0x343d seq_en_micro 0 3440 3440 fiu_mem_start 15 setup_tag_read; Flow J cc=False 0x3448 seq_br_type 0 Branch False seq_branch_adr 3448 0x3448 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3441 3441 fiu_len_fill_lit 5c zero-fill 0x1c; Flow J cc=False 0x3448 fiu_mem_start 15 setup_tag_read fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 3448 0x3448 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3442 3442 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3448 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 3448 0x3448 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f 3443 3443 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3445 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3445 0x3445 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3444 3444 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3448 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3448 0x3448 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0b GP0b typ_frame 1 3445 3445 ioc_load_wdr 0 ; Flow J cc=True 0x344c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 344c 0x344c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 3446 3446 seq_br_type 0 Branch False; Flow J cc=False 0x3448 seq_branch_adr 3448 0x3448 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3447 3447 seq_br_type 5 Call True; Flow C cc=True 0x34da seq_branch_adr 34da 0x34da seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 3448 3448 fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x343d fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 343d 0x343d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 31 TR05:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 6 A_MINUS_B val_b_adr 29 VR08:09 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 8 3449 3449 fiu_mem_start 14 start_name_query; Flow J cc=True 0x3438 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3438 0x3438 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3f VR06:1f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 344a 344a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 344b 0x344b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 344b 344b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 344c 344c fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3447 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3447 0x3447 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 344d 344d ioc_load_wdr 0 ; Flow J 0x3448 seq_br_type 3 Unconditional Branch seq_branch_adr 3448 0x3448 seq_en_micro 0 val_b_adr 0f GP0f 344e 344e fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 344f ; -------------------------------------------------------------------------------------- 344f ; Comes from: 344f ; 3467 C True from color 0x0000 344f ; -------------------------------------------------------------------------------------- 344f 344f fiu_tivi_src c mar_0xc; Flow C 0x362a ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 362a 0x362a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 3450 3450 fiu_mem_start 2 start-rd; Flow C 0x33de ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3451 3451 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3452 seq_br_type 2 Push (branch address) seq_branch_adr 344e 0x344e seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3452 3452 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3453 3453 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3456 seq_br_type 1 Branch True seq_branch_adr 3456 0x3456 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 3454 3454 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 3455 3455 ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0c GP0c val_b_adr 0c GP0c 3456 3456 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362c 0x362c seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 3457 3457 seq_en_micro 0 3458 3458 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3459 3459 fiu_load_oreg 1 hold_oreg; Flow C 0x3426 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 345a 345a fiu_tivi_src c mar_0xc; Flow R cc=False ; Flow J cc=True 0x344f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 344f 0x344f seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 345b 345b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x345c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 345c 0x345c typ_mar_cntl 6 INCREMENT_MAR 345c ; -------------------------------------------------------------------------------------- 345c ; Comes from: 345c ; 3466 C from color 0x0000 345c ; -------------------------------------------------------------------------------------- 345c 345c fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 345d 345d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 345e 345e fiu_load_oreg 1 hold_oreg ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_frame d val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 345f 345f ioc_adrbs 2 typ ; Flow C 0x3426 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_a_adr 2c TR12:0c typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3460 3460 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 3461 3461 fiu_load_oreg 1 hold_oreg; Flow C 0x3426 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3462 3462 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3463 3463 fiu_load_oreg 1 hold_oreg; Flow C 0x3426 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3464 3464 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3465 3465 fiu_load_oreg 1 hold_oreg; Flow J 0x3426 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3466 3466 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x345c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 345c 0x345c typ_mar_cntl 6 INCREMENT_MAR 3467 3467 fiu_tivi_src c mar_0xc; Flow C cc=True 0x344f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 344f 0x344f seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d val_rand a PASS_B_HIGH 3468 3468 ioc_adrbs 1 val ; Flow J 0x3469 seq_br_type 3 Unconditional Branch seq_branch_adr 3469 0x3469 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 3469 3469 fiu_mem_start 11 start_tag_query; Flow C 0x3495 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3495 0x3495 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 346a 346a fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x346e fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 346e 0x346e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 3 346b 346b fiu_mem_start 2 start-rd; Flow C 0x33de ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 346c 346c fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 346d 346d ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 0b GP0b 346e 346e fiu_mem_start 2 start-rd; Flow J 0x346f ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 347c 0x347c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 4 val_rand a PASS_B_HIGH 346f 346f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 36 TR07:16 typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 3470 3470 fiu_len_fill_lit 48 zero-fill 0x8; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_b_adr 16 CSA/VAL_BUS 3471 3471 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3472 3472 fiu_mem_start 2 start-rd; Flow C 0x33de fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 3473 3473 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3474 3474 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 1 typ_frame 1 val_b_adr 0c GP0c 3475 3475 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3476 3476 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 3477 3477 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 3478 3478 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3479 3479 fiu_mem_start 15 setup_tag_read fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR02:11 typ_frame 2 val_a_adr 2b VR12:0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 347a 347a ioc_tvbs a fiu+mem; Flow J cc=False 0x3498 seq_br_type 0 Branch False seq_branch_adr 3498 0x3498 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 347b 347b fiu_mem_start 10 start_physical_tag_wr; Flow J 0x349c seq_br_type 3 Unconditional Branch seq_branch_adr 349c 0x349c seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 347c 347c ioc_adrbs 1 val ; Flow J 0x3b75 seq_br_type 3 Unconditional Branch seq_branch_adr 3b75 0x3b75 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 347d ; -------------------------------------------------------------------------------------- 347d ; Comes from: 347d ; 027c C from color 0x0000 347d ; -------------------------------------------------------------------------------------- 347d 347d fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 347e 347e fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 347f 347f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d 3480 3480 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f 3481 3481 ioc_tvbs 2 fiu+val; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 3482 3482 fiu_load_oreg 1 hold_oreg; Flow C 0x3426 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3483 3483 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 13 ONES typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d 3484 3484 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x34f4 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 3485 3485 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x349b fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 349b 0x349b seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 3486 3486 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 3487 3487 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 3488 3488 fiu_load_oreg 1 hold_oreg; Flow C 0x3426 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3489 3489 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 348a 348a fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR02:01 val_frame 2 348b 348b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3426 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3426 0x3426 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 348c 348c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR0d:05 val_alu_func 1a PASS_B val_b_adr 0d GP0d val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d val_rand 9 PASS_A_HIGH 348d 348d fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR0d:04 val_frame d 348e 348e ioc_load_wdr 0 ; Flow J 0x33de seq_br_type 3 Unconditional Branch seq_branch_adr 33de 0x33de seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 348f ; -------------------------------------------------------------------------------------- 348f ; Comes from: 348f ; 2ac8 C from color 0x2abf 348f ; -------------------------------------------------------------------------------------- 348f 348f fiu_mem_start 4 continue fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 3490 3490 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3491 3491 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR07:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 3492 3492 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f 3493 3493 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33de fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3494 3494 fiu_load_oreg 1 hold_oreg; Flow J 0x3426 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3426 0x3426 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3495 ; -------------------------------------------------------------------------------------- 3495 ; Comes from: 3495 ; 027d C True from color 0x0000 3495 ; 0d9f C False from color 0x0000 3495 ; 0daf C from color 0x0da1 3495 ; 3416 C from color 0x22cd 3495 ; 3469 C from color 0x0000 3495 ; -------------------------------------------------------------------------------------- 3495 3495 seq_br_type 7 Unconditional Call; Flow C 0x34f4 seq_branch_adr 34f4 0x34f4 seq_en_micro 0 3496 3496 fiu_mem_start 15 setup_tag_read; Flow R cc=False ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 3497 0x3497 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3497 3497 fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3498 3498 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3499 3499 ioc_load_wdr 0 ; Flow C 0x34da seq_br_type 7 Unconditional Call seq_branch_adr 34da 0x34da seq_en_micro 0 val_b_adr 0f GP0f 349a 349a seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 349b ; -------------------------------------------------------------------------------------- 349b ; Comes from: 349b ; 3485 C True from color 0x0f07 349b ; -------------------------------------------------------------------------------------- 349b 349b fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 349c 349c ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 0f GP0f 349d ; -------------------------------------------------------------------------------------- 349d ; Comes from: 349d ; 0305 C from color 0x0000 349d ; 0405 C from color 0x03f0 349d ; 05b8 C from color 0x05a7 349d ; 06e0 C from color 0x06ce 349d ; 0919 C from color 0x0000 349d ; 0959 C from color MACRO_Execute_Module,Is_Callable 349d ; 0963 C from color MACRO_Execute_Module,Is_Callable 349d ; 097d C from color MACRO_Execute_Module,Is_Callable 349d ; 0b6e C from color 0x0000 349d ; 0db3 C from color 0x0db3 349d ; 2d41 C from color ML_break_class 349d ; 2ea9 C from color 0x0000 349d ; 2ee2 C from color 0x2ec9 349d ; 2f49 C from color 0x06b6 349d ; 32b8 C from color 0x0000 349d ; 32ba C from color 0x0000 349d ; 33c5 C from color 0x0000 349d ; 34be C from color 0x0000 349d ; 396b C from color 0x03fa 349d ; 39ac C from color 0x0000 349d ; 39c1 C from color 0x0000 349d ; 3a1d C from color 0x0000 349d ; 3a39 C from color 0x3a39 349d ; 3a6a C from color 0x0000 349d ; 3ada C from color 0x3ad9 349d ; 3b43 C from color 0x0000 349d ; -------------------------------------------------------------------------------------- 349d 349d fiu_mem_start 11 start_tag_query ioc_tvbs 3 fiu+fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 349e 349e fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 349f 349f seq_br_type 7 Unconditional Call; Flow C 0x34f5 seq_branch_adr 34f5 0x34f5 seq_en_micro 0 34a0 34a0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x34a9 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 34a9 0x34a9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 34a1 34a1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x34a2 ; Flow J cc=#0x0 0x34a2 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 34a2 0x34a2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 34a2 34a2 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 34a3 34a3 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34a4 34a4 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34a5 34a5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0xefc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 0efc 0x0efc seq_en_micro 0 val_c_adr 30 GP0f 34a6 34a6 fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34a7 34a7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 34a8 34a8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x349d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 349d 0x349d seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 23 VR0d:03 val_b_adr 21 VR0d:01 val_frame d 34a9 34a9 seq_b_timing 1 Latch Condition; Flow C cc=False 0xfba seq_br_type 4 Call False seq_branch_adr 0fba 0x0fba seq_en_micro 0 34aa 34aa fiu_len_fill_reg_ctl 2 ; Flow J 0x34a7 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34a7 0x34a7 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34ab 34ab fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34ac ; -------------------------------------------------------------------------------------- 34ac ; Comes from: 34ac ; 2f25 C from color 0x06b6 34ac ; 3669 C from color 0x0200 34ac ; 3934 C from color 0x062d 34ac ; 3a24 C from color 0x03fa 34ac ; -------------------------------------------------------------------------------------- 34ac 34ac seq_en_micro 0 34ad 34ad fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34ae ; -------------------------------------------------------------------------------------- 34ae ; Comes from: 34ae ; 2f45 C from color 0x06b6 34ae ; 3997 C from color 0x398f 34ae ; -------------------------------------------------------------------------------------- 34ae 34ae seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34af 34af seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 34b0 0x34b0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34b0 34b0 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x34b3 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34b3 0x34b3 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34b1 34b1 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 34b2 34b2 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34b3 34b3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34b4 34b4 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34b5 34b5 fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34b6 34b6 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34b7 34b7 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34ab ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ab 0x34ab seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34b8 34b8 fiu_mem_start 11 start_tag_query; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34b9 0x34b9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0b GP0b val_frame 5 34b9 34b9 seq_en_micro 0 34ba 34ba fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34ab seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ab 0x34ab seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34bb 34bb seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 34bc 34bc fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34ac fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34ac 0x34ac seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34bd 34bd fiu_tivi_src c mar_0xc; Flow J 0x34be ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 34be 0x34be seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34be 34be seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_en_micro 0 34bf 34bf fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34c1 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 34c1 0x34c1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34c0 ; -------------------------------------------------------------------------------------- 34c0 ; Comes from: 34c0 ; 0378 C from color 0x0377 34c0 ; 2ef3 C from color 0x2ee7 34c0 ; 2f0d C from color 0x2ec9 34c0 ; 3943 C from color 0x0913 34c0 ; 3961 C from color 0x03fa 34c0 ; -------------------------------------------------------------------------------------- 34c0 34c0 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34c1 34c1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x34bd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34bd 0x34bd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34c2 34c2 fiu_mem_start 6 start_rd_if_false; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 34c3 0x34c3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34c3 34c3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34c4 34c4 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34c5 34c5 fiu_tivi_src c mar_0xc; Flow C 0x34f6 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f6 0x34f6 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34c6 34c6 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34c7 34c7 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34be ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34be 0x34be seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34c8 34c8 fiu_mem_start 11 start_tag_query; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34c9 0x34c9 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 2d VR05:0d val_frame 5 34c9 34c9 seq_en_micro 0 34ca 34ca fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34be seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34be 0x34be seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34cb 34cb seq_br_type 7 Unconditional Call; Flow C 0x33c9 seq_branch_adr 33c9 0x33c9 seq_en_micro 0 34cc 34cc fiu_mem_start 6 start_rd_if_false; Flow R cc=False ; Flow J cc=True 0x34c0 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34c0 0x34c0 seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34cd ; -------------------------------------------------------------------------------------- 34cd ; Comes from: 34cd ; 08a7 C from color 0x08a5 34cd ; 0f8c C from color 0x0efa 34cd ; -------------------------------------------------------------------------------------- 34cd 34cd fiu_mem_start f start_physical_tag_rd; Flow C 0x34e3 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 34e3 0x34e3 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 34ce ; -------------------------------------------------------------------------------------- 34ce ; Comes from: 34ce ; 0dd5 C from color 0x0000 34ce ; -------------------------------------------------------------------------------------- 34ce 34ce fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 21 VR11:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 34cf 34cf fiu_load_var 1 hold_var; Flow J cc=False 0x34d1 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 34d1 0x34d1 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_frame 3 34d0 34d0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 34d1 34d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_source 0 FIU_BUS 34d2 34d2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 34d3 34d3 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 7 INC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 34d4 34d4 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x2a84 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 34d5 34d5 fiu_mem_start 2 start-rd; Flow C 0x33de ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 34d6 34d6 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 34d7 34d7 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 0d GP0d 34d8 34d8 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 34d9 34d9 fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0x34db fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34db 0x34db seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 34da ; -------------------------------------------------------------------------------------- 34da ; Comes from: 34da ; 0ff2 C from color 0x0ff2 34da ; 1023 C from color 0x0fd2 34da ; 107b C from color 0x107b 34da ; 342f C from color 0x0d36 34da ; 3447 C True from color 0x0d36 34da ; -------------------------------------------------------------------------------------- 34da 34da fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x34e1 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34e1 0x34e1 seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 34db 34db fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 34dc 34dc fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 34dd 34dd fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 34de 34de fiu_mem_start 2 start-rd; Flow C 0x33de fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33de 0x33de seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 34df 34df fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 34e0 34e0 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 34e1 34e1 seq_en_micro 0 typ_c_adr 1c TR0c:03 typ_frame c val_c_adr 1c VR0c:03 val_frame c 34e2 34e2 fiu_mem_start f start_physical_tag_rd; Flow J 0x34e4 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 34e4 0x34e4 seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 1d TR0c:02 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34e3 ; -------------------------------------------------------------------------------------- 34e3 ; Comes from: 34e3 ; 34cd C from color 0x0f07 34e3 ; -------------------------------------------------------------------------------------- 34e3 34e3 fiu_mem_start 15 setup_tag_read; Flow J 0x34e5 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34e5 0x34e5 seq_en_micro 0 typ_c_adr 1d TR0c:02 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 31 VR02:11 val_frame 2 34e4 34e4 fiu_mem_start 15 setup_tag_read seq_en_micro 0 34e5 34e5 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x34ed fiu_mem_start 15 setup_tag_read fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ed 0x34ed seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 29 VR0c:09 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 34e6 34e6 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x34ed fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ed 0x34ed seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 19 X_XOR_B val_b_adr 26 VR0c:06 val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 34e7 34e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x34f2 seq_br_type 1 Branch True seq_branch_adr 34f2 0x34f2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 34e8 34e8 fiu_mem_start 2 start-rd; Flow J 0x34e9 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 34ec 0x34ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 22 TR0c:02 typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 25 VR0c:05 val_frame c 34e9 34e9 seq_b_timing 0 Early Condition; Flow J cc=True 0x34ef seq_br_type 1 Branch True seq_branch_adr 34ef 0x34ef seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 34ea 34ea fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x34ee fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ee 0x34ee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 28 VR0c:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 34eb 34eb fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34ec 34ec ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0c:04 typ_frame c val_b_adr 24 VR0c:04 val_frame c 34ed 34ed ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 23 TR0c:03 typ_frame c val_b_adr 23 VR0c:03 val_frame c 34ee 34ee fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 24 TR0c:04 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR0c:07 typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c 34ef 34ef fiu_tivi_src 1 tar_val; Flow J cc=True 0x34f1 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34f1 0x34f1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_source 0 FIU_BUS val_frame c val_rand 9 PASS_A_HIGH 34f0 34f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x34ee seq_br_type 1 Branch True seq_branch_adr 34ee 0x34ee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 24 TR0c:04 typ_frame c val_a_adr 24 VR0c:04 val_alu_func 1c DEC_A val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 34f1 34f1 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34f2 34f2 seq_br_type 3 Unconditional Branch; Flow J 0x34ed seq_branch_adr 34ed 0x34ed seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR0c:02 typ_c_adr 1a TR0c:05 typ_c_mux_sel 0 ALU typ_frame c 34f3 ; -------------------------------------------------------------------------------------- 34f3 ; Comes from: 34f3 ; 0d55 C from color 0x0000 34f3 ; 0e03 C from color 0x0000 34f3 ; 0eaa C from color 0x0000 34f3 ; 0ed8 C from color 0x0ed8 34f3 ; 100b C from color 0x0fd2 34f3 ; 3406 C from color 0x22cd 34f3 ; -------------------------------------------------------------------------------------- 34f3 34f3 seq_en_micro 0 34f4 ; -------------------------------------------------------------------------------------- 34f4 ; Comes from: 34f4 ; 0f7c C from color 0x0efa 34f4 ; 2ac6 C from color 0x2abf 34f4 ; 3484 C from color 0x0f07 34f4 ; 3495 C from color 0x3495 34f4 ; 3b5f C from color 0x3b5f 34f4 ; -------------------------------------------------------------------------------------- 34f4 34f4 seq_en_micro 0 34f5 ; -------------------------------------------------------------------------------------- 34f5 ; Comes from: 34f5 ; 084a C from color 0x0820 34f5 ; 0d45 C from color 0x0000 34f5 ; 0d89 C from color 0x0000 34f5 ; 0ef2 C from color 0x0000 34f5 ; 0f80 C from color 0x0efa 34f5 ; 0fa5 C from color 0x0efa 34f5 ; 0fb1 C from color 0x0efa 34f5 ; 1033 C from color 0x0fd2 34f5 ; 103b C from color 0x0fd2 34f5 ; 33ce C from color 0x0f07 34f5 ; 342a C from color 0x0d36 34f5 ; 349f C from color 0x349d 34f5 ; -------------------------------------------------------------------------------------- 34f5 34f5 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34f6 ; -------------------------------------------------------------------------------------- 34f6 ; Comes from: 34f6 ; 101f C from color 0x0fd2 34f6 ; 1060 C from color 0x0000 34f6 ; 33e5 C from color 0x0000 34f6 ; 3404 C from color 0x22cd 34f6 ; 341c C from color 0x0000 34f6 ; 34b5 C from color 0x0000 34f6 ; 34c5 C from color 0x0000 34f6 ; -------------------------------------------------------------------------------------- 34f6 34f6 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x34f9 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 34f9 0x34f9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34f7 34f7 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 34f8 34f8 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 34f9 34f9 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 34fa 34fa fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 34fb ; -------------------------------------------------------------------------------------- 34fb ; Comes from: 34fb ; 33fa C from color 0x0000 34fb ; 39ef C from color 0x0000 34fb ; 3a14 C from color 0x0000 34fb ; -------------------------------------------------------------------------------------- 34fb 34fb fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34fc ; -------------------------------------------------------------------------------------- 34fc ; Comes from: 34fc ; 08e1 C from color 0x0127 34fc ; 0b88 C from color 0x0b85 34fc ; 0b8b C from color 0x0b85 34fc ; 0e10 C from color 0x0000 34fc ; 0f0d C from color 0x0000 34fc ; 0f9e C from color 0x0efa 34fc ; 0ff8 C from color 0x0fd2 34fc ; 0ffe C from color 0x0fd2 34fc ; 1078 C from color 0x0efa 34fc ; 1081 C from color 0x0efa 34fc ; 33d5 C from color 0x0f07 34fc ; -------------------------------------------------------------------------------------- 34fc 34fc fiu_mem_start 15 setup_tag_read; Flow R seq_br_type a Unconditional Return seq_en_micro 0 34fd ; -------------------------------------------------------------------------------------- 34fd ; Comes from: 34fd ; 2aff C from color 0x2afb 34fd ; -------------------------------------------------------------------------------------- 34fd 34fd fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x3511 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3511 0x3511 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 34fe 34fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3506 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3506 0x3506 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 34ff 34ff ioc_fiubs 0 fiu ; Flow C cc=False 0x329c ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 329c 0x329c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3500 3500 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3501 3501 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x3507 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3507 0x3507 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 3502 3502 ioc_fiubs 0 fiu ; Flow J cc=False 0x3504 seq_br_type 0 Branch False seq_branch_adr 3504 0x3504 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 33 VR02:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 3503 3503 fiu_mem_start 3 start-wr; Flow J cc=True 0x3504 ; Flow J cc=#0x0 0x3509 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3509 0x3509 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3504 3504 ioc_fiubs 0 fiu 3505 3505 seq_b_timing 0 Early Condition; Flow J cc=True 0x3506 ; Flow J cc=#0x0 0x3509 seq_br_type b Case False seq_branch_adr 3509 0x3509 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3506 3506 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3507 3507 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3508 0x3508 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3508 3508 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 3509 3509 ioc_load_wdr 0 ; Flow J 0x3510 seq_br_type 3 Unconditional Branch seq_branch_adr 3510 0x3510 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 350a 350a ioc_load_wdr 0 ; Flow J 0x3510 seq_br_type 3 Unconditional Branch seq_branch_adr 3510 0x3510 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 350b 350b ioc_load_wdr 0 ; Flow J 0x3510 seq_br_type 3 Unconditional Branch seq_branch_adr 3510 0x3510 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 350c 350c seq_br_type 7 Unconditional Call; Flow C 0x330d seq_branch_adr 330d 0x330d seq_random 05 ? 350d 350d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_random 02 ? val_a_adr 06 GP06 350e 350e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 45 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR07:18 val_alu_func 1a PASS_B val_frame 7 350f 350f ioc_load_wdr 0 ; Flow J 0x3510 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3510 0x3510 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3510 3510 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3511 3511 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x329c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_frame 2 3512 3512 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 3c TR07:1c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 3513 3513 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 39 TR02:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3514 3514 fiu_mem_start 3 start-wr; Flow J cc=True 0x3515 ; Flow J cc=#0x0 0x3509 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3509 0x3509 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3515 3515 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32ac fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3516 3516 ioc_fiubs 0 fiu ; Flow C cc=True 0x351a ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 351a 0x351a seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3517 3517 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3518 0x3518 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 06 GP06 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3518 3518 seq_br_type 4 Call False; Flow C cc=False 0x32a0 seq_branch_adr 32a0 0x32a0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 3519 3519 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a0 seq_br_type 9 Return False seq_branch_adr 32a0 0x32a0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 351a ; -------------------------------------------------------------------------------------- 351a ; Comes from: 351a ; 3516 C True from color 0x0000 351a ; -------------------------------------------------------------------------------------- 351a 351a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3520 seq_br_type 1 Branch True seq_branch_adr 3520 0x3520 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 351b 351b typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 351c 351c typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 351d 351d typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 351e 351e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 351f 351f ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3520 3520 seq_br_type a Unconditional Return; Flow R val_a_adr 08 GP08 val_alu_func 7 INC_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3521 3521 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3522 3522 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3523 3523 ioc_fiubs 0 fiu ; Flow J cc=True 0x3576 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3576 0x3576 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 3524 3524 seq_br_type 3 Unconditional Branch; Flow J 0x3526 seq_branch_adr 3526 0x3526 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3525 3525 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3577 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3577 0x3577 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_rand 9 PASS_A_HIGH 3526 3526 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0f GP0f 3527 3527 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x352e ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 352e 0x352e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 3528 3528 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3531 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3531 0x3531 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3529 3529 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_b_adr 06 GP06 352a 352a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 352b 352b fiu_length_src 0 length_register; Flow J cc=False 0x3543 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 3543 0x3543 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_c_adr 31 GP0e val_c_source 0 FIU_BUS 352c 352c seq_br_type 2 Push (branch address); Flow J 0x352d seq_branch_adr 3525 0x3525 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 352d 352d seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 352e 352e fiu_load_var 1 hold_var; Flow J cc=False 0x353b fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 353b 0x353b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 352f 352f fiu_load_tar 1 hold_tar; Flow J cc=True 0x3529 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3529 0x3529 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3530 3530 seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 3531 3531 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x3575 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3575 0x3575 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand 1 INC_LOOP_COUNTER 3532 3532 fiu_tivi_src 1 tar_val; Flow J cc=True 0x353f ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 353f 0x353f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3533 3533 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3534 3534 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3538 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3538 0x3538 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3535 3535 fiu_length_src 0 length_register; Flow J cc=False 0x3541 fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3541 0x3541 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3536 3536 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3541 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3541 0x3541 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3537 3537 fiu_load_oreg 1 hold_oreg; Flow J 0x3529 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3529 0x3529 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0d GP0d 3538 3538 fiu_load_var 1 hold_var; Flow J cc=False 0x3541 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3541 0x3541 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3539 3539 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 353a 353a fiu_length_src 0 length_register; Flow J 0x3536 fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 3536 0x3536 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 353b 353b fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 353c 353c fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x210 fiu_mem_start a start_continue_if_false fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 353d 353d ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 353e 353e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3533 seq_br_type 1 Branch True seq_branch_adr 3533 0x3533 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 353f 353f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3540 3540 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3522 seq_br_type 3 Unconditional Branch seq_branch_adr 3522 0x3522 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3541 3541 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3542 3542 seq_br_type 3 Unconditional Branch; Flow J 0x3522 seq_branch_adr 3522 0x3522 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3543 3543 fiu_length_src 0 length_register; Flow J cc=True 0x354c fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 354c 0x354c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 3544 3544 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3545 3545 fiu_fill_mode_src 0 ; Flow J cc=False 0x3548 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3548 0x3548 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3546 3546 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3547 3547 ioc_load_wdr 0 ; Flow J 0x354e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 354e 0x354e seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3548 3548 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3549 3549 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 354a 354a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 354b 354b ioc_load_wdr 0 ; Flow J 0x354e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 354e 0x354e val_b_adr 0e GP0e 354c 354c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 354d 354d ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 354e 354e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 354f 354f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 07 GP07 3550 3550 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 35 TR02:15 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f 3551 3551 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3554 ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3554 0x3554 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 37 GP08 val_c_source 0 FIU_BUS 3552 3552 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA 3553 3553 ioc_load_wdr 0 ; Flow J 0x3558 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3558 0x3558 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 3554 3554 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 3555 3555 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3556 3556 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR 3557 3557 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 3558 3558 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3594 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3594 0x3594 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_b_adr 07 GP07 3559 3559 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 355a 355a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_b_adr 06 GP06 355b 355b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 355c 355c seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 13 355d 355d seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 355e 355e fiu_fill_mode_src 0 ; Flow J cc=True 0x356a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 356a 0x356a seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 355f 355f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3560 3560 fiu_fill_mode_src 0 ; Flow J cc=False 0x356c fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 356c 0x356c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3561 3561 fiu_fill_mode_src 0 ; Flow C cc=False 0x3573 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3573 0x3573 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3562 3562 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3563 3563 fiu_mem_start 7 start_wr_if_true ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3564 3564 ioc_load_wdr 0 ; Flow J cc=True 0x3594 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3594 0x3594 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 val_b_adr 06 GP06 3565 3565 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3566 3566 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3567 3567 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3568 3568 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 3569 3569 fiu_fill_mode_src 0 ; Flow J 0x355f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 355f 0x355f val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 356a 356a seq_br_type 0 Branch False; Flow J cc=False 0x3594 seq_branch_adr 3594 0x3594 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 356b 356b seq_br_type 3 Unconditional Branch; Flow J 0x3568 seq_branch_adr 3568 0x3568 typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 356c 356c fiu_fill_mode_src 0 ; Flow C cc=False 0x3570 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3570 0x3570 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 356d 356d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 356e 356e fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 356f 356f ioc_load_wdr 0 ; Flow J 0x3563 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3563 0x3563 val_b_adr 0e GP0e 3570 ; -------------------------------------------------------------------------------------- 3570 ; Comes from: 3570 ; 356c C False from color 0x0000 3570 ; -------------------------------------------------------------------------------------- 3570 3570 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 3571 3571 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3572 3572 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 3573 ; -------------------------------------------------------------------------------------- 3573 ; Comes from: 3573 ; 3561 C False from color 0x0000 3573 ; -------------------------------------------------------------------------------------- 3573 3573 fiu_mem_start 2 start-rd; Flow C 0x3575 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 3575 0x3575 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 3574 3574 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3575 ; -------------------------------------------------------------------------------------- 3575 ; Comes from: 3575 ; 1b25 C from color MACRO_Execute_Access,Deallocate 3575 ; 3531 C from color 0x0000 3575 ; 3573 C from color 0x3573 3575 ; -------------------------------------------------------------------------------------- 3575 3575 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3576 3576 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 3577 3577 ioc_tvbs 1 typ+fiu val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3578 3578 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32ac fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3579 3579 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS 357a 357a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x358a seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 358a 0x358a seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 357b 357b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a0 seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 357c 357c seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 357d 357d ioc_fiubs 2 typ ; Flow J cc=True 0x3584 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3584 0x3584 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 357e 357e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 08 GP08 357f 357f ioc_load_wdr 0 ; Flow J cc=False 0x3587 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3587 0x3587 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 06 GP06 3580 3580 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x3587 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 3587 0x3587 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 3581 3581 fiu_fill_mode_src 0 ; Flow J cc=False 0x3590 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3590 0x3590 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 3582 3582 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3583 3583 ioc_load_wdr 0 ; Flow J 0x3594 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3594 0x3594 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 3584 3584 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3585 3585 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x357e seq_br_type 0 Branch False seq_branch_adr 357e 0x357e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3586 3586 seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 3587 3587 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3588 3588 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3589 3589 fiu_load_var 1 hold_var; Flow J 0x3577 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3577 0x3577 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 358a ; -------------------------------------------------------------------------------------- 358a ; Comes from: 358a ; 357a C True from color 0x0000 358a ; -------------------------------------------------------------------------------------- 358a 358a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3520 seq_br_type 1 Branch True seq_branch_adr 3520 0x3520 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 358b 358b typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 358c 358c typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 7 358d 358d typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 358e 358e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 358f 358f ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3590 3590 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3591 3591 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 3592 3592 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 3593 3593 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 3594 3594 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3595 3595 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3596 ; -------------------------------------------------------------------------------------- 3596 ; Comes from: 3596 ; 10c8 C from color 0x10aa 3596 ; 10cd C from color 0x10c1 3596 ; 10e2 C from color 0x10d6 3596 ; 10f6 C from color 0x10d7 3596 ; 1124 C from color 0x110f 3596 ; 1134 C from color 0x110f 3596 ; 1142 C from color 0x110f 3596 ; 114c C from color 0x110f 3596 ; 115b C from color 0x1117 3596 ; 1164 C from color 0x1164 3596 ; 117f C from color 0x111d 3596 ; 1196 C from color 0x111d 3596 ; 11c3 C from color 0x111d 3596 ; 11ce C from color 0x111d 3596 ; 120c C from color 0x10c1 3596 ; 1220 C from color 0x10d6 3596 ; 1233 C from color 0x1201 3596 ; 123c C from color 0x1201 3596 ; 1289 C from color 0x10d6 3596 ; 12b0 C from color 0x125f 3596 ; -------------------------------------------------------------------------------------- 3596 3596 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x3597 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3599 0x3599 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 07 GP07 3597 3597 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3515 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3515 0x3515 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 3598 3598 seq_br_type 3 Unconditional Branch; Flow J 0x3521 seq_branch_adr 3521 0x3521 seq_random 06 Pop_stack+? val_c_adr 39 GP06 3599 3599 fiu_mem_start 3 start-wr; Flow C cc=False 0x32a0 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 32a0 0x32a0 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 359a 359a ioc_fiubs 2 typ ; Flow R cc=True ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 359b 0x359b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 359b 359b ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 359c 359c fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 359d 359d ioc_fiubs 1 val ; Flow J 0x359e seq_br_type 2 Push (branch address) seq_branch_adr 35a2 0x35a2 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 359e 359e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x35a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35a1 0x35a1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 37 VR13:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 359f 359f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3515 fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3515 0x3515 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 35a0 35a0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 35a1 35a1 seq_br_type 3 Unconditional Branch; Flow J 0x32fe seq_branch_adr 32fe 0x32fe seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 35a2 35a2 fiu_load_var 1 hold_var; Flow C 0x210 fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35a3 35a3 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35a4 35a4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 35a5 35a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME 35a6 35a6 fiu_fill_mode_src 0 ; Flow J cc=False 0x35a8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35a8 0x35a8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 35a7 35a7 fiu_fill_mode_src 0 ; Flow J 0x35ab fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35ab 0x35ab typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35a8 35a8 fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35a9 35a9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 35aa 35aa fiu_load_var 1 hold_var; Flow J 0x35ab fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 35ab 0x35ab seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 35ab 35ab ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 35ac 35ac fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 3a VR05:1a val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 35ad 35ad fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35ae 35ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ae seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 35af 35af fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 35b0 0x35b0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR11:07 val_frame 11 35b0 35b0 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 35b1 35b1 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_b_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 35b2 35b2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 35b3 35b3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 35b4 35b4 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x35bc fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35bc 0x35bc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 35b5 35b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x35b9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 35b9 0x35b9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 35b6 35b6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3e GP01 val_c_source 0 FIU_BUS 35b7 35b7 ioc_tvbs 2 fiu+val seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35b8 35b8 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x35bb fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 35bb 0x35bb seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 35b9 35b9 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 35ba 35ba fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 35bb 0x35bb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 4 35bb 35bb seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 typ_csa_cntl 3 POP_CSA 35bc 35bc fiu_load_var 1 hold_var; Flow J 0x35ba fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 35ba 0x35ba seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 35bd 35bd ioc_fiubs 2 typ ; Flow J cc=True 0x35c6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35c6 0x35c6 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35be 35be seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 35bf 35bf seq_b_timing 1 Latch Condition; Flow J cc=True 0x35c5 seq_br_type 1 Branch True seq_branch_adr 35c5 0x35c5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 35c0 35c0 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32b1 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35c1 35c1 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35c2 35c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32b1 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 35c3 35c3 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32b1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b1 0x32b1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 35c4 35c4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 35c5 35c5 fiu_mem_start 2 start-rd; Flow J 0x35c1 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 35c1 0x35c1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35c6 35c6 seq_br_type 3 Unconditional Branch; Flow J 0x35c4 seq_branch_adr 35c4 0x35c4 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35c7 35c7 seq_br_type 4 Call False; Flow C cc=False 0x32b1 seq_branch_adr 32b1 0x32b1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35c8 35c8 fiu_mem_start 2 start-rd; Flow C cc=True 0x32b1 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b1 0x32b1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35c9 35c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32b1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 35ca 35ca fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 35cb 35cb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35cd fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35cd 0x35cd seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35cc 35cc ioc_load_wdr 0 ; Flow J cc=False 0x35ce ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 35ce 0x35ce seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 35cd 35cd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 35ce 35ce fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe 35cf 35cf seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 35d0 35d0 seq_br_type 4 Call False; Flow C cc=False 0x32b1 seq_branch_adr 32b1 0x32b1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35d1 35d1 fiu_mem_start 2 start-rd; Flow C cc=True 0x32b1 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b1 0x32b1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 35d2 35d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32b1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32b1 0x32b1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 35d3 35d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 35d4 35d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35cc fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 35cc 0x35cc seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35d5 35d5 seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 35d6 35d6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x326e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 35d7 35d7 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 35d8 35d8 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35d9 35d9 ioc_load_wdr 0 typ_csa_cntl 3 POP_CSA 35da 35da fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 35db 35db fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x326e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 326e 0x326e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 35dc 35dc fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 35dd 35dd fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 35de 0x35de seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 35de 35de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 35df 35df fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x35e8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 35e8 0x35e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 35e0 35e0 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 35e1 35e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3271 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 35e2 35e2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 35e3 35e3 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35e4 35e4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 35e5 35e5 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 35e6 35e6 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d48 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d48 0x1d48 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 35e7 35e7 seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 35e8 35e8 ioc_fiubs 0 fiu ; Flow J cc=True 0x3604 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3604 0x3604 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 35e9 35e9 fiu_load_tar 1 hold_tar; Flow J cc=False 0x35ec fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35ec 0x35ec seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 35ea 35ea fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3605 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3605 0x3605 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 35eb 35eb seq_br_type 7 Unconditional Call; Flow C 0x3279 seq_branch_adr 3279 0x3279 seq_en_micro 0 seq_random 02 ? 35ec 35ec fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 35ed 35ed fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35ee 35ee fiu_mem_start a start_continue_if_false; Flow J cc=False 0x35f1 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35f1 0x35f1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 35ef 35ef fiu_fill_mode_src 0 ; Flow C cc=False 0x3600 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3600 0x3600 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 35f0 35f0 seq_br_type 3 Unconditional Branch; Flow J 0x35f4 seq_branch_adr 35f4 0x35f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 35f1 35f1 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35f2 35f2 fiu_fill_mode_src 0 ; Flow C cc=False 0x3600 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3600 0x3600 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 35f3 35f3 seq_br_type 3 Unconditional Branch; Flow J 0x35f4 seq_branch_adr 35f4 0x35f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 35f4 35f4 seq_b_timing 1 Latch Condition; Flow J cc=True 0x35f7 seq_br_type 1 Branch True seq_branch_adr 35f7 0x35f7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 35f5 35f5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 35f6 35f6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 35f7 35f7 seq_br_type 1 Branch True; Flow J cc=True 0x3605 seq_branch_adr 3605 0x3605 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B 35f8 35f8 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 35f9 35f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 35fe 0x35fe typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35fa 35fa fiu_mem_start a start_continue_if_false; Flow J cc=False 0x35fc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35fc 0x35fc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 35fb 35fb fiu_fill_mode_src 0 ; Flow J 0x35f8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35f8 0x35f8 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 35fc 35fc fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35fd 35fd fiu_fill_mode_src 0 ; Flow J 0x35f8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35f8 0x35f8 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 35fe 35fe seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 35ff 35ff seq_br_type 3 Unconditional Branch; Flow J 0x3605 seq_branch_adr 3605 0x3605 seq_en_micro 0 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3600 ; -------------------------------------------------------------------------------------- 3600 ; Comes from: 3600 ; 35ef C False from color 0x0000 3600 ; 35f2 C False from color 0x0000 3600 ; -------------------------------------------------------------------------------------- 3600 3600 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3602 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3602 0x3602 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3601 3601 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3602 3602 fiu_load_var 1 hold_var; Flow C cc=False 0x3077 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3077 0x3077 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3603 3603 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3604 3604 fiu_mem_start 2 start-rd; Flow C 0x2454 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2454 0x2454 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3605 3605 fiu_mem_start 2 start-rd; Flow C cc=True 0x3271 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 3606 3606 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3607 3607 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x360a ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 360a 0x360a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 3608 3608 fiu_mem_start 2 start-rd; Flow C 0x323f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323f 0x323f typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3609 3609 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 360a 360a fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 360b 360b fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 39 GP06 val_c_source 0 FIU_BUS 360c 360c val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 360d 360d ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 360e 360e seq_br_type 5 Call True; Flow C cc=True 0x1eee seq_branch_adr 1eee 0x1eee seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 360f 360f fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3610 0x3610 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 3610 3610 seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 3611 3611 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3612 3612 fiu_len_fill_lit 75 zero-fill 0x35 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3613 3613 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3616 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3616 0x3616 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_frame 19 val_a_adr 38 VR12:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3614 3614 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 3615 3615 fiu_mem_start 3 start-wr seq_en_micro 0 3616 3616 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_c_adr 1e TR19:01 typ_frame 19 val_b_adr 0d GP0d val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 3617 3617 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3619 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3619 0x3619 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3618 3618 fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x211 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 39 TR12:19 typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 20 VR19:00 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 3619 3619 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2b VR11:0b val_frame 11 361a 361a ioc_load_wdr 0 ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_frame 2 361b 361b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 23 TR0d:03 typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 1c TR0d:03 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 29 VR0d:09 val_alu_func 0 PASS_A val_c_adr 15 VR0d:0a val_c_mux_sel 2 ALU val_frame d 361c 361c fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 7f fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 21 TR11:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 11 val_b_adr 30 VR02:10 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame 2 361d 361d fiu_tivi_src c mar_0xc; Flow C cc=True 0xbab ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0bab 0x0bab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 16 VR0d:09 val_c_source 0 FIU_BUS val_frame d 361e 361e seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 361f 361f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 22 TR11:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 3620 3620 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 0e GP0e val_a_adr 2f VR02:0f val_b_adr 39 VR02:19 val_frame 2 3621 3621 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_frame d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 3622 3622 ioc_fiubs 0 fiu ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 0e GP0e val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3623 3623 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3713 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3713 0x3713 seq_en_micro 0 seq_random 0a ? typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3624 ; -------------------------------------------------------------------------------------- 3624 ; Comes from: 3624 ; 0fbc C from color 0x0fbb 3624 ; -------------------------------------------------------------------------------------- 3624 3624 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x3611 fiu_load_mdr 1 hold_mdr fiu_offs_lit 02 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3611 0x3611 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2a VR05:0a val_frame 5 3625 3625 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_frame 3 3626 3626 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 3627 3627 ioc_fiubs 0 fiu ; Flow J 0x3613 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3613 0x3613 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3628 3628 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3611 fiu_load_mdr 1 hold_mdr fiu_offs_lit 03 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3611 0x3611 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2b VR05:0b val_frame 5 3629 3629 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3611 fiu_load_mdr 1 hold_mdr fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3611 0x3611 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR06:01 val_frame 6 362a ; -------------------------------------------------------------------------------------- 362a ; Comes from: 362a ; 344f C from color 0x02c9 362a ; -------------------------------------------------------------------------------------- 362a 362a fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3611 fiu_load_mdr 1 hold_mdr fiu_offs_lit 05 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3611 0x3611 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 3d VR02:1d val_frame 2 362b 362b fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3611 fiu_load_mdr 1 hold_mdr fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3611 0x3611 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 23 VR07:03 val_frame 7 362c 362c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x362d ; Flow J cc=#0x0 0x362d seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 362d 0x362d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 28 VR05:08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 362d 362d seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 362e 362e fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 362f 362f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3630 3630 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3631 3631 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3632 3632 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3633 3633 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363a 0x363a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3634 3634 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363f fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363f 0x363f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3635 3635 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3636 3636 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363d fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363d 0x363d seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3637 3637 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3644 fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3644 0x3644 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3638 3638 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3646 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3646 0x3646 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3639 ; -------------------------------------------------------------------------------------- 3639 ; Comes from: 3639 ; 363a C from color 0x362e 3639 ; 3641 C from color 0x0fd2 3639 ; -------------------------------------------------------------------------------------- 3639 3639 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 363a 363a fiu_mem_start 2 start-rd; Flow C 0x3639 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3639 0x3639 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 363b 363b fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 363c 363c ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 2 typ_frame 1f val_b_adr 0c GP0c 363d 363d fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 7d fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 363e 363e ioc_load_wdr 0 ; Flow J 0x3b5d ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b5d 0x3b5d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 363f 363f ioc_adrbs 1 val ; Flow C 0xfd2 seq_br_type 7 Unconditional Call seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3640 3640 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3641 0x3641 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3641 3641 fiu_mem_start 2 start-rd; Flow C 0x3639 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3639 0x3639 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3642 3642 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3643 3643 ioc_adrbs 2 typ ; Flow R cc=True ; Flow J cc=False 0x1051 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 1051 0x1051 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3644 3644 ioc_adrbs 1 val ; Flow C 0xfd2 seq_br_type 7 Unconditional Call seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3645 3645 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3646 3646 seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3647 3647 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3648 3648 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3649 3649 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 32 VR03:12 val_frame 3 364a 364a ioc_load_wdr 0 ; Flow J 0x3b4e ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 364b ; -------------------------------------------------------------------------------------- 364b ; Comes from: 364b ; 0141 C from color 0x0141 364b ; 08f6 C from color 0x0127 364b ; -------------------------------------------------------------------------------------- 364b 364b fiu_load_var 1 hold_var; Flow C 0x364d fiu_vmux_sel 1 fill value ioc_random f disable delay timer seq_br_type 7 Unconditional Call seq_branch_adr 364d 0x364d seq_en_micro 0 364c 364c fiu_load_var 1 hold_var; Flow J 0x3650 fiu_vmux_sel 1 fill value ioc_random d disable slice timer seq_br_type 3 Unconditional Branch seq_branch_adr 3650 0x3650 seq_en_micro 0 364d ; -------------------------------------------------------------------------------------- 364d ; Comes from: 364d ; 364b C from color 0x3381 364d ; -------------------------------------------------------------------------------------- 364d 364d fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 364e 364e ioc_random 7 load delay timer ioc_tvbs 2 fiu+val seq_en_micro 0 364f 364f ioc_random b clear delay event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 3650 3650 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 3651 ; -------------------------------------------------------------------------------------- 3651 ; Comes from: 3651 ; 0763 C from color 0x0000 3651 ; 07bd C from color 0x07b9 3651 ; 0f78 C from color 0x0f64 3651 ; -------------------------------------------------------------------------------------- 3651 3651 ioc_random 6 load slice timer ioc_tvbs 2 fiu+val seq_en_micro 0 3652 3652 ioc_random a clear slice event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 3653 ; -------------------------------------------------------------------------------------- 3653 ; Comes from: 3653 ; 0567 C from color 0x0567 3653 ; 05a0 C from color 0x0599 3653 ; 0812 C from color 0x0000 3653 ; 0ee8 C from color 0x0ee8 3653 ; -------------------------------------------------------------------------------------- 3653 3653 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 3654 3654 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3655 3655 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 3656 3656 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 39 VR03:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3657 3657 fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 39 VR03:19 val_frame 3 3658 3658 ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3659 3659 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 365a 365a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 365b 365b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 365c 365c seq_en_micro 0 365d 365d fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 365e 365e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 365f 365f fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 val_b_adr 3a VR04:1a val_frame 4 3660 3660 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x3667 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3667 0x3667 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 05 VR04:1a val_c_mux_sel 2 ALU val_frame 4 3661 3661 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3662 3662 seq_en_micro 0 3663 3663 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 05 TR04:1a typ_c_mux_sel 0 ALU typ_frame 4 3664 3664 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3665 3665 seq_br_type 0 Branch False; Flow J cc=False 0x3667 seq_branch_adr 3667 0x3667 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3a TR04:1a typ_b_adr 2d TR04:0d typ_frame 4 3666 3666 fiu_mem_start 2 start-rd; Flow J 0x3662 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3662 0x3662 seq_en_micro 0 typ_a_adr 2d TR04:0d typ_alu_func 0 PASS_A typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3667 3667 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3668 3668 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 3669 3669 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 366a 366a fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 366b 366b ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 4 366c 366c fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 366d 366d fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3676 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3676 0x3676 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 366e 366e fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 366f 366f seq_en_micro 0 3670 3670 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 3671 3671 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3676 seq_br_type 1 Branch True seq_branch_adr 3676 0x3676 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3672 3672 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3673 3673 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 04 GP04 3674 3674 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 3675 3675 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3676 3676 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x20a ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1e TR17:01 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3677 3677 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 3678 3678 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3679 3679 fiu_len_fill_lit 44 zero-fill 0x4 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 367a 367a ioc_load_wdr 0 ; Flow J cc=True 0x3682 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3682 0x3682 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 367b 367b seq_br_type 4 Call False; Flow C cc=False 0x20a seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 367c 367c ioc_tvbs 2 fiu+val; Flow J cc=True 0x3680 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3680 0x3680 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 367d 367d seq_b_timing 1 Latch Condition; Flow J cc=True 0x3684 seq_br_type 1 Branch True seq_branch_adr 3684 0x3684 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 367e 367e seq_b_timing 1 Latch Condition; Flow J cc=True 0x368c seq_br_type 1 Branch True seq_branch_adr 368c 0x368c seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 367f 367f seq_b_timing 1 Latch Condition; Flow J cc=True 0x368c seq_br_type 1 Branch True seq_branch_adr 368c 0x368c seq_en_micro 0 3680 3680 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 3681 3681 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3682 3682 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b56 fiu_load_mdr 1 hold_mdr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3b56 0x3b56 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 3683 3683 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 3684 3684 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3688 seq_br_type 1 Branch True seq_branch_adr 3688 0x3688 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 3685 3685 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3686 3686 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3687 3687 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20a ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3688 3688 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3689 3689 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 368a 368a seq_br_type 1 Branch True; Flow J cc=True 0x3680 seq_branch_adr 3680 0x3680 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 368b 368b seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 368c 368c fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 368d 368d seq_en_micro 0 368e 368e fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 368f 368f fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x58b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 058b 0x058b seq_en_micro 0 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 3690 3690 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3691 ; -------------------------------------------------------------------------------------- 3691 ; Comes from: 3691 ; 0e0f C from color 0x0000 3691 ; 1071 C from color 0x0efa 3691 ; 3b6e C from color 0x0bab 3691 ; -------------------------------------------------------------------------------------- 3691 3691 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 3692 3692 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 3693 3693 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3694 3694 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 3695 3695 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 3696 3696 fiu_mem_start 4 continue ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR04:03 val_frame 4 3697 3697 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x369a fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 369a 0x369a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 3698 3698 seq_br_type 7 Unconditional Call; Flow C 0x6ec seq_branch_adr 06ec 0x06ec seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 3699 3699 seq_br_type 3 Unconditional Branch; Flow J 0x36b0 seq_branch_adr 36b0 0x36b0 seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 369a 369a fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x36a4 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36a4 0x36a4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3c TR09:1c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 369b 369b ioc_adrbs 1 val ; Flow C cc=#0x0 0x36a0 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 36a0 0x36a0 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_frame 4 369c 369c fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 369d 369d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS 369e 369e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 369f 369f ioc_load_wdr 0 ; Flow J 0x36b0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36b0 0x36b0 seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 36a0 ; -------------------------------------------------------------------------------------- 36a0 ; Comes from: 36a0 ; 369b C #0x0 from color 0x05a7 36a0 ; -------------------------------------------------------------------------------------- 36a0 36a0 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36a1 36a1 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36a2 36a2 seq_br_type 3 Unconditional Branch; Flow J 0x3b89 seq_branch_adr 3b89 0x3b89 seq_en_micro 0 36a3 36a3 seq_br_type 3 Unconditional Branch; Flow J 0x3b8b seq_branch_adr 3b8b 0x3b8b seq_en_micro 0 36a4 36a4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3698 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3698 0x3698 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36a5 36a5 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36a6 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 36a9 0x36a9 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 36a6 36a6 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 36a7 36a7 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 36a8 36a8 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36a9 36a9 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 36aa 36aa seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 36ab 36ab fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36ac 36ac fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36ad 36ad fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 36 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 36ae 36ae fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_en_micro 0 36af 36af fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36b0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36b0 0x36b0 seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_source 0 FIU_BUS typ_frame 4 36b0 36b0 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3b TR05:1b typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_c_adr 13 VR04:0c val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 36b1 36b1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 val_a_adr 26 VR04:06 val_alu_func 6 A_MINUS_B val_b_adr 2c VR04:0c val_frame 4 36b2 36b2 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36b3 36b3 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36b4 36b4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 12 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 36b5 36b5 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 36b6 36b6 ioc_fiubs 1 val ; Flow J cc=False 0x36be ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 36be 0x36be seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 38 VR05:18 val_frame 5 36b7 36b7 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2c TR04:0c typ_alu_func 0 PASS_A typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 3c VR12:1c val_frame 12 36b8 36b8 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36b9 36b9 ioc_load_wdr 0 ; Flow J cc=True 0x36c0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 36c0 0x36c0 seq_en_micro 0 36ba 36ba fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 26 VR04:06 val_frame 4 36bb 36bb ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36bc 36bc seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36bd 0x36bd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 26 VR04:06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36bd 36bd seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36be 36be ioc_tvbs 2 fiu+val; Flow J cc=False 0x36b8 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 36b8 0x36b8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36bf 36bf fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36b8 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36b8 0x36b8 seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 36c0 36c0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 22 TR04:02 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 36c1 36c1 seq_en_micro 0 36c2 36c2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_a_adr 31 VR04:11 val_alu_func 0 PASS_A val_c_adr 13 VR04:0c val_c_mux_sel 2 ALU val_frame 4 36c3 36c3 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR04:03 val_frame 4 36c4 36c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR04:03 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36c5 36c5 seq_en_micro 0 val_a_adr 2c VR04:0c val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36c6 36c6 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 36c7 36c7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36c8 36c8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 2c VR04:0c val_frame 4 36c9 36c9 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36ca 36ca seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36cb 0x36cb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 36cb 36cb seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36cc ; -------------------------------------------------------------------------------------- 36cc ; 0x0010 Halt InMicrocode 36cc ; -------------------------------------------------------------------------------------- 36cc MACRO_Halt_InMicrocode: 36cc 36cc dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36cc ioc_random 14 clear cpu running seq_en_micro 0 seq_random 01 Halt+? 36cd 36cd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36ce ; -------------------------------------------------------------------------------------- 36ce ; 0x0011 QQUnknown InMicrocode 36ce ; -------------------------------------------------------------------------------------- 36ce MACRO_36ce_QQUnknown_InMicrocode: 36ce 36ce dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36ce fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36cf 36cf <halt> ; Flow R 36d0 ; -------------------------------------------------------------------------------------- 36d0 ; 0x0012 QQUnknown InMicrocode 36d0 ; -------------------------------------------------------------------------------------- 36d0 MACRO_36d0_QQUnknown_InMicrocode: 36d0 36d0 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d1 36d1 <halt> ; Flow R 36d2 ; -------------------------------------------------------------------------------------- 36d2 ; 0x0013 QQUnknown InMicrocode 36d2 ; -------------------------------------------------------------------------------------- 36d2 MACRO_36d2_QQUnknown_InMicrocode: 36d2 36d2 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d3 36d3 <halt> ; Flow R 36d4 ; -------------------------------------------------------------------------------------- 36d4 ; 0x0014 QQUnknown InMicrocode 36d4 ; -------------------------------------------------------------------------------------- 36d4 MACRO_36d4_QQUnknown_InMicrocode: 36d4 36d4 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d5 36d5 <halt> ; Flow R 36d6 ; -------------------------------------------------------------------------------------- 36d6 ; 0x0015 QQUnknown InMicrocode 36d6 ; -------------------------------------------------------------------------------------- 36d6 MACRO_36d6_QQUnknown_InMicrocode: 36d6 36d6 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d7 36d7 <halt> ; Flow R 36d8 ; -------------------------------------------------------------------------------------- 36d8 ; 0x0016 QQUnknown InMicrocode 36d8 ; -------------------------------------------------------------------------------------- 36d8 MACRO_36d8_QQUnknown_InMicrocode: 36d8 36d8 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d9 36d9 <halt> ; Flow R 36da ; -------------------------------------------------------------------------------------- 36da ; 0x0017 QQUnknown InMicrocode 36da ; -------------------------------------------------------------------------------------- 36da MACRO_36da_QQUnknown_InMicrocode: 36da 36da dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36da fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36db 36db <halt> ; Flow R 36dc ; -------------------------------------------------------------------------------------- 36dc ; 0x0018 QQUnknown InMicrocode 36dc ; -------------------------------------------------------------------------------------- 36dc MACRO_36dc_QQUnknown_InMicrocode: 36dc 36dc dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36dc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36dd 36dd <halt> ; Flow R 36de ; -------------------------------------------------------------------------------------- 36de ; 0x0019 QQUnknown InMicrocode 36de ; -------------------------------------------------------------------------------------- 36de MACRO_36de_QQUnknown_InMicrocode: 36de 36de dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36de fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36df 36df <halt> ; Flow R 36e0 ; -------------------------------------------------------------------------------------- 36e0 ; 0x001a QQUnknown InMicrocode 36e0 ; -------------------------------------------------------------------------------------- 36e0 MACRO_36e0_QQUnknown_InMicrocode: 36e0 36e0 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e1 36e1 <halt> ; Flow R 36e2 ; -------------------------------------------------------------------------------------- 36e2 ; 0x001b QQUnknown InMicrocode 36e2 ; -------------------------------------------------------------------------------------- 36e2 MACRO_36e2_QQUnknown_InMicrocode: 36e2 36e2 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e3 36e3 <halt> ; Flow R 36e4 ; -------------------------------------------------------------------------------------- 36e4 ; 0x001c QQUnknown InMicrocode 36e4 ; -------------------------------------------------------------------------------------- 36e4 MACRO_36e4_QQUnknown_InMicrocode: 36e4 36e4 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e5 36e5 <halt> ; Flow R 36e6 ; -------------------------------------------------------------------------------------- 36e6 ; 0x001d QQUnknown InMicrocode 36e6 ; -------------------------------------------------------------------------------------- 36e6 MACRO_36e6_QQUnknown_InMicrocode: 36e6 36e6 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e7 36e7 <halt> ; Flow R 36e8 ; -------------------------------------------------------------------------------------- 36e8 ; 0x001e QQUnknown InMicrocode 36e8 ; -------------------------------------------------------------------------------------- 36e8 MACRO_36e8_QQUnknown_InMicrocode: 36e8 36e8 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e9 36e9 <halt> ; Flow R 36ea ; -------------------------------------------------------------------------------------- 36ea ; 0x001f QQUnknown InMicrocode 36ea ; -------------------------------------------------------------------------------------- 36ea MACRO_36ea_QQUnknown_InMicrocode: 36ea 36ea dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36ea fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36eb 36eb fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36ed fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36ed 0x36ed typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 27 VR05:07 val_frame 5 36ec 36ec fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36ed fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36ed 0x36ed typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 36ed 36ed fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 2f VR02:0f val_frame 2 36ee 36ee fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 36ef 36ef fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x36f1 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36f1 0x36f1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_c_adr 3f GP00 val_frame 7 val_rand 9 PASS_A_HIGH 36f0 36f0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x36f1 ; Flow J cc=#0x0 0x36f5 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 36f5 0x36f5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f1 36f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x36f4 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36f4 0x36f4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f2 36f2 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x42f seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 36f3 36f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36f4 36f4 seq_br_type 3 Unconditional Branch; Flow J 0x32a6 seq_branch_adr 32a6 0x32a6 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 36f5 36f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3cb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 03cb 0x03cb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f6 36f6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36fd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36fd 0x36fd seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f7 36f7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3701 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3701 0x3701 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f8 36f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36fd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36fd 0x36fd seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f9 36f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36ff fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36ff 0x36ff seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36fa 36fa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36fb 36fb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36fc 36fc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36fd 36fd ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 36fe 36fe seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 36ff 36ff ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 3700 3700 seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 3701 3701 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 3702 3702 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 2c TR02:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 3703 3703 ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 3704 3704 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3705 3705 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 3706 3706 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 val_b_adr 16 CSA/VAL_BUS 3707 3707 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3711 fiu_offs_lit 65 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3711 0x3711 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 3708 3708 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3709 3709 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x370b fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 370b 0x370b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3c TR09:1c typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 370a 370a fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x3b75 fiu_offs_lit 65 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 370b 370b ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 09 GP09 val_rand a PASS_B_HIGH 370c 370c fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3708 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3708 0x3708 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 370d 370d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 370e 370e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3711 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3711 0x3711 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 370f 370f fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3710 3710 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3711 3711 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3712 3712 seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 typ_a_adr 35 TR13:15 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 3713 3713 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 3714 3714 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3731 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3731 0x3731 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3715 3715 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3716 3716 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3718 fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3718 0x3718 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3717 3717 seq_b_timing 0 Early Condition; Flow J cc=True 0x3718 ; Flow J cc=#0x0 0x3723 seq_br_type b Case False seq_branch_adr 3723 0x3723 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b 3718 3718 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3719 3719 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x470 seq_br_type 0 Branch False seq_branch_adr 0470 0x0470 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 32 VR03:12 val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 3 371a 371a fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR09:0f val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 9 val_rand a PASS_B_HIGH 371b 371b ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 2b VR09:0b val_frame 9 371c 371c fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 2 val_rand a PASS_B_HIGH 371d 371d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 371e 371e fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 371f 371f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x211 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0211 0x0211 3720 3720 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 25 TR02:05 typ_b_adr 20 TR02:00 typ_frame 2 3721 3721 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 23 VR02:03 val_frame 2 3722 3722 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3723 ; Flow J cc=#0x0 0x0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 1a TR02:05 typ_c_source 0 FIU_BUS typ_frame 2 3723 3723 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3724 3724 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372b 0x372b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3725 3725 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372d 0x372d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3726 3726 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3727 3727 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3728 3728 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3729 3729 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372a 372a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372b 372b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 372c 372c seq_br_type 3 Unconditional Branch; Flow J 0x412 seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 372d 372d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 372e 372e ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 372f 372f seq_b_timing 1 Latch Condition; Flow J cc=True 0x412 seq_br_type 1 Branch True seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3730 3730 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3731 3731 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x3719 seq_branch_adr 3719 0x3719 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 3732 3732 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3733 3733 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 3734 3734 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x3753 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3753 0x3753 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3735 3735 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x379e fiu_load_var 1 hold_var fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 379e 0x379e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 28 VR09:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3736 3736 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=#0x0 0x3763 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3763 0x3763 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3737 3737 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_b_adr 02 GP02 3738 3738 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x376f ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 376f 0x376f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3739 3739 ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 373a 373a fiu_load_tar 1 hold_tar; Flow J cc=False 0x373d fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 373d 0x373d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 373b 373b seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 373c 373c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 373d 373d ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 1 373e 373e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 373f 373f ioc_fiubs 0 fiu ; Flow J cc=False 0x373a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 373a 0x373a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3740 3740 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 3741 3741 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x376b fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 376b 0x376b seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 3742 3742 fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3743 3743 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3744 3744 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_source 0 FIU_BUS val_frame 2 3745 3745 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3759 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3759 0x3759 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3746 3746 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3747 3747 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3756 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3756 0x3756 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 3748 3748 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3749 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 375c 0x375c typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3749 3749 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34ac ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 34ac 0x34ac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 374a 374a fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 val_rand a PASS_B_HIGH 374b 374b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 374c 374c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37a1 0x37a1 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 374d 374d seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 374e 374e ioc_adrbs 3 seq ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 374f 374f fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3750 3750 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3751 0x3751 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3751 3751 seq_br_type 7 Unconditional Call; Flow C 0x33bc seq_branch_adr 33bc 0x33bc 3752 3752 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3753 3753 fiu_tivi_src c mar_0xc; Flow J cc=False 0x3755 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3755 0x3755 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3754 3754 seq_br_type 3 Unconditional Branch; Flow J 0x378f seq_branch_adr 378f 0x378f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3755 3755 fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3756 3756 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3757 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 375c 0x375c typ_a_adr 06 GP06 3757 3757 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3758 3758 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3749 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3749 0x3749 typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3759 3759 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 375a 375a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 375b 375b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3747 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3747 0x3747 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 375c 375c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 375d 375d fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x37a1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37a1 0x37a1 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 375e 375e ioc_load_wdr 0 ; Flow C 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 375f 375f fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3760 3760 seq_random 03 ? 3761 3761 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 3762 3762 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3763 ; -------------------------------------------------------------------------------------- 3763 ; Comes from: 3763 ; 3736 C #0x0 from color 0x0000 3763 ; -------------------------------------------------------------------------------------- 3763 3763 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3764 3764 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3765 3765 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3766 3766 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3767 3767 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3768 3768 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3769 3769 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3782 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3782 0x3782 seq_random 06 Pop_stack+? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 32 VR03:12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 3 376a 376a seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 376b ; -------------------------------------------------------------------------------------- 376b ; Comes from: 376b ; 3741 C #0x0 from color 0x373a 376b ; -------------------------------------------------------------------------------------- 376b 376b seq_br_type a Unconditional Return; Flow R seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 05 ? typ_b_adr 06 GP06 376c 376c ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 376d 376d ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 376e 376e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 376f 376f ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 3770 3770 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 3771 3771 ioc_fiubs 0 fiu ; Flow J 0x3740 seq_br_type 3 Unconditional Branch seq_branch_adr 3740 0x3740 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3772 3772 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3b TR05:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 3773 3773 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_frame d 3774 3774 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3b TR05:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 5 3775 3775 seq_br_type 0 Branch False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 0f GP0f typ_b_adr 0e GP0e 3776 3776 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3777 3777 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3778 3778 ioc_load_wdr 0 ; Flow J 0x3779 seq_br_type 2 Push (branch address) seq_branch_adr 329a 0x329a typ_b_adr 02 GP02 3779 3779 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 377a 377a ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 06 Pop_stack+? typ_b_adr 2e TR02:0e typ_frame 2 377b 377b ioc_adrbs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 377c 377c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3742 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3742 0x3742 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 02 GP02 377d 377d seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 377e 377e ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 377f 377f fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 3780 3780 ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3781 3781 fiu_vmux_sel 1 fill value; Flow J 0x3741 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3741 0x3741 typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 3782 3782 ioc_tvbs 5 seq+seq; Flow J cc=True 0x377d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 377d 0x377d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3783 3783 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A 3784 3784 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR09:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3785 3785 fiu_mem_start 3 start-wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 3786 3786 fiu_mem_start 2 start-rd; Flow C cc=False 0x211 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 3787 3787 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3788 3788 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x378d fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 378d 0x378d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 32 VR07:12 val_frame 7 3789 3789 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 378a 378a fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x378b fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 378f 0x378f typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 378b 378b seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 378c 378c ioc_adrbs 1 val ; Flow J 0x3b75 seq_br_type 3 Unconditional Branch seq_branch_adr 3b75 0x3b75 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 378d 378d ioc_adrbs 1 val ; Flow C 0x3469 seq_br_type 7 Unconditional Call seq_branch_adr 3469 0x3469 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 378e 378e ioc_adrbs 1 val ; Flow C 0x3b75 seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 378f 378f fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 06 GP06 typ_b_adr 06 GP06 3790 3790 ioc_adrbs 1 val typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 3791 3791 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3792 3792 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 3793 3793 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3794 3794 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3795 3795 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3796 3796 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3797 3797 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 3798 3798 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3799 3799 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 379a 379a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 379b 379b fiu_len_fill_lit 6b zero-fill 0x2b; Flow C 0x32fe fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_random 15 ? typ_a_adr 06 GP06 typ_mar_cntl 9 LOAD_MAR_CODE 379c 379c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 379d 379d fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 379e 379e ioc_adrbs 1 val ; Flow C 0x3b75 seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 379f 379f fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR09:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 37a0 37a0 ioc_load_wdr 0 ; Flow J 0x378f seq_br_type 3 Unconditional Branch seq_branch_adr 378f 0x378f 37a1 37a1 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 37a2 37a2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37aa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37aa 0x37aa seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 37a3 37a3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37a4 37a4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37a5 37a5 fiu_load_tar 1 hold_tar; Flow J cc=False 0x37a8 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 37a8 0x37a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37a6 37a6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val 37a7 37a7 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x375e fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 375e 0x375e typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 37a8 37a8 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37a9 37a9 ioc_load_wdr 0 ; Flow J 0x375f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 375f 0x375f typ_b_adr 06 GP06 37aa 37aa fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37ab 37ab fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37ac 37ac fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37ad 37ad fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37ae 37ae ioc_load_wdr 0 ; Flow J 0x375f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 375f 0x375f typ_b_adr 06 GP06 37af 37af <halt> ; Flow R 37b0 ; -------------------------------------------------------------------------------------- 37b0 ; Comes from: 37b0 ; 37dc C from color MACRO_Execute_Family,Count 37b0 ; -------------------------------------------------------------------------------------- 37b0 37b0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37b1 37b1 fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37b2 37b2 fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 37b3 37b3 ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x3276 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 37b4 ; -------------------------------------------------------------------------------------- 37b4 ; 0x0137 Execute Entry,Rendezvous 37b4 ; -------------------------------------------------------------------------------------- 37b4 MACRO_Execute_Entry,Rendezvous: 37b4 37b4 dispatch_brk_class 5 ; Flow J cc=True 0x38dc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 37b4 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38dc 0x38dc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A 37b5 37b5 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37b6 37b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37b7 37b7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37b8 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37b4 MACRO_Execute_Entry,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand a PASS_B_HIGH val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37b8 37b8 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x37c0 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 37c0 0x37c0 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37b9 37b9 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x38dc fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38dc 0x38dc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 37ba 37ba fiu_mem_start 3 start-wr; Flow J 0x37bb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37bb 0x37bb seq_random 02 ? typ_alu_func 1b A_OR_B typ_b_adr 2d TR02:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37bb 37bb fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x37bc fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 37bc 37bc fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x337f fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_frame 2 37bd 37bd fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37be 37be seq_br_type 7 Unconditional Call; Flow C 0x38e4 seq_branch_adr 38e4 0x38e4 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 37bf 37bf seq_br_type 3 Unconditional Branch; Flow J 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 37c0 37c0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x38dc fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38dc 0x38dc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 37c1 37c1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37c3 seq_br_type 1 Branch True seq_branch_adr 37c3 0x37c3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37c2 37c2 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37c3 37c3 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 37c4 37c4 ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A 37c5 37c5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37c6 37c6 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x37c8 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 37c8 0x37c8 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 37c7 37c7 ioc_load_wdr 0 ; Flow J 0x3896 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37c8 37c8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37c9 37c9 fiu_tivi_src 2 tar_fiu; Flow J 0x3896 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 typ_a_adr 14 ZEROS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37ca ; -------------------------------------------------------------------------------------- 37ca ; 0x0133 Execute Family,Rendezvous 37ca ; -------------------------------------------------------------------------------------- 37ca MACRO_Execute_Family,Rendezvous: 37ca 37ca dispatch_brk_class 5 ; Flow J cc=True 0x38de dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 37ca fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38de 0x38de seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP 37cb 37cb ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37cc 37cc seq_br_type 7 Unconditional Call; Flow C 0x37b0 seq_branch_adr 37b0 0x37b0 typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37cd 37cd fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37ce fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37ca MACRO_Execute_Family,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37ce 37ce fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x37d1 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 37d1 0x37d1 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 37cf 37cf fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x38de fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38de 0x38de seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 37d0 37d0 fiu_mem_start 3 start-wr; Flow J 0x37bb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37bb 0x37bb typ_alu_func 1b A_OR_B typ_b_adr 29 TR09:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37d1 37d1 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x38de fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38de 0x38de seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 37d2 37d2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37c3 seq_br_type 1 Branch True seq_branch_adr 37c3 0x37c3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37d3 37d3 seq_br_type 3 Unconditional Branch; Flow J 0x37c2 seq_branch_adr 37c2 0x37c2 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 37d4 ; -------------------------------------------------------------------------------------- 37d4 ; 0x0136 Execute Entry,Count 37d4 ; -------------------------------------------------------------------------------------- 37d4 MACRO_Execute_Entry,Count: 37d4 37d4 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 37d4 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 37d5 37d5 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 37d6 37d6 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 37d7 37d7 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH 37d8 37d8 fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 37d9 37d9 <halt> ; Flow R 37da ; -------------------------------------------------------------------------------------- 37da ; 0x0132 Execute Family,Count 37da ; -------------------------------------------------------------------------------------- 37da MACRO_Execute_Family,Count: 37da 37da dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 37da fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 37db 37db ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 37dc 37dc seq_br_type 7 Unconditional Call; Flow C 0x37b0 seq_branch_adr 37b0 0x37b0 typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37dd 37dd fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 1c ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 37de ; -------------------------------------------------------------------------------------- 37de ; 0x013f Execute Select,Rendezvous 37de ; -------------------------------------------------------------------------------------- 37de MACRO_Execute_Select,Rendezvous: 37de 37de dispatch_brk_class 5 ; Flow J cc=True 0x38e0 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 37de fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38e0 0x38e0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 37df 37df fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 37e0 37e0 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37e1 37e1 ioc_fiubs 1 val ; Flow J cc=True 0x37f1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 37f1 0x37f1 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_b_adr 16 CSA/VAL_BUS 37e2 37e2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 37e3 37e3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x37e4 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 37e4 0x37e4 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 20 VR02:00 val_frame 2 37e4 37e4 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x37e8 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 37e8 0x37e8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 6 typ_rand 1 INC_LOOP_COUNTER 37e5 37e5 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 37e6 37e6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 37e7 37e7 ioc_fiubs 0 fiu seq_en_micro 0 37e8 37e8 seq_b_timing 0 Early Condition; Flow J cc=True 0x37e9 ; Flow J cc=#0x0 0x37e9 seq_br_type b Case False seq_branch_adr 37e9 0x37e9 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 37e9 37e9 fiu_load_var 1 hold_var; Flow J 0x37ed fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 37ed 0x37ed val_b_adr 22 VR07:02 val_frame 7 37ea 37ea seq_br_type 3 Unconditional Branch; Flow J 0x3827 seq_branch_adr 3827 0x3827 seq_en_micro 0 37eb 37eb fiu_load_var 1 hold_var; Flow J 0x37ed fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 37ed 0x37ed typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 31 VR06:11 val_frame 6 37ec 37ec seq_br_type 3 Unconditional Branch; Flow J 0x3827 seq_branch_adr 3827 0x3827 seq_en_micro 0 37ed 37ed fiu_mem_start 2 start-rd; Flow J cc=True 0x37ef ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37ef 0x37ef seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37ee 37ee seq_br_type 3 Unconditional Branch; Flow J 0x37e4 seq_branch_adr 37e4 0x37e4 37ef 37ef seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 37f0 37f0 seq_br_type 7 Unconditional Call; Flow C 0x3827 seq_branch_adr 3827 0x3827 seq_en_micro 0 37f1 37f1 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x37ff seq_br_type 0 Branch False seq_branch_adr 37ff 0x37ff seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 37f2 37f2 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 37f3 37f3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 37f4 37f4 fiu_mem_start 2 start-rd; Flow J 0x37f5 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 37f5 0x37f5 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 37f5 37f5 seq_br_type 3 Unconditional Branch; Flow J 0x37f6 seq_branch_adr 37f6 0x37f6 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 37f6 37f6 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x37fa fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 37fa 0x37fa seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37f7 37f7 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 37f8 37f8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 37f9 37f9 ioc_fiubs 0 fiu seq_en_micro 0 37fa 37fa fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x3801 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3801 0x3801 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 37fb 37fb fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x3827 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3827 0x3827 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 20 TR02:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37fc 37fc ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x37f6 seq_br_type 1 Branch True seq_branch_adr 37f6 0x37f6 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 37fd 37fd fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 37fe 37fe seq_br_type 3 Unconditional Branch; Flow J 0x37f6 seq_branch_adr 37f6 0x37f6 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 37ff 37ff ioc_adrbs 2 typ ; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3800 3800 fiu_mem_start 2 start-rd; Flow J 0x37f5 seq_br_type 3 Unconditional Branch seq_branch_adr 37f5 0x37f5 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 3801 ; -------------------------------------------------------------------------------------- 3801 ; Comes from: 3801 ; 37fa C #0x0 from color 0x37e0 3801 ; -------------------------------------------------------------------------------------- 3801 3801 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 3802 3802 fiu_load_tar 1 hold_tar; Flow J 0x3806 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3806 0x3806 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 3803 3803 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x3805 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 3805 0x3805 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3804 3804 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3814 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 3814 0x3814 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3805 3805 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3806 3806 ioc_load_wdr 0 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP val_b_adr 10 TOP 3807 3807 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 3808 3808 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3809 0x3809 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3809 3809 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 380a 380a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 380b 380b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 380c 380c fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 380d 380d fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 0 fiu typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 380e 380e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 380f 380f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3812 seq_br_type 1 Branch True seq_branch_adr 3812 0x3812 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 3810 3810 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 3811 3811 ioc_load_wdr 0 ; Flow J 0x3896 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3812 3812 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 3813 3813 ioc_load_wdr 0 ; Flow J 0x3896 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3814 3814 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 3815 3815 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3823 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3823 0x3823 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 3816 3816 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 3817 3817 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3818 0x3818 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3818 3818 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 3819 3819 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 381a 381a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 381b 381b fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 381c 381c ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 381d 381d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 381e 381e seq_b_timing 1 Latch Condition; Flow J cc=True 0x3821 seq_br_type 1 Branch True seq_branch_adr 3821 0x3821 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 381f 381f fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 3820 3820 ioc_load_wdr 0 ; Flow J 0x3896 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3821 3821 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 3822 3822 ioc_load_wdr 0 ; Flow J 0x3896 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3896 0x3896 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3823 3823 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3824 3824 ioc_tvbs 2 fiu+val; Flow C 0x38e4 seq_br_type 7 Unconditional Call seq_branch_adr 38e4 0x38e4 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3825 3825 seq_br_type 5 Call True; Flow C cc=True 0x3276 seq_branch_adr 3276 0x3276 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 09 GP09 typ_c_lit 0 typ_frame 1e 3826 3826 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3827 ; -------------------------------------------------------------------------------------- 3827 ; Comes from: 3827 ; 37f0 C from color 0x37e0 3827 ; 37fb C True from color 0x37e0 3827 ; -------------------------------------------------------------------------------------- 3827 3827 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 2e TR07:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 3828 3828 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 1 3829 3829 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x382a ; Flow J cc=#0x0 0x3831 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3831 0x3831 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 382a 382a fiu_load_var 1 hold_var; Flow J cc=True 0x382b ; Flow J cc=#0x0 0x3847 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3847 0x3847 seq_en_micro 0 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 382b 382b fiu_mem_start 3 start-wr; Flow J 0x382c ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 382c 382c fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x337f fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 382d 382d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x38e4 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 38e4 0x38e4 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 382e 382e seq_b_timing 1 Latch Condition; Flow J cc=True 0x3373 seq_br_type 1 Branch True seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 382f 382f seq_br_type 5 Call True; Flow C cc=True 0x327b seq_branch_adr 327b 0x327b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3830 3830 seq_br_type 7 Unconditional Call; Flow C 0x32b2 seq_branch_adr 32b2 0x32b2 3831 3831 seq_br_type 3 Unconditional Branch; Flow J 0x3834 seq_branch_adr 3834 0x3834 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3832 3832 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3836 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3836 0x3836 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 3833 3833 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3834 3834 fiu_load_var 1 hold_var; Flow J cc=True 0x382b fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 382b 0x382b typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 3835 3835 seq_br_type 7 Unconditional Call; Flow C 0x382b seq_branch_adr 382b 0x382b val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3836 3836 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA 3837 3837 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3843 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3843 0x3843 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR07:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3838 3838 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f 3839 3839 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 383a 383a fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x383b fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 383f 0x383f typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 20 VR11:00 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 383b 383b ioc_tvbs 2 fiu+val; Flow C 0x38e4 seq_br_type 7 Unconditional Call seq_branch_adr 38e4 0x38e4 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 383c 383c fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3373 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 383d 383d seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 383e 383e seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 383f 383f fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3841 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3841 0x3841 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 3840 3840 seq_br_type 3 Unconditional Branch; Flow J 0x3845 seq_branch_adr 3845 0x3845 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 3841 3841 seq_br_type 2 Push (branch address); Flow J 0x3842 seq_branch_adr 383f 0x383f 3842 3842 seq_br_type 3 Unconditional Branch; Flow J 0x38e2 seq_branch_adr 38e2 0x38e2 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3843 3843 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3844 3844 seq_br_type 7 Unconditional Call; Flow C 0x38e4 seq_branch_adr 38e4 0x38e4 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3845 3845 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3846 3846 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3847 3847 seq_br_type 3 Unconditional Branch; Flow J 0x3834 seq_branch_adr 3834 0x3834 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3848 3848 fiu_load_tar 1 hold_tar; Flow J 0x3849 fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3849 0x3849 seq_int_reads 5 RESOLVE RAM typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3849 3849 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x384b fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 384b 0x384b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 384a 384a ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x385b seq_br_type 1 Branch True seq_branch_adr 385b 0x385b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 384b 384b fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 384c 384c fiu_mem_start 2 start-rd; Flow J cc=False 0x3859 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 3859 0x3859 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR02:03 val_alu_func 1 A_PLUS_B val_b_adr 37 VR02:17 val_frame 2 384d 384d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3857 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3857 0x3857 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 384e 384e fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 384f 384f fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3850 3850 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3851 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 384c 0x384c typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3851 3851 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3852 0x3852 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 3852 3852 ioc_fiubs 2 typ ; Flow R cc=True ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 3853 0x3853 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 3853 3853 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3854 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 23 VR02:03 val_frame 2 3854 3854 ioc_fiubs 0 fiu ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_alu_func 1b A_OR_B typ_b_adr 20 TR11:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3855 3855 seq_br_type 7 Unconditional Call; Flow C 0x38e4 seq_branch_adr 38e4 0x38e4 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 3856 3856 seq_br_type 3 Unconditional Branch; Flow J 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3857 3857 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? 3858 3858 seq_br_type 3 Unconditional Branch; Flow J 0x384c seq_branch_adr 384c 0x384c 3859 3859 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_b_adr 22 TR06:02 typ_frame 6 typ_mar_cntl 4 RESTORE_MAR 385a 385a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 385b 385b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x385c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 385d 0x385d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_c_adr 36 GP09 val_c_source 0 FIU_BUS 385c 385c fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x39b6 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 39b6 0x39b6 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 385d 385d typ_a_adr 21 TR07:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 385e 385e seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 385f 385f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x386e seq_br_type 1 Branch True seq_branch_adr 386e 0x386e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3860 3860 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 3861 3861 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x3892 seq_br_type 0 Branch False seq_branch_adr 3892 0x3892 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3862 3862 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3863 3863 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 3864 3864 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3865 3865 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3869 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3869 0x3869 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3866 3866 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 3867 3867 ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 3868 3868 seq_br_type 3 Unconditional Branch; Flow J 0x385f seq_branch_adr 385f 0x385f typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3869 3869 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 386a 386a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 386b 386b ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 386c 386c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 386d 386d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3868 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3868 0x3868 seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 386e 386e fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 386f 386f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3874 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3874 0x3874 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3870 3870 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 3871 3871 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3872 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 386e 0x386e typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 3872 3872 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3873 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3873 3873 ioc_tvbs 1 typ+fiu; Flow J 0x3373 seq_br_type 3 Unconditional Branch seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3874 3874 fiu_mem_start 2 start-rd; Flow C 0x3347 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3347 0x3347 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3875 3875 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x387b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 387b 0x387b seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3876 3876 ioc_fiubs 2 typ ; Flow J 0x3877 seq_br_type 3 Unconditional Branch seq_branch_adr 3877 0x3877 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3877 3877 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3890 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3890 0x3890 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 3878 3878 fiu_load_oreg 1 hold_oreg; Flow C 0x335c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335c 0x335c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 3879 3879 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x387b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 387b 0x387b seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 387a 387a ioc_fiubs 2 typ ; Flow J 0x3877 seq_br_type 3 Unconditional Branch seq_branch_adr 3877 0x3877 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 387b 387b seq_br_type 3 Unconditional Branch; Flow J 0x387f seq_branch_adr 387f 0x387f 387c 387c seq_br_type 3 Unconditional Branch; Flow J 0x387f seq_branch_adr 387f 0x387f 387d 387d fiu_mem_start 2 start-rd; Flow J 0x3457 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3457 0x3457 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 387e 387e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3882 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3882 0x3882 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 387f 387f seq_br_type 2 Push (branch address); Flow J 0x3880 seq_branch_adr 3877 0x3877 3880 3880 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 3881 3881 ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3882 3882 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3883 3883 ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3884 3884 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3885 3885 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 3886 3886 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x388f seq_br_type 1 Branch True seq_branch_adr 388f 0x388f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 3887 3887 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 3888 3888 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x388a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 388a 0x388a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3889 3889 fiu_fill_mode_src 0 ; Flow J 0x388c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 388c 0x388c typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 388a 388a fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 388b 388b fiu_fill_mode_src 0 ; Flow J 0x388c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 388c 0x388c typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 388c 388c ioc_fiubs 2 typ ; Flow J 0x388d seq_br_type 2 Push (branch address) seq_branch_adr 3886 0x3886 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 388d 388d fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 388e 388e ioc_fiubs 0 fiu ; Flow J 0x39e0 seq_br_type 3 Unconditional Branch seq_branch_adr 39e0 0x39e0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 388f 388f seq_br_type 3 Unconditional Branch; Flow J 0x3877 seq_branch_adr 3877 0x3877 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3890 3890 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a84 seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 3891 3891 seq_br_type 3 Unconditional Branch; Flow J 0x3860 seq_branch_adr 3860 0x3860 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3892 3892 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 3893 3893 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3894 3894 ioc_load_wdr 0 ; Flow J 0x3895 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3895 3895 fiu_mem_start 2 start-rd; Flow J 0x3466 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3466 0x3466 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3896 3896 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3897 3897 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 3898 3898 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3899 3899 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x389b fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 389b 0x389b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_b_adr 20 VR02:00 val_frame 2 389a 389a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x389a ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 389a 0x389a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 14 BOT - 1 389b 389b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x38a3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38a3 0x38a3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2f VR02:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 389c 389c fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x389d fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 389d 0x389d typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 389d 389d ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 0 LOAD_CONTROL_TOP 389e 389e fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 389f 389f seq_b_timing 0 Early Condition; Flow J cc=True 0x38a4 seq_br_type 1 Branch True seq_branch_adr 38a4 0x38a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 38a0 38a0 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x389d ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 389d 0x389d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 38a1 38a1 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 38a2 38a2 fiu_mem_start 2 start-rd; Flow J 0x389d ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 389d 0x389d seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 38a3 38a3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 38a4 38a4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 38a5 38a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 38a6 38a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 38a7 38a7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 38a8 38a8 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x38a9 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 38b0 0x38b0 seq_int_reads 0 TYP VAL BUS seq_random 31 ? typ_b_adr 03 GP03 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38a9 38a9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 39 ? typ_a_adr 22 TR02:02 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 38aa 38aa fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x38ad fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 38ad 0x38ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_frame 2 38ab 38ab fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38ac 38ac fiu_mem_start 2 start-rd; Flow J 0x2abf ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2abf 0x2abf typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38ad 38ad fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38ae 38ae ioc_tvbs 1 typ+fiu val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38af 38af fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2abf fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2abf 0x2abf typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 38b0 38b0 ioc_adrbs 1 val ; Flow C cc=True 0x38b7 ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 38b7 0x38b7 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 38b1 38b1 seq_br_type 3 Unconditional Branch; Flow J 0x38b5 seq_branch_adr 38b5 0x38b5 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 38b2 38b2 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38b3 38b3 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ae seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 38b4 38b4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 38b5 38b5 seq_br_type 7 Unconditional Call; Flow C 0x38e4 seq_branch_adr 38e4 0x38e4 seq_en_micro 0 38b6 38b6 fiu_mem_start 2 start-rd; Flow J 0x38b2 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 38b2 0x38b2 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 38b7 ; -------------------------------------------------------------------------------------- 38b7 ; Comes from: 38b7 ; 38b0 C True from color 0x38b0 38b7 ; -------------------------------------------------------------------------------------- 38b7 38b7 fiu_mem_start 2 start-rd; Flow C 0x32fe fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 38b8 38b8 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 38b9 38b9 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38bd ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38bd 0x38bd seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38ba 38ba fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 24 TR05:04 typ_frame 5 38bb 38bb fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 38bc 38bc ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 38bd 38bd fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38be 38be <default> 38bf 38bf fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x38c8 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38c8 0x38c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38c0 38c0 seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 38c1 38c1 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38c7 ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38c7 0x38c7 seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38c2 38c2 <default> 38c3 38c3 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 36 TR13:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38c4 38c4 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 38c5 38c5 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 38c6 0x38c6 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 38c6 38c6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 38c7 38c7 fiu_mem_start 2 start-rd; Flow J 0x38be ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38be 0x38be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38c8 38c8 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38c9 38c9 seq_b_timing 0 Early Condition; Flow J cc=True 0x38ca ; Flow J cc=#0x0 0x38ca seq_br_type b Case False seq_branch_adr 38ca 0x38ca seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 38ca 38ca seq_br_type 3 Unconditional Branch; Flow J 0x38cf seq_branch_adr 38cf 0x38cf 38cb 38cb seq_br_type 3 Unconditional Branch; Flow J 0x38d4 seq_branch_adr 38d4 0x38d4 38cc 38cc seq_br_type 3 Unconditional Branch; Flow J 0x38d8 seq_branch_adr 38d8 0x38d8 38cd 38cd seq_br_type 3 Unconditional Branch; Flow J 0x38ce seq_branch_adr 38ce 0x38ce 38ce 38ce ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38cf 38cf ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 38d0 38d0 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 37 TR13:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38d1 38d1 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 38d2 38d2 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38d3 38d3 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 38d4 38d4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 01 GP01 val_b_adr 39 VR02:19 val_frame 2 38d5 38d5 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 38d6 38d6 fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38d7 38d7 fiu_mem_start 2 start-rd; Flow J 0x38be ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38be 0x38be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38d8 38d8 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 11 val_rand a PASS_B_HIGH 38d9 38d9 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 38da 38da fiu_mem_start 3 start-wr; Flow C 0x3b5d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b5d 0x3b5d seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38db 38db fiu_mem_start 2 start-rd; Flow J 0x38be ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38be 0x38be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38dc 38dc seq_br_type 7 Unconditional Call; Flow C 0x38e2 seq_branch_adr 38e2 0x38e2 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38dd 38dd seq_br_type 3 Unconditional Branch; Flow J 0x37b4 seq_branch_adr 37b4 MACRO_Execute_Entry,Rendezvous 38de 38de seq_br_type 7 Unconditional Call; Flow C 0x38e2 seq_branch_adr 38e2 0x38e2 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38df 38df seq_br_type 3 Unconditional Branch; Flow J 0x37ca seq_branch_adr 37ca MACRO_Execute_Family,Rendezvous 38e0 38e0 seq_br_type 7 Unconditional Call; Flow C 0x38e2 seq_branch_adr 38e2 0x38e2 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38e1 38e1 seq_br_type 3 Unconditional Branch; Flow J 0x37de seq_branch_adr 37de MACRO_Execute_Select,Rendezvous 38e2 ; -------------------------------------------------------------------------------------- 38e2 ; Comes from: 38e2 ; 38e0 C from color MACRO_Execute_Select,Rendezvous 38e2 ; -------------------------------------------------------------------------------------- 38e2 38e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 38e3 38e3 fiu_mem_start 3 start-wr; Flow J 0x3b4e fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 38e4 ; -------------------------------------------------------------------------------------- 38e4 ; Comes from: 38e4 ; 37be C from color 0x0000 38e4 ; 3824 C from color 0x3803 38e4 ; 382d C from color 0x0000 38e4 ; 383b C from color 0x0000 38e4 ; 3844 C from color 0x0000 38e4 ; 3855 C from color 0x0000 38e4 ; 38b5 C from color 0x38b0 38e4 ; -------------------------------------------------------------------------------------- 38e4 38e4 ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38e5 38e5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 38e6 38e6 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f 38e7 38e7 ioc_adrbs 1 val ; Flow C 0x33e2 seq_br_type 7 Unconditional Call seq_branch_adr 33e2 0x33e2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 09 GP09 38e8 38e8 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 38e9 38e9 ioc_tvbs 2 fiu+val; Flow C 0x3373 seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38ea 38ea fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 38eb 38eb fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 3c TR12:1c typ_b_adr 07 GP07 typ_frame 12 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 38ec 38ec fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 38ed 38ed fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x38f1 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 38f1 0x38f1 typ_a_adr 30 TR1b:10 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 38ee 38ee fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 31 TR1b:11 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 38ef 38ef fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 33 TR1b:13 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 38f0 38f0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x38f4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 38f4 0x38f4 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 38f1 38f1 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 32 TR1b:12 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 38f2 38f2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 34 TR1b:14 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 38f3 38f3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x38f4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 38f4 0x38f4 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 38f4 38f4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 35 TR1b:15 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 35 VR1b:15 val_frame 1b 38f5 38f5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 08 GP08 typ_b_adr 36 TR1b:16 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 36 VR1b:16 val_frame 1b 38f6 38f6 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 38 TR1b:18 typ_b_adr 37 TR1b:17 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 37 VR1b:17 val_frame 1b 38f7 38f7 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 31 VR07:11 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 38f8 38f8 ioc_load_wdr 0 ; Flow C cc=True 0x390e seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 390e 0x390e typ_b_adr 39 TR1b:19 typ_frame 1b val_b_adr 39 VR1b:19 val_frame 1b 38f9 38f9 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 38fa 38fa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 3d TR1b:1d typ_b_adr 04 GP04 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 38fb 38fb fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3d VR1b:1d val_frame 1b 38fc 38fc ioc_load_wdr 0 ; Flow C cc=True 0x3910 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3910 0x3910 typ_b_adr 3e TR1b:1e typ_frame 1b val_b_adr 3e VR1b:1e val_frame 1b 38fd 38fd ioc_adrbs 1 val ; Flow C 0x3ae7 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3ae7 0x3ae7 typ_alu_func 1a PASS_B typ_b_adr 33 TR05:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 0 PASS_A 38fe 38fe fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3907 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3907 0x3907 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 08 GP08 38ff 38ff fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 3900 3900 ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3901 3901 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 0 LOAD_CONTROL_TOP val_rand 2 DEC_LOOP_COUNTER 3902 3902 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3903 3903 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 22 VR06:02 val_frame 6 3904 3904 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL 3905 3905 ioc_load_wdr 0 ; Flow C cc=True 0x390d ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 390d 0x390d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3906 3906 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3903 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3903 0x3903 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 3907 3907 fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3908 0x3908 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 21 VR06:01 val_frame 6 3908 3908 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 3909 3909 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 38 VR09:18 val_frame 9 390a 390a fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 37 VR09:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 9 390b 390b ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 390c 390c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 390d 390d seq_br_type 3 Unconditional Branch; Flow J 0x2a84 seq_branch_adr 2a84 0x2a84 390e ; -------------------------------------------------------------------------------------- 390e ; Comes from: 390e ; 38f8 C True from color 0x0000 390e ; -------------------------------------------------------------------------------------- 390e 390e val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 2d VR1b:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1b 390f 390f seq_br_type a Unconditional Return; Flow R val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 29 VR05:09 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 3910 ; -------------------------------------------------------------------------------------- 3910 ; Comes from: 3910 ; 38fc C True from color 0x0000 3910 ; -------------------------------------------------------------------------------------- 3910 3910 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 33 TR05:13 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 39 VR05:19 val_frame 5 val_rand 9 PASS_A_HIGH 3911 3911 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 06 GP06 val_b_adr 06 GP06 3912 3912 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 3913 3913 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3914 3914 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3915 3915 ioc_load_wdr 0 ; Flow R cc=False ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3916 0x3916 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3916 3916 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3917 3917 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3918 3918 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3919 ; -------------------------------------------------------------------------------------- 3919 ; Comes from: 3919 ; 0218 C from color MACRO_Action_Accept_Activation 3919 ; 2eb5 C from color 0x2eaf 3919 ; 2eb6 C from color 0x2eaf 3919 ; -------------------------------------------------------------------------------------- 3919 3919 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x391a fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3922 0x3922 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3a VR02:1a val_frame 2 391a 391a ioc_tvbs 2 fiu+val; Flow C 0x3373 seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 seq_random 02 ? typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 391b 391b fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 391c 391c seq_b_timing 1 Latch Condition; Flow J cc=True 0x391f seq_br_type 1 Branch True seq_branch_adr 391f 0x391f typ_a_adr 30 TR08:10 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 391d 391d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 391e 391e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 391f 391f fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3920 3920 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3ae8 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3ae8 0x3ae8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3921 3921 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 3922 3922 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 08 GP08 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3923 3923 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3924 3924 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame f typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3925 3925 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3933 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3933 0x3933 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3926 3926 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x392a fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 392a 0x392a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3927 3927 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 3928 3928 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN 3929 3929 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN 392a 392a fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 392b 0x392b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1c typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 392b 392b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 392c 392c fiu_fill_mode_src 0 ; Flow J cc=False 0x392e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 392e 0x392e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 392d 392d fiu_fill_mode_src 0 ; Flow J 0x3931 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3931 0x3931 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 392e 392e fiu_fill_mode_src 0 ; Flow C cc=False 0x307b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 307b 0x307b seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 392f 392f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3930 3930 fiu_load_var 1 hold_var; Flow J 0x3931 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3931 0x3931 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 3931 3931 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 3932 3932 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3933 3933 seq_br_type 7 Unconditional Call; Flow C 0x3938 seq_branch_adr 3938 0x3938 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3934 3934 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3935 3935 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3936 3936 fiu_mem_start 3 start-wr; Flow J 0x3937 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 326a 0x326a typ_a_adr 30 TR08:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3937 3937 ioc_load_wdr 0 ; Flow J 0x6bd seq_br_type 3 Unconditional Branch seq_branch_adr 06bd 0x06bd typ_b_adr 02 GP02 val_b_adr 02 GP02 3938 ; -------------------------------------------------------------------------------------- 3938 ; Comes from: 3938 ; 3933 C from color 0x062d 3938 ; -------------------------------------------------------------------------------------- 3938 3938 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3939 3939 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 393a 393a ioc_load_wdr 0 ; Flow J cc=True 0x3aeb ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aeb 0x3aeb seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_frame 5 393b 393b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 393c 393c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR 393d 393d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3b GP04 val_c_source 0 FIU_BUS 393e 393e fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 393f 393f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 3940 3940 seq_br_type a Unconditional Return; Flow R 3941 ; -------------------------------------------------------------------------------------- 3941 ; Comes from: 3941 ; 0931 C from color 0x0000 3941 ; -------------------------------------------------------------------------------------- 3941 3941 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3942 3942 ioc_tvbs 2 fiu+val; Flow C 0x3373 seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3943 3943 fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3944 3944 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3947 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3947 0x3947 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3945 3945 <default> 3946 3946 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3948 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3948 0x3948 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3947 3947 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3948 3948 seq_br_type 7 Unconditional Call; Flow C 0x3ae7 seq_branch_adr 3ae7 0x3ae7 3949 3949 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 394a 394a fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a4 fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 08 GP08 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 394b 394b fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 39 TR1b:19 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 394c 394c ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 01 GP01 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 01 GP01 394d 394d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 394e 394e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 394f 394f fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3e VR03:1e val_frame 3 3950 3950 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34c0 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 seq_random 02 ? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3951 3951 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x395a ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 395a 0x395a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3952 3952 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_b_adr 08 GP08 typ_frame 1b 3953 3953 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x395a fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 395a 0x395a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3954 3954 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 3955 3955 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 3956 3956 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3957 3957 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3958 3958 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER 3959 3959 ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 395a 395a fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 395b 395b fiu_mem_start 3 start-wr; Flow C cc=False 0x20d ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 395c 395c ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1 val_b_adr 0f GP0f 395d ; -------------------------------------------------------------------------------------- 395d ; Comes from: 395d ; 022f C True from color MACRO_Action_Signal_Activated 395d ; 2ebb C from color 0x0000 395d ; 2ebc C from color 0x0000 395d ; -------------------------------------------------------------------------------------- 395d 395d fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3972 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3972 0x3972 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 09 GP09 395e 395e seq_br_type 0 Branch False; Flow J cc=False 0x396b seq_branch_adr 396b 0x396b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 395f 395f fiu_load_tar 1 hold_tar; Flow J cc=False 0x3aeb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3aeb 0x3aeb seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 3960 3960 ioc_load_wdr 0 ; Flow C cc=True 0x398f ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 398f 0x398f seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 04 GP04 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 3961 3961 fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3962 3962 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x396d ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 396d 0x396d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3963 3963 seq_br_type 2 Push (branch address); Flow J 0x3964 seq_branch_adr 3965 0x3965 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3964 3964 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True ; Flow J cc=False 0x3966 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 3966 0x3966 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3965 3965 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x62f ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 062f 0x062f seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3966 3966 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3967 ; Flow J cc=#0x0 0x3973 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 3973 0x3973 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_c_adr 3f GP00 val_frame 5 3967 3967 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 3968 0x3968 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3968 3968 ioc_load_wdr 0 ; Flow C cc=False 0x32a4 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a4 0x32a4 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 5 3969 3969 fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 396a 396a seq_br_type 3 Unconditional Branch; Flow J 0x3961 seq_branch_adr 3961 0x3961 396b 396b seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 396c 396c seq_br_type 1 Branch True; Flow J cc=True 0x395d seq_branch_adr 395d 0x395d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 396d 396d fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 396e 396e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3971 seq_br_type 1 Branch True seq_branch_adr 3971 0x3971 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 04 GP04 typ_b_adr 08 GP08 396f 396f fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3970 3970 ioc_load_wdr 0 typ_b_adr 03 GP03 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 3971 3971 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3972 3972 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3973 3973 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3974 3974 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3975 3975 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3976 3976 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3979 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3979 0x3979 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3977 3977 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x3983 ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 3983 0x3983 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3978 3978 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x3986 ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 3986 0x3986 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3979 3979 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x397e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 397e 0x397e typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 397a 397a ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 397b 397b ioc_tvbs 2 fiu+val typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 397c 397c seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 397d 397d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 397e 397e seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 397f 397f ioc_adrbs 3 seq ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3980 3980 fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3981 3981 seq_b_timing 1 Latch Condition; Flow C cc=True 0x33bc seq_br_type 5 Call True seq_branch_adr 33bc 0x33bc 3982 3982 seq_br_type 7 Unconditional Call; Flow C 0x326a seq_branch_adr 326a 0x326a typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3983 3983 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3989 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3989 0x3989 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 3984 3984 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_b_adr 01 GP01 3985 3985 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3986 3986 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3989 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3989 0x3989 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 3987 3987 ioc_load_wdr 0 ; Flow J cc=True 0x398c ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 398c 0x398c seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 9 PASS_A_HIGH 3988 3988 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3989 ; -------------------------------------------------------------------------------------- 3989 ; Comes from: 3989 ; 3983 C True from color 0x3976 3989 ; 3986 C True from color 0x3978 3989 ; -------------------------------------------------------------------------------------- 3989 3989 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 398a 398a fiu_mem_start 7 start_wr_if_true; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 398b 0x398b 398b 398b fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR02:11 val_frame 2 398c 398c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x398d fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 398d 398d ioc_load_wdr 0 ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 398e 398e ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 398f ; -------------------------------------------------------------------------------------- 398f ; Comes from: 398f ; 3960 C True from color 0x03fa 398f ; -------------------------------------------------------------------------------------- 398f 398f seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3990 0x3990 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 3990 3990 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3991 3991 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3992 3992 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3993 3993 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x399e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 399e 0x399e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 3994 3994 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3995 0x3995 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3995 3995 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3996 3996 ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 3997 3997 fiu_mem_start 2 start-rd; Flow C 0x34ae ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34ae 0x34ae typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 2b TR06:0b typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3998 3998 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 3999 3999 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x39a0 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 39a0 0x39a0 typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 399a 399a fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 399b 399b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 399c 399c fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3c GP03 val_c_source 0 FIU_BUS 399d 399d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3999 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3999 0x3999 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 399e 399e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x39a0 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 39a0 0x39a0 typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 399f 399f seq_br_type 3 Unconditional Branch; Flow J 0x3990 seq_branch_adr 3990 0x3990 39a0 ; -------------------------------------------------------------------------------------- 39a0 ; Comes from: 39a0 ; 3999 C from color 0x398f 39a0 ; 399e C from color 0x398f 39a0 ; -------------------------------------------------------------------------------------- 39a0 39a0 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 39a1 39a1 fiu_mem_start 3 start-wr; Flow J 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39a2 39a2 fiu_mem_start 2 start-rd; Flow J cc=False 0x39a6 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39a6 0x39a6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 39a3 39a3 <default> 39a4 39a4 fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c5 0x39c5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39a5 39a5 seq_br_type 3 Unconditional Branch; Flow J 0x39c1 seq_branch_adr 39c1 0x39c1 seq_en_micro 0 39a6 39a6 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39a7 39a7 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 39a8 39a8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3373 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39a9 39a9 fiu_mem_start 2 start-rd; Flow J cc=False 0x39b0 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39b0 0x39b0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 39aa 39aa seq_br_type 2 Push (branch address); Flow J 0x39ab seq_branch_adr 39b2 0x39b2 39ab 39ab fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c5 0x39c5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39ac 39ac seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39ad 39ad seq_br_type 1 Branch True; Flow J cc=True 0x39c3 seq_branch_adr 39c3 0x39c3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39ae 39ae fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_frame 2 39af 39af ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39b0 39b0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 39b1 39b1 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39b2 39b2 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x68d fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 39b3 39b3 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39b4 39b4 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x68d seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 39b5 39b5 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39b6 39b6 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR11:01 val_frame 11 39b7 39b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3373 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39b8 39b8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39b9 39b9 seq_br_type 2 Push (branch address); Flow J 0x39ba seq_branch_adr 39bc 0x39bc 39ba 39ba fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c5 0x39c5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39bb 39bb seq_br_type 3 Unconditional Branch; Flow J 0x39c1 seq_branch_adr 39c1 0x39c1 seq_en_micro 0 39bc 39bc seq_br_type 1 Branch True; Flow J cc=True 0x39be seq_branch_adr 39be 0x39be seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_frame 2 39bd 39bd ioc_adrbs 2 typ ; Flow C 0x3b75 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b75 0x3b75 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39be 39be fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39bf 39bf fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 39c0 39c0 ioc_load_wdr 0 ; Flow C 0x68d seq_br_type 7 Unconditional Call seq_branch_adr 068d 0x068d typ_b_adr 05 GP05 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 39c1 39c1 fiu_tivi_src c mar_0xc; Flow C 0x349d ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 39c2 39c2 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39c3 39c3 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39c4 39c4 fiu_load_tar 1 hold_tar; Flow J 0x39c5 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39c5 0x39c5 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39c5 39c5 ioc_load_wdr 0 ; Flow J cc=True 0x39c7 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39c7 0x39c7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 5 39c6 39c6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3aea seq_br_type 9 Return False seq_branch_adr 3aea 0x3aea seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? val_a_adr 3e VR05:1e val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_frame 5 39c7 39c7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 2e TR02:0e typ_b_adr 08 GP08 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39c8 39c8 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 39c9 39c9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 39ca 39ca fiu_load_var 1 hold_var; Flow J cc=True 0x39db fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39db 0x39db seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 39cb 39cb seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 39cc 0x39cc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_frame 5 39cc 39cc fiu_mem_start 2 start-rd; Flow C 0x34ae ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ae 0x34ae typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39cd 39cd fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39ce 39ce fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 39cf 39cf fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 31 GP0e val_c_source 0 FIU_BUS 39d0 39d0 fiu_load_var 1 hold_var; Flow J cc=False 0x39d2 fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 39d2 0x39d2 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 39d1 39d1 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x39db seq_br_type 8 Return True seq_branch_adr 39db 0x39db seq_en_micro 0 39d2 39d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x39d6 seq_br_type 1 Branch True seq_branch_adr 39d6 0x39d6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 39d3 39d3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 39d4 0x39d4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 39d4 39d4 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39d5 39d5 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 39d6 39d6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 39d7 0x39d7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 39d7 39d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x39da seq_br_type 1 Branch True seq_branch_adr 39da 0x39da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 39d8 39d8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39d9 39d9 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 39da 39da fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39db 39db fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 09 GP09 val_b_adr 0e GP0e 39dc 39dc ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 39dd 39dd fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39de 39de fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39df 39df fiu_load_tar 1 hold_tar; Flow J 0x39c5 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39c5 0x39c5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 39e0 39e0 seq_br_type 7 Unconditional Call; Flow C 0x337f seq_branch_adr 337f 0x337f 39e1 39e1 fiu_mem_start 2 start-rd; Flow J 0x39e2 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 39e1 0x39e1 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39e2 39e2 fiu_mem_start 4 continue seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 39e3 39e3 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3a1d fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a1d 0x3a1d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 39e4 39e4 fiu_load_var 1 hold_var; Flow J cc=True 0x3a13 fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3a13 0x3a13 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39e5 39e5 seq_br_type 0 Branch False; Flow J cc=False 0x39ee seq_branch_adr 39ee 0x39ee seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39e6 39e6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x39f3 fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 39f3 0x39f3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 34 TR08:14 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39e7 39e7 seq_br_type 1 Branch True; Flow J cc=True 0x3a1f seq_branch_adr 3a1f 0x3a1f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39e8 39e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a1f seq_br_type 1 Branch True seq_branch_adr 3a1f 0x3a1f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 39e9 39e9 seq_br_type 1 Branch True; Flow J cc=True 0x3a07 seq_branch_adr 3a07 0x3a07 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 2 39ea 39ea seq_br_type 1 Branch True; Flow J cc=True 0x39f7 seq_branch_adr 39f7 0x39f7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39eb 39eb fiu_mem_start 2 start-rd; Flow J cc=True 0x39f2 ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 39f2 0x39f2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 39ec 39ec fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x39ed fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3a1f 0x3a1f typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 39ed 39ed ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 39ee 39ee fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 39ef 39ef ioc_fiubs 1 val ; Flow C 0x34fb seq_br_type 7 Unconditional Call seq_branch_adr 34fb 0x34fb seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2a VR05:0a val_frame 5 39f0 39f0 ioc_tvbs 8 typ+mem; Flow J cc=True 0x39e6 seq_br_type 1 Branch True seq_branch_adr 39e6 0x39e6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 2d VR05:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 39f1 39f1 fiu_mem_start 2 start-rd; Flow J 0x34ae ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34ae 0x34ae typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39f2 39f2 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 05 ? 39f3 39f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 38 TR07:18 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39f4 39f4 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR13:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 39f5 39f5 fiu_mem_start 3 start-wr; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR07:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 39f6 39f6 ioc_load_wdr 0 ; Flow J 0x3a0f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a0f 0x3a0f typ_b_adr 03 GP03 39f7 39f7 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 39f8 39f8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x39eb seq_br_type 1 Branch True seq_branch_adr 39eb 0x39eb seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 39f9 39f9 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39fa 39fa ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 39fb 39fb fiu_mem_start 3 start-wr; Flow J 0x39fc seq_br_type 2 Push (branch address) seq_branch_adr 3a02 0x3a02 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 39fc 39fc ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 39fd 39fd fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 39fe 39fe fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 39ff 39ff ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 3a00 3a00 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 3a01 3a01 seq_br_type 3 Unconditional Branch; Flow J 0x3a1f seq_branch_adr 3a1f 0x3a1f 3a02 3a02 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3a03 3a03 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a04 3a04 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a05 3a05 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3a06 3a06 ioc_load_wdr 0 ; Flow J 0x3a3e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a3e 0x3a3e val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3a07 3a07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fe fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 2d TR08:0d typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a08 3a08 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 32 TR13:12 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3b VR13:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 3a09 3a09 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a11 seq_br_type 1 Branch True seq_branch_adr 3a11 0x3a11 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_a_adr 21 TR07:01 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR09:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 3a0a 3a0a fiu_mem_start 3 start-wr; Flow J 0x3a0b seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a0b 3a0b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a0c 3a0c fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 3a0d 3a0d fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a0e 3a0e ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 3a0f 3a0f seq_b_timing 1 Latch Condition; Flow C cc=False 0x6b4 seq_br_type 4 Call False seq_branch_adr 06b4 0x06b4 seq_en_micro 0 3a10 3a10 seq_br_type 3 Unconditional Branch; Flow J 0x3a13 seq_branch_adr 3a13 0x3a13 3a11 3a11 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a12 3a12 ioc_load_wdr 0 ; Flow J 0x3a0f seq_br_type 3 Unconditional Branch seq_branch_adr 3a0f 0x3a0f seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a13 3a13 fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a14 3a14 seq_br_type 7 Unconditional Call; Flow C 0x34fb seq_branch_adr 34fb 0x34fb seq_en_micro 0 3a15 3a15 ioc_tvbs 8 typ+mem; Flow J cc=True 0x3a19 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a19 0x3a19 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a16 3a16 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a17 3a17 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a18 3a18 fiu_mem_start 3 start-wr; Flow J 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a19 3a19 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a1a 3a1a seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 3a1b 3a1b ioc_adrbs 3 seq ; Flow C 0x6bd seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3a1c 3a1c seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3a1d 3a1d seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a1e 3a1e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3a1f 0x3a1f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a1f 3a1f seq_en_micro 0 seq_random 06 Pop_stack+? 3a20 3a20 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a84 seq_br_type 9 Return False seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT 3a21 ; -------------------------------------------------------------------------------------- 3a21 ; Comes from: 3a21 ; 0288 C from color 0x0000 3a21 ; 03fb C from color 0x0000 3a21 ; -------------------------------------------------------------------------------------- 3a21 3a21 fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a22 3a22 fiu_load_tar 1 hold_tar; Flow C cc=False 0x3a39 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3a39 0x3a39 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a23 3a23 ioc_load_wdr 0 ; Flow J cc=True 0x3aeb ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aeb 0x3aeb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 5 3a24 3a24 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 3a25 3a25 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a26 3a26 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a27 3a27 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a28 3a28 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a2a seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a2a 0x3a2a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 3a29 3a29 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a35 seq_br_type 8 Return True seq_branch_adr 3a35 0x3a35 seq_en_micro 0 3a2a 3a2a ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a2b 0x3a2b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a2b 3a2b fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a2c 3a2c ioc_load_wdr 0 ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a2d 3a2d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a2e 3a2e ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a2f 3a2f fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a30 3a30 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a31 3a31 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a32 3a32 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3a33 3a33 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3a34 0x3a34 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 3a34 3a34 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a2d seq_br_type 8 Return True seq_branch_adr 3a2d 0x3a2d 3a35 3a35 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a36 3a36 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a37 3a37 fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a38 3a38 seq_br_type 3 Unconditional Branch; Flow J 0x3a24 seq_branch_adr 3a24 0x3a24 3a39 ; -------------------------------------------------------------------------------------- 3a39 ; Comes from: 3a39 ; 3a22 C False from color 0x03fa 3a39 ; -------------------------------------------------------------------------------------- 3a39 3a39 ioc_adrbs 2 typ ; Flow C 0x349d seq_br_type 7 Unconditional Call seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a3a 3a3a seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a3b 3a3b fiu_mem_start 2 start-rd; Flow C 0x32fe ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a3c 3a3c fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a3d 3a3d ioc_fiubs 1 val ; Flow J 0x3a3f seq_br_type 3 Unconditional Branch seq_branch_adr 3a3f 0x3a3f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3e 3a3e ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3f 3a3f ioc_adrbs 1 val ; Flow J 0x3a40 seq_br_type 2 Push (branch address) seq_branch_adr 3a3d 0x3a3d typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a40 3a40 ioc_fiubs 1 val ; Flow J 0x3a45 seq_br_type 3 Unconditional Branch seq_branch_adr 3a45 0x3a45 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 29 VR05:09 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3a41 3a41 ioc_fiubs 1 val ; Flow J 0x3a43 seq_br_type 3 Unconditional Branch seq_branch_adr 3a43 0x3a43 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a42 3a42 ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a43 3a43 ioc_adrbs 1 val ; Flow J 0x3a44 seq_br_type 2 Push (branch address) seq_branch_adr 3a42 0x3a42 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a44 3a44 ioc_fiubs 1 val ; Flow J 0x3a45 seq_br_type 3 Unconditional Branch seq_branch_adr 3a45 0x3a45 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 23 VR07:03 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3a45 3a45 fiu_mem_start 5 start_rd_if_true; Flow C cc=True 0x34c0 ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 34c0 0x34c0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS 3a46 3a46 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3aad ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3aad 0x3aad typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a47 3a47 fiu_mem_start 4 continue; Flow C cc=False 0x3a6e ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3a6e 0x3a6e seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 3a48 3a48 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a49 3a49 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3aad fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aad 0x3aad seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2a VR05:0a val_frame 5 3a4a 3a4a ioc_fiubs 0 fiu ; Flow J cc=True 0x3aaf seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aaf 0x3aaf seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_c_adr 3e GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a4b 3a4b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3ac4 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3ac4 0x3ac4 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 01 GP01 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 3a4c 3a4c fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x3aac fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aac 0x3aac seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 3a4d 3a4d fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad9 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad9 0x3ad9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_rand 9 PASS_A_HIGH 3a4e 3a4e fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad9 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad9 0x3ad9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3a4f 3a4f fiu_mem_start 2 start-rd; Flow J cc=False 0x3a5c ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a5c 0x3a5c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR05:04 val_frame 5 3a50 3a50 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x32fe fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe seq_en_micro 0 typ_a_adr 03 GP03 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a51 3a51 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3a52 3a52 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3a99 fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3a99 0x3a99 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a53 3a53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3aab seq_br_type 5 Call True seq_branch_adr 3aab 0x3aab seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 3a54 3a54 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a57 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a57 0x3a57 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a55 3a55 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 3a56 3a56 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a57 3a57 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3a98 seq_br_type 5 Call True seq_branch_adr 3a98 0x3a98 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3a58 3a58 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x3373 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3373 0x3373 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a59 3a59 fiu_load_var 1 hold_var; Flow J cc=False 0x3a71 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3a71 0x3a71 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 3a5a 3a5a fiu_mem_start 2 start-rd; Flow C 0x3394 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a5b 3a5b fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x3a71 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3a71 0x3a71 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a5c 3a5c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3a50 seq_br_type 0 Branch False seq_branch_adr 3a50 0x3a50 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR05:07 val_frame 5 3a5d 3a5d fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a5e 3a5e ioc_fiubs 1 val ; Flow C 0x3ad9 seq_br_type 7 Unconditional Call seq_branch_adr 3ad9 0x3ad9 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 3a5f 3a5f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3abe fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3abe 0x3abe seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a60 3a60 ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a61 3a61 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x3a68 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a68 0x3a68 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a62 3a62 ioc_fiubs 2 typ ; Flow J cc=True 0x3a50 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a50 0x3a50 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 05 GP05 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a63 3a63 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3ad9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad9 0x3ad9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a64 3a64 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a50 seq_br_type 0 Branch False seq_branch_adr 3a50 0x3a50 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3a65 3a65 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3a50 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a50 0x3a50 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 3a66 3a66 fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad9 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad9 0x3ad9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 3a67 3a67 seq_br_type 3 Unconditional Branch; Flow J 0x3a50 seq_branch_adr 3a50 0x3a50 seq_en_micro 0 3a68 3a68 ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a69 3a69 seq_br_type 1 Branch True; Flow J cc=True 0x3a50 seq_branch_adr 3a50 0x3a50 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 3a6a 3a6a seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_en_micro 0 3a6b 3a6b ioc_fiubs 1 val ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a6c 0x3a6c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a6c 3a6c ioc_adrbs 1 val ; Flow J 0x3a6d seq_br_type 2 Push (branch address) seq_branch_adr 3a46 0x3a46 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a6d 3a6d fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34c0 ioc_tvbs 5 seq+seq seq_br_type 9 Return False seq_branch_adr 34c0 0x34c0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS 3a6e ; -------------------------------------------------------------------------------------- 3a6e ; Comes from: 3a6e ; 3a47 C False from color 0x0000 3a6e ; -------------------------------------------------------------------------------------- 3a6e 3a6e seq_br_type 7 Unconditional Call; Flow C 0x3373 seq_branch_adr 3373 0x3373 seq_en_micro 0 3a6f 3a6f fiu_mem_start 5 start_rd_if_true ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a70 3a70 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 3a71 3a71 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 3a72 3a72 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a73 3a73 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 3a74 3a74 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 3a75 3a75 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3a77 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3a77 0x3a77 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a76 3a76 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a77 3a77 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x3a78 ; Flow J cc=#0x0 0x3a78 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3a78 0x3a78 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS 3a78 3a78 ioc_adrbs 1 val ; Flow J 0x3acb seq_br_type 3 Unconditional Branch seq_branch_adr 3acb 0x3acb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a79 3a79 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7a 3a7a seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7b 3a7b seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7c 3a7c seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7d 3a7d seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7e 3a7e seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a7f 3a7f fiu_mem_start 2 start-rd; Flow J 0x3acf ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3acf 0x3acf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3a80 3a80 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a81 3a81 seq_br_type 3 Unconditional Branch; Flow J 0x3ad1 seq_branch_adr 3ad1 0x3ad1 3a82 3a82 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a83 3a83 ioc_adrbs 1 val ; Flow J 0x3acd seq_br_type 3 Unconditional Branch seq_branch_adr 3acd 0x3acd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a84 3a84 ioc_tvbs 2 fiu+val; Flow J 0x3ad6 seq_br_type 3 Unconditional Branch seq_branch_adr 3ad6 0x3ad6 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a85 3a85 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a86 3a86 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a87 3a87 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a88 3a88 ioc_adrbs 1 val ; Flow J 0x3acd seq_br_type 3 Unconditional Branch seq_branch_adr 3acd 0x3acd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a89 3a89 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8a 3a8a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8b 3a8b seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a8c 3a8c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8d 3a8d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8e 3a8e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8f 3a8f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a90 3a90 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a91 3a91 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a92 3a92 ioc_adrbs 1 val ; Flow J 0x3acd seq_br_type 3 Unconditional Branch seq_branch_adr 3acd 0x3acd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a93 3a93 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3a94 3a94 fiu_mem_start 2 start-rd; Flow J 0x3acf ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3acf 0x3acf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3a95 3a95 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a96 3a96 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a97 3a97 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a98 3a98 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3aad seq_br_type 9 Return False seq_branch_adr 3aad 0x3aad seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR13:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 13 3a99 3a99 val_c_adr 3e GP01 3a9a 3a9a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3ab8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ab8 0x3ab8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3a9b 3a9b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3a98 seq_br_type 5 Call True seq_branch_adr 3a98 0x3a98 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3a9c 3a9c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a9d 3a9d ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3a9e 3a9e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3aa3 seq_br_type 1 Branch True seq_branch_adr 3aa3 0x3aa3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 3a9f 3a9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3aa3 seq_br_type 1 Branch True seq_branch_adr 3aa3 0x3aa3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 3aa0 3aa0 seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3aa1 3aa1 ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3aa2 3aa2 ioc_fiubs 2 typ ; Flow J 0x3a45 seq_br_type 3 Unconditional Branch seq_branch_adr 3a45 0x3a45 typ_a_adr 06 GP06 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3aa3 3aa3 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3aa4 3aa4 ioc_adrbs 2 typ ; Flow J cc=True 0x3aa2 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aa2 0x3aa2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 26 VR05:06 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 5 3aa5 3aa5 seq_br_type 7 Unconditional Call; Flow C 0x34c0 seq_branch_adr 34c0 0x34c0 3aa6 3aa6 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3aad ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3aad 0x3aad typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3aa7 3aa7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 3aa8 3aa8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 3aa9 3aa9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 31 TR02:11 typ_frame 2 3aaa 3aaa ioc_load_wdr 0 ; Flow J 0x3aa2 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3aa2 0x3aa2 3aab 3aab seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x3aad seq_br_type 8 Return True seq_branch_adr 3aad 0x3aad seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 3aac 3aac fiu_mem_start 3 start-wr; Flow C 0x32fe ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe typ_b_adr 05 GP05 3aad 3aad seq_br_type 1 Branch True; Flow J cc=True 0x3ae6 seq_branch_adr 3ae6 0x3ae6 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 08 GP08 3aae 3aae seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 3aaf 3aaf seq_br_type 1 Branch True; Flow J cc=True 0x3ab8 seq_branch_adr 3ab8 0x3ab8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR13:14 typ_frame 13 3ab0 3ab0 fiu_mem_start 2 start-rd; Flow C 0x32ff ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3ab1 3ab1 fiu_tivi_src 1 tar_val; Flow C 0x210 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3ab2 3ab2 ioc_tvbs 5 seq+seq; Flow J cc=True 0x3ab8 seq_br_type 1 Branch True seq_branch_adr 3ab8 0x3ab8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3ab3 3ab3 fiu_mem_start 2 start-rd; Flow J 0x3ab4 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3a3d 0x3a3d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR13:1c val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 13 val_rand a PASS_B_HIGH 3ab4 3ab4 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3ab5 3ab5 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3ab6 3ab6 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 3ab7 3ab7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a4b seq_br_type 1 Branch True seq_branch_adr 3a4b 0x3a4b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 39 TR13:19 typ_frame 13 3ab8 3ab8 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 01 GP01 3ab9 3ab9 fiu_mem_start 2 start-rd; Flow J cc=True 0x3aba ; Flow J cc=#0x0 0x3aba ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3aba 0x3aba seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3aba 3aba seq_br_type 3 Unconditional Branch; Flow J 0x3ac4 seq_branch_adr 3ac4 0x3ac4 3abb 3abb seq_br_type 3 Unconditional Branch; Flow J 0x3ac4 seq_branch_adr 3ac4 0x3ac4 3abc 3abc seq_br_type 3 Unconditional Branch; Flow J 0x3ac7 seq_branch_adr 3ac7 0x3ac7 3abd 3abd seq_br_type 3 Unconditional Branch; Flow J 0x3ac9 seq_branch_adr 3ac9 0x3ac9 3abe 3abe fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3ac1 ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ac1 0x3ac1 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3abf 3abf fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3a60 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a60 0x3a60 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3ac0 3ac0 seq_br_type 3 Unconditional Branch; Flow J 0x3ac3 seq_branch_adr 3ac3 0x3ac3 seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3ac1 3ac1 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3ac2 3ac2 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3ac3 3ac3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3ac5 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ac5 0x3ac5 seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 39 VR02:19 val_frame 2 3ac4 3ac4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3ac5 3ac5 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 3ac6 3ac6 fiu_mem_start 3 start-wr; Flow J 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3ac7 3ac7 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3ac8 3ac8 fiu_mem_start 3 start-wr; Flow J 0x3b5d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b5d 0x3b5d seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3ac9 3ac9 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3aca 3aca fiu_mem_start 3 start-wr; Flow J 0x3b4e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4e 0x3b4e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3acb 3acb seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3acc 3acc seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3acd 3acd seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3ace 3ace seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 3acf 3acf seq_br_type 2 Push (branch address); Flow J 0x3ad0 seq_branch_adr 3ad6 0x3ad6 3ad0 3ad0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a21 0x3a21 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3ad1 3ad1 ioc_adrbs 3 seq ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3ad2 3ad2 seq_br_type 7 Unconditional Call; Flow C 0x662 seq_branch_adr 0662 0x0662 3ad3 3ad3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3ad5 seq_br_type 1 Branch True seq_branch_adr 3ad5 0x3ad5 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3ad4 3ad4 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3ad5 3ad5 seq_br_type 3 Unconditional Branch; Flow J 0x3ad6 seq_branch_adr 3ad6 0x3ad6 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3ad6 3ad6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3ad7 3ad7 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3ad8 3ad8 ioc_load_wdr 0 ; Flow J 0x62f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 062f 0x062f typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3ad9 ; -------------------------------------------------------------------------------------- 3ad9 ; Comes from: 3ad9 ; 3a4d C True from color 0x0000 3ad9 ; 3a4e C True from color 0x0000 3ad9 ; 3a5e C from color 0x0000 3ad9 ; 3a63 C True from color 0x0000 3ad9 ; 3a66 C True from color 0x0000 3ad9 ; -------------------------------------------------------------------------------------- 3ad9 3ad9 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3ada 0x3ada seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3ada 3ada seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3adb 3adb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 06 Pop_stack+? 3adc 3adc seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3add 3add fiu_mem_start 2 start-rd; Flow C 0x34c0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c0 0x34c0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3ade 3ade fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3adf 0x3adf seq_int_reads 6 CONTROL TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3adf 3adf ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3ae0 0x3ae0 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3ae0 3ae0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 32 TR09:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3ae1 3ae1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3ae4 seq_br_type 1 Branch True seq_branch_adr 3ae4 0x3ae4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR07:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3ae2 3ae2 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3ae4 seq_br_type 1 Branch True seq_branch_adr 3ae4 0x3ae4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3ae3 3ae3 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3ae4 3ae4 fiu_mem_start 3 start-wr 3ae5 3ae5 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3ae6 3ae6 seq_br_type 7 Unconditional Call; Flow C 0x69b seq_branch_adr 069b 0x069b seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3ae7 ; -------------------------------------------------------------------------------------- 3ae7 ; Comes from: 3ae7 ; 3948 C from color 0x0913 3ae7 ; -------------------------------------------------------------------------------------- 3ae7 3ae7 fiu_mem_start 2 start-rd; Flow C 0x34ac fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 3ae8 3ae8 fiu_mem_start 2 start-rd; Flow C 0x3394 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3394 0x3394 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3ae9 3ae9 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x33bc seq_br_type 9 Return False seq_branch_adr 33bc 0x33bc 3aea 3aea seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3aeb 3aeb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3aec ; -------------------------------------------------------------------------------------- 3aec ; 0x00ad Action InMicrocode,Package,Field_Execute_Dynamic 3aec ; -------------------------------------------------------------------------------------- 3aec MACRO_Action_InMicrocode,Package,Field_Execute_Dynamic: 3aec 3aec dispatch_brk_class 0 ; Flow J 0x3aed dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3aec seq_br_type 2 Push (branch address) seq_branch_adr 3af2 0x3af2 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3aed 3aed ioc_fiubs 1 val ; Flow J 0x3aef seq_br_type 3 Unconditional Branch seq_branch_adr 3aef 0x3aef typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3aee ; -------------------------------------------------------------------------------------- 3aee ; 0x1700-0x17ff Execute Task,Entry_Call,fieldnum 3aee ; -------------------------------------------------------------------------------------- 3aee MACRO_Execute_Task,Entry_Call,fieldnum: 3aee 3aee dispatch_brk_class 5 ; Flow J 0x3aef dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_uadr 3aee ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3af3 0x3af3 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3aef 3aef ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3af0 3af0 fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3af1 3af1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3af2 3af2 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3af4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3af4 0x3af4 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3af3 3af3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3af4 3af4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3af5 3af5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3af6 3af6 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3af7 3af7 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3af8 3af8 fiu_mem_start 2 start-rd; Flow J 0x36ec ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36ec 0x36ec typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3af9 3af9 <halt> ; Flow R 3afa ; -------------------------------------------------------------------------------------- 3afa ; 0x00aa QQUnknown InMicrocode 3afa ; -------------------------------------------------------------------------------------- 3afa MACRO_3afa_QQUnknown_InMicrocode: 3afa 3afa dispatch_brk_class 0 ; Flow J 0x3afb dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3afa seq_br_type 2 Push (branch address) seq_branch_adr 3b00 0x3b00 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3afb 3afb ioc_fiubs 1 val ; Flow J 0x3afd seq_br_type 3 Unconditional Branch seq_branch_adr 3afd 0x3afd typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3afc ; -------------------------------------------------------------------------------------- 3afc ; 0x1400-0x14ff Execute Task,Family_Call,fieldnum 3afc ; -------------------------------------------------------------------------------------- 3afc MACRO_Execute_Task,Family_Call,fieldnum: 3afc 3afc dispatch_brk_class 5 ; Flow J 0x3afd dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3afc ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b01 0x3b01 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3afd 3afd ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3afe 3afe fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3aff 3aff fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b00 3b00 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b02 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b02 0x3b02 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b01 3b01 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b02 3b02 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b03 3b03 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b04 3b04 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b05 3b05 ioc_tvbs 3 fiu+fiu typ_a_adr 22 TR01:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b06 3b06 fiu_mem_start 2 start-rd; Flow J 0x36ec ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36ec 0x36ec typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b07 3b07 <halt> ; Flow R 3b08 ; -------------------------------------------------------------------------------------- 3b08 ; 0x00ab QQUnknown InMicrocode 3b08 ; -------------------------------------------------------------------------------------- 3b08 MACRO_3b08_QQUnknown_InMicrocode: 3b08 3b08 dispatch_brk_class 0 ; Flow J 0x3b09 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b08 seq_br_type 2 Push (branch address) seq_branch_adr 3b0e 0x3b0e typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b09 3b09 ioc_fiubs 1 val ; Flow J 0x3b0b seq_br_type 3 Unconditional Branch seq_branch_adr 3b0b 0x3b0b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b0a ; -------------------------------------------------------------------------------------- 3b0a ; 0x1500-0x15ff Execute Task,Timed_Call,fieldnum 3b0a ; -------------------------------------------------------------------------------------- 3b0a MACRO_Execute_Task,Timed_Call,fieldnum: 3b0a 3b0a dispatch_brk_class 5 ; Flow J 0x3b0b dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3b0a ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b0f 0x3b0f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b0b 3b0b ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b0c 3b0c fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b0d 3b0d fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b0e 3b0e fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b10 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b10 0x3b10 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b0f 3b0f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b10 3b10 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b11 3b11 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b12 3b12 ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b13 3b13 ioc_tvbs 3 fiu+fiu typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b14 3b14 fiu_mem_start 2 start-rd; Flow J 0x36eb ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_a_adr 04 GP04 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b15 3b15 <halt> ; Flow R 3b16 ; -------------------------------------------------------------------------------------- 3b16 ; 0x00a8 QQUnknown InMicrocode 3b16 ; -------------------------------------------------------------------------------------- 3b16 MACRO_3b16_QQUnknown_InMicrocode: 3b16 3b16 dispatch_brk_class 0 ; Flow J 0x3b17 dispatch_csa_valid 5 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b16 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b1d 0x3b1d typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 3b17 3b17 ioc_fiubs 1 val ; Flow J 0x3b19 seq_br_type 3 Unconditional Branch seq_branch_adr 3b19 0x3b19 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b18 ; -------------------------------------------------------------------------------------- 3b18 ; 0x1200-0x12ff Execute Task,Family_Timed,fieldnum 3b18 ; -------------------------------------------------------------------------------------- 3b18 MACRO_Execute_Task,Family_Timed,fieldnum: 3b18 3b18 dispatch_brk_class 5 ; Flow J 0x3b19 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_uadr 3b18 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b1f 0x3b1f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b19 3b19 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b1a 3b1a ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_b_adr 1d TOP - 3 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3b1b 3b1b fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b1c 3b1c fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3b1d 3b1d fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b1e 3b1e fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3b21 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3b21 0x3b21 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b1f 3b1f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b20 3b20 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b21 3b21 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3b22 3b22 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b23 3b23 ioc_tvbs 3 fiu+fiu typ_a_adr 29 TR07:09 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b24 3b24 fiu_mem_start 2 start-rd; Flow J 0x36eb ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b25 3b25 <halt> ; Flow R 3b26 ; -------------------------------------------------------------------------------------- 3b26 ; 0x00ac QQUnknown InMicrocode 3b26 ; -------------------------------------------------------------------------------------- 3b26 MACRO_3b26_QQUnknown_InMicrocode: 3b26 3b26 dispatch_brk_class 0 ; Flow J 0x3b27 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3b26 seq_br_type 2 Push (branch address) seq_branch_adr 3b2c 0x3b2c typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b27 3b27 ioc_fiubs 1 val ; Flow J 0x3b29 seq_br_type 3 Unconditional Branch seq_branch_adr 3b29 0x3b29 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b28 ; -------------------------------------------------------------------------------------- 3b28 ; 0x1600-0x16ff Execute Task,Conditional_Call,fieldnum 3b28 ; -------------------------------------------------------------------------------------- 3b28 MACRO_Execute_Task,Conditional_Call,fieldnum: 3b28 3b28 dispatch_brk_class 5 ; Flow J 0x3b29 dispatch_csa_valid 2 dispatch_uadr 3b28 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b2d 0x3b2d typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b29 3b29 ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3b2a 3b2a fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b2b 3b2b fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b2c 3b2c fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b2e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b2e 0x3b2e typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b2d 3b2d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b2e 3b2e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b2f 3b2f fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b30 3b30 ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b31 3b31 ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR01:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b32 3b32 fiu_mem_start 2 start-rd; Flow J 0x36eb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b33 3b33 <halt> ; Flow R 3b34 ; -------------------------------------------------------------------------------------- 3b34 ; 0x00a9 QQUnknown InMicrocode 3b34 ; -------------------------------------------------------------------------------------- 3b34 MACRO_3b34_QQUnknown_InMicrocode: 3b34 3b34 dispatch_brk_class 0 ; Flow J 0x3b35 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3b34 seq_br_type 2 Push (branch address) seq_branch_adr 3b3a 0x3b3a typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b35 3b35 ioc_fiubs 1 val ; Flow J 0x3b37 seq_br_type 3 Unconditional Branch seq_branch_adr 3b37 0x3b37 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b36 ; -------------------------------------------------------------------------------------- 3b36 ; 0x1300-0x13ff Execute Task,Family_Cond,fieldnum 3b36 ; -------------------------------------------------------------------------------------- 3b36 MACRO_Execute_Task,Family_Cond,fieldnum: 3b36 3b36 dispatch_brk_class 5 ; Flow J 0x3b37 dispatch_csa_valid 3 dispatch_uadr 3b36 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b3b 0x3b3b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b37 3b37 ioc_fiubs 1 val ; Flow C 0x337f seq_br_type 7 Unconditional Call seq_branch_adr 337f 0x337f typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b38 3b38 fiu_mem_start 2 start-rd; Flow C 0x3b41 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b39 3b39 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b3a 3b3a fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b3c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b3c 0x3b3c typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b3b 3b3b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b3c 3b3c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b3d 3b3d fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b3e 3b3e ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b3f 3b3f ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR07:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b40 3b40 fiu_mem_start 2 start-rd; Flow J 0x36eb ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b41 ; -------------------------------------------------------------------------------------- 3b41 ; Comes from: 3b41 ; 3b1b C from color MACRO_3b16_QQUnknown_InMicrocode 3b41 ; -------------------------------------------------------------------------------------- 3b41 3b41 ioc_tvbs 5 seq+seq; Flow J cc=False 0x3b46 seq_br_type 0 Branch False seq_branch_adr 3b46 0x3b46 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3b42 3b42 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b48 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3b48 0x3b48 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b43 3b43 seq_br_type 7 Unconditional Call; Flow C 0x349d seq_branch_adr 349d 0x349d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b44 3b44 seq_br_type 1 Branch True; Flow J cc=True 0x3b4c seq_branch_adr 3b4c 0x3b4c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b45 3b45 seq_br_type 3 Unconditional Branch; Flow J 0x32a5 seq_branch_adr 32a5 0x32a5 3b46 3b46 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b47 3b47 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x3b49 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b49 0x3b49 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 13 ONES val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3b48 3b48 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b49 0x3b49 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR01:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 3b49 3b49 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a5 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3b4a 3b4a ioc_load_wdr 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 3b4b 3b4b fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3b4c 3b4c fiu_mem_start 2 start-rd; Flow J 0x3b41 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3b41 0x3b41 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b4d ; -------------------------------------------------------------------------------------- 3b4d ; Comes from: 3b4d ; 3b93 C from color 0x3b8f 3b4d ; -------------------------------------------------------------------------------------- 3b4d 3b4d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3b4e ; -------------------------------------------------------------------------------------- 3b4e ; Comes from: 3b4e ; 0625 C from color 0x05fb 3b4e ; 38d6 C from color 0x38b7 3b4e ; 3969 C from color 0x03fa 3b4e ; 3a2f C from color 0x3a2c 3b4e ; 3a37 C from color 0x03fa 3b4e ; -------------------------------------------------------------------------------------- 3b4e 3b4e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b4f 3b4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b50 3b50 fiu_tivi_src c mar_0xc; Flow J 0x3b51 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068f 0x068f seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b51 3b51 ioc_fiubs 2 typ ; Flow J 0x7b6 seq_br_type 3 Unconditional Branch seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b52 ; -------------------------------------------------------------------------------------- 3b52 ; Comes from: 3b52 ; 05ab C from color 0x05a7 3b52 ; 06d3 C from color 0x06d2 3b52 ; -------------------------------------------------------------------------------------- 3b52 3b52 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b53 3b53 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b54 3b54 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b55 3b55 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b56 3b56 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert seq_en_micro 0 3b57 3b57 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b58 3b58 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b59 3b59 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 30 TR03:10 typ_frame 3 3b5a 3b5a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3b5b 3b5b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b5c 3b5c fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 3b5d ; -------------------------------------------------------------------------------------- 3b5d ; Comes from: 3b5d ; 38da C from color 0x38b7 3b5d ; -------------------------------------------------------------------------------------- 3b5d 3b5d fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_frame 2 3b5e ; -------------------------------------------------------------------------------------- 3b5e ; Comes from: 3b5e ; 3b70 C from color 0x0bab 3b5e ; -------------------------------------------------------------------------------------- 3b5e 3b5e fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3b5f 3b5f ioc_tvbs 1 typ+fiu; Flow C 0x34f4 seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 4 3b60 3b60 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3b63 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3b63 0x3b63 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A 3b61 3b61 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b65 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 3b65 0x3b65 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 3d VR02:1d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3b62 3b62 ioc_tvbs 5 seq+seq; Flow J cc=True 0x3b63 ; Flow J cc=#0x0 0x3b64 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b64 0x3b64 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b63 3b63 seq_br_type 3 Unconditional Branch; Flow J 0x3b65 seq_branch_adr 3b65 0x3b65 seq_en_micro 0 3b64 3b64 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 3b65 3b65 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b66 3b66 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b67 3b67 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f typ_frame 3 3b68 3b68 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3b69 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 33 VR04:13 val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b69 3b69 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x3b6a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3b6a 3b6a fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3b6b ; Flow J cc=#0x0 0x3b6c fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b6c 0x3b6c seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3b6b 3b6b ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0xbab ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0bab 0x0bab seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 3 LEFT_I_A typ_frame d val_b_adr 0c GP0c 3b6c 3b6c seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b6c seq_br_type 1 Branch True seq_branch_adr 3b6c 0x3b6c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 3b6d 3b6d seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 3b6e 3b6e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3691 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3691 0x3691 seq_en_micro 0 seq_int_reads 6 CONTROL TOP val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b6f 3b6f seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3b70 3b70 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x3b5e fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b5e 0x3b5e seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3b71 3b71 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 3b72 3b72 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x3b74 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3b74 0x3b74 seq_en_micro 0 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3b73 3b73 fiu_mem_start 3 start-wr; Flow J cc=False 0x3b70 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3b70 0x3b70 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 3b74 3b74 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3b75 ; -------------------------------------------------------------------------------------- 3b75 ; Comes from: 3b75 ; 0410 C from color 0x0410 3b75 ; 0627 C from color 0x0627 3b75 ; 0687 C from color 0x0687 3b75 ; 07eb C from color 0x07e8 3b75 ; 38ce C from color 0x38b7 3b75 ; 38e4 C from color 0x38e4 3b75 ; -------------------------------------------------------------------------------------- 3b75 3b75 fiu_tivi_src c mar_0xc; Flow R cc=False fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 9 Return False seq_branch_adr 3b76 0x3b76 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3b76 3b76 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 3b77 3b77 fiu_mem_start 5 start_rd_if_true; Flow C 0x3b80 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3b80 0x3b80 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 30 TR03:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3b78 3b78 seq_br_type 3 Unconditional Branch; Flow J 0x3b77 seq_branch_adr 3b77 0x3b77 seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b79 3b79 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd2b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d2b 0x0d2b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 3b7a 3b7a fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0x3b7b fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3b74 0x3b74 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3b7b 3b7b fiu_mem_start 5 start_rd_if_true; Flow C 0x3b80 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3b80 0x3b80 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 31 TR03:11 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_alu_func 13 ONES val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3b7c 3b7c seq_br_type 3 Unconditional Branch; Flow J 0x3b7b seq_branch_adr 3b7b 0x3b7b seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b7d 3b7d ioc_load_wdr 0 ; Flow C cc=True 0x2a84 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a84 0x2a84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 3b7e 3b7e fiu_mem_start 5 start_rd_if_true; Flow J 0x3b80 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b80 0x3b80 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3b7f 3b7f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 3b80 ; -------------------------------------------------------------------------------------- 3b80 ; Comes from: 3b80 ; 3b77 C from color 0x0000 3b80 ; 3b7b C from color 0x3b79 3b80 ; -------------------------------------------------------------------------------------- 3b80 3b80 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3b88 seq_br_type 0 Branch False seq_branch_adr 3b88 0x3b88 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_latch 1 val_a_adr 33 VR04:13 val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 3b81 3b81 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3b82 3b82 fiu_mem_start 4 continue; Flow J cc=True 0x3b7d fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3b7d 0x3b7d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3b83 3b83 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b7f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3b7f 0x3b7f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU 3b84 3b84 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b85 3b85 fiu_load_oreg 1 hold_oreg ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 32 GP0d val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3b86 3b86 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 3b87 3b87 fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x3b7d ioc_adrbs 2 typ seq_br_type 9 Return False seq_branch_adr 3b7d 0x3b7d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 0d GP0d typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0c GP0c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b88 3b88 fiu_load_tar 1 hold_tar; Flow J 0x3b4d fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 3 Unconditional Branch seq_branch_adr 3b4d 0x3b4d seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3b89 3b89 fiu_mem_start 11 start_tag_query; Flow C 0x3b8d fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b8d 0x3b8d seq_en_micro 0 typ_a_adr 31 TR03:11 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 33 VR04:13 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b8a 3b8a ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b8b 3b8b fiu_mem_start 11 start_tag_query; Flow C 0x3b8d fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b8d 0x3b8d seq_en_micro 0 typ_a_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b8c 3b8c ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b8d ; -------------------------------------------------------------------------------------- 3b8d ; Comes from: 3b8d ; 3b89 C from color 0x36a0 3b8d ; 3b8b C from color 0x36a3 3b8d ; -------------------------------------------------------------------------------------- 3b8d 3b8d fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3b8e 3b8e fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b8f 3b8f ioc_fiubs 1 val ; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3b90 0x3b90 seq_en_micro 0 val_a_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b90 3b90 fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3b91 3b91 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3b94 seq_br_type 0 Branch False seq_branch_adr 3b94 0x3b94 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b92 3b92 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 seq_en_micro 0 3b93 3b93 fiu_mem_start 11 start_tag_query; Flow C 0x3b4d seq_br_type 7 Unconditional Call seq_branch_adr 3b4d 0x3b4d seq_en_micro 0 3b94 3b94 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 4 val_rand a PASS_B_HIGH 3b95 3b95 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b90 seq_br_type 1 Branch True seq_branch_adr 3b90 0x3b90 seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3b96 3b96 fiu_mem_start e start_physical_wr ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d val_alu_func 0 PASS_A 3b97 3b97 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3b98 3b98 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x3b9a fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 3b9a 0x3b9a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 6a ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 2a VR05:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 3b99 3b99 seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 3b9a 3b9a fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x32c5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32c5 0x32c5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR05:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR09:00 val_frame 9 3b9b 3b9b fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x3b9c ; Flow J cc=#0x0 0x3ba9 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 3ba9 0x3ba9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 31 TR02:11 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 3b9c 3b9c fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x3ba2 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3ba2 0x3ba2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 3b9d 3b9d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3b9e 3b9e typ_a_adr 01 GP01 typ_alu_func 10 NOT_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 3b9f 3b9f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x3ba1 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3ba1 0x3ba1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3ba0 3ba0 seq_br_type 3 Unconditional Branch; Flow J 0x3b9f seq_branch_adr 3b9f 0x3b9f seq_en_micro 0 typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 2b BOT - 1 3ba1 3ba1 fiu_mem_start 2 start-rd; Flow J 0x3ba6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba6 0x3ba6 seq_en_micro 0 seq_random 15 ? typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 2b BOT - 1 3ba2 3ba2 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3ba3 3ba3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 3ba4 3ba4 ioc_load_wdr 0 ; Flow J cc=False 0x3ba3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3ba3 0x3ba3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 14 BOT - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 3ba5 3ba5 fiu_mem_start 2 start-rd; Flow J 0x3ba6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba6 0x3ba6 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3ba6 3ba6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3ba7 ; Flow J cc=#0x0 0x3ba9 seq_br_type b Case False seq_branch_adr 3ba9 0x3ba9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3ba7 3ba7 seq_br_type 7 Unconditional Call; Flow C 0x2a84 seq_branch_adr 2a84 0x2a84 3ba8 3ba8 fiu_mem_start 2 start-rd; Flow J 0x3ba6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba6 0x3ba6 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3ba9 3ba9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdcc seq_br_type 3 Unconditional Branch seq_branch_adr 0dcc 0x0dcc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3baa 3baa ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdd7 seq_br_type 3 Unconditional Branch seq_branch_adr 0dd7 0x0dd7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bab 3bab ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdda seq_br_type 3 Unconditional Branch seq_branch_adr 0dda 0x0dda seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bac 3bac ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd3c seq_br_type 3 Unconditional Branch seq_branch_adr 0d3c 0x0d3c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bad 3bad ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe4c seq_br_type 3 Unconditional Branch seq_branch_adr 0e4c 0x0e4c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bae 3bae ioc_tvbs c mem+mem+csa+dummy; Flow J 0xde8 seq_br_type 3 Unconditional Branch seq_branch_adr 0de8 0x0de8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3baf 3baf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xedd seq_br_type 3 Unconditional Branch seq_branch_adr 0edd 0x0edd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb0 3bb0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd60 seq_br_type 3 Unconditional Branch seq_branch_adr 0d60 0x0d60 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb1 3bb1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdec seq_br_type 3 Unconditional Branch seq_branch_adr 0dec 0x0dec seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb2 3bb2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdf7 seq_br_type 3 Unconditional Branch seq_branch_adr 0df7 0x0df7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb3 3bb3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdfa seq_br_type 3 Unconditional Branch seq_branch_adr 0dfa 0x0dfa seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb4 3bb4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdfc seq_br_type 3 Unconditional Branch seq_branch_adr 0dfc 0x0dfc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb5 3bb5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe13 seq_br_type 3 Unconditional Branch seq_branch_adr 0e13 0x0e13 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb6 3bb6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe21 seq_br_type 3 Unconditional Branch seq_branch_adr 0e21 0x0e21 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb7 3bb7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe53 seq_br_type 3 Unconditional Branch seq_branch_adr 0e53 0x0e53 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb8 3bb8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe2f seq_br_type 3 Unconditional Branch seq_branch_adr 0e2f 0x0e2f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb9 3bb9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe34 seq_br_type 3 Unconditional Branch seq_branch_adr 0e34 0x0e34 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bba 3bba ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe39 seq_br_type 3 Unconditional Branch seq_branch_adr 0e39 0x0e39 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbb 3bbb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe5b seq_br_type 3 Unconditional Branch seq_branch_adr 0e5b 0x0e5b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbc 3bbc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe3b seq_br_type 3 Unconditional Branch seq_branch_adr 0e3b 0x0e3b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbd 3bbd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe3f seq_br_type 3 Unconditional Branch seq_branch_adr 0e3f 0x0e3f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbe 3bbe ioc_tvbs c mem+mem+csa+dummy; Flow J 0x883 seq_br_type 3 Unconditional Branch seq_branch_adr 0883 0x0883 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbf 3bbf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xec8 seq_br_type 3 Unconditional Branch seq_branch_adr 0ec8 0x0ec8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc0 3bc0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee8 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee8 0x0ee8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc1 3bc1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeeb seq_br_type 3 Unconditional Branch seq_branch_adr 0eeb 0x0eeb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc2 3bc2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xecd seq_br_type 3 Unconditional Branch seq_branch_adr 0ecd 0x0ecd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc3 3bc3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xece seq_br_type 3 Unconditional Branch seq_branch_adr 0ece 0x0ece seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc4 3bc4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed1 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed1 0x0ed1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc5 3bc5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe9f seq_br_type 3 Unconditional Branch seq_branch_adr 0e9f 0x0e9f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc6 3bc6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x799 seq_br_type 3 Unconditional Branch seq_branch_adr 0799 0x0799 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc7 3bc7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3659 seq_br_type 3 Unconditional Branch seq_branch_adr 3659 0x3659 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc8 3bc8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed8 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed8 0x0ed8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc9 3bc9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf6 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf6 0x2cf6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bca 3bca ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d19 seq_br_type 3 Unconditional Branch seq_branch_adr 2d19 0x2d19 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcb 3bcb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cfd seq_br_type 3 Unconditional Branch seq_branch_adr 2cfd 0x2cfd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcc 3bcc ioc_tvbs c mem+mem+csa+dummy; Flow J 0x345 seq_br_type 3 Unconditional Branch seq_branch_adr 0345 0x0345 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcd 3bcd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xde2 seq_br_type 3 Unconditional Branch seq_branch_adr 0de2 0x0de2 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bce 3bce ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee3 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee3 0x0ee3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcf 3bcf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd66 seq_br_type 3 Unconditional Branch seq_branch_adr 0d66 0x0d66 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd0 3bd0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdc4 seq_br_type 3 Unconditional Branch seq_branch_adr 0dc4 0x0dc4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd1 3bd1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd76 seq_br_type 3 Unconditional Branch seq_branch_adr 0d76 0x0d76 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd2 3bd2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe87 seq_br_type 3 Unconditional Branch seq_branch_adr 0e87 0x0e87 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd3 3bd3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe98 seq_br_type 3 Unconditional Branch seq_branch_adr 0e98 0x0e98 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd4 3bd4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe55 seq_br_type 3 Unconditional Branch seq_branch_adr 0e55 0x0e55 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd5 3bd5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xedc seq_br_type 3 Unconditional Branch seq_branch_adr 0edc 0x0edc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd6 3bd6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x334 seq_br_type 3 Unconditional Branch seq_branch_adr 0334 0x0334 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd7 3bd7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe41 seq_br_type 3 Unconditional Branch seq_branch_adr 0e41 0x0e41 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd8 3bd8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xddc seq_br_type 3 Unconditional Branch seq_branch_adr 0ddc 0x0ddc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd9 3bd9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x87b seq_br_type 3 Unconditional Branch seq_branch_adr 087b 0x087b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bda 3bda ioc_tvbs c mem+mem+csa+dummy; Flow J 0x903 seq_br_type 3 Unconditional Branch seq_branch_adr 0903 0x0903 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdb 3bdb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x905 seq_br_type 3 Unconditional Branch seq_branch_adr 0905 0x0905 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdc 3bdc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb38 seq_br_type 3 Unconditional Branch seq_branch_adr 0b38 0x0b38 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdd 3bdd ioc_tvbs c mem+mem+csa+dummy; Flow J 0x913 seq_br_type 3 Unconditional Branch seq_branch_adr 0913 0x0913 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bde 3bde ioc_tvbs c mem+mem+csa+dummy; Flow J 0x917 seq_br_type 3 Unconditional Branch seq_branch_adr 0917 0x0917 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdf 3bdf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeda seq_br_type 3 Unconditional Branch seq_branch_adr 0eda 0x0eda seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be0 3be0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3668 seq_br_type 3 Unconditional Branch seq_branch_adr 3668 0x3668 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be1 3be1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf9 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf9 0x2cf9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be2 3be2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe52 seq_br_type 3 Unconditional Branch seq_branch_adr 0e52 0x0e52 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be3 3be3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe72 seq_br_type 3 Unconditional Branch seq_branch_adr 0e72 0x0e72 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be4 3be4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe81 seq_br_type 3 Unconditional Branch seq_branch_adr 0e81 0x0e81 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be5 3be5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x919 seq_br_type 3 Unconditional Branch seq_branch_adr 0919 0x0919 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be6 3be6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x977 seq_br_type 3 Unconditional Branch seq_branch_adr 0977 0x0977 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be7 3be7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cfa seq_br_type 3 Unconditional Branch seq_branch_adr 2cfa 0x2cfa seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be8 3be8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe7a seq_br_type 3 Unconditional Branch seq_branch_adr 0e7a 0x0e7a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be9 3be9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dbf seq_br_type 3 Unconditional Branch seq_branch_adr 2dbf 0x2dbf seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bea 3bea ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d08 seq_br_type 3 Unconditional Branch seq_branch_adr 2d08 0x2d08 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3beb 3beb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d10 seq_br_type 3 Unconditional Branch seq_branch_adr 2d10 0x2d10 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bec 3bec ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d13 seq_br_type 3 Unconditional Branch seq_branch_adr 2d13 0x2d13 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bed 3bed ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35d6 seq_br_type 3 Unconditional Branch seq_branch_adr 35d6 0x35d6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bee 3bee ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35db seq_br_type 3 Unconditional Branch seq_branch_adr 35db 0x35db seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bef 3bef ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb70 seq_br_type 3 Unconditional Branch seq_branch_adr 0b70 0x0b70 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf0 3bf0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35d0 seq_br_type 3 Unconditional Branch seq_branch_adr 35d0 0x35d0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf1 3bf1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d03 seq_br_type 3 Unconditional Branch seq_branch_adr 2d03 0x2d03 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf2 3bf2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d05 seq_br_type 3 Unconditional Branch seq_branch_adr 2d05 0x2d05 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf3 3bf3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3b71 seq_br_type 3 Unconditional Branch seq_branch_adr 3b71 0x3b71 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf4 3bf4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3b79 seq_br_type 3 Unconditional Branch seq_branch_adr 3b79 0x3b79 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf5 3bf5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x95c seq_br_type 3 Unconditional Branch seq_branch_adr 095c 0x095c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf6 3bf6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb31 seq_br_type 3 Unconditional Branch seq_branch_adr 0b31 0x0b31 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf7 3bf7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cfb seq_br_type 3 Unconditional Branch seq_branch_adr 2cfb 0x2cfb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf8 3bf8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35ac seq_br_type 3 Unconditional Branch seq_branch_adr 35ac 0x35ac seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf9 3bf9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35b4 seq_br_type 3 Unconditional Branch seq_branch_adr 35b4 0x35b4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfa 3bfa ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35bd seq_br_type 3 Unconditional Branch seq_branch_adr 35bd 0x35bd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfb 3bfb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35b1 seq_br_type 3 Unconditional Branch seq_branch_adr 35b1 0x35b1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfc 3bfc ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d00 seq_br_type 3 Unconditional Branch seq_branch_adr 2d00 0x2d00 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfd 3bfd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd50 seq_br_type 3 Unconditional Branch seq_branch_adr 0d50 0x0d50 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfe 3bfe ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed0 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed0 0x0ed0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bff 3bff ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2be1 seq_br_type 3 Unconditional Branch seq_branch_adr 2be1 0x2be1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c00 3c00 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe84 seq_br_type 3 Unconditional Branch seq_branch_adr 0e84 0x0e84 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c01 3c01 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35df seq_br_type 3 Unconditional Branch seq_branch_adr 35df 0x35df seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c02 3c02 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35c7 seq_br_type 3 Unconditional Branch seq_branch_adr 35c7 0x35c7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c03 3c03 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x767 seq_br_type 3 Unconditional Branch seq_branch_adr 0767 0x0767 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c04 3c04 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x776 seq_br_type 3 Unconditional Branch seq_branch_adr 0776 0x0776 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c05 3c05 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x774 seq_br_type 3 Unconditional Branch seq_branch_adr 0774 0x0774 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c06 3c06 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x784 seq_br_type 3 Unconditional Branch seq_branch_adr 0784 0x0784 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c07 3c07 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x775 seq_br_type 3 Unconditional Branch seq_branch_adr 0775 0x0775 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c08 3c08 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb95 seq_br_type 3 Unconditional Branch seq_branch_adr 0b95 0x0b95 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c09 3c09 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed6 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed6 0x0ed6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0a 3c0a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x34f seq_br_type 3 Unconditional Branch seq_branch_adr 034f 0x034f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0b 3c0b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36a seq_br_type 3 Unconditional Branch seq_branch_adr 036a 0x036a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0c 3c0c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36c seq_br_type 3 Unconditional Branch seq_branch_adr 036c 0x036c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0d 3c0d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x377 seq_br_type 3 Unconditional Branch seq_branch_adr 0377 0x0377 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0e 3c0e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d21 seq_br_type 3 Unconditional Branch seq_branch_adr 2d21 0x2d21 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0f 3c0f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x349 seq_br_type 3 Unconditional Branch seq_branch_adr 0349 0x0349 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c10 3c10 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x794 seq_br_type 3 Unconditional Branch seq_branch_adr 0794 0x0794 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c11 3c11 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee5 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee5 0x0ee5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c12 3c12 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe9d seq_br_type 3 Unconditional Branch seq_branch_adr 0e9d 0x0e9d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c13 3c13 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cde seq_br_type 3 Unconditional Branch seq_branch_adr 2cde 0x2cde seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c14 3c14 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed7 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed7 0x0ed7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c15 3c15 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeec seq_br_type 3 Unconditional Branch seq_branch_adr 0eec 0x0eec seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c16 3c16 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeee seq_br_type 3 Unconditional Branch seq_branch_adr 0eee 0x0eee seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c17 3c17 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xda1 seq_br_type 3 Unconditional Branch seq_branch_adr 0da1 0x0da1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c18 3c18 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dd4 seq_br_type 3 Unconditional Branch seq_branch_adr 2dd4 0x2dd4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c19 3c19 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdb5 seq_br_type 3 Unconditional Branch seq_branch_adr 0db5 0x0db5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1a 3c1a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1b 3c1b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1c 3c1c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1d 3c1d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1e 3c1e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1f 3c1f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c20 3c20 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c21 3c21 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c22 3c22 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c23 3c23 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe59 seq_br_type 3 Unconditional Branch seq_branch_adr 0e59 0x0e59 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c24 3c24 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c5 seq_br_type 3 Unconditional Branch seq_branch_adr 32c5 0x32c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c25 3c25 <default>
PyReveng3/R1000.Disassembly disass_ucode.py /tmp/_aa_r1k_dfs/r1k_dfs/b2/b223d4e3f.tmp.0.19618 /tmp/_aa_r1k_dfs/r1k_dfs/b2/b223d4e3f.tmp.1.19619
FN /tmp/_aa_r1k_dfs/r1k_dfs/b2/b223d4e3f.tmp.0.19618
CX <__main__.R1kUcode object at 0x2ba252248d0> CX.M <word_mem 0x100-0x3c26, @14 bits, 0 attr>
Case table at 0x0000 lacks width <leaf 0x735-0x736 R1KUCODE>
? None <leaf 0x0-0x1 R1KUCODE>
Case table at 0x0bb2 lacks width <leaf 0xbae-0xbaf R1KUCODE>
Case table at 0x0bff lacks width <leaf 0xbfe-0xbff R1KUCODE>
Case table at 0x0bcd lacks width <leaf 0xbcc-0xbcd R1KUCODE>
Case table at 0x081f lacks width <leaf 0x81d-0x81e R1KUCODE>
Case table at 0x0830 lacks width <leaf 0x82f-0x830 R1KUCODE>
Case table at 0x3723 lacks width <leaf 0x3717-0x3718 R1KUCODE>
Case table at 0x04af lacks width <leaf 0x4ae-0x4af R1KUCODE>
Case table at 0x22cd lacks width <leaf 0x22ca-0x22cb R1KUCODE>
Case table at 0x2d67 lacks width <leaf 0x149-0x14a R1KUCODE>
Case table at 0x34a2 lacks width <leaf 0x34a1-0x34a2 R1KUCODE>
Case table at 0x2d57 lacks width <leaf 0x2d56-0x2d57 R1KUCODE>
Case table at 0x0f11 lacks width <leaf 0xef3-0xef4 R1KUCODE>
Case table at 0x0ef7 lacks width <leaf 0xef4-0xef5 R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x69e-0x69f R1KUCODE>
Case table at 0x3973 lacks width <leaf 0x3966-0x3967 R1KUCODE>
Case table at 0x3352 lacks width <leaf 0x334c-0x334d R1KUCODE>
Case table at 0x334e lacks width <leaf 0x334d-0x334e R1KUCODE>
Case table at 0x0260 lacks width <leaf 0x24f-0x250 R1KUCODE>
Case table at 0x335f lacks width <leaf 0x335e-0x335f R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c1-0x2c2 R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c5-0x2c6 R1KUCODE>
Case table at 0x3aba lacks width <leaf 0x3ab9-0x3aba R1KUCODE>
Case table at 0x0396 lacks width <leaf 0x38e-0x38f R1KUCODE>
Case table at 0x03c0 lacks width <leaf 0x3b9-0x3ba R1KUCODE>
Case table at 0x03f8 lacks width <leaf 0x3f6-0x3f7 R1KUCODE>
Case table at 0x04b8 lacks width <leaf 0x4b3-0x4b4 R1KUCODE>
Case table at 0x3509 lacks width <leaf 0x3503-0x3504 R1KUCODE>
Case table at 0x3509 lacks width <leaf 0x3505-0x3506 R1KUCODE>
Case table at 0x3509 lacks width <leaf 0x3514-0x3515 R1KUCODE>
Case table at 0x0516 lacks width <leaf 0x514-0x515 R1KUCODE>
Case table at 0x04f5 lacks width <leaf 0x4f0-0x4f1 R1KUCODE>
Case table at 0x0552 lacks width <leaf 0x551-0x552 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x635-0x636 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x63b-0x63c R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x697-0x698 R1KUCODE>
Case table at 0x0802 lacks width <leaf 0x801-0x802 R1KUCODE>
Case table at 0x331b lacks width <leaf 0x3313-0x3314 R1KUCODE>
Case table at 0x331b lacks width <leaf 0x3314-0x3315 R1KUCODE>
Case table at 0x331b lacks width <leaf 0x3317-0x3318 R1KUCODE>
Case table at 0x331b lacks width <leaf 0x331a-0x331b R1KUCODE>
Case table at 0x332a lacks width <leaf 0x3329-0x332a R1KUCODE>
Case table at 0x332a lacks width <leaf 0x3327-0x3328 R1KUCODE>
Case table at 0x332a lacks width <leaf 0x3324-0x3325 R1KUCODE>
Case table at 0x332a lacks width <leaf 0x3325-0x3326 R1KUCODE>
Case table at 0x0983 lacks width <leaf 0x982-0x983 R1KUCODE>
Case table at 0x0993 lacks width <leaf 0x992-0x993 R1KUCODE>
Case table at 0x09a5 lacks width <leaf 0x9a4-0x9a5 R1KUCODE>
Case table at 0x09b5 lacks width <leaf 0x9b4-0x9b5 R1KUCODE>
Case table at 0x0a29 lacks width <leaf 0xa28-0xa29 R1KUCODE>
Case table at 0x0a3b lacks width <leaf 0xa3a-0xa3b R1KUCODE>
Case table at 0x0a52 lacks width <leaf 0xa4f-0xa50 R1KUCODE>
Case table at 0x0a63 lacks width <leaf 0xa50-0xa51 R1KUCODE>
Case table at 0x0a73 lacks width <leaf 0xa72-0xa73 R1KUCODE>
Case table at 0x0a63 lacks width <leaf 0xa62-0xa63 R1KUCODE>
Case table at 0x0a87 lacks width <leaf 0xa86-0xa87 R1KUCODE>
Case table at 0x0a9b lacks width <leaf 0xa9a-0xa9b R1KUCODE>
Case table at 0x1d49 lacks width <leaf 0x1d48-0x1d49 R1KUCODE>
Case table at 0x0abb lacks width <leaf 0xab9-0xaba R1KUCODE>
Case table at 0x0c69 lacks width <leaf 0xc68-0xc69 R1KUCODE>
Case table at 0x0ccd lacks width <leaf 0xccc-0xccd R1KUCODE>
Case table at 0x0dd2 lacks width <leaf 0xdd1-0xdd2 R1KUCODE>
Case table at 0x0e0c lacks width <leaf 0xe0a-0xe0b R1KUCODE>
Case table at 0x0e0e lacks width <leaf 0xe0c-0xe0d R1KUCODE>
Case table at 0x36a0 lacks width <leaf 0x369b-0x369c R1KUCODE>
Case table at 0x0e18 lacks width <leaf 0xe17-0xe18 R1KUCODE>
Case table at 0x1003 lacks width <leaf 0xfea-0xfeb R1KUCODE>
Case table at 0x1056 lacks width <leaf 0x1054-0x1055 R1KUCODE>
Case table at 0x0e5f lacks width <leaf 0xe5d-0xe5e R1KUCODE>
Case table at 0x0eb3 lacks width <leaf 0xeb2-0xeb3 R1KUCODE>
Case table at 0x0efe lacks width <leaf 0xefd-0xefe R1KUCODE>
Case table at 0x0fcd lacks width <leaf 0xfcc-0xfcd R1KUCODE>
Case table at 0x0fc5 lacks width <leaf 0xfc3-0xfc4 R1KUCODE>
Case table at 0x362d lacks width <leaf 0x362c-0x362d R1KUCODE>
Case table at 0x1030 lacks width <leaf 0x102e-0x102f R1KUCODE>
Case table at 0x1027 lacks width <leaf 0x1030-0x1031 R1KUCODE>
Case table at 0x1027 lacks width <leaf 0x1026-0x1027 R1KUCODE>
Case table at 0x101e lacks width <leaf 0x101d-0x101e R1KUCODE>
Case table at 0x1027 lacks width <leaf 0x101e-0x101f R1KUCODE>
Case table at 0x10b8 lacks width <leaf 0x10a9-0x10aa R1KUCODE>
Case table at 0x10b8 lacks width <leaf 0x10ad-0x10ae R1KUCODE>
Case table at 0x10d5 lacks width <leaf 0x10d3-0x10d4 R1KUCODE>
Case table at 0x10b8 lacks width <leaf 0x10b1-0x10b2 R1KUCODE>
Case table at 0x10b8 lacks width <leaf 0x10b5-0x10b6 R1KUCODE>
Case table at 0x110f lacks width <leaf 0x1101-0x1102 R1KUCODE>
Case table at 0x110f lacks width <leaf 0x1105-0x1106 R1KUCODE>
Case table at 0x110f lacks width <leaf 0x1109-0x110a R1KUCODE>
Case table at 0x110f lacks width <leaf 0x110d-0x110e R1KUCODE>
Case table at 0x116b lacks width <leaf 0x1163-0x1164 R1KUCODE>
Case table at 0x119a lacks width <leaf 0x1173-0x1174 R1KUCODE>
Case table at 0x11f3 lacks width <leaf 0x11e5-0x11e6 R1KUCODE>
Case table at 0x11f3 lacks width <leaf 0x11e9-0x11ea R1KUCODE>
Case table at 0x11f3 lacks width <leaf 0x11ed-0x11ee R1KUCODE>
Case table at 0x11f3 lacks width <leaf 0x11f1-0x11f2 R1KUCODE>
Case table at 0x1251 lacks width <leaf 0x1243-0x1244 R1KUCODE>
Case table at 0x1251 lacks width <leaf 0x1247-0x1248 R1KUCODE>
Case table at 0x1251 lacks width <leaf 0x124b-0x124c R1KUCODE>
Case table at 0x1251 lacks width <leaf 0x124f-0x1250 R1KUCODE>
Case table at 0x1686 lacks width <leaf 0x1685-0x1686 R1KUCODE>
Case table at 0x168c lacks width <leaf 0x168b-0x168c R1KUCODE>
Case table at 0x1692 lacks width <leaf 0x1691-0x1692 R1KUCODE>
Case table at 0x191d lacks width <leaf 0x1911-0x1912 R1KUCODE>
Case table at 0x1d28 lacks width <leaf 0x1d0c-0x1d0d R1KUCODE>
Case table at 0x1ca5 lacks width <leaf 0x1ca4-0x1ca5 R1KUCODE>
Case table at 0x26bf lacks width <leaf 0x26bc-0x26bd R1KUCODE>
Case table at 0x26d9 lacks width <leaf 0x26d5-0x26d6 R1KUCODE>
Case table at 0x1ec1 lacks width <leaf 0x1ec0-0x1ec1 R1KUCODE>
Case table at 0x1f66 lacks width <leaf 0x1f60-0x1f61 R1KUCODE>
Case table at 0x20a8 lacks width <leaf 0x2011-0x2012 R1KUCODE>
Case table at 0x206f lacks width <leaf 0x206d-0x206e R1KUCODE>
Case table at 0x20a8 lacks width <leaf 0x20cd-0x20ce R1KUCODE>
Case table at 0x206f lacks width <leaf 0x209e-0x209f R1KUCODE>
Case table at 0x206f lacks width <leaf 0x20a1-0x20a2 R1KUCODE>
Case table at 0x20a8 lacks width <leaf 0x2116-0x2117 R1KUCODE>
Case table at 0x20a8 lacks width <leaf 0x211b-0x211c R1KUCODE>
Case table at 0x206f lacks width <leaf 0x20a6-0x20a7 R1KUCODE>
Case table at 0x20a8 lacks width <leaf 0x2120-0x2121 R1KUCODE>
Case table at 0x21c9 lacks width <leaf 0x21c4-0x21c5 R1KUCODE>
Case table at 0x21f3 lacks width <leaf 0x21ed-0x21ee R1KUCODE>
Case table at 0x2210 lacks width <leaf 0x220f-0x2210 R1KUCODE>
Case table at 0x2310 lacks width <leaf 0x230f-0x2310 R1KUCODE>
Case table at 0x2555 lacks width <leaf 0x2610-0x2611 R1KUCODE>
Case table at 0x2555 lacks width <leaf 0x2552-0x2553 R1KUCODE>
Case table at 0x26e4 lacks width <leaf 0x26e1-0x26e2 R1KUCODE>
Case table at 0x2555 lacks width <leaf 0x25a7-0x25a8 R1KUCODE>
Case table at 0x25b3 lacks width <leaf 0x25ad-0x25ae R1KUCODE>
Case table at 0x2678 lacks width <leaf 0x2667-0x2668 R1KUCODE>
Case table at 0x2678 lacks width <leaf 0x26b4-0x26b5 R1KUCODE>
Case table at 0x26d9 lacks width <leaf 0x26f7-0x26f8 R1KUCODE>
Case table at 0x27b4 lacks width <leaf 0x27b3-0x27b4 R1KUCODE>
Case table at 0x27b4 lacks width <leaf 0x27ba-0x27bb R1KUCODE>
Case table at 0x27df lacks width <leaf 0x27de-0x27df R1KUCODE>
Case table at 0x27e3 lacks width <leaf 0x27e2-0x27e3 R1KUCODE>
Case table at 0x2b05 lacks width <leaf 0x2afa-0x2afb R1KUCODE>
Case table at 0x2b1a lacks width <leaf 0x2b17-0x2b18 R1KUCODE>
Case table at 0x2b70 lacks width <leaf 0x2b6e-0x2b6f R1KUCODE>
Case table at 0x3ba9 lacks width <leaf 0x3b9b-0x3b9c R1KUCODE>
Case table at 0x3ba9 lacks width <leaf 0x3ba6-0x3ba7 R1KUCODE>
Case table at 0x2c4f lacks width <leaf 0x2c4d-0x2c4e R1KUCODE>
Case table at 0x2c60 lacks width <leaf 0x2c5e-0x2c5f R1KUCODE>
Case table at 0x2f72 lacks width <leaf 0x2f6c-0x2f6d R1KUCODE>
Case table at 0x2e1b lacks width <leaf 0x2e16-0x2e17 R1KUCODE>
Case table at 0x2e40 lacks width <leaf 0x2e3f-0x2e40 R1KUCODE>
Case table at 0x2e5b lacks width <leaf 0x2e59-0x2e5a R1KUCODE>
Case table at 0x2eaf lacks width <leaf 0x2eae-0x2eaf R1KUCODE>
Case table at 0x2eeb lacks width <leaf 0x2ee9-0x2eea R1KUCODE>
Case table at 0x2f72 lacks width <leaf 0x2f70-0x2f71 R1KUCODE>
Case table at 0x3763 lacks width <leaf 0x3736-0x3737 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x305c-0x305d R1KUCODE>
Case table at 0x305d lacks width <leaf 0x305d-0x305e R1KUCODE>
Case table at 0x305d lacks width <leaf 0x305e-0x305f R1KUCODE>
Case table at 0x305d lacks width <leaf 0x305f-0x3060 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3060-0x3061 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3061-0x3062 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3062-0x3063 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3063-0x3064 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3064-0x3065 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3065-0x3066 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3066-0x3067 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3067-0x3068 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3068-0x3069 R1KUCODE>
Case table at 0x305d lacks width <leaf 0x3069-0x306a R1KUCODE>
Case table at 0x305d lacks width <leaf 0x306a-0x306b R1KUCODE>
Case table at 0x305d lacks width <leaf 0x306b-0x306c R1KUCODE>
Case table at 0x305d lacks width <leaf 0x306c-0x306d R1KUCODE>
Case table at 0x318a lacks width <leaf 0x3183-0x3184 R1KUCODE>
Case table at 0x36f5 lacks width <leaf 0x36f0-0x36f1 R1KUCODE>
Case table at 0x0000 lacks width <leaf 0x3722-0x3723 R1KUCODE>
Case table at 0x376b lacks width <leaf 0x3741-0x3742 R1KUCODE>
Case table at 0x37e9 lacks width <leaf 0x37e8-0x37e9 R1KUCODE>
Case table at 0x3801 lacks width <leaf 0x37fa-0x37fb R1KUCODE>
Case table at 0x3831 lacks width <leaf 0x3829-0x382a R1KUCODE>
Case table at 0x3847 lacks width <leaf 0x382a-0x382b R1KUCODE>
Case table at 0x387b lacks width <leaf 0x3875-0x3876 R1KUCODE>
Case table at 0x387b lacks width <leaf 0x3879-0x387a R1KUCODE>
Case table at 0x38ca lacks width <leaf 0x38c9-0x38ca R1KUCODE>
Case table at 0x3a78 lacks width <leaf 0x3a77-0x3a78 R1KUCODE>
Case table at 0x3b64 lacks width <leaf 0x3b62-0x3b63 R1KUCODE>
Case table at 0x3b6c lacks width <leaf 0x3b6a-0x3b6b R1KUCODE>
? None <leaf 0x3c40-0x3c41 R1KUCODE>
fiu_len_fill_reg_ctl 1 {3}
fiu_load_mdr 1 {0}
fiu_load_oreg 1 {0}
fiu_mem_start 1 {2}
fiu_oreg_src 1 {1}
ioc_adrbs 1 {3}
seq_lex_adr 1 {0}
typ_mar_cntl 1 {14}
typ_priv_check 1 {7}
Stranger in color <Color 15 0x117-0x73c #2> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 24 0x127-0x2abe #136> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 44 0x148-0x3c13 #100> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 61 0x160-0x2a64 #13> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 175 0x200-0x3be0 #47> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 176 0x201-0x20b #2> <Stretch 202 259> <Color 177 0x202-0x20c #2>
Stranger in color <Color 177 0x202-0x20c #2> <Stretch 203 260> <Color 178 0x203-0xed5 #25>
Stranger in color <Color 178 0x203-0xed5 #25> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 179 0x204-0x20e #2> <Stretch 205 262> <Color 180 0x205-0x20f #2>
Stranger in color <Color 180 0x205-0x20f #2> <Stretch 206 263> <Color 181 0x206-0x210 #2>
Stranger in color <Color 181 0x206-0x210 #2> <Stretch 207 264> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 182 0x208-0x212 #2> <Stretch 209 266> <Color 183 0x209-0x213 #2>
Stranger in color <Color 183 0x209-0x213 #2> <Stretch 20a 267> <Color 175 0x200-0x3be0 #47>
Stranger in color <Color 184 0x214-0x335b #50> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 193 0x2c9-0x387d #12> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 194 0x2ca-0x2d5 #6> <Stretch 2cb 460> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 210 0x377-0x3c0d #10> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 214 0x397-0x3a1 #8> <Stretch 398 665> <Color 215 0x398-0x3c3 #16>
Stranger in color <Color 215 0x398-0x3c3 #16> <Stretch 39b 668> <Color 214 0x397-0x3a1 #8>
Stranger in color <Color 219 0x3c1-0x3ca #8> <Stretch 3c2 707> <Color 215 0x398-0x3c3 #16>
Stranger in color <Color 222 0x3f0-0x407 #17> <Stretch 3f7 760> <Color 223 0x3f7-0x3f7 #1>
Stranger in color <Color 225 0x3fa-0x3aeb #51> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 244 0x4fa-0x50a #13> <Stretch 4fd 1022> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 261 0x573-0x598 #18> <Stretch 576 1143> <Color 262 0x576-0x577 #2>
Stranger in color <Color 270 0x5a7-0x36cc #93> <Stretch 5dd 1246> <Color 277 0x5db-0x364f #17>
Stranger in color <Color 277 0x5db-0x364f #17> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 283 0x5fb-0x626 #15> <Stretch 606 1287> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 287 0x62d-0x3937 #25> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 293 0x66a-0x68c #28> <Stretch 683 1412> <Color 294 0x683-0x683 #1>
Stranger in color <Color 302 0x6b6-0x398e #58> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 305 0x6ce-0x6e5 #10> <Stretch 6d2 1491> <Color 306 0x6d2-0x6fb #29>
Stranger in color <Color 306 0x6d2-0x6fb #29> <Stretch 6db 1500> <Color 307 0x6db-0x6db #1>
Stranger in color <Color 315 0x767-0x3c06 #45> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 317 0x794-0x3c10 #6> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 318 0x799-0x3bc6 #8> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 323 0x7b5-0x3b51 #6> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 324 0x7b9-0x7e7 #18> <Stretch 7c0 1729> <Color 325 0x7c0-0x7c0 #1>
Stranger in color <Color 334 0x820-0x870 #47> <Stretch 821 1826> <Color 335 0x821-0x87a #11>
Stranger in color <Color 335 0x821-0x87a #11> <Stretch 822 1827> <Color 334 0x820-0x870 #47>
Stranger in color <Color 338 0x903-0x3bda #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 339 0x905-0x3bdb #15> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 340 0x913-0x3bdd #19> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 341 0x917-0x3bde #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 346 0x950-0x3bf5 #33> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 348 0x980-0x3164 #6> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 350 0x98c-0x12d5 #16> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 353 0x990-0x3163 #7> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 354 0x995-0x30cd #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 358 0x9a2-0x2f9c #6> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 360 0x9a8-0x22c2 #64> <Stretch 1f44 7749> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 361 0x9ab-0x183c #37> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 362 0x9ac-0x1467 #50> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 363 0x9ad-0x17f3 #6> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 364 0x9ae-0x174c #11> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 367 0x9b2-0x2fa0 #6> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 373 0x9cc-0x9f6 #39> <Stretch 9e1 2274> <Color 374 0x9e1-0x9e4 #4>
Stranger in color <Color 383 0xa26-0x306d #80> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 384 0xa2b-0x28fd #44> <Stretch 1f44 7749> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 385 0xa2f-0x1ab5 #78> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 386 0xa31-0x1810 #21> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 387 0xa32-0x17aa #15> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 388 0xa33-0x1b13 #20> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 389 0xa35-0xc4f #17> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 393 0xa50-0x2fed #36> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 397 0xa57-0xa5c #2> <Stretch a58 2393> <Color 398 0xa58-0xa5d #2>
Stranger in color <Color 398 0xa58-0xa5d #2> <Stretch a59 2394> <Color 393 0xa50-0x2fed #36>
Stranger in color <Color 402 0xa75-0x28f9 #15> <Stretch 1f44 7749> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 403 0xa76-0xa82 #6> <Stretch a78 2425> <Color 404 0xa78-0x1bb2 #14>
Stranger in color <Color 404 0xa78-0x1bb2 #14> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 405 0xa7a-0x14b2 #4> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 406 0xa7c-0x17b3 #5> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 407 0xa7d-0x1b00 #12> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 408 0xa7e-0xc40 #13> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 410 0xa8a-0xa96 #6> <Stretch a8c 2445> <Color 411 0xa8c-0x1bc0 #14>
Stranger in color <Color 411 0xa8c-0x1bc0 #14> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 412 0xa8e-0x14b6 #4> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 413 0xa90-0x17b7 #5> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 414 0xa91-0x1b06 #6> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 415 0xa92-0xc46 #7> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 417 0xa9e-0xaa9 #5> <Stretch aa0 2465> <Color 418 0xaa0-0x1bd4 #20>
Stranger in color <Color 418 0xaa0-0x1bd4 #20> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 419 0xaa1-0x1ac5 #17> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 420 0xaa2-0x14f0 #46> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 421 0xaa4-0x17c2 #6> <Stretch b18 2585> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 427 0xac3-0xacd #2> <Stretch ac4 2501> <Color 428 0xac4-0xade #18>
Stranger in color <Color 428 0xac4-0xade #18> <Stretch ac5 2502> <Color 429 0xac5-0xac5 #1>
Stranger in color <Color 438 0xb70-0x3bef #5> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 445 0xb95-0x3c08 #23> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 446 0xbab-0x3bf3 #106> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 447 0xc07-0xc18 #12> <Stretch c08 2825> <Color 448 0xc08-0xc08 #1>
Stranger in color <Color 489 0xd36-0x3bd7 #106> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 491 0xda1-0x3c17 #19> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 492 0xdb3-0x3c19 #17> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 494 0xdda-0x3bab #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 495 0xde8-0x3bae #5> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 496 0xdfa-0x3bb3 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 497 0xe21-0x3bb6 #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 500 0xe39-0x3bba #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 501 0xe4c-0x3bad #7> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 502 0xe52-0x3be2 #2> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 503 0xe53-0x3bb7 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 504 0xe55-0x3bd4 #5> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 505 0xe59-0x3c23 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 506 0xe5b-0x3bbb #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 508 0xe7a-0x3be8 #8> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 509 0xe81-0x3be4 #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 510 0xe84-0x3c00 #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 511 0xe9d-0x3c12 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 512 0xecd-0x3bc2 #2> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 513 0xed8-0x3bc8 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 514 0xedc-0x3bd5 #2> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 515 0xee3-0x3bce #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 516 0xee5-0x3c11 #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 517 0xee8-0x3bc0 #4> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 518 0xeeb-0x3bc1 #2> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 519 0xeec-0x3c15 #3> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 520 0xefa-0x3b5e #193> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 522 0xf07-0x34d1 #39> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 528 0xf64-0xf7b #17> <Stretch f66 3687> <Color 529 0xf66-0x275f #7>
Stranger in color <Color 529 0xf66-0x275f #7> <Stretch 1f44 7749> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 536 0xfc9-0x362d #11> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 541 0xfd2-0x3643 #137> <Stretch 297b 10364> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 543 0x1057-0x105e #6> <Stretch 105c 3933> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 557 0x10aa-0x10d3 #28> <Stretch 10bc 4029> <Color 558 0x10bc-0x10bc #1>
Stranger in color <Color 561 0x10c1-0x120d #18> <Stretch 10c2 4035> <Color 562 0x10c2-0x10c2 #1>
Stranger in color <Color 566 0x10d6-0x128d #69> <Stretch 10d7 4056> <Color 567 0x10d7-0x10fd #19>
Stranger in color <Color 567 0x10d7-0x10fd #19> <Stretch 10dd 4062> <Color 566 0x10d6-0x128d #69>
Stranger in color <Color 580 0x110f-0x1155 #55> <Stretch 1112 4115> <Color 581 0x1112-0x1113 #2>
Stranger in color <Color 584 0x1117-0x115f #7> <Stretch 1118 4121> <Color 585 0x1118-0x1163 #4>
Stranger in color <Color 585 0x1118-0x1163 #4> <Stretch 1119 4122> <Color 586 0x1119-0x1119 #1>
Stranger in color <Color 589 0x111c-0x1173 #4> <Stretch 111d 4126> <Color 590 0x111d-0x11d5 #78>
Stranger in color <Color 590 0x111d-0x11d5 #78> <Stretch 1123 4132> <Color 580 0x110f-0x1155 #55>
Stranger in color <Color 594 0x119a-0x11a1 #7> <Stretch 119b 4252> <Color 595 0x119b-0x11a7 #7>
Stranger in color <Color 595 0x119b-0x11a7 #7> <Stretch 119c 4253> <Color 594 0x119a-0x11a1 #7>
Stranger in color <Color 613 0x1201-0x1240 #27> <Stretch 1207 4360> <Color 561 0x10c1-0x120d #18>
Stranger in color <Color 628 0x125f-0x12be #50> <Stretch 1260 4449> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 633 0x12d6-0x130d #55> <Stretch 130b 4620> <Color 634 0x130b-0x130b #1>
Stranger in color <Color 641 0x1372-0x1437 #147> <Stretch 1399 4762> <Color 642 0x1399-0x139b #3>
Stranger in color <Color 662 0x14f4-0x1e49 #64> <Stretch 1a49 6474> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 667 0x15f0-0x1686 #13> <Stretch 15fa 5371> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 668 0x1628-0x168d #3> <Stretch 162a 5419> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 670 0x163a-0x168f #3> <Stretch 163c 5437> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 671 0x164a-0x1692 #5> <Stretch 164c 5453> <Color 672 0x164c-0x1693 #4>
Stranger in color <Color 672 0x164c-0x1693 #4> <Stretch 164e 5455> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 674 0x165e-0x1695 #4> <Stretch 1660 5473> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 695 0x1782-0x1795 #17> <Stretch 1789 5770> <Color 696 0x1789-0x178a #2>
Stranger in color <Color 731 0x1931-0x1938 #4> <Stretch 1933 6196> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 766 0x1b5a-0x1b6f #11> <Stretch 1b60 6753> <Color 360 0x9a8-0x22c2 #64>
Stranger in color <Color 769 0x1b7e-0x2261 #14> <Stretch 1f44 7749> <Color 0 0x0-0x3c24 #5346>
Stranger in color <Color 772 0x1b98-0x1ba1 #4> <Stretch 1b9a 6811> <Color 773 0x1b9a-0x1b9f #4>
Stranger in color <Color 773 0x1b9a-0x1b9f #4> <Stretch 1b9c 6813> <Color 774 0x1b9c-0x1b9d #2>
Stranger in color <Color 821 0x1d2a-0x1dad #71> <Stretch 1d2e 7215> <Color 822 0x1d2e-0x1d30 #3>
Stranger in color <Color 827 0x1d39-0x1db8 #9> <Stretch 1d3a 7227> <Color 828 0x1d3a-0x1d3a #1>
Stranger in color <Color 846 0x1e82-0x1e97 #16> <Stretch 1e8d 7566> <Color 847 0x1e8d-0x1e8f #3>
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PFX /tmp/_aa_r1k_dfs/r1k_dfs/b2/b223d4e3f.tmp