|
DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - metrics - download
Length: 394240 (0x60400)
Types: M200_UCODE
Names: »P2UCODE.M200_UCODE«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─⟦this⟧ »P2UCODE.M200_UCODE«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─⟦this⟧ »P2UCODE.M200_UCODE«
└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
└─⟦this⟧ »P2UCODE.M200_UCODE«
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
└─⟦this⟧ »P2UCODE.M200_UCODE«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─⟦this⟧ »P2UCODE.M200_UCODE«
0100 ; -------------------------------------------------------------------------------------- 0100 ; no details_be4f86 0100 ; Initial Register File (adr, typ, val, frame:offset) where non-zero 0100 ; 000 TR00:00 0000000000000000 VR00:00 0000000000000000 0100 ; 001 TR00:01 0000000000000000 VR00:01 0000000000000000 0100 ; 002 TR00:02 0000000000000000 VR00:02 0000000000000000 0100 ; 003 TR00:03 0000000000000000 VR00:03 0000000000000000 0100 ; 004 TR00:04 0000000000000000 VR00:04 0000000000000000 0100 ; 005 TR00:05 0000000000000000 VR00:05 0000000000000000 0100 ; 006 TR00:06 0000000000000000 VR00:06 0000000000000000 0100 ; 007 TR00:07 0000000000000000 VR00:07 0000000000000000 0100 ; 008 TR00:08 0000000000000000 VR00:08 0000000000000000 0100 ; 009 TR00:09 0000000000000000 VR00:09 0000000000000000 0100 ; 00a TR00:0a 0000000000000000 VR00:0a 0000000000000000 0100 ; 00b TR00:0b 0000000000000000 VR00:0b 0000000000000000 0100 ; 00c TR00:0c 0000000000000000 VR00:0c 0000000000000000 0100 ; 00d TR00:0d 0000000000000000 VR00:0d 0000000000000000 0100 ; 00e TR00:0e 0000000000000000 VR00:0e 0000000000000000 0100 ; 00f TR00:0f 0000000000000000 VR00:0f 0000000000000000 0100 ; 010 TR00:10 0000000000000000 VR00:10 0000000000000000 0100 ; 011 TR00:11 0000000000000000 VR00:11 0000000000000000 0100 ; 012 TR00:12 0000000000000000 VR00:12 0000000000000000 0100 ; 013 TR00:13 0000000000000000 VR00:13 0000000000000000 0100 ; 014 TR00:14 0000000000000000 VR00:14 0000000000000000 0100 ; 015 TR00:15 0000000000000000 VR00:15 0000000000000000 0100 ; 016 TR00:16 0000000000000000 VR00:16 0000000000000000 0100 ; 017 TR00:17 0000000000000000 VR00:17 0000000000000000 0100 ; 018 TR00:18 0000000000000000 VR00:18 0000000000000000 0100 ; 019 TR00:19 0000000000000000 VR00:19 0000000000000000 0100 ; 01a TR00:1a 0000000000000000 VR00:1a 0000000000000000 0100 ; 01b TR00:1b 0000000000000000 VR00:1b 0000000000000000 0100 ; 01c TR00:1c 0000000000000000 VR00:1c 0000000000000000 0100 ; 01d TR00:1d 0000000000000000 VR00:1d 0000000000000000 0100 ; 01e TR00:1e 0000000000000000 VR00:1e 0000000000000000 0100 ; 01f TR00:1f 0000000000000000 VR00:1f 0000000000000000 0100 ; 020 TR01:00 0000000000000000 VR01:00 0000000000000000 0100 ; 021 TR01:01 0000000000000000 VR01:01 0000000000000000 0100 ; 022 TR01:02 0000000000000000 VR01:02 0000000000000000 0100 ; 023 TR01:03 0000000000000000 VR01:03 0000000000000000 0100 ; 024 TR01:04 0000000000000000 VR01:04 0000000000000000 0100 ; 025 TR01:05 0000000000000000 VR01:05 0000000000000000 0100 ; 026 TR01:06 0000000000000000 VR01:06 0000000000000000 0100 ; 027 TR01:07 0000000000000000 VR01:07 0000000000000000 0100 ; 028 TR01:08 0000000000000000 VR01:08 0000000000000000 0100 ; 029 TR01:09 0000000000000000 VR01:09 0000000000000000 0100 ; 02a TR01:0a 0000000000000000 VR01:0a 0000000000000000 0100 ; 02b TR01:0b 0000000000000000 VR01:0b 0000000000000000 0100 ; 02c TR01:0c 0000000000000000 VR01:0c 0000000000000000 0100 ; 02d TR01:0d 0000000000000000 VR01:0d 0000000000000000 0100 ; 02e TR01:0e 0000000000000000 VR01:0e 0000000000000000 0100 ; 02f TR01:0f 0000000000000000 VR01:0f 0000000000000000 0100 ; 030 TR01:10 0000000000000000 VR01:10 0000000000000000 0100 ; 031 TR01:11 0000000000000000 VR01:11 0000000000000000 0100 ; 032 TR01:12 0000000000000000 VR01:12 0000000000000000 0100 ; 033 TR01:13 0000000000000000 VR01:13 0000000000000000 0100 ; 034 TR01:14 0000000000000000 VR01:14 0000000000000000 0100 ; 035 TR01:15 0000000000000000 VR01:15 0000000000000000 0100 ; 036 TR01:16 0000000000000000 VR01:16 0000000000000000 0100 ; 037 TR01:17 0000000000000000 VR01:17 0000000000000000 0100 ; 038 TR01:18 0000000000000000 VR01:18 0000000000000000 0100 ; 039 TR01:19 0000000000000000 VR01:19 0000000000000000 0100 ; 03a TR01:1a 0000000000000000 VR01:1a 0000000000000000 0100 ; 03b TR01:1b 0000000000000000 VR01:1b 0000000000000000 0100 ; 03c TR01:1c 0000000000000000 VR01:1c 0000000000000000 0100 ; 03d TR01:1d 0000000000000000 VR01:1d 0000000000000000 0100 ; 03e TR01:1e 0000000000000000 VR01:1e 0000000000000000 0100 ; 03f TR01:1f 0000000000000000 VR01:1f 0000000000000000 0100 ; 040 TR02:00 0000000000000000 VR02:00 0000000000000000 0100 ; 041 TR02:01 0000000000000000 VR02:01 0000000000000000 0100 ; 042 TR02:02 0000000000000000 VR02:02 0000000000000000 0100 ; 043 TR02:03 0000000000000000 VR02:03 0000000000000000 0100 ; 044 TR02:04 0000000000000000 VR02:04 0000000000000000 0100 ; 045 TR02:05 0000000000000000 VR02:05 0000000000000000 0100 ; 046 TR02:06 0000000000000000 VR02:06 0000000000000000 0100 ; 047 TR02:07 0000000000000000 VR02:07 0000000000000000 0100 ; 048 TR02:08 0000000000000000 VR02:08 0000000000000000 0100 ; 049 TR02:09 0000000000000000 VR02:09 0000000000000000 0100 ; 04a TR02:0a 0000000000000000 VR02:0a 0000000000000000 0100 ; 04b TR02:0b 0000000000000000 VR02:0b 0000000000000000 0100 ; 04c TR02:0c 0000000000000000 VR02:0c 0000000000000000 0100 ; 04d TR02:0d 0000000000000000 VR02:0d 0000000000000000 0100 ; 04e TR02:0e 0000000000000000 VR02:0e 0000000000000000 0100 ; 04f TR02:0f 0000000000000000 VR02:0f 0000000000000000 0100 ; 050 TR02:10 0000000000000000 VR02:10 0000000000000000 0100 ; 051 TR02:11 0000000000000000 VR02:11 0000000000000000 0100 ; 052 TR02:12 0000000000000000 VR02:12 0000000000000000 0100 ; 053 TR02:13 0000000000000000 VR02:13 0000000000000000 0100 ; 054 TR02:14 0000000000000000 VR02:14 0000000000000000 0100 ; 055 TR02:15 0000000000000000 VR02:15 0000000000000000 0100 ; 056 TR02:16 0000000000000000 VR02:16 0000000000000000 0100 ; 057 TR02:17 0000000000000000 VR02:17 0000000000000000 0100 ; 058 TR02:18 0000000000000000 VR02:18 0000000000000000 0100 ; 059 TR02:19 0000000000000000 VR02:19 0000000000000000 0100 ; 05a TR02:1a 0000000000000000 VR02:1a 0000000000000000 0100 ; 05b TR02:1b 0000000000000000 VR02:1b 0000000000000000 0100 ; 05c TR02:1c 0000000000000000 VR02:1c 0000000000000000 0100 ; 05d TR02:1d 0000000000000000 VR02:1d 0000000000000000 0100 ; 05e TR02:1e 0000000000000000 VR02:1e 0000000000000000 0100 ; 05f TR02:1f 0000000000000000 VR02:1f 0000000000000000 0100 ; 060 TR03:00 0000000000000000 VR03:00 0000000000000000 0100 ; 061 TR03:01 0000000000000000 VR03:01 0000000000000000 0100 ; 062 TR03:02 0000000000000000 VR03:02 0000000000000000 0100 ; 063 TR03:03 0000000000000000 VR03:03 0000000000000000 0100 ; 064 TR03:04 0000000000000000 VR03:04 0000000000000000 0100 ; 065 TR03:05 0000000000000000 VR03:05 0000000000000000 0100 ; 066 TR03:06 0000000000000000 VR03:06 0000000000000000 0100 ; 067 TR03:07 0000000000000000 VR03:07 0000000000000000 0100 ; 068 TR03:08 0000000000000000 VR03:08 0000000000000000 0100 ; 069 TR03:09 0000000000000000 VR03:09 0000000000000000 0100 ; 06a TR03:0a 0000000000000000 VR03:0a 0000000000000000 0100 ; 06b TR03:0b 0000000000000000 VR03:0b 0000000000000000 0100 ; 06c TR03:0c 0000000000000000 VR03:0c 0000000000000000 0100 ; 06d TR03:0d 0000000000000000 VR03:0d 0000000000000000 0100 ; 06e TR03:0e 0000000000000000 VR03:0e 0000000000000000 0100 ; 06f TR03:0f 0000000000000000 VR03:0f 0000000000000000 0100 ; 070 TR03:10 0000000000000000 VR03:10 0000000000000000 0100 ; 071 TR03:11 0000000000000000 VR03:11 0000000000000000 0100 ; 072 TR03:12 0000000000000000 VR03:12 0000000000000000 0100 ; 073 TR03:13 0000000000000000 VR03:13 0000000000000000 0100 ; 074 TR03:14 0000000000000000 VR03:14 0000000000000000 0100 ; 075 TR03:15 0000000000000000 VR03:15 0000000000000000 0100 ; 076 TR03:16 0000000000000000 VR03:16 0000000000000000 0100 ; 077 TR03:17 0000000000000000 VR03:17 0000000000000000 0100 ; 078 TR03:18 0000000000000000 VR03:18 0000000000000000 0100 ; 079 TR03:19 0000000000000000 VR03:19 0000000000000000 0100 ; 07a TR03:1a 0000000000000000 VR03:1a 0000000000000000 0100 ; 07b TR03:1b 0000000000000000 VR03:1b 0000000000000000 0100 ; 07c TR03:1c 0000000000000000 VR03:1c 0000000000000000 0100 ; 07d TR03:1d 0000000000000000 VR03:1d 0000000000000000 0100 ; 07e TR03:1e 0000000000000000 VR03:1e 0000000000000000 0100 ; 07f TR03:1f 0000000000000000 VR03:1f 0000000000000000 0100 ; 080 TR04:00 0000000000000000 VR04:00 0000000000000000 0100 ; 081 TR04:01 0000000000000000 VR04:01 0000000000000000 0100 ; 082 TR04:02 0000000000000000 VR04:02 0000000000000000 0100 ; 083 TR04:03 0000000000000000 VR04:03 0000000000000000 0100 ; 084 TR04:04 0000000000000000 VR04:04 0000000000000000 0100 ; 085 TR04:05 0000000000000000 VR04:05 0000000000000000 0100 ; 086 TR04:06 0000000000000000 VR04:06 0000000000000000 0100 ; 087 TR04:07 0000000000000000 VR04:07 0000000000000000 0100 ; 088 TR04:08 0000000000000000 VR04:08 0000000000000000 0100 ; 089 TR04:09 0000000000000000 VR04:09 0000000000000000 0100 ; 08a TR04:0a 0000000000000000 VR04:0a 0000000000000000 0100 ; 08b TR04:0b 0000000000000000 VR04:0b 0000000000000000 0100 ; 08c TR04:0c 0000000000000000 VR04:0c 0000000000000000 0100 ; 08d TR04:0d 0000000000000000 VR04:0d 0000000000000000 0100 ; 08e TR04:0e 0000000000000000 VR04:0e 0000000000000000 0100 ; 08f TR04:0f 0000000000000000 VR04:0f 0000000000000000 0100 ; 090 TR04:10 0000000000000000 VR04:10 0000000000000000 0100 ; 091 TR04:11 0000000000000000 VR04:11 0000000000000000 0100 ; 092 TR04:12 0000000000000000 VR04:12 0000000000000000 0100 ; 093 TR04:13 0000000000000000 VR04:13 0000000000000000 0100 ; 094 TR04:14 0000000000000000 VR04:14 0000000000000000 0100 ; 095 TR04:15 0000000000000000 VR04:15 0000000000000000 0100 ; 096 TR04:16 0000000000000000 VR04:16 0000000000000000 0100 ; 097 TR04:17 0000000000000000 VR04:17 0000000000000000 0100 ; 098 TR04:18 0000000000000000 VR04:18 0000000000000000 0100 ; 099 TR04:19 0000000000000000 VR04:19 0000000000000000 0100 ; 09a TR04:1a 0000000000000000 VR04:1a 0000000000000000 0100 ; 09b TR04:1b 0000000000000000 VR04:1b 0000000000000000 0100 ; 09c TR04:1c 0000000000000000 VR04:1c 0000000000000000 0100 ; 09d TR04:1d 0000000000000000 VR04:1d 0000000000000000 0100 ; 09e TR04:1e 0000000000000000 VR04:1e 0000000000000000 0100 ; 09f TR04:1f 0000000000000000 VR04:1f 0000000000000000 0100 ; 0a0 TR05:00 0000000000000000 VR05:00 0000000000000000 0100 ; 0a1 TR05:01 0000000000000000 VR05:01 0000000000000000 0100 ; 0a2 TR05:02 0000000000000000 VR05:02 0000000000000000 0100 ; 0a3 TR05:03 0000000000000000 VR05:03 0000000000000000 0100 ; 0a4 TR05:04 0000000000000000 VR05:04 0000000000000000 0100 ; 0a5 TR05:05 0000000000000000 VR05:05 0000000000000000 0100 ; 0a6 TR05:06 0000000000000000 VR05:06 0000000000000000 0100 ; 0a7 TR05:07 0000000000000000 VR05:07 0000000000000000 0100 ; 0a8 TR05:08 0000000000000000 VR05:08 0000000000000000 0100 ; 0a9 TR05:09 0000000000000000 VR05:09 0000000000000000 0100 ; 0aa TR05:0a 0000000000000000 VR05:0a 0000000000000000 0100 ; 0ab TR05:0b 0000000000000000 VR05:0b 0000000000000000 0100 ; 0ac TR05:0c 0000000000000000 VR05:0c 0000000000000000 0100 ; 0ad TR05:0d 0000000000000000 VR05:0d 0000000000000000 0100 ; 0ae TR05:0e 0000000000000000 VR05:0e 0000000000000000 0100 ; 0af TR05:0f 0000000000000000 VR05:0f 0000000000000000 0100 ; 0b0 TR05:10 0000000000000000 VR05:10 0000000000000000 0100 ; 0b1 TR05:11 0000000000000000 VR05:11 0000000000000000 0100 ; 0b2 TR05:12 0000000000000000 VR05:12 0000000000000000 0100 ; 0b3 TR05:13 0000000000000000 VR05:13 0000000000000000 0100 ; 0b4 TR05:14 0000000000000000 VR05:14 0000000000000000 0100 ; 0b5 TR05:15 0000000000000000 VR05:15 0000000000000000 0100 ; 0b6 TR05:16 0000000000000000 VR05:16 0000000000000000 0100 ; 0b7 TR05:17 0000000000000000 VR05:17 0000000000000000 0100 ; 0b8 TR05:18 0000000000000000 VR05:18 0000000000000000 0100 ; 0b9 TR05:19 0000000000000000 VR05:19 0000000000000000 0100 ; 0ba TR05:1a 0000000000000000 VR05:1a 0000000000000000 0100 ; 0bb TR05:1b 0000000000000000 VR05:1b 0000000000000000 0100 ; 0bc TR05:1c 0000000000000000 VR05:1c 0000000000000000 0100 ; 0bd TR05:1d 0000000000000000 VR05:1d 0000000000000000 0100 ; 0be TR05:1e 0000000000000000 VR05:1e 0000000000000000 0100 ; 0bf TR05:1f 0000000000000000 VR05:1f 0000000000000000 0100 ; 0c0 TR06:00 0000000000000000 VR06:00 0000000000000000 0100 ; 0c1 TR06:01 0000000000000000 VR06:01 0000000000000000 0100 ; 0c2 TR06:02 0000000000000000 VR06:02 0000000000000000 0100 ; 0c3 TR06:03 0000000000000000 VR06:03 0000000000000000 0100 ; 0c4 TR06:04 0000000000000000 VR06:04 0000000000000000 0100 ; 0c5 TR06:05 0000000000000000 VR06:05 0000000000000000 0100 ; 0c6 TR06:06 0000000000000000 VR06:06 0000000000000000 0100 ; 0c7 TR06:07 0000000000000000 VR06:07 0000000000000000 0100 ; 0c8 TR06:08 0000000000000000 VR06:08 0000000000000000 0100 ; 0c9 TR06:09 0000000000000000 VR06:09 0000000000000000 0100 ; 0ca TR06:0a 0000000000000000 VR06:0a 0000000000000000 0100 ; 0cb TR06:0b 0000000000000000 VR06:0b 0000000000000000 0100 ; 0cc TR06:0c 0000000000000000 VR06:0c 0000000000000000 0100 ; 0cd TR06:0d 0000000000000000 VR06:0d 0000000000000000 0100 ; 0ce TR06:0e 0000000000000000 VR06:0e 0000000000000000 0100 ; 0cf TR06:0f 0000000000000000 VR06:0f 0000000000000000 0100 ; 0d0 TR06:10 0000000000000000 VR06:10 0000000000000000 0100 ; 0d1 TR06:11 0000000000000000 VR06:11 0000000000000000 0100 ; 0d2 TR06:12 0000000000000000 VR06:12 0000000000000000 0100 ; 0d3 TR06:13 0000000000000000 VR06:13 0000000000000000 0100 ; 0d4 TR06:14 0000000000000000 VR06:14 0000000000000000 0100 ; 0d5 TR06:15 0000000000000000 VR06:15 0000000000000000 0100 ; 0d6 TR06:16 0000000000000000 VR06:16 0000000000000000 0100 ; 0d7 TR06:17 0000000000000000 VR06:17 0000000000000000 0100 ; 0d8 TR06:18 0000000000000000 VR06:18 0000000000000000 0100 ; 0d9 TR06:19 0000000000000000 VR06:19 0000000000000000 0100 ; 0da TR06:1a 0000000000000000 VR06:1a 0000000000000000 0100 ; 0db TR06:1b 0000000000000000 VR06:1b 0000000000000000 0100 ; 0dc TR06:1c 0000000000000000 VR06:1c 0000000000000000 0100 ; 0dd TR06:1d 0000000000000000 VR06:1d 0000000000000000 0100 ; 0de TR06:1e 0000000000000000 VR06:1e 0000000000000000 0100 ; 0df TR06:1f 0000000000000000 VR06:1f 0000000000000000 0100 ; 0e0 TR07:00 0000000000000000 VR07:00 0000000000000000 0100 ; 0e1 TR07:01 0000000000000000 VR07:01 0000000000000000 0100 ; 0e2 TR07:02 0000000000000000 VR07:02 0000000000000000 0100 ; 0e3 TR07:03 0000000000000000 VR07:03 0000000000000000 0100 ; 0e4 TR07:04 0000000000000000 VR07:04 0000000000000000 0100 ; 0e5 TR07:05 0000000000000000 VR07:05 0000000000000000 0100 ; 0e6 TR07:06 0000000000000000 VR07:06 0000000000000000 0100 ; 0e7 TR07:07 0000000000000000 VR07:07 0000000000000000 0100 ; 0e8 TR07:08 0000000000000000 VR07:08 0000000000000000 0100 ; 0e9 TR07:09 0000000000000000 VR07:09 0000000000000000 0100 ; 0ea TR07:0a 0000000000000000 VR07:0a 0000000000000000 0100 ; 0eb TR07:0b 0000000000000000 VR07:0b 0000000000000000 0100 ; 0ec TR07:0c 0000000000000000 VR07:0c 0000000000000000 0100 ; 0ed TR07:0d 0000000000000000 VR07:0d 0000000000000000 0100 ; 0ee TR07:0e 0000000000000000 VR07:0e 0000000000000000 0100 ; 0ef TR07:0f 0000000000000000 VR07:0f 0000000000000000 0100 ; 0f0 TR07:10 0000000000000000 VR07:10 0000000000000000 0100 ; 0f1 TR07:11 0000000000000000 VR07:11 0000000000000000 0100 ; 0f2 TR07:12 0000000000000000 VR07:12 0000000000000000 0100 ; 0f3 TR07:13 0000000000000000 VR07:13 0000000000000000 0100 ; 0f4 TR07:14 0000000000000000 VR07:14 0000000000000000 0100 ; 0f5 TR07:15 0000000000000000 VR07:15 0000000000000000 0100 ; 0f6 TR07:16 0000000000000000 VR07:16 0000000000000000 0100 ; 0f7 TR07:17 0000000000000000 VR07:17 0000000000000000 0100 ; 0f8 TR07:18 0000000000000000 VR07:18 0000000000000000 0100 ; 0f9 TR07:19 0000000000000000 VR07:19 0000000000000000 0100 ; 0fa TR07:1a 0000000000000000 VR07:1a 0000000000000000 0100 ; 0fb TR07:1b 0000000000000000 VR07:1b 0000000000000000 0100 ; 0fc TR07:1c 0000000000000000 VR07:1c 0000000000000000 0100 ; 0fd TR07:1d 0000000000000000 VR07:1d 0000000000000000 0100 ; 0fe TR07:1e 0000000000000000 VR07:1e 0000000000000000 0100 ; 0ff TR07:1f 0000000000000000 VR07:1f 0000000000000000 0100 ; 100 TR08:00 0000000000000000 VR08:00 0000000000000000 0100 ; 101 TR08:01 0000000000000000 VR08:01 0000000000000000 0100 ; 102 TR08:02 0000000000000000 VR08:02 0000000000000000 0100 ; 103 TR08:03 0000000000000000 VR08:03 0000000000000000 0100 ; 104 TR08:04 0000000000000000 VR08:04 0000000000000000 0100 ; 105 TR08:05 0000000000000000 VR08:05 0000000000000000 0100 ; 106 TR08:06 0000000000000000 VR08:06 0000000000000000 0100 ; 107 TR08:07 0000000000000000 VR08:07 0000000000000000 0100 ; 108 TR08:08 0000000000000000 VR08:08 0000000000000000 0100 ; 109 TR08:09 0000000000000000 VR08:09 0000000000000000 0100 ; 10a TR08:0a 0000000000000000 VR08:0a 0000000000000000 0100 ; 10b TR08:0b 0000000000000000 VR08:0b 0000000000000000 0100 ; 10c TR08:0c 0000000000000000 VR08:0c 0000000000000000 0100 ; 10d TR08:0d 0000000000000000 VR08:0d 0000000000000000 0100 ; 10e TR08:0e 0000000000000000 VR08:0e 0000000000000000 0100 ; 10f TR08:0f 0000000000000000 VR08:0f 0000000000000000 0100 ; 110 TR08:10 0000000000000000 VR08:10 0000000000000000 0100 ; 111 TR08:11 0000000000000000 VR08:11 0000000000000000 0100 ; 112 TR08:12 0000000000000000 VR08:12 0000000000000000 0100 ; 113 TR08:13 0000000000000000 VR08:13 0000000000000000 0100 ; 114 TR08:14 0000000000000000 VR08:14 0000000000000000 0100 ; 115 TR08:15 0000000000000000 VR08:15 0000000000000000 0100 ; 116 TR08:16 0000000000000000 VR08:16 0000000000000000 0100 ; 117 TR08:17 0000000000000000 VR08:17 0000000000000000 0100 ; 118 TR08:18 0000000000000000 VR08:18 0000000000000000 0100 ; 119 TR08:19 0000000000000000 VR08:19 0000000000000000 0100 ; 11a TR08:1a 0000000000000000 VR08:1a 0000000000000000 0100 ; 11b TR08:1b 0000000000000000 VR08:1b 0000000000000000 0100 ; 11c TR08:1c 0000000000000000 VR08:1c 0000000000000000 0100 ; 11d TR08:1d 0000000000000000 VR08:1d 0000000000000000 0100 ; 11e TR08:1e 0000000000000000 VR08:1e 0000000000000000 0100 ; 11f TR08:1f 0000000000000000 VR08:1f 0000000000000000 0100 ; 120 TR09:00 0000000000000000 VR09:00 0000000000000000 0100 ; 121 TR09:01 0000000000000000 VR09:01 0000000000000000 0100 ; 122 TR09:02 0000000000000000 VR09:02 0000000000000000 0100 ; 123 TR09:03 0000000000000000 VR09:03 0000000000000000 0100 ; 124 TR09:04 0000000000000000 VR09:04 0000000000000000 0100 ; 125 TR09:05 0000000000000000 VR09:05 0000000000000000 0100 ; 126 TR09:06 0000000000000000 VR09:06 0000000000000000 0100 ; 127 TR09:07 0000000000000000 VR09:07 0000000000000000 0100 ; 128 TR09:08 0000000000000000 VR09:08 0000000000000000 0100 ; 129 TR09:09 0000000000000000 VR09:09 0000000000000000 0100 ; 12a TR09:0a 0000000000000000 VR09:0a 0000000000000000 0100 ; 12b TR09:0b 0000000000000000 VR09:0b 0000000000000000 0100 ; 12c TR09:0c 0000000000000000 VR09:0c 0000000000000000 0100 ; 12d TR09:0d 0000000000000000 VR09:0d 0000000000000000 0100 ; 12e TR09:0e 0000000000000000 VR09:0e 0000000000000000 0100 ; 12f TR09:0f 0000000000000000 VR09:0f 0000000000000000 0100 ; 130 TR09:10 0000000000000000 VR09:10 0000000000000000 0100 ; 131 TR09:11 0000000000000000 VR09:11 0000000000000000 0100 ; 132 TR09:12 0000000000000000 VR09:12 0000000000000000 0100 ; 133 TR09:13 0000000000000000 VR09:13 0000000000000000 0100 ; 134 TR09:14 0000000000000000 VR09:14 0000000000000000 0100 ; 135 TR09:15 0000000000000000 VR09:15 0000000000000000 0100 ; 136 TR09:16 0000000000000000 VR09:16 0000000000000000 0100 ; 137 TR09:17 0000000000000000 VR09:17 0000000000000000 0100 ; 138 TR09:18 0000000000000000 VR09:18 0000000000000000 0100 ; 139 TR09:19 0000000000000000 VR09:19 0000000000000000 0100 ; 13a TR09:1a 0000000000000000 VR09:1a 0000000000000000 0100 ; 13b TR09:1b 0000000000000000 VR09:1b 0000000000000000 0100 ; 13c TR09:1c 0000000000000000 VR09:1c 0000000000000000 0100 ; 13d TR09:1d 0000000000000000 VR09:1d 0000000000000000 0100 ; 13e TR09:1e 0000000000000000 VR09:1e 0000000000000000 0100 ; 13f TR09:1f 0000000000000000 VR09:1f 0000000000000000 0100 ; 140 TR0a:00 0000000000000000 VR0a:00 0000000000000000 0100 ; 141 TR0a:01 0000000000000000 VR0a:01 0000000000000000 0100 ; 142 TR0a:02 0000000000000000 VR0a:02 0000000000000000 0100 ; 143 TR0a:03 0000000000000000 VR0a:03 0000000000000000 0100 ; 144 TR0a:04 0000000000000000 VR0a:04 0000000000000000 0100 ; 145 TR0a:05 0000000000000000 VR0a:05 0000000000000000 0100 ; 146 TR0a:06 0000000000000000 VR0a:06 0000000000000000 0100 ; 147 TR0a:07 0000000000000000 VR0a:07 0000000000000000 0100 ; 148 TR0a:08 0000000000000000 VR0a:08 0000000000000000 0100 ; 149 TR0a:09 0000000000000000 VR0a:09 0000000000000000 0100 ; 14a TR0a:0a 0000000000000000 VR0a:0a 0000000000000000 0100 ; 14b TR0a:0b 0000000000000000 VR0a:0b 0000000000000000 0100 ; 14c TR0a:0c 0000000000000000 VR0a:0c 0000000000000000 0100 ; 14d TR0a:0d 0000000000000000 VR0a:0d 0000000000000000 0100 ; 14e TR0a:0e 0000000000000000 VR0a:0e 0000000000000000 0100 ; 14f TR0a:0f 0000000000000000 VR0a:0f 0000000000000000 0100 ; 150 TR0a:10 0000000000000000 VR0a:10 0000000000000000 0100 ; 151 TR0a:11 0000000000000000 VR0a:11 0000000000000000 0100 ; 152 TR0a:12 0000000000000000 VR0a:12 0000000000000000 0100 ; 153 TR0a:13 0000000000000000 VR0a:13 0000000000000000 0100 ; 154 TR0a:14 0000000000000000 VR0a:14 0000000000000000 0100 ; 155 TR0a:15 0000000000000000 VR0a:15 0000000000000000 0100 ; 156 TR0a:16 0000000000000000 VR0a:16 0000000000000000 0100 ; 157 TR0a:17 0000000000000000 VR0a:17 0000000000000000 0100 ; 158 TR0a:18 0000000000000000 VR0a:18 0000000000000000 0100 ; 159 TR0a:19 0000000000000000 VR0a:19 0000000000000000 0100 ; 15a TR0a:1a 0000000000000000 VR0a:1a 0000000000000000 0100 ; 15b TR0a:1b 0000000000000000 VR0a:1b 0000000000000000 0100 ; 15c TR0a:1c 0000000000000000 VR0a:1c 0000000000000000 0100 ; 15d TR0a:1d 0000000000000000 VR0a:1d 0000000000000000 0100 ; 15e TR0a:1e 0000000000000000 VR0a:1e 0000000000000000 0100 ; 15f TR0a:1f 0000000000000000 VR0a:1f 0000000000000000 0100 ; 160 TR0b:00 0000000000000000 VR0b:00 0000000000000000 0100 ; 161 TR0b:01 0000000000000000 VR0b:01 0000000000000000 0100 ; 162 TR0b:02 0000000000000000 VR0b:02 0000000000000000 0100 ; 163 TR0b:03 0000000000000000 VR0b:03 0000000000000000 0100 ; 164 TR0b:04 0000000000000000 VR0b:04 0000000000000000 0100 ; 165 TR0b:05 0000000000000000 VR0b:05 0000000000000000 0100 ; 166 TR0b:06 0000000000000000 VR0b:06 0000000000000000 0100 ; 167 TR0b:07 0000000000000000 VR0b:07 0000000000000000 0100 ; 168 TR0b:08 0000000000000000 VR0b:08 0000000000000000 0100 ; 169 TR0b:09 0000000000000000 VR0b:09 0000000000000000 0100 ; 16a TR0b:0a 0000000000000000 VR0b:0a 0000000000000000 0100 ; 16b TR0b:0b 0000000000000000 VR0b:0b 0000000000000000 0100 ; 16c TR0b:0c 0000000000000000 VR0b:0c 0000000000000000 0100 ; 16d TR0b:0d 0000000000000000 VR0b:0d 0000000000000000 0100 ; 16e TR0b:0e 0000000000000000 VR0b:0e 0000000000000000 0100 ; 16f TR0b:0f 0000000000000000 VR0b:0f 0000000000000000 0100 ; 170 TR0b:10 0000000000000000 VR0b:10 0000000000000000 0100 ; 171 TR0b:11 0000000000000000 VR0b:11 0000000000000000 0100 ; 172 TR0b:12 0000000000000000 VR0b:12 0000000000000000 0100 ; 173 TR0b:13 0000000000000000 VR0b:13 0000000000000000 0100 ; 174 TR0b:14 0000000000000000 VR0b:14 0000000000000000 0100 ; 175 TR0b:15 0000000000000000 VR0b:15 0000000000000000 0100 ; 176 TR0b:16 0000000000000000 VR0b:16 0000000000000000 0100 ; 177 TR0b:17 0000000000000000 VR0b:17 0000000000000000 0100 ; 178 TR0b:18 0000000000000000 VR0b:18 0000000000000000 0100 ; 179 TR0b:19 0000000000000000 VR0b:19 0000000000000000 0100 ; 17a TR0b:1a 0000000000000000 VR0b:1a 0000000000000000 0100 ; 17b TR0b:1b 0000000000000000 VR0b:1b 0000000000000000 0100 ; 17c TR0b:1c 0000000000000000 VR0b:1c 0000000000000000 0100 ; 17d TR0b:1d 0000000000000000 VR0b:1d 0000000000000000 0100 ; 17e TR0b:1e 0000000000000000 VR0b:1e 0000000000000000 0100 ; 17f TR0b:1f 0000000000000000 VR0b:1f 0000000000000000 0100 ; 180 TR0c:00 0000000000000000 VR0c:00 0000000000000000 0100 ; 181 TR0c:01 0000000000000000 VR0c:01 0000000000000000 0100 ; 182 TR0c:02 0000000000000000 VR0c:02 0000000000000000 0100 ; 183 TR0c:03 0000000000000000 VR0c:03 0000000000000000 0100 ; 184 TR0c:04 0000000000000000 VR0c:04 0000000000000000 0100 ; 185 TR0c:05 0000000000000000 VR0c:05 0000000000000000 0100 ; 186 TR0c:06 0000000000000000 VR0c:06 0000000000000000 0100 ; 187 TR0c:07 0000000000000000 VR0c:07 0000000000000000 0100 ; 188 TR0c:08 0000000000000000 VR0c:08 0000000000000000 0100 ; 189 TR0c:09 0000000000000000 VR0c:09 0000000000000000 0100 ; 18a TR0c:0a 0000000000000000 VR0c:0a 0000000000000000 0100 ; 18b TR0c:0b 0000000000000000 VR0c:0b 0000000000000000 0100 ; 18c TR0c:0c 0000000000000000 VR0c:0c 0000000000000000 0100 ; 18d TR0c:0d 0000000000000000 VR0c:0d 0000000000000000 0100 ; 18e TR0c:0e 0000000000000000 VR0c:0e 0000000000000000 0100 ; 18f TR0c:0f 0000000000000000 VR0c:0f 0000000000000000 0100 ; 190 TR0c:10 0000000000000000 VR0c:10 0000000000000000 0100 ; 191 TR0c:11 0000000000000000 VR0c:11 0000000000000000 0100 ; 192 TR0c:12 0000000000000000 VR0c:12 0000000000000000 0100 ; 193 TR0c:13 0000000000000000 VR0c:13 0000000000000000 0100 ; 194 TR0c:14 0000000000000000 VR0c:14 0000000000000000 0100 ; 195 TR0c:15 0000000000000000 VR0c:15 0000000000000000 0100 ; 196 TR0c:16 0000000000000000 VR0c:16 0000000000000000 0100 ; 197 TR0c:17 0000000000000000 VR0c:17 0000000000000000 0100 ; 198 TR0c:18 0000000000000000 VR0c:18 0000000000000000 0100 ; 199 TR0c:19 0000000000000000 VR0c:19 0000000000000000 0100 ; 19a TR0c:1a 0000000000000000 VR0c:1a 0000000000000000 0100 ; 19b TR0c:1b 0000000000000000 VR0c:1b 0000000000000000 0100 ; 19c TR0c:1c 0000000000000000 VR0c:1c 0000000000000000 0100 ; 19d TR0c:1d 0000000000000000 VR0c:1d 0000000000000000 0100 ; 19e TR0c:1e 0000000000000000 VR0c:1e 0000000000000000 0100 ; 19f TR0c:1f 0000000000000000 VR0c:1f 0000000000000000 0100 ; 1a0 TR0d:00 0000000000000000 VR0d:00 0000000000000000 0100 ; 1a1 TR0d:01 0000000000000000 VR0d:01 0000000000000000 0100 ; 1a2 TR0d:02 0000000000000000 VR0d:02 0000000000000000 0100 ; 1a3 TR0d:03 0000000000000000 VR0d:03 0000000000000000 0100 ; 1a4 TR0d:04 0000000000000000 VR0d:04 0000000000000000 0100 ; 1a5 TR0d:05 0000000000000000 VR0d:05 0000000000000000 0100 ; 1a6 TR0d:06 0000000000000000 VR0d:06 0000000000000000 0100 ; 1a7 TR0d:07 0000000000000000 VR0d:07 0000000000000000 0100 ; 1a8 TR0d:08 0000000000000000 VR0d:08 0000000000000000 0100 ; 1a9 TR0d:09 0000000000000000 VR0d:09 0000000000000000 0100 ; 1aa TR0d:0a 0000000000000000 VR0d:0a 0000000000000000 0100 ; 1ab TR0d:0b 0000000000000000 VR0d:0b 0000000000000000 0100 ; 1ac TR0d:0c 0000000000000000 VR0d:0c 0000000000000000 0100 ; 1ad TR0d:0d 0000000000000000 VR0d:0d 0000000000000000 0100 ; 1ae TR0d:0e 0000000000000000 VR0d:0e 0000000000000000 0100 ; 1af TR0d:0f 0000000000000000 VR0d:0f 0000000000000000 0100 ; 1b0 TR0d:10 0000000000000000 VR0d:10 0000000000000000 0100 ; 1b1 TR0d:11 0000000000000000 VR0d:11 0000000000000000 0100 ; 1b2 TR0d:12 0000000000000000 VR0d:12 0000000000000000 0100 ; 1b3 TR0d:13 0000000000000000 VR0d:13 0000000000000000 0100 ; 1b4 TR0d:14 0000000000000000 VR0d:14 0000000000000000 0100 ; 1b5 TR0d:15 0000000000000000 VR0d:15 0000000000000000 0100 ; 1b6 TR0d:16 0000000000000000 VR0d:16 0000000000000000 0100 ; 1b7 TR0d:17 0000000000000000 VR0d:17 0000000000000000 0100 ; 1b8 TR0d:18 0000000000000000 VR0d:18 0000000000000000 0100 ; 1b9 TR0d:19 0000000000000000 VR0d:19 0000000000000000 0100 ; 1ba TR0d:1a 0000000000000000 VR0d:1a 0000000000000000 0100 ; 1bb TR0d:1b 0000000000000000 VR0d:1b 0000000000000000 0100 ; 1bc TR0d:1c 0000000000000000 VR0d:1c 0000000000000000 0100 ; 1bd TR0d:1d 0000000000000000 VR0d:1d 0000000000000000 0100 ; 1be TR0d:1e 0000000000000000 VR0d:1e 0000000000000000 0100 ; 1bf TR0d:1f 0000000000000000 VR0d:1f 0000000000000000 0100 ; 1c0 TR0e:00 0000000000000000 VR0e:00 0000000000000000 0100 ; 1c1 TR0e:01 0000000000000000 VR0e:01 0000000000000000 0100 ; 1c2 TR0e:02 0000000000000000 VR0e:02 0000000000000000 0100 ; 1c3 TR0e:03 0000000000000000 VR0e:03 0000000000000000 0100 ; 1c4 TR0e:04 0000000000000000 VR0e:04 0000000000000000 0100 ; 1c5 TR0e:05 0000000000000000 VR0e:05 0000000000000000 0100 ; 1c6 TR0e:06 0000000000000000 VR0e:06 0000000000000000 0100 ; 1c7 TR0e:07 0000000000000000 VR0e:07 0000000000000000 0100 ; 1c8 TR0e:08 0000000000000000 VR0e:08 0000000000000000 0100 ; 1c9 TR0e:09 0000000000000000 VR0e:09 0000000000000000 0100 ; 1ca TR0e:0a 0000000000000000 VR0e:0a 0000000000000000 0100 ; 1cb TR0e:0b 0000000000000000 VR0e:0b 0000000000000000 0100 ; 1cc TR0e:0c 0000000000000000 VR0e:0c 0000000000000000 0100 ; 1cd TR0e:0d 0000000000000000 VR0e:0d 0000000000000000 0100 ; 1ce TR0e:0e 0000000000000000 VR0e:0e 0000000000000000 0100 ; 1cf TR0e:0f 0000000000000000 VR0e:0f 0000000000000000 0100 ; 1d0 TR0e:10 0000000000000000 VR0e:10 0000000000000000 0100 ; 1d1 TR0e:11 0000000000000000 VR0e:11 0000000000000000 0100 ; 1d2 TR0e:12 0000000000000000 VR0e:12 0000000000000000 0100 ; 1d3 TR0e:13 0000000000000000 VR0e:13 0000000000000000 0100 ; 1d4 TR0e:14 0000000000000000 VR0e:14 0000000000000000 0100 ; 1d5 TR0e:15 0000000000000000 VR0e:15 0000000000000000 0100 ; 1d6 TR0e:16 0000000000000000 VR0e:16 0000000000000000 0100 ; 1d7 TR0e:17 0000000000000000 VR0e:17 0000000000000000 0100 ; 1d8 TR0e:18 0000000000000000 VR0e:18 0000000000000000 0100 ; 1d9 TR0e:19 0000000000000000 VR0e:19 0000000000000000 0100 ; 1da TR0e:1a 0000000000000000 VR0e:1a 0000000000000000 0100 ; 1db TR0e:1b 0000000000000000 VR0e:1b 0000000000000000 0100 ; 1dc TR0e:1c 0000000000000000 VR0e:1c 0000000000000000 0100 ; 1dd TR0e:1d 0000000000000000 VR0e:1d 0000000000000000 0100 ; 1de TR0e:1e 0000000000000000 VR0e:1e 0000000000000000 0100 ; 1df TR0e:1f 0000000000000000 VR0e:1f 0000000000000000 0100 ; 1e0 TR0f:00 0000000000000000 VR0f:00 0000000000000000 0100 ; 1e1 TR0f:01 0000000000000000 VR0f:01 0000000000000000 0100 ; 1e2 TR0f:02 0000000000000000 VR0f:02 0000000000000000 0100 ; 1e3 TR0f:03 0000000000000000 VR0f:03 0000000000000000 0100 ; 1e4 TR0f:04 0000000000000000 VR0f:04 0000000000000000 0100 ; 1e5 TR0f:05 0000000000000000 VR0f:05 0000000000000000 0100 ; 1e6 TR0f:06 0000000000000000 VR0f:06 0000000000000000 0100 ; 1e7 TR0f:07 0000000000000000 VR0f:07 0000000000000000 0100 ; 1e8 TR0f:08 0000000000000000 VR0f:08 0000000000000000 0100 ; 1e9 TR0f:09 0000000000000000 VR0f:09 0000000000000000 0100 ; 1ea TR0f:0a 0000000000000000 VR0f:0a 0000000000000000 0100 ; 1eb TR0f:0b 0000000000000000 VR0f:0b 0000000000000000 0100 ; 1ec TR0f:0c 0000000000000000 VR0f:0c 0000000000000000 0100 ; 1ed TR0f:0d 0000000000000000 VR0f:0d 0000000000000000 0100 ; 1ee TR0f:0e 0000000000000000 VR0f:0e 0000000000000000 0100 ; 1ef TR0f:0f 0000000000000000 VR0f:0f 0000000000000000 0100 ; 1f0 TR0f:10 0000000000000000 VR0f:10 0000000000000000 0100 ; 1f1 TR0f:11 0000000000000000 VR0f:11 0000000000000000 0100 ; 1f2 TR0f:12 0000000000000000 VR0f:12 0000000000000000 0100 ; 1f3 TR0f:13 0000000000000000 VR0f:13 0000000000000000 0100 ; 1f4 TR0f:14 0000000000000000 VR0f:14 0000000000000000 0100 ; 1f5 TR0f:15 0000000000000000 VR0f:15 0000000000000000 0100 ; 1f6 TR0f:16 0000000000000000 VR0f:16 0000000000000000 0100 ; 1f7 TR0f:17 0000000000000000 VR0f:17 0000000000000000 0100 ; 1f8 TR0f:18 0000000000000000 VR0f:18 0000000000000000 0100 ; 1f9 TR0f:19 0000000000000000 VR0f:19 0000000000000000 0100 ; 1fa TR0f:1a 0000000000000000 VR0f:1a 0000000000000000 0100 ; 1fb TR0f:1b 0000000000000000 VR0f:1b 0000000000000000 0100 ; 1fc TR0f:1c 0000000000000000 VR0f:1c 0000000000000000 0100 ; 1fd TR0f:1d 0000000000000000 VR0f:1d 0000000000000000 0100 ; 1fe TR0f:1e 0000000000000000 VR0f:1e 0000000000000000 0100 ; 1ff TR0f:1f 0000000000000000 VR0f:1f 0000000000000000 0100 ; 200 TR10:00 0000000000000000 VR10:00 0000000000000000 0100 ; 201 TR10:01 0000000000000000 VR10:01 0000000000000000 0100 ; 202 TR10:02 0000000000000000 VR10:02 0000000000000000 0100 ; 203 TR10:03 0000000000000000 VR10:03 0000000000000000 0100 ; 204 TR10:04 0000000000000000 VR10:04 0000000000000000 0100 ; 205 TR10:05 0000000000000000 VR10:05 0000000000000000 0100 ; 206 TR10:06 0000000000000000 VR10:06 0000000000000000 0100 ; 207 TR10:07 0000000000000000 VR10:07 0000000000000000 0100 ; 208 TR10:08 0000000000000000 VR10:08 0000000000000000 0100 ; 209 TR10:09 0000000000000000 VR10:09 0000000000000000 0100 ; 20a TR10:0a 0000000000000000 VR10:0a 0000000000000000 0100 ; 20b TR10:0b 0000000000000000 VR10:0b 0000000000000000 0100 ; 20c TR10:0c 0000000000000000 VR10:0c 0000000000000000 0100 ; 20d TR10:0d 0000000000000000 VR10:0d 0000000000000000 0100 ; 20e TR10:0e 0000000000000000 VR10:0e 0000000000000000 0100 ; 20f TR10:0f 0000000000000000 VR10:0f 0000000000000000 0100 ; 210 TR10:10 0000000000000000 VR10:10 0000000000000000 0100 ; 211 TR10:11 0000000000000000 VR10:11 0000000000000000 0100 ; 212 TR10:12 0000000000000000 VR10:12 0000000000000000 0100 ; 213 TR10:13 0000000000000000 VR10:13 0000000000000000 0100 ; 214 TR10:14 0000000000000000 VR10:14 0000000000000000 0100 ; 215 TR10:15 0000000000000000 VR10:15 0000000000000000 0100 ; 216 TR10:16 0000000000000000 VR10:16 0000000000000000 0100 ; 217 TR10:17 0000000000000000 VR10:17 0000000000000000 0100 ; 218 TR10:18 0000000000000000 VR10:18 0000000000000000 0100 ; 219 TR10:19 0000000000000000 VR10:19 0000000000000000 0100 ; 21a TR10:1a 0000000000000000 VR10:1a 0000000000000000 0100 ; 21b TR10:1b 0000000000000000 VR10:1b 0000000000000000 0100 ; 21c TR10:1c 0000000000000000 VR10:1c 0000000000000000 0100 ; 21d TR10:1d 0000000000000000 VR10:1d 0000000000000000 0100 ; 21e TR10:1e 0000000000000000 VR10:1e 0000000000000000 0100 ; 21f TR10:1f 0000000000000000 VR10:1f 0000000000000000 0100 ; 220 TR11:00 0000000000000000 VR11:00 0000000000000000 0100 ; 221 TR11:01 0000000000000000 VR11:01 0000000000000000 0100 ; 222 TR11:02 0000000000000000 VR11:02 0000000000000000 0100 ; 223 TR11:03 0000000000000000 VR11:03 0000000000000000 0100 ; 224 TR11:04 0000000000000000 VR11:04 0000000000000000 0100 ; 225 TR11:05 0000000000000000 VR11:05 0000000000000000 0100 ; 226 TR11:06 0000000000000000 VR11:06 0000000000000000 0100 ; 227 TR11:07 0000000000000000 VR11:07 0000000000000000 0100 ; 228 TR11:08 0000000000000000 VR11:08 0000000000000000 0100 ; 229 TR11:09 0000000000000000 VR11:09 0000000000000000 0100 ; 22a TR11:0a 0000000000000000 VR11:0a 0000000000000000 0100 ; 22b TR11:0b 0000000000000000 VR11:0b 0000000000000000 0100 ; 22c TR11:0c 0000000000000000 VR11:0c 0000000000000000 0100 ; 22d TR11:0d 0000000000000000 VR11:0d 0000000000000000 0100 ; 22e TR11:0e 0000000000000000 VR11:0e 0000000000000000 0100 ; 22f TR11:0f 0000000000000000 VR11:0f 0000000000000000 0100 ; 230 TR11:10 0000000000000000 VR11:10 0000000000000000 0100 ; 231 TR11:11 0000000000000000 VR11:11 0000000000000000 0100 ; 232 TR11:12 0000000000000000 VR11:12 0000000000000000 0100 ; 233 TR11:13 0000000000000000 VR11:13 0000000000000000 0100 ; 234 TR11:14 0000000000000000 VR11:14 0000000000000000 0100 ; 235 TR11:15 0000000000000000 VR11:15 0000000000000000 0100 ; 236 TR11:16 0000000000000000 VR11:16 0000000000000000 0100 ; 237 TR11:17 0000000000000000 VR11:17 0000000000000000 0100 ; 238 TR11:18 0000000000000000 VR11:18 0000000000000000 0100 ; 239 TR11:19 0000000000000000 VR11:19 0000000000000000 0100 ; 23a TR11:1a 0000000000000000 VR11:1a 0000000000000000 0100 ; 23b TR11:1b 0000000000000000 VR11:1b 0000000000000000 0100 ; 23c TR11:1c 0000000000000000 VR11:1c 0000000000000000 0100 ; 23d TR11:1d 0000000000000000 VR11:1d 0000000000000000 0100 ; 23e TR11:1e 0000000000000000 VR11:1e 0000000000000000 0100 ; 23f TR11:1f 0000000000000000 VR11:1f 0000000000000000 0100 ; 240 TR12:00 0000000000000000 VR12:00 0000000000000000 0100 ; 241 TR12:01 0000000000000000 VR12:01 0000000000000000 0100 ; 242 TR12:02 0000000000000080 VR12:02 0000000000000000 0100 ; 243 TR12:03 0000000010000000 VR12:03 0000000000000000 0100 ; 244 TR12:04 0000000020000000 VR12:04 0000000000000000 0100 ; 245 TR12:05 0000000030000000 VR12:05 0000000000000000 0100 ; 246 TR12:06 ffffffff30000000 VR12:06 0000000000000000 0100 ; 247 TR12:07 ffffffff20000000 VR12:07 0000000000000000 0100 ; 248 TR12:08 0000000120000000 VR12:08 0000000000000000 0100 ; 249 TR12:09 0000000000000000 VR12:09 0000000000000000 0100 ; 24a TR12:0a 0000000000000a00 VR12:0a 0000000000000000 0100 ; 24b TR12:0b 0000000000000009 VR12:0b 0000000000000000 0100 ; 24c TR12:0c 0000000000000e00 VR12:0c 0000000000000000 0100 ; 24d TR12:0d 00000000f4000004 VR12:0d 0000000000000000 0100 ; 24e TR12:0e 0010001000100000 VR12:0e 0000000000000000 0100 ; 24f TR12:0f 0100010101020000 VR12:0f 0000000000000000 0100 ; 250 TR12:10 a000a200a400a600 VR12:10 0000000000000000 0100 ; 251 TR12:11 8000820084008600 VR12:11 0000000000000000 0100 ; 252 TR12:12 0020002100220023 VR12:12 0000000000000000 0100 ; 253 TR12:13 0014001500160017 VR12:13 0000000000000000 0100 ; 254 TR12:14 0010001100120013 VR12:14 0000000000000000 0100 ; 255 TR12:15 0000000000008000 VR12:15 0000000000000000 0100 ; 256 TR12:16 0000000100000000 VR12:16 0000000000000000 0100 ; 257 TR12:17 00000000000003fe VR12:17 0000000000000000 0100 ; 258 TR12:18 0000000000100000 VR12:18 0000000000000000 0100 ; 259 TR12:19 00000000000003f0 VR12:19 0000000000000000 0100 ; 25a TR12:1a 0000000008000000 VR12:1a 0000000000000000 0100 ; 25b TR12:1b 0000000010000000 VR12:1b 0000000000000060 0100 ; 25c TR12:1c 0000000040000000 VR12:1c 0000000000002710 0100 ; 25d TR12:1d 0000000080000000 VR12:1d 00000000ffffff80 0100 ; 25e TR12:1e 0000040000000000 VR12:1e 0014001500160017 0100 ; 25f TR12:1f 0000000000000800 VR12:1f 0000000080000000 0100 ; 260 TR13:00 000000000000001d VR13:00 000000007ffeffff 0100 ; 261 TR13:01 ffffffff7fffffff VR13:01 4000400040004000 0100 ; 262 TR13:02 ffffffffbfffffff VR13:02 000000000000000f 0100 ; 263 TR13:03 ffffffffdfffffff VR13:03 d000d000d000d000 0100 ; 264 TR13:04 ffffffffefffffff VR13:04 e801ea01ec01ee01 0100 ; 265 TR13:05 fffffffff7ffffff VR13:05 0350035003510352 0100 ; 266 TR13:06 0000000060000000 VR13:06 000000000000fff0 0100 ; 267 TR13:07 0000000048000000 VR13:07 000000000006ffa0 0100 ; 268 TR13:08 0000000028000000 VR13:08 0fff0fff0fff0fff 0100 ; 269 TR13:09 000000000007ffff VR13:09 0000000000000070 0100 ; 26a TR13:0a 0000000000000005 VR13:0a 0000000000008000 0100 ; 26b TR13:0b 0000000000000016 VR13:0b 0100000000000000 0100 ; 26c TR13:0c 0000000000000024 VR13:0c 0080000000000000 0100 ; 26d TR13:0d 000000000000000d VR13:0d 000000000007c000 0100 ; 26e TR13:0e 000000000000000e VR13:0e 000000000000000a 0100 ; 26f TR13:0f 0000000000000015 VR13:0f 00ffffff0007ffff 0100 ; 270 TR13:10 000000000000005f VR13:10 0000000000000018 0100 ; 271 TR13:11 000000000000006f VR13:11 00ffffff00000000 0100 ; 272 TR13:12 0000000000000077 VR13:12 000000000007fff0 0100 ; 273 TR13:13 000000000000007a VR13:13 000000000000003d 0100 ; 274 TR13:14 000000000000007b VR13:14 000000000000000c 0100 ; 275 TR13:15 000000000000007d VR13:15 00ffff0000000000 0100 ; 276 TR13:16 000000000000007e VR13:16 0000000000001f80 0100 ; 277 TR13:17 000000000000001e VR13:17 0000000000002000 0100 ; 278 TR13:18 000000000000002e VR13:18 0000000000000012 0100 ; 279 TR13:19 0000000000000013 VR13:19 0000000000000020 0100 ; 27a TR13:1a 000000000000001f VR13:1a 0000000000000019 0100 ; 27b TR13:1b 00000000000fc000 VR13:1b 000000000001e000 0100 ; 27c TR13:1c 0000003c60000000 VR13:1c 00000000000003fe 0100 ; 27d TR13:1d fffffbffffffffff VR13:1d 000000000001e041 0100 ; 27e TR13:1e 0350035003500350 VR13:1e 0001ff0000000000 0100 ; 27f TR13:1f 00000000000003f1 VR13:1f 000000000001f800 0100 ; 280 TR14:00 5a5a5a5adc6edc6e VR14:00 00000000000003f1 0100 ; 281 TR14:01 5a5a5a5a36c936ca VR14:01 00000000000003f0 0100 ; 282 TR14:02 5a5a5a5a36c936c8 VR14:02 0000000100000005 0100 ; 283 TR14:03 a5a5a5a536c936c9 VR14:03 111111111fffffff 0100 ; 284 TR14:04 6c936c935a5a5a5a VR14:04 00000000000000ff 0100 ; 285 TR14:05 c936c9365a5a5a5a VR14:05 0000000000ff0000 0100 ; 286 TR14:06 936c936c5a5a5a5a VR14:06 000000000000ff00 0100 ; 287 TR14:07 0000000007ffff80 VR14:07 0000000001000000 0100 ; 288 TR14:08 000000000000000f VR14:08 0000000000010000 0100 ; 289 TR14:09 ffffffff07ffff80 VR14:09 0000000200000000 0100 ; 28a TR14:0a 0000000000000007 VR14:0a 0001000000000000 0100 ; 28b TR14:0b f0f0f0f000000000 VR14:0b ffff000000000000 0100 ; 28c TR14:0c d000d000d000d000 VR14:0c 0000ffff00000000 0100 ; 28d TR14:0d 0fff0fff0fff0fff VR14:0d ffff0000ffffffff 0100 ; 28e TR14:0e 0000000000000780 VR14:0e ffffffff0000ffff 0100 ; 28f TR14:0f e001e201e401e601 VR14:0f 000000000000ffff 0100 ; 290 TR14:10 4000400040004000 VR14:10 0000000000000000 0100 ; 291 TR14:11 000000000000003b VR14:11 fffffff111111111 0100 ; 292 TR14:12 0000000000000003 VR14:12 fffffff100000000 0100 ; 293 TR14:13 0000000000000006 VR14:13 0000000100000001 0100 ; 294 TR14:14 000000000000000c VR14:14 0000000000000005 0100 ; 295 TR14:15 0000000000000018 VR14:15 000000001fffffff 0100 ; 296 TR14:16 0000000000000030 VR14:16 1111111111111111 0100 ; 297 TR14:17 0000000000000044 VR14:17 0000000000000040 0100 ; 298 TR14:18 0000000000000060 VR14:18 fffffffffffffc00 0100 ; 299 TR14:19 0000000000000064 VR14:19 0000000000000400 0100 ; 29a TR14:1a fffffffffff80000 VR14:1a 0000000000000200 0100 ; 29b TR14:1b 0000000000000014 VR14:1b 0000000000000020 0100 ; 29c TR14:1c 000000000000003e VR14:1c 0000000000000010 0100 ; 29d TR14:1d 00000000f0000000 VR14:1d 0000000000000008 0100 ; 29e TR14:1e 00000000f7800000 VR14:1e 0000000000000004 0100 ; 29f TR14:1f 0000000004000000 VR14:1f 00000000000003ff 0100 ; 2a0 TR15:00 36c936c9936c936c VR15:00 5a5a5a5a5a5a5a5a 0100 ; 2a1 TR15:01 36c936c948124812 VR15:01 a5a5a5a5a5a5a5a5 0100 ; 2a2 TR15:02 36c936c924812481 VR15:02 36c936c936c936c9 0100 ; 2a3 TR15:03 36c936c9db7edb7e VR15:03 6c936c936c936c93 0100 ; 2a4 TR15:04 36c936c9b7edb7ed VR15:04 c936c936c936c936 0100 ; 2a5 TR15:05 00000000ffffffff VR15:05 936c936c936c936c 0100 ; 2a6 TR15:06 36c936c96d926d92 VR15:06 1248124812481248 0100 ; 2a7 TR15:07 36c936c96d926d93 VR15:07 2481248124812481 0100 ; 2a8 TR15:08 36c936c991239123 VR15:08 4812481248124812 0100 ; 2a9 TR15:09 36c936c991239124 VR15:09 8124812481248124 0100 ; 2aa TR15:0a 36c936c9dc6edc6f VR15:0a 7edb7edb7edb7edb 0100 ; 2ab TR15:0b 36c936c9dc6edc6e VR15:0b edb7edb7edb7edb7 0100 ; 2ac TR15:0c 5a5a5a5a00000000 VR15:0c db7edb7edb7edb7e 0100 ; 2ad TR15:0d 5a5a5a5affffffff VR15:0d b7edb7edb7edb7ed 0100 ; 2ae TR15:0e 5a5a5a5a36c936c9 VR15:0e 5a5a5a5a5a5a5a5b 0100 ; 2af TR15:0f 5a5a5a5ac936c936 VR15:0f a5a5a5a5a5a5a5a6 0100 ; 2b0 TR15:10 5a5a5a5aa5a5a5a5 VR15:10 36c936c936c936ca 0100 ; 2b1 TR15:11 5a5a5a5a12481248 VR15:11 6c936c936c936c94 0100 ; 2b2 TR15:12 5a5a5a5a7edb7edb VR15:12 c936c936c936c937 0100 ; 2b3 TR15:13 5a5a5a5a6c936c93 VR15:13 936c936c936c936d 0100 ; 2b4 TR15:14 5a5a5a5aedb7edb7 VR15:14 5a5a5a5a5a5a5a59 0100 ; 2b5 TR15:15 5a5a5a5a81248124 VR15:15 a5a5a5a5a5a5a5a4 0100 ; 2b6 TR15:16 5a5a5a5a936c936c VR15:16 36c936c936c936c8 0100 ; 2b7 TR15:17 5a5a5a5a48124812 VR15:17 6c936c936c936c92 0100 ; 2b8 TR15:18 5a5a5a5a24812481 VR15:18 c936c936c936c935 0100 ; 2b9 TR15:19 5a5a5a5adb7edb7e VR15:19 936c936c936c936b 0100 ; 2ba TR15:1a 5a5a5a5ab7edb7ed VR15:1a 1239123912391239 0100 ; 2bb TR15:1b 5a5a5a5a6d926d92 VR15:1b 2391239123912391 0100 ; 2bc TR15:1c 5a5a5a5a6d926d93 VR15:1c 3912391239123912 0100 ; 2bd TR15:1d 5a5a5a5a91239123 VR15:1d 9123912391239123 0100 ; 2be TR15:1e 5a5a5a5a91239124 VR15:1e 1239123912391238 0100 ; 2bf TR15:1f 5a5a5a5adc6edc6f VR15:1f 2391239123912390 0100 ; 2c0 TR16:00 3912391239123911 VR16:00 3912391239123911 0100 ; 2c1 TR16:01 9123912391239124 VR16:01 9123912391239124 0100 ; 2c2 TR16:02 6edc6edc6edc6edc VR16:02 6edc6edc6edc6edc 0100 ; 2c3 TR16:03 edc6edc6edc6edc6 VR16:03 edc6edc6edc6edc6 0100 ; 2c4 TR16:04 dc6edc6edc6edc6e VR16:04 dc6edc6edc6edc6e 0100 ; 2c5 TR16:05 c6edc6edc6edc6ed VR16:05 c6edc6edc6edc6ed 0100 ; 2c6 TR16:06 6edc6edc6edc6edb VR16:06 6edc6edc6edc6edb 0100 ; 2c7 TR16:07 edc6edc6edc6edc7 VR16:07 edc6edc6edc6edc7 0100 ; 2c8 TR16:08 dc6edc6edc6edc6f VR16:08 dc6edc6edc6edc6f 0100 ; 2c9 TR16:09 c6edc6edc6edc6ee VR16:09 c6edc6edc6edc6ee 0100 ; 2ca TR16:0a b4b4b4b4b4b4b4b4 VR16:0a b4b4b4b4b4b4b4b4 0100 ; 2cb TR16:0b b4b4b4b4b4b4b4b5 VR16:0b b4b4b4b4b4b4b4b5 0100 ; 2cc TR16:0c 4b4b4b4b4b4b4b4a VR16:0c 4b4b4b4b4b4b4b4a 0100 ; 2cd TR16:0d 4b4b4b4b4b4b4b4b VR16:0d 4b4b4b4b4b4b4b4b 0100 ; 2ce TR16:0e 6d926d926d926d92 VR16:0e 6d926d926d926d92 0100 ; 2cf TR16:0f 6d926d926d926d93 VR16:0f 6d926d926d926d93 0100 ; 2d0 TR16:10 d926d926d926d926 VR16:10 d926d926d926d926 0100 ; 2d1 TR16:11 d926d926d926d927 VR16:11 d926d926d926d927 0100 ; 2d2 TR16:12 926d926d926d926c VR16:12 926d926d926d926c 0100 ; 2d3 TR16:13 926d926d926d926d VR16:13 926d926d926d926d 0100 ; 2d4 TR16:14 26d926d926d926d8 VR16:14 26d926d926d926d8 0100 ; 2d5 TR16:15 26d926d926d926d9 VR16:15 26d926d926d926d9 0100 ; 2d6 TR16:16 36c936c900000000 VR16:16 36c936c900000000 0100 ; 2d7 TR16:17 36c936c9ffffffff VR16:17 36c936c9ffffffff 0100 ; 2d8 TR16:18 36c936c95a5a5a5a VR16:18 36c936c95a5a5a5a 0100 ; 2d9 TR16:19 36c936c9c936c936 VR16:19 36c936c9c936c936 0100 ; 2da TR16:1a 36c936c9a5a5a5a5 VR16:1a 36c936c9a5a5a5a5 0100 ; 2db TR16:1b 36c936c912481248 VR16:1b 36c936c912481248 0100 ; 2dc TR16:1c 36c936c97edb7edb VR16:1c 36c936c97edb7edb 0100 ; 2dd TR16:1d 36c936c96c936c93 VR16:1d 36c936c96c936c93 0100 ; 2de TR16:1e 36c936c9edb7edb7 VR16:1e 36c936c9edb7edb7 0100 ; 2df TR16:1f 36c936c981248124 VR16:1f 36c936c981248124 0100 ; 2e0 TR17:00 5a5a5a5a5a5a5a5a VR17:00 36c936c9936c936c 0100 ; 2e1 TR17:01 a5a5a5a5a5a5a5a5 VR17:01 36c936c948124812 0100 ; 2e2 TR17:02 36c936c936c936c9 VR17:02 36c936c924812481 0100 ; 2e3 TR17:03 6c936c936c936c93 VR17:03 36c936c9db7edb7e 0100 ; 2e4 TR17:04 c936c936c936c936 VR17:04 36c936c9b7edb7ed 0100 ; 2e5 TR17:05 936c936c936c936c VR17:05 00000000ffffffff 0100 ; 2e6 TR17:06 1248124812481248 VR17:06 36c936c96d926d92 0100 ; 2e7 TR17:07 2481248124812481 VR17:07 36c936c96d926d93 0100 ; 2e8 TR17:08 4812481248124812 VR17:08 36c936c991239123 0100 ; 2e9 TR17:09 8124812481248124 VR17:09 36c936c991239124 0100 ; 2ea TR17:0a 7edb7edb7edb7edb VR17:0a 36c936c9dc6edc6f 0100 ; 2eb TR17:0b edb7edb7edb7edb7 VR17:0b 36c936c9dc6edc6e 0100 ; 2ec TR17:0c db7edb7edb7edb7e VR17:0c 5a5a5a5a00000000 0100 ; 2ed TR17:0d b7edb7edb7edb7ed VR17:0d 5a5a5a5affffffff 0100 ; 2ee TR17:0e 5a5a5a5a5a5a5a5b VR17:0e 5a5a5a5a36c936c9 0100 ; 2ef TR17:0f a5a5a5a5a5a5a5a6 VR17:0f 5a5a5a5ac936c936 0100 ; 2f0 TR17:10 36c936c936c936ca VR17:10 5a5a5a5aa5a5a5a5 0100 ; 2f1 TR17:11 6c936c936c936c94 VR17:11 5a5a5a5a12481248 0100 ; 2f2 TR17:12 c936c936c936c937 VR17:12 5a5a5a5a7edb7edb 0100 ; 2f3 TR17:13 936c936c936c936d VR17:13 5a5a5a5a6c936c93 0100 ; 2f4 TR17:14 5a5a5a5a5a5a5a59 VR17:14 5a5a5a5aedb7edb7 0100 ; 2f5 TR17:15 a5a5a5a5a5a5a5a4 VR17:15 5a5a5a5a81248124 0100 ; 2f6 TR17:16 36c936c936c936c8 VR17:16 5a5a5a5a936c936c 0100 ; 2f7 TR17:17 6c936c936c936c92 VR17:17 5a5a5a5a48124812 0100 ; 2f8 TR17:18 c936c936c936c935 VR17:18 5a5a5a5a24812481 0100 ; 2f9 TR17:19 936c936c936c936b VR17:19 5a5a5a5adb7edb7e 0100 ; 2fa TR17:1a 1239123912391239 VR17:1a 5a5a5a5ab7edb7ed 0100 ; 2fb TR17:1b 2391239123912391 VR17:1b 5a5a5a5a6d926d92 0100 ; 2fc TR17:1c 3912391239123912 VR17:1c 5a5a5a5a6d926d93 0100 ; 2fd TR17:1d 9123912391239123 VR17:1d 5a5a5a5a91239123 0100 ; 2fe TR17:1e 1239123912391238 VR17:1e 5a5a5a5a91239124 0100 ; 2ff TR17:1f 2391239123912390 VR17:1f 5a5a5a5adc6edc6f 0100 ; 300 TR18:00 0000000000000000 VR18:00 5a5a5a5adc6edc6e 0100 ; 301 TR18:01 0000000000000001 VR18:01 5a5a5a5a36c936ca 0100 ; 302 TR18:02 ffffffffffffffff VR18:02 5a5a5a5a36c936c8 0100 ; 303 TR18:03 7fffffffffffffff VR18:03 0000ffffffffffff 0100 ; 304 TR18:04 ffffffff00000000 VR18:04 00005a5a5a5a5a5a 0100 ; 305 TR18:05 00000000000003ff VR18:05 0000a5a5a5a5a5a5 0100 ; 306 TR18:06 fffffffffffffc00 VR18:06 000036c936c936c9 0100 ; 307 TR18:07 8000000000000000 VR18:07 00006c936c936c93 0100 ; 308 TR18:08 000000000000003f VR18:08 0000c936c936c936 0100 ; 309 TR18:09 000000000000ffff VR18:09 0000936c936c936c 0100 ; 30a TR18:0a 00000000001f8000 VR18:0a 000000000000fe02 0100 ; 30b TR18:0b 00000000081f8000 VR18:0b 0000000000008101 0100 ; 30c TR18:0c 000000000000007f VR18:0c 0000000080000002 0100 ; 30d TR18:0d 800000000000007f VR18:0d 0000800000020000 0100 ; 30e TR18:0e ffffffffffffff7f VR18:0e 8000000200000000 0100 ; 30f TR18:0f ffffffffffffff80 VR18:0f 36c96c93c936936c 0100 ; 310 TR18:10 0c00000000000000 VR18:10 5a5aa5a55a5aa5a5 0100 ; 311 TR18:11 0600000000000000 VR18:11 5a5aa5a5a5a55a5a 0100 ; 312 TR18:12 0500000000000000 VR18:12 000000001355ecaa 0100 ; 313 TR18:13 0000000000000500 VR18:13 000000002372dc8d 0100 ; 314 TR18:14 fffffffff0000000 VR18:14 000000002651d9ae 0100 ; 315 TR18:15 ffffffffff9f8007 VR18:15 000000003407cbf8 0100 ; 316 TR18:16 ffffffffff9f8000 VR18:16 000000004640b9bf 0100 ; 317 TR18:17 0000000000002710 VR18:17 000000004703b8fc 0100 ; 318 TR18:18 0340034003400340 VR18:18 000000005f63a09c 0100 ; 319 TR18:19 01ff000000000000 VR18:19 0000000082317dce 0100 ; 31a TR18:1a 0fff000000000000 VR18:1a 00000000fffe0001 0100 ; 31b TR18:1b 000000000000006c VR18:1b a5a5a5a536c936c9 0100 ; 31c TR18:1c 0000000000000074 VR18:1c 6c936c935a5a5a5a 0100 ; 31d TR18:1d 0000000000000038 VR18:1d c936c9365a5a5a5a 0100 ; 31e TR18:1e 0000000000000028 VR18:1e 936c936c5a5a5a5a 0100 ; 31f TR18:1f 0000000000000010 VR18:1f 0000000000000000 0100 ; 320 TR19:00 0000000000000000 VR19:00 0000000000000000 0100 ; 321 TR19:01 0000000000000000 VR19:01 0000000000000000 0100 ; 322 TR19:02 0000000000000000 VR19:02 0000000000000000 0100 ; 323 TR19:03 0000000000000000 VR19:03 0000000000000000 0100 ; 324 TR19:04 0000000000000000 VR19:04 0000000000000000 0100 ; 325 TR19:05 0000000000000000 VR19:05 0000000000000000 0100 ; 326 TR19:06 0000000000000108 VR19:06 0000000000000000 0100 ; 327 TR19:07 0000000000000110 VR19:07 0000000000000000 0100 ; 328 TR19:08 0000000000000120 VR19:08 0000000000000000 0100 ; 329 TR19:09 0000000000000128 VR19:09 0000000000000000 0100 ; 32a TR19:0a 0000000000000138 VR19:0a 0000000000000000 0100 ; 32b TR19:0b 0000000000000140 VR19:0b 0000000000000000 0100 ; 32c TR19:0c 0000000000000148 VR19:0c 0000000000000000 0100 ; 32d TR19:0d 0000000000000158 VR19:0d 5555555555555555 0100 ; 32e TR19:0e 0000000000000160 VR19:0e aaaaaaaaaaaaaaaa 0100 ; 32f TR19:0f 0000000000000170 VR19:0f 0000000000000006 0100 ; 330 TR19:10 0000000000000178 VR19:10 0000010000000000 0100 ; 331 TR19:11 0000000000000180 VR19:11 0000000000000001 0100 ; 332 TR19:12 0000000000000188 VR19:12 ffffffffffffffff 0100 ; 333 TR19:13 0000000000000190 VR19:13 00000000ffff0000 0100 ; 334 TR19:14 00000000000001a0 VR19:14 000000000000002e 0100 ; 335 TR19:15 00000000000001a8 VR19:15 000000000000001e 0100 ; 336 TR19:16 00000000000001b0 VR19:16 000000000000000e 0100 ; 337 TR19:17 00000000000001b8 VR19:17 ffffffffffff0000 0100 ; 338 TR19:18 00000000000001c0 VR19:18 ffffffff00000000 0100 ; 339 TR19:19 00000000000001c8 VR19:19 0000000000000000 0100 ; 33a TR19:1a 00000000000001d0 VR19:1a 0000000000000000 0100 ; 33b TR19:1b 00000000000001d8 VR19:1b 8000000000000000 0100 ; 33c TR19:1c 00000000000001e0 VR19:1c 7fffffffffffffff 0100 ; 33d TR19:1d 00000000000001e8 VR19:1d ffffffffefffffff 0100 ; 33e TR19:1e 00000000000001f0 VR19:1e 00000000ffffffff 0100 ; 33f TR19:1f 00000000000001f8 VR19:1f 0000000000000800 0100 ; 340 TR1a:00 0000000000000020 VR1a:00 0000000000000000 0100 ; 341 TR1a:01 fffffff111111111 VR1a:01 000000000000001f 0100 ; 342 TR1a:02 fffffff100000000 VR1a:02 000000000000001d 0100 ; 343 TR1a:03 0000000100000005 VR1a:03 000000000000001b 0100 ; 344 TR1a:04 0000000000000005 VR1a:04 0000000000000019 0100 ; 345 TR1a:05 0000000100000001 VR1a:05 0000000000000017 0100 ; 346 TR1a:06 111111111fffffff VR1a:06 0000000000000015 0100 ; 347 TR1a:07 000000001fffffff VR1a:07 0000000000000013 0100 ; 348 TR1a:08 1111111111111111 VR1a:08 0000000000000011 0100 ; 349 TR1a:09 0000000000000400 VR1a:09 000000000000000f 0100 ; 34a TR1a:0a 0000000000000200 VR1a:0a 000000000000000d 0100 ; 34b TR1a:0b 0000000000000008 VR1a:0b 000000000000000b 0100 ; 34c TR1a:0c 0000000000000100 VR1a:0c 0000000000000009 0100 ; 34d TR1a:0d 0000000000000004 VR1a:0d 0000000000000007 0100 ; 34e TR1a:0e 0000000000000003 VR1a:0e 0000000000000005 0100 ; 34f TR1a:0f 5555555555555555 VR1a:0f 0000000100000000 0100 ; 350 TR1a:10 aaaaaaaaaaaaaaaa VR1a:10 0000004000000000 0100 ; 351 TR1a:11 0004000000000000 VR1a:11 0000000000000003 0100 ; 352 TR1a:12 0000000020000000 VR1a:12 0000000000000002 0100 ; 353 TR1a:13 0000003c60000000 VR1a:13 fffffffffffffffe 0100 ; 354 TR1a:14 000000000000003f VR1a:14 0000000000000001 0100 ; 355 TR1a:15 0000000000000002 VR1a:15 0000000000000040 0100 ; 356 TR1a:16 0000000000000001 VR1a:16 000000000000003f 0100 ; 357 TR1a:17 0000000000000040 VR1a:17 0000000000000360 0100 ; 358 TR1a:18 00000000000003df VR1a:18 000000000000039f 0100 ; 359 TR1a:19 0000000000008000 VR1a:19 000000000000003e 0100 ; 35a TR1a:1a 000000000000039f VR1a:1a 000000000000007f 0100 ; 35b TR1a:1b 00000000001f8000 VR1a:1b 0000000000000080 0100 ; 35c TR1a:1c 0000000000000080 VR1a:1c ffffffffffffff00 0100 ; 35d TR1a:1d ffffffffffffe07f VR1a:1d 0000000000000100 0100 ; 35e TR1a:1e ffffffffffffffff VR1a:1e ffffffffffffffff 0100 ; 35f TR1a:1f 0000000000000000 VR1a:1f 0000000000000000 0100 ; 360 TR1b:00 0000000000000000 VR1b:00 0000000000000001 0100 ; 361 TR1b:01 0000000000000000 VR1b:01 0000000000000003 0100 ; 362 TR1b:02 0000000000000000 VR1b:02 0000000000000007 0100 ; 363 TR1b:03 0000000000000000 VR1b:03 000000000000000f 0100 ; 364 TR1b:04 0000000000000000 VR1b:04 000000000000001f 0100 ; 365 TR1b:05 0000000000000000 VR1b:05 000000000000003f 0100 ; 366 TR1b:06 0000000000000000 VR1b:06 000000000000007f 0100 ; 367 TR1b:07 0000000000000000 VR1b:07 00000000000000ff 0100 ; 368 TR1b:08 0000000000000000 VR1b:08 00000000000001ff 0100 ; 369 TR1b:09 0000000000000000 VR1b:09 00000000000003ff 0100 ; 36a TR1b:0a 0000000000000000 VR1b:0a 00000000000007ff 0100 ; 36b TR1b:0b 0000000000000000 VR1b:0b 0000000000000fff 0100 ; 36c TR1b:0c 0000000000000000 VR1b:0c 0000000000001fff 0100 ; 36d TR1b:0d 0000000000000000 VR1b:0d 0000000000003fff 0100 ; 36e TR1b:0e 0000000000000000 VR1b:0e 0000000000007fff 0100 ; 36f TR1b:0f 0000000000000000 VR1b:0f 000000000000ffff 0100 ; 370 TR1b:10 0000000000000000 VR1b:10 000000000001ffff 0100 ; 371 TR1b:11 0000000000000000 VR1b:11 000000000003ffff 0100 ; 372 TR1b:12 0000000000000000 VR1b:12 000000000007ffff 0100 ; 373 TR1b:13 0000000000000000 VR1b:13 00000000000fffff 0100 ; 374 TR1b:14 0000000000000000 VR1b:14 00000000001fffff 0100 ; 375 TR1b:15 0000000000000000 VR1b:15 00000000003fffff 0100 ; 376 TR1b:16 0000000000000000 VR1b:16 00000000007fffff 0100 ; 377 TR1b:17 0000000000000000 VR1b:17 0000000000ffffff 0100 ; 378 TR1b:18 0000000000000000 VR1b:18 0000000001ffffff 0100 ; 379 TR1b:19 0000000000000000 VR1b:19 0000000003ffffff 0100 ; 37a TR1b:1a 0000000000000000 VR1b:1a 0000000007ffffff 0100 ; 37b TR1b:1b 0000000000000000 VR1b:1b 000000000fffffff 0100 ; 37c TR1b:1c 0000000000000000 VR1b:1c 000000001fffffff 0100 ; 37d TR1b:1d 0000000000000000 VR1b:1d 000000003fffffff 0100 ; 37e TR1b:1e 0000000000000000 VR1b:1e 000000007fffffff 0100 ; 37f TR1b:1f 0000000000000000 VR1b:1f 00000000ffffffff 0100 ; 380 TR1c:00 0000000000000000 VR1c:00 00000001ffffffff 0100 ; 381 TR1c:01 0000000000000000 VR1c:01 00000003ffffffff 0100 ; 382 TR1c:02 0000000000000000 VR1c:02 00000007ffffffff 0100 ; 383 TR1c:03 0000000000000000 VR1c:03 0000000fffffffff 0100 ; 384 TR1c:04 0000000000000000 VR1c:04 0000001fffffffff 0100 ; 385 TR1c:05 0000000000000000 VR1c:05 0000003fffffffff 0100 ; 386 TR1c:06 0000000000000000 VR1c:06 0000007fffffffff 0100 ; 387 TR1c:07 0000000000000000 VR1c:07 000000ffffffffff 0100 ; 388 TR1c:08 0000000000000000 VR1c:08 000001ffffffffff 0100 ; 389 TR1c:09 0000000000000000 VR1c:09 000003ffffffffff 0100 ; 38a TR1c:0a 0000000000000000 VR1c:0a 000007ffffffffff 0100 ; 38b TR1c:0b 0000000000000000 VR1c:0b 00000fffffffffff 0100 ; 38c TR1c:0c 0000000000000000 VR1c:0c 00001fffffffffff 0100 ; 38d TR1c:0d 0000000000000000 VR1c:0d 00003fffffffffff 0100 ; 38e TR1c:0e 0000000000000000 VR1c:0e 00007fffffffffff 0100 ; 38f TR1c:0f 0000000000000000 VR1c:0f 0000ffffffffffff 0100 ; 390 TR1c:10 0000000000000000 VR1c:10 0001ffffffffffff 0100 ; 391 TR1c:11 0000000000000000 VR1c:11 0003ffffffffffff 0100 ; 392 TR1c:12 0000000000000000 VR1c:12 0007ffffffffffff 0100 ; 393 TR1c:13 0000000000000000 VR1c:13 000fffffffffffff 0100 ; 394 TR1c:14 0000000000000000 VR1c:14 001fffffffffffff 0100 ; 395 TR1c:15 0000000000000000 VR1c:15 003fffffffffffff 0100 ; 396 TR1c:16 0000000000000000 VR1c:16 007fffffffffffff 0100 ; 397 TR1c:17 0000000000000000 VR1c:17 00ffffffffffffff 0100 ; 398 TR1c:18 0000000000000000 VR1c:18 01ffffffffffffff 0100 ; 399 TR1c:19 0000000000000000 VR1c:19 03ffffffffffffff 0100 ; 39a TR1c:1a 0000000000000000 VR1c:1a 07ffffffffffffff 0100 ; 39b TR1c:1b 0000000000000000 VR1c:1b 0fffffffffffffff 0100 ; 39c TR1c:1c 0000000000000000 VR1c:1c 1fffffffffffffff 0100 ; 39d TR1c:1d 0000000000000000 VR1c:1d 3fffffffffffffff 0100 ; 39e TR1c:1e 0000000000000000 VR1c:1e 7fffffffffffffff 0100 ; 39f TR1c:1f 0000000000000000 VR1c:1f ffffffffffffffff 0100 ; 3a0 TR1d:00 0000000000000001 VR1d:00 ffffffffffffffff 0100 ; 3a1 TR1d:01 0000000000000003 VR1d:01 ffffffffffffffff 0100 ; 3a2 TR1d:02 0000000000000007 VR1d:02 ffffffffffffffff 0100 ; 3a3 TR1d:03 000000000000000f VR1d:03 ffffffffffffffff 0100 ; 3a4 TR1d:04 000000000000001f VR1d:04 ffffffffffffffff 0100 ; 3a5 TR1d:05 000000000000003f VR1d:05 ffffffffffffffff 0100 ; 3a6 TR1d:06 000000000000007f VR1d:06 ffffffffffffffff 0100 ; 3a7 TR1d:07 00000000000000ff VR1d:07 ffffffffffffffff 0100 ; 3a8 TR1d:08 00000000000001ff VR1d:08 ffffffffffffffff 0100 ; 3a9 TR1d:09 00000000000003ff VR1d:09 ffffffffffffffff 0100 ; 3aa TR1d:0a 00000000000007ff VR1d:0a ffffffffffffffff 0100 ; 3ab TR1d:0b 0000000000000fff VR1d:0b ffffffffffffffff 0100 ; 3ac TR1d:0c 0000000000001fff VR1d:0c ffffffffffffffff 0100 ; 3ad TR1d:0d 0000000000003fff VR1d:0d ffffffffffffffff 0100 ; 3ae TR1d:0e 0000000000007fff VR1d:0e ffffffffffffffff 0100 ; 3af TR1d:0f 000000000000ffff VR1d:0f ffffffffffffffff 0100 ; 3b0 TR1d:10 000000000001ffff VR1d:10 ffffffffffffffff 0100 ; 3b1 TR1d:11 000000000003ffff VR1d:11 ffffffffffffffff 0100 ; 3b2 TR1d:12 000000000007ffff VR1d:12 ffffffffffffffff 0100 ; 3b3 TR1d:13 00000000000fffff VR1d:13 ffffffffffffffff 0100 ; 3b4 TR1d:14 00000000001fffff VR1d:14 ffffffffffffffff 0100 ; 3b5 TR1d:15 00000000003fffff VR1d:15 ffffffffffffffff 0100 ; 3b6 TR1d:16 00000000007fffff VR1d:16 ffffffffffffffff 0100 ; 3b7 TR1d:17 0000000000ffffff VR1d:17 ffffffffffffffff 0100 ; 3b8 TR1d:18 0000000001ffffff VR1d:18 ffffffffffffffff 0100 ; 3b9 TR1d:19 0000000003ffffff VR1d:19 ffffffffffffffff 0100 ; 3ba TR1d:1a 0000000007ffffff VR1d:1a ffffffffffffffff 0100 ; 3bb TR1d:1b 000000000fffffff VR1d:1b ffffffffffffffff 0100 ; 3bc TR1d:1c 000000001fffffff VR1d:1c ffffffffffffffff 0100 ; 3bd TR1d:1d 000000003fffffff VR1d:1d ffffffffffffffff 0100 ; 3be TR1d:1e 000000007fffffff VR1d:1e ffffffffffffffff 0100 ; 3bf TR1d:1f 00000000ffffffff VR1d:1f ffffffffffffffff 0100 ; 3c0 TR1e:00 00000001ffffffff VR1e:00 ffffffffffffffff 0100 ; 3c1 TR1e:01 00000003ffffffff VR1e:01 ffffffffffffffff 0100 ; 3c2 TR1e:02 00000007ffffffff VR1e:02 ffffffffffffffff 0100 ; 3c3 TR1e:03 0000000fffffffff VR1e:03 ffffffffffffffff 0100 ; 3c4 TR1e:04 0000001fffffffff VR1e:04 ffffffffffffffff 0100 ; 3c5 TR1e:05 0000003fffffffff VR1e:05 ffffffffffffffff 0100 ; 3c6 TR1e:06 0000007fffffffff VR1e:06 ffffffffffffffff 0100 ; 3c7 TR1e:07 000000ffffffffff VR1e:07 ffffffffffffffff 0100 ; 3c8 TR1e:08 000001ffffffffff VR1e:08 ffffffffffffffff 0100 ; 3c9 TR1e:09 000003ffffffffff VR1e:09 ffffffffffffffff 0100 ; 3ca TR1e:0a 000007ffffffffff VR1e:0a ffffffffffffffff 0100 ; 3cb TR1e:0b 00000fffffffffff VR1e:0b ffffffffffffffff 0100 ; 3cc TR1e:0c 00001fffffffffff VR1e:0c ffffffffffffffff 0100 ; 3cd TR1e:0d 00003fffffffffff VR1e:0d ffffffffffffffff 0100 ; 3ce TR1e:0e 00007fffffffffff VR1e:0e ffffffffffffffff 0100 ; 3cf TR1e:0f 0000ffffffffffff VR1e:0f ffffffffffffffff 0100 ; 3d0 TR1e:10 0001ffffffffffff VR1e:10 ffffffffffffffff 0100 ; 3d1 TR1e:11 0003ffffffffffff VR1e:11 ffffffffffffffff 0100 ; 3d2 TR1e:12 0007ffffffffffff VR1e:12 ffffffffffffffff 0100 ; 3d3 TR1e:13 000fffffffffffff VR1e:13 ffffffffffffffff 0100 ; 3d4 TR1e:14 001fffffffffffff VR1e:14 ffffffffffffffff 0100 ; 3d5 TR1e:15 003fffffffffffff VR1e:15 ffffffffffffffff 0100 ; 3d6 TR1e:16 007fffffffffffff VR1e:16 ffffffffffffffff 0100 ; 3d7 TR1e:17 00ffffffffffffff VR1e:17 ffffffffffffffff 0100 ; 3d8 TR1e:18 01ffffffffffffff VR1e:18 ffffffffffffffff 0100 ; 3d9 TR1e:19 03ffffffffffffff VR1e:19 ffffffffffffffff 0100 ; 3da TR1e:1a 07ffffffffffffff VR1e:1a ffffffffffffffff 0100 ; 3db TR1e:1b 0fffffffffffffff VR1e:1b ffffffffffffffff 0100 ; 3dc TR1e:1c 1fffffffffffffff VR1e:1c ffffffffffffffff 0100 ; 3dd TR1e:1d 3fffffffffffffff VR1e:1d ffffffffffffffff 0100 ; 3de TR1e:1e 7fffffffffffffff VR1e:1e ffffffffffffffff 0100 ; 3df TR1e:1f ffffffffffffffff VR1e:1f ffffffffffffffff 0100 ; 3e0 TCSA0 00c80009ad06726d VCSA0 00050008574e4d20 0100 ; 3e1 TCSA1 0000000000000000 VCSA1 0000000000000000 0100 ; 3e2 TCSA2 0000000000000000 VCSA2 0000000000000000 0100 ; 3e3 TCSA3 0000000000000000 VCSA3 0000000000000000 0100 ; 3e4 TCSA4 0000000000000000 VCSA4 0000000000000000 0100 ; 3e5 TCSA5 0000000000000000 VCSA5 0000000000000000 0100 ; 3e6 TCSA6 0000000000000000 VCSA6 0000000000000000 0100 ; 3e7 TCSA7 0000000000000000 VCSA7 0000000000000000 0100 ; 3e8 TCSA8 0000000000000000 VCSA8 0000000000000000 0100 ; 3e9 TCSA9 0000000000000000 VCSA9 0000000000000000 0100 ; 3ea TCSAa 0000000000000000 VCSAa 0000000000000000 0100 ; 3eb TCSAb 0000000000000000 VCSAb 0000000000000000 0100 ; 3ec TCSAc 0000000000000000 VCSAc 0000000000000000 0100 ; 3ed TCSAd 0000000000000000 VCSAd 0000000000000000 0100 ; 3ee TCSAe 0000000000000000 VCSAe 0000000000000000 0100 ; 3ef TCSAf 0000000000000000 VCSAf 0000000000000000 0100 ; 3f0 TGP0 0000000000000000 VGP0 0000000000000000 0100 ; 3f1 TGP1 0000000000000000 VGP1 0000000000000000 0100 ; 3f2 TGP2 0000000000000000 VGP2 0000000000000000 0100 ; 3f3 TGP3 0000000000000000 VGP3 0000000000000000 0100 ; 3f4 TGP4 0000000000000000 VGP4 0000000000000000 0100 ; 3f5 TGP5 0000000000000000 VGP5 0000000000000000 0100 ; 3f6 TGP6 0000000000000000 VGP6 0000000000000000 0100 ; 3f7 TGP7 0000000000000000 VGP7 0000000000000000 0100 ; 3f8 TGP8 0000000000000000 VGP8 0000000000000000 0100 ; 3f9 TGP9 0000000000000000 VGP9 0000000000000000 0100 ; 3fa TGPa 0000000000000000 VGPa 0000000000000000 0100 ; 3fb TGPb 0000000000000000 VGPb 0000000000000000 0100 ; 3fc TGPc 0000000000000000 VGPc 0000000000000000 0100 ; 3fd TGPd 0000000000000000 VGPd 0000000000000000 0100 ; 3fe TGPe 0000000000000000 VGPe 0000000000000000 0100 ; 3ff TGPf 0000000000000000 VGPf 0000000000000000 0100 ; 0100 ; Defaults not shown: 0100 ; =================== 0100 ; dispatch_csa_free 0 0100 ; dispatch_ibuff_fill 0 0100 ; dispatch_ignore 0 0100 ; dispatch_mem_strt 4 MEMORY NOT STARTED 0100 ; dispatch_uses_tos 0 0100 ; fiu_fill_mode_src 1 0100 ; fiu_len_fill_lit 7f zero-fill 0x3f 0100 ; fiu_len_fill_reg_ctl 3 len=unchanged, fill=unchanged 0100 ; fiu_length_src 1 length_literal 0100 ; fiu_load_mdr 0 load_mdr 0100 ; fiu_load_oreg 0 load_oreg 0100 ; fiu_load_tar 0 load_tar 0100 ; fiu_load_var 0 load_var 0100 ; fiu_mem_start 19 nop_0x19 0100 ; fiu_offs_lit 00 0100 ; fiu_offset_src 1 offset_literal 0100 ; fiu_op_sel 0 extract 0100 ; fiu_oreg_src 1 merge data register 0100 ; fiu_rdata_src 1 mdr 0100 ; fiu_tivi_src 0 tar_var 0100 ; fiu_vmux_sel 2 VI 0100 ; ioc_adrbs 0 fiu 0100 ; ioc_fiubs 3 seq 0100 ; ioc_load_wdr 1 0100 ; ioc_random 0 noop 0100 ; ioc_tvbs 0 typ+val 0100 ; seq_b_timing 2 Late Condition, Hint True (or unconditional branch) 0100 ; seq_br_type 6 Continue 0100 ; seq_branch_adr 0000 0100 ; seq_cond_sel 46 SEQ.previously_latched_cond 0100 ; seq_en_micro 1 0100 ; seq_int_reads 3 TOP OF THE MICRO STACK 0100 ; seq_latch 0 0100 ; seq_lex_adr 0 0100 ; seq_random 00 ? 0100 ; typ_a_adr 00 GP00 0100 ; typ_alu_func 1f ZEROS 0100 ; typ_b_adr 00 GP00 0100 ; typ_c_adr 29 WRITE_DISABLE 0100 ; typ_c_lit 3 0100 ; typ_c_mux_sel 1 WDR 0100 ; typ_c_source 1 MUX 0100 ; typ_csa_cntl 6 NOP 0100 ; typ_frame 0 0100 ; typ_mar_cntl 0 NOP 0100 ; typ_priv_check 7 NOP 0100 ; typ_rand f INC_DEC_128 0100 ; val_a_adr 00 GP00 0100 ; val_alu_func 1f ZEROS 0100 ; val_b_adr 00 GP00 0100 ; val_c_adr 29 WRITE_DISABLE 0100 ; val_c_mux_sel 3 WDR 0100 ; val_c_source 1 MUX 0100 ; val_frame 0 0100 ; val_m_a_src 3 Bits 48…63 0100 ; val_m_b_src 3 Bits 48…63 0100 ; val_rand 0 NO_OP 0100 ; 0100 ; Early macro event: ME_STOP_MACH 0100 ; -------------------------------------------------------------------------------------- 0100 ME_STOP_MACH: 0100 0100 <halt> ; Flow R 0101 0101 <halt> ; Flow R 0102 0102 <halt> ; Flow R 0103 0103 <halt> ; Flow R 0104 0104 <halt> ; Flow R 0105 0105 <halt> ; Flow R 0106 0106 <halt> ; Flow R 0107 0107 <halt> ; Flow R 0108 ; -------------------------------------------------------------------------------------- 0108 ; Early macro event: ME_GP_TIME 0108 ; -------------------------------------------------------------------------------------- 0108 ME_GP_TIME: 0108 0108 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 26 TR19:06 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0109 0109 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 010a 010a <halt> ; Flow R 010b 010b <halt> ; Flow R 010c 010c <halt> ; Flow R 010d 010d <halt> ; Flow R 010e 010e <halt> ; Flow R 010f 010f <halt> ; Flow R 0110 ; -------------------------------------------------------------------------------------- 0110 ; Early macro event: ME_SL_TIME 0110 ; -------------------------------------------------------------------------------------- 0110 ME_SL_TIME: 0110 0110 seq_en_micro 0 typ_a_adr 27 TR19:07 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0111 0111 ioc_random a clear slice event seq_en_micro 0 0112 0112 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0113 0113 <halt> ; Flow R 0114 0114 <halt> ; Flow R 0115 0115 <halt> ; Flow R 0116 0116 <halt> ; Flow R 0117 0117 <halt> ; Flow R 0118 ; -------------------------------------------------------------------------------------- 0118 ; Early macro event: ME_SPARE1 0118 ; -------------------------------------------------------------------------------------- 0118 ME_SPARE1: 0118 0118 <halt> ; Flow R 0119 0119 <halt> ; Flow R 011a 011a <halt> ; Flow R 011b 011b <halt> ; Flow R 011c 011c <halt> ; Flow R 011d 011d <halt> ; Flow R 011e 011e <halt> ; Flow R 011f 011f <halt> ; Flow R 0120 ; -------------------------------------------------------------------------------------- 0120 ; Early macro event: ME_PACKET 0120 ; -------------------------------------------------------------------------------------- 0120 ME_PACKET: 0120 0120 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 28 TR19:08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0121 0121 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0122 0122 <halt> ; Flow R 0123 0123 <halt> ; Flow R 0124 0124 <halt> ; Flow R 0125 0125 <halt> ; Flow R 0126 0126 <halt> ; Flow R 0127 0127 <halt> ; Flow R 0128 ; -------------------------------------------------------------------------------------- 0128 ; Early macro event: ME_STATUS 0128 ; -------------------------------------------------------------------------------------- 0128 ME_STATUS: 0128 0128 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 29 TR19:09 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0129 0129 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 012a 012a <halt> ; Flow R 012b 012b <halt> ; Flow R 012c 012c <halt> ; Flow R 012d 012d <halt> ; Flow R 012e 012e <halt> ; Flow R 012f 012f <halt> ; Flow R 0130 ; -------------------------------------------------------------------------------------- 0130 ; Early macro event: ME_SPARE0 0130 ; -------------------------------------------------------------------------------------- 0130 ME_SPARE0: 0130 0130 <halt> ; Flow R 0131 0131 <halt> ; Flow R 0132 0132 <halt> ; Flow R 0133 0133 <halt> ; Flow R 0134 0134 <halt> ; Flow R 0135 0135 <halt> ; Flow R 0136 0136 <halt> ; Flow R 0137 0137 <halt> ; Flow R 0138 ; -------------------------------------------------------------------------------------- 0138 ; Early macro event: ME_REFRESH 0138 ; -------------------------------------------------------------------------------------- 0138 ME_REFRESH: 0138 0138 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 0139 0139 <default> 013a 013a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 013b 013b <halt> ; Flow R 013c 013c <halt> ; Flow R 013d 013d <halt> ; Flow R 013e 013e <halt> ; Flow R 013f 013f <halt> ; Flow R 0140 ; -------------------------------------------------------------------------------------- 0140 ; Late macro event: ML_IBUF_empty 0140 ; -------------------------------------------------------------------------------------- 0140 ML_IBUF_empty: 0140 0140 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0141 0141 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21a9 seq_br_type 5 Call True seq_branch_adr 21a9 0x21a9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 val_alu_func 13 ONES val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0142 0142 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 25 VR17:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 17 0143 0143 val_alu_func 1 A_PLUS_B val_b_adr 3b VR1a:1b val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 1a 0144 0144 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 3d VR12:1d val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 0145 ; -------------------------------------------------------------------------------------- 0145 ; Micro event: UE_MACHINE_STARTUP 0145 ; -------------------------------------------------------------------------------------- 0145 UE_MACHINE_STARTUP: 0145 0145 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21a6 seq_br_type 5 Call True seq_branch_adr 21a6 0x21a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0b GP0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0146 0146 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 55 SEQ.E_MACRO_PEND seq_int_reads 0 TYP VAL BUS seq_random 28 Load_ibuff+Load_save_offset+? typ_b_adr 0e GP0e typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 0e GP0e 0147 0147 <halt> ; Flow R 0148 ; -------------------------------------------------------------------------------------- 0148 ; Late macro event: ML_break_class 0148 ; -------------------------------------------------------------------------------------- 0148 ML_break_class: 0148 0148 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 0149 0149 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_b_adr 22 TR18:02 typ_frame 18 val_alu_func 13 ONES val_b_adr 32 VR19:12 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 19 014a 014a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 014b 014b <halt> ; Flow R 014c 014c <halt> ; Flow R 014d 014d <halt> ; Flow R 014e 014e <halt> ; Flow R 014f 014f <halt> ; Flow R 0150 ; -------------------------------------------------------------------------------------- 0150 ; Late macro event: ML_pullup 0150 ; -------------------------------------------------------------------------------------- 0150 ML_pullup: 0150 0150 <halt> ; Flow R 0151 0151 <halt> ; Flow R 0152 0152 <halt> ; Flow R 0153 0153 <halt> ; Flow R 0154 0154 <halt> ; Flow R 0155 0155 <halt> ; Flow R 0156 0156 <halt> ; Flow R 0157 0157 <halt> ; Flow R 0158 ; -------------------------------------------------------------------------------------- 0158 ; Late macro event: ML_TOS_INVLD 0158 ; -------------------------------------------------------------------------------------- 0158 ML_TOS_INVLD: 0158 0158 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b5 seq_br_type 5 Call True seq_branch_adr 21b5 0x21b5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 0159 0159 seq_en_micro 0 val_alu_func 13 ONES val_c_adr 37 GP08 val_c_mux_sel 2 ALU 015a 015a seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 015b 015b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 015c 015c <halt> ; Flow R 015d 015d <halt> ; Flow R 015e 015e <halt> ; Flow R 015f 015f <halt> ; Flow R 0160 ; -------------------------------------------------------------------------------------- 0160 ; Late macro event: ML_Resolve Reference 0160 ; -------------------------------------------------------------------------------------- 0160 ML_Resolve Reference: 0160 0160 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b3 seq_br_type 5 Call True seq_branch_adr 21b3 0x21b3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 0161 0161 seq_en_micro 0 val_alu_func 13 ONES val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0162 0162 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 09 GP09 val_b_adr 09 GP09 0163 0163 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0164 0164 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0165 0165 <halt> ; Flow R 0166 0166 <halt> ; Flow R 0167 0167 <halt> ; Flow R 0168 ; -------------------------------------------------------------------------------------- 0168 ; Late macro event: ML_SEQ_STOP 0168 ; -------------------------------------------------------------------------------------- 0168 ML_SEQ_STOP: 0168 0168 <halt> ; Flow R 0169 0169 <halt> ; Flow R 016a 016a <halt> ; Flow R 016b 016b <halt> ; Flow R 016c 016c <halt> ; Flow R 016d 016d <halt> ; Flow R 016e 016e <halt> ; Flow R 016f 016f <halt> ; Flow R 0170 ; -------------------------------------------------------------------------------------- 0170 ; Late macro event: ML_CSA_Underflow 0170 ; -------------------------------------------------------------------------------------- 0170 ML_CSA_Underflow: 0170 0170 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b2 seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 0171 0171 seq_en_micro 0 val_alu_func 13 ONES val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0172 0172 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0173 0173 <halt> ; Flow R 0174 0174 <halt> ; Flow R 0175 0175 <halt> ; Flow R 0176 0176 <halt> ; Flow R 0177 0177 <halt> ; Flow R 0178 ; -------------------------------------------------------------------------------------- 0178 ; Late macro event: ML_CSA_overflow 0178 ; -------------------------------------------------------------------------------------- 0178 ML_CSA_overflow: 0178 0178 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 0179 0179 seq_en_micro 0 val_alu_func 13 ONES val_c_adr 39 GP06 val_c_mux_sel 2 ALU 017a 017a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL 017b 017b <halt> ; Flow R 017c 017c <halt> ; Flow R 017d 017d <halt> ; Flow R 017e 017e <halt> ; Flow R 017f 017f <halt> ; Flow R 0180 ; -------------------------------------------------------------------------------------- 0180 ; Micro event: UE_MEM_EXP 0180 ; -------------------------------------------------------------------------------------- 0180 UE_MEM_EXP: 0180 0180 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 31 TR19:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0181 0181 seq_br_type a Unconditional Return; Flow R 0182 0182 <halt> ; Flow R 0183 0183 <halt> ; Flow R 0184 0184 <halt> ; Flow R 0185 0185 <halt> ; Flow R 0186 0186 <halt> ; Flow R 0187 0187 <halt> ; Flow R 0188 ; -------------------------------------------------------------------------------------- 0188 ; Micro event: UE_ECC 0188 ; -------------------------------------------------------------------------------------- 0188 UE_ECC: 0188 0188 seq_br_type 1 Branch True; Flow J cc=True 0x1601 seq_branch_adr 1601 0x1601 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_frame 5 0189 0189 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 32 TR19:12 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 018a 018a <halt> ; Flow R 018b 018b <halt> ; Flow R 018c 018c <halt> ; Flow R 018d 018d <halt> ; Flow R 018e 018e <halt> ; Flow R 018f 018f <halt> ; Flow R 0190 ; -------------------------------------------------------------------------------------- 0190 ; Micro event: UE_BKPT 0190 ; -------------------------------------------------------------------------------------- 0190 UE_BKPT: 0190 0190 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? typ_a_adr 33 TR19:13 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 0191 0191 seq_br_type a Unconditional Return; Flow R 0192 0192 <halt> ; Flow R 0193 0193 <halt> ; Flow R 0194 0194 <halt> ; Flow R 0195 0195 <halt> ; Flow R 0196 0196 <halt> ; Flow R 0197 0197 <halt> ; Flow R 0198 ; -------------------------------------------------------------------------------------- 0198 ; Micro event: UE_CHK_EXIT 0198 ; -------------------------------------------------------------------------------------- 0198 UE_CHK_EXIT: 0198 0198 <halt> ; Flow R 0199 0199 <halt> ; Flow R 019a 019a <halt> ; Flow R 019b 019b <halt> ; Flow R 019c 019c <halt> ; Flow R 019d 019d <halt> ; Flow R 019e 019e <halt> ; Flow R 019f 019f <halt> ; Flow R 01a0 ; -------------------------------------------------------------------------------------- 01a0 ; Micro event: UE_FIELD_ERROR 01a0 ; -------------------------------------------------------------------------------------- 01a0 UE_FIELD_ERROR: 01a0 01a0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 01a1 0x01a1 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 01a1 01a1 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 01a1 0x01a1 seq_random 01 Halt+? 01a2 01a2 <halt> ; Flow R 01a3 01a3 <halt> ; Flow R 01a4 01a4 <halt> ; Flow R 01a5 01a5 <halt> ; Flow R 01a6 01a6 <halt> ; Flow R 01a7 01a7 <halt> ; Flow R 01a8 ; -------------------------------------------------------------------------------------- 01a8 ; Micro event: UE_CLASS 01a8 ; -------------------------------------------------------------------------------------- 01a8 UE_CLASS: 01a8 01a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 10 NOT_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3a GP05 val_c_mux_sel 2 ALU 01a9 01a9 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 01aa 01aa seq_br_type a Unconditional Return; Flow R typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 14 01ab 01ab <halt> ; Flow R 01ac 01ac <halt> ; Flow R 01ad 01ad <halt> ; Flow R 01ae 01ae <halt> ; Flow R 01af 01af <halt> ; Flow R 01b0 ; -------------------------------------------------------------------------------------- 01b0 ; Micro event: UE_BIN_EQ 01b0 ; -------------------------------------------------------------------------------------- 01b0 UE_BIN_EQ: 01b0 01b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_frame 18 01b1 01b1 seq_br_type a Unconditional Return; Flow R typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 31 VR19:11 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 01b2 01b2 <halt> ; Flow R 01b3 01b3 <halt> ; Flow R 01b4 01b4 <halt> ; Flow R 01b5 01b5 <halt> ; Flow R 01b6 01b6 <halt> ; Flow R 01b7 01b7 <halt> ; Flow R 01b8 ; -------------------------------------------------------------------------------------- 01b8 ; Micro event: UE_BIN_OP 01b8 ; -------------------------------------------------------------------------------------- 01b8 UE_BIN_OP: 01b8 01b8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR1a:15 typ_frame 1a 01b9 01b9 seq_br_type a Unconditional Return; Flow R typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 32 VR1a:12 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 01ba 01ba <halt> ; Flow R 01bb 01bb <halt> ; Flow R 01bc 01bc <halt> ; Flow R 01bd 01bd <halt> ; Flow R 01be 01be <halt> ; Flow R 01bf 01bf <halt> ; Flow R 01c0 ; -------------------------------------------------------------------------------------- 01c0 ; Micro event: UE_TOS_OP 01c0 ; -------------------------------------------------------------------------------------- 01c0 UE_TOS_OP: 01c0 01c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR1a:0b typ_frame 1a 01c1 01c1 seq_br_type a Unconditional Return; Flow R typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3d VR14:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 01c2 01c2 <halt> ; Flow R 01c3 01c3 <halt> ; Flow R 01c4 01c4 <halt> ; Flow R 01c5 01c5 <halt> ; Flow R 01c6 01c6 <halt> ; Flow R 01c7 01c7 <halt> ; Flow R 01c8 ; -------------------------------------------------------------------------------------- 01c8 ; Micro event: UE_TOSI_OP 01c8 ; -------------------------------------------------------------------------------------- 01c8 UE_TOSI_OP: 01c8 01c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_frame 1a 01c9 01c9 seq_br_type a Unconditional Return; Flow R typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3e VR14:1e val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 01ca 01ca <halt> ; Flow R 01cb 01cb <halt> ; Flow R 01cc 01cc <halt> ; Flow R 01cd 01cd <halt> ; Flow R 01ce 01ce <halt> ; Flow R 01cf 01cf <halt> ; Flow R 01d0 ; -------------------------------------------------------------------------------------- 01d0 ; Micro event: UE_PAGE_X 01d0 ; -------------------------------------------------------------------------------------- 01d0 UE_PAGE_X: 01d0 01d0 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 01d1 01d1 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 01d2 01d2 fiu_mem_start c start_if_incmplt; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 6e INCOMPLETE_MEMORY_CYCLE_FOR_PAGE_CROSSING seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3b VR1a:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 1a 01d3 01d3 <halt> ; Flow R 01d4 01d4 <halt> ; Flow R 01d5 01d5 <halt> ; Flow R 01d6 01d6 <halt> ; Flow R 01d7 01d7 <halt> ; Flow R 01d8 ; -------------------------------------------------------------------------------------- 01d8 ; Micro event: UE_CHK_SYS 01d8 ; -------------------------------------------------------------------------------------- 01d8 UE_CHK_SYS: 01d8 01d8 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 3b TR19:1b typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 01d9 01d9 seq_br_type a Unconditional Return; Flow R 01da 01da <halt> ; Flow R 01db 01db <halt> ; Flow R 01dc 01dc <halt> ; Flow R 01dd 01dd <halt> ; Flow R 01de 01de <halt> ; Flow R 01df 01df <halt> ; Flow R 01e0 ; -------------------------------------------------------------------------------------- 01e0 ; Micro event: UE_NEW_PAK 01e0 ; -------------------------------------------------------------------------------------- 01e0 UE_NEW_PAK: 01e0 01e0 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 3c TR19:1c typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 01e1 01e1 seq_br_type a Unconditional Return; Flow R 01e2 01e2 <halt> ; Flow R 01e3 01e3 <halt> ; Flow R 01e4 01e4 <halt> ; Flow R 01e5 01e5 <halt> ; Flow R 01e6 01e6 <halt> ; Flow R 01e7 01e7 <halt> ; Flow R 01e8 ; -------------------------------------------------------------------------------------- 01e8 ; Micro event: UE_NEW_STS 01e8 ; -------------------------------------------------------------------------------------- 01e8 UE_NEW_STS: 01e8 01e8 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 3d TR19:1d typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 01e9 01e9 seq_br_type a Unconditional Return; Flow R 01ea 01ea <halt> ; Flow R 01eb 01eb <halt> ; Flow R 01ec 01ec <halt> ; Flow R 01ed 01ed <halt> ; Flow R 01ee 01ee <halt> ; Flow R 01ef 01ef <halt> ; Flow R 01f0 ; -------------------------------------------------------------------------------------- 01f0 ; Micro event: UE_XFER_CP 01f0 ; -------------------------------------------------------------------------------------- 01f0 UE_XFER_CP: 01f0 01f0 ioc_random 14 clear cpu running; Flow R seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 3e TR19:1e typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 01f1 01f1 seq_br_type a Unconditional Return; Flow R 01f2 01f2 <halt> ; Flow R 01f3 01f3 <halt> ; Flow R 01f4 01f4 <halt> ; Flow R 01f5 01f5 <halt> ; Flow R 01f6 01f6 <halt> ; Flow R 01f7 01f7 <halt> ; Flow R 01f8 ; -------------------------------------------------------------------------------------- 01f8 ; 0x0002-0x0006 Illegal - 01f8 ; 0x0009-0x000f Illegal - 01f8 ; 0x0024-0x0030 Illegal - 01f8 ; 0x0037-0x0038 Illegal - 01f8 ; 0x003f-0x0040 Illegal - 01f8 ; 0x0047-0x0048 Illegal - 01f8 ; 0x004f-0x0050 Illegal - 01f8 ; 0x0057-0x0058 Illegal - 01f8 ; 0x005f-0x0067 Illegal - 01f8 ; 0x0077-0x007f Illegal - 01f8 ; 0x0083-0x0086 Illegal - 01f8 ; 0x0094 Illegal - 01f8 ; 0x00ae-0x00b2 Illegal - 01f8 ; 0x00c0-0x00c3 Illegal - 01f8 ; 0x00df Illegal - 01f8 ; 0x0103-0x0105 Illegal - 01f8 ; 0x0108 Illegal - 01f8 ; 0x0113 Illegal - 01f8 ; 0x0130-0x0131 Illegal - 01f8 ; 0x0134-0x0135 Illegal - 01f8 ; 0x0138-0x013b Illegal - 01f8 ; 0x0150-0x015a Illegal - 01f8 ; 0x0173-0x0176 Illegal - 01f8 ; 0x0183-0x0188 Illegal - 01f8 ; 0x018c Illegal - 01f8 ; 0x0193-0x019a Illegal - 01f8 ; 0x01b3-0x01bd Illegal - 01f8 ; 0x01c8-0x01c9 Illegal - 01f8 ; 0x01e3-0x01ea Illegal - 01f8 ; 0x0203-0x0204 Illegal - 01f8 ; 0x0207 Illegal - 01f8 ; 0x0283-0x028f Illegal - 01f8 ; 0x0293-0x0298 Illegal - 01f8 ; 0x02a3 Illegal - 01f8 ; 0x02a6-0x02a7 Illegal - 01f8 ; 0x02ac-0x02af Illegal - 01f8 ; 0x02b3-0x02bd Illegal - 01f8 ; 0x02c3-0x02c5 Illegal - 01f8 ; 0x02c8 Illegal - 01f8 ; 0x02ca Illegal - 01f8 ; 0x02cc-0x02cd Illegal - 01f8 ; 0x02d3-0x02fa Illegal - 01f8 ; 0x0300-0x0302 Illegal - 01f8 ; 0x0308-0x0310 Illegal - 01f8 ; 0x0313-0x0314 Illegal - 01f8 ; 0x0317 Illegal - 01f8 ; 0x031a Illegal - 01f8 ; 0x031f Illegal - 01f8 ; 0x0323 Illegal - 01f8 ; 0x0329 Illegal - 01f8 ; 0x032c Illegal - 01f8 ; 0x032f-0x0332 Illegal - 01f8 ; 0x0338-0x033f Illegal - 01f8 ; 0x0344-0x0345 Illegal - 01f8 ; 0x034a Illegal - 01f8 ; 0x034d Illegal - 01f8 ; 0x0357 Illegal - 01f8 ; 0x035a Illegal - 01f8 ; 0x035f-0x0369 Illegal - 01f8 ; 0x0370-0x0373 Illegal - 01f8 ; 0x0375-0x0376 Illegal - 01f8 ; 0x0379 Illegal - 01f8 ; 0x037c Illegal - 01f8 ; 0x037f-0x0383 Illegal - 01f8 ; 0x0388-0x038b Illegal - 01f8 ; 0x0390-0x0394 Illegal - 01f8 ; 0x03aa Illegal - 01f8 ; 0x03af-0x03b4 Illegal - 01f8 ; 0x03c0-0x03c3 Illegal - 01f8 ; 0x03c8-0x03cb Illegal - 01f8 ; 0x03d0 Illegal - 01f8 ; 0x03d7 Illegal - 01f8 ; 0x03e2 Illegal - 01f8 ; 0x03e7 Illegal - 01f8 ; 0x03f4 Illegal - 01f8 ; 0x03ff Illegal - 01f8 ; 0x1e00-0x1fff Illegal - 01f8 ; 0x3100-0x33ff Illegal - 01f8 ; 0x3500-0x35ff Illegal - 01f8 ; 0x3900-0x3bff Illegal - 01f8 ; 0x3d00-0x3dff Illegal - 01f8 ; 0x4040-0x40ff Illegal - 01f8 ; 0x0007 Action Break_Optional 01f8 ; 0x0008 Action Idle 01f8 ; 0x0018-0x001f QQUnknown InMicrocode 01f8 ; 0x0070-0x0076 QQUnknown InMicrocode 01f8 ; 0x0080-0x0082 QQUnknown InMicrocode 01f8 ; 0x00a8-0x00ac QQUnknown InMicrocode 01f8 ; 0x0128 QQUnknown InMicrocode 01f8 ; 0x0205 QQUnknown InMicrocode 01f8 ; 0x0031 Store_Top Heap_Access,At_Offset_1 01f8 ; 0x0032 Store_Top Heap_Access,At_Offset_2 01f8 ; 0x0033 Store_Top Heap_Access,At_Offset_3 01f8 ; 0x0034 Store_Top Heap_Access,At_Offset_4 01f8 ; 0x0035 Store_Top Heap_Access,At_Offset_5 01f8 ; 0x0036 Store_Top Heap_Access,At_Offset_6 01f8 ; 0x0039 Store_Top Access,At_Offset_1 01f8 ; 0x003a Store_Top Access,At_Offset_2 01f8 ; 0x003b Store_Top Access,At_Offset_3 01f8 ; 0x003c Store_Top Access,At_Offset_4 01f8 ; 0x003d Store_Top Access,At_Offset_5 01f8 ; 0x003e Store_Top Access,At_Offset_6 01f8 ; 0x0041 Store_Top_Unchecked Float,At_Offset_1 01f8 ; 0x0042 Store_Top_Unchecked Float,At_Offset_2 01f8 ; 0x0043 Store_Top_Unchecked Float,At_Offset_3 01f8 ; 0x0044 Store_Top_Unchecked Float,At_Offset_4 01f8 ; 0x0045 Store_Top_Unchecked Float,At_Offset_5 01f8 ; 0x0046 Store_Top_Unchecked Float,At_Offset_6 01f8 ; 0x0049 Store_Top Float,At_Offset_1 01f8 ; 0x004a Store_Top Float,At_Offset_2 01f8 ; 0x004b Store_Top Float,At_Offset_3 01f8 ; 0x004c Store_Top Float,At_Offset_4 01f8 ; 0x004d Store_Top Float,At_Offset_5 01f8 ; 0x004e Store_Top Float,At_Offset_6 01f8 ; 0x0051 Store_Top_Unchecked Discrete,At_Offset_1 01f8 ; 0x0052 Store_Top_Unchecked Discrete,At_Offset_2 01f8 ; 0x0053 Store_Top_Unchecked Discrete,At_Offset_3 01f8 ; 0x0054 Store_Top_Unchecked Discrete,At_Offset_4 01f8 ; 0x0055 Store_Top_Unchecked Discrete,At_Offset_5 01f8 ; 0x0056 Store_Top_Unchecked Discrete,At_Offset_6 01f8 ; 0x0059 Store_Top Discrete,At_Offset_1 01f8 ; 0x005a Store_Top Discrete,At_Offset_2 01f8 ; 0x005b Store_Top Discrete,At_Offset_3 01f8 ; 0x005c Store_Top Discrete,At_Offset_4 01f8 ; 0x005d Store_Top Discrete,At_Offset_5 01f8 ; 0x005e Store_Top Discrete,At_Offset_6 01f8 ; 0x0068 Action Establish_Frame 01f8 ; 0x0069 Action Query_Frame 01f8 ; 0x006a Action Alter_Break_Mask 01f8 ; 0x006b Action Query_Break_Address 01f8 ; 0x006c Action Query_Break_Mask 01f8 ; 0x006d Action Query_Break_Cause 01f8 ; 0x006e Action Exit_Break 01f8 ; 0x006f Action Break_Unconditional 01f8 ; 0x0087 Execute Discrete,Diana_Spare2 01f8 ; 0x0088 Execute Heap_Access,Diana_Spare2 01f8 ; 0x0089 Execute Discrete,Diana_Spare1 01f8 ; 0x008a Execute Discrete,Diana_Spare0 01f8 ; 0x008b Execute Heap_Access,Diana_Seq_Type_Get_Head 01f8 ; 0x008c Execute Heap_Access,Diana_Put_Node_On_Seq_Type 01f8 ; 0x008d Execute Heap_Access,Diana_Allocate_Tree_Node 01f8 ; 0x008e Execute Discrete,Diana_Arity_For_Kind 01f8 ; 0x008f Execute Discrete,Diana_Map_Kind_To_Vci 01f8 ; 0x0090 Action Store_String_Extended,pse 01f8 ; 0x0091 Action Push_String_Extended_Indexed,pse 01f8 ; 0x0092 Action Push_String_Extended,pse 01f8 ; 0x0093 PushFullAddress InMicrocode,caddr 01f8 ; 0x0095 Execute Package,Field_Reference_Dynamic 01f8 ; 0x0096 Execute Package,Field_Execute_Dynamic 01f8 ; 0x0097 Execute Package,Field_Write_Dynamic 01f8 ; 0x0098 Execute Package,Field_Read_Dynamic 01f8 ; 0x0099 Action Reference_Dynamic 01f8 ; 0x009a Action Call_Dynamic 01f8 ; 0x009b Action Store_Dynamic 01f8 ; 0x009c Action Load_Dynamic 01f8 ; 0x009d Action Jump_Nonzero_Dynamic 01f8 ; 0x009e Action Jump_Zero_Dynamic 01f8 ; 0x009f Action Jump_Dynamic 01f8 ; 0x00a0 Action Push_Structure_Extended,abs,mark 01f8 ; 0x00a1 Action Push_Float_Extended 01f8 ; 0x00a2 Action Push_Discrete_Extended 01f8 ; 0x00a3 Action Loop_Decreasing_Extended,abs,>JC 01f8 ; 0x00a4 Action Loop_Increasing_Extended,abs,>JC 01f8 ; 0x00a5 Action Jump_Nonzero_Extended,abs,>JC 01f8 ; 0x00a6 Action Jump_Zero_Extended,abs,>JC 01f8 ; 0x00a7 Action Jump_Extended,abs,>J 01f8 ; 0x00ad Action InMicrocode,Package,Field_Execute_Dynamic 01f8 ; 0x00b3 Action Increase_Priority 01f8 ; 0x00b4 Action Name_Partner 01f8 ; 0x00b5 Action Make_Parent 01f8 ; 0x00b6 Action Make_Scope 01f8 ; 0x00b7 Action Make_Self 01f8 ; 0x00b8 Action Set_Priority 01f8 ; 0x00b9 Action Get_Priority 01f8 ; 0x00ba Action Initiate_Delay 01f8 ; 0x00bb Action Signal_Completion,>R 01f8 ; 0x00bc Action Signal_Activated 01f8 ; 0x00bd Action Activate_Heap_Tasks 01f8 ; 0x00be Action Activate_Tasks 01f8 ; 0x00bf Action Accept_Activation 01f8 ; 0x00c4 Action Make_Default 01f8 ; 0x00c5 Action Set_Block_Start 01f8 ; 0x00c6 Action Check_Subprogram_Elaborated 01f8 ; 0x00c7 Action Elaborate_Subprogram 01f8 ; 0x00c8 Action Pop_Auxiliary_Range 01f8 ; 0x00c9 Action Pop_Auxiliary_Loop 01f8 ; 0x00ca Action Exit_Nullary_Function,>R 01f8 ; 0x00cb Action Pop_Block_With_Result 01f8 ; 0x00cc Action Pop_Block 01f8 ; 0x00cd Action Spare6_Action 01f8 ; 0x00ce Action Pop_Auxiliary 01f8 ; 0x00cf Action Mark_Auxiliary 01f8 ; 0x00d0 Action Swap_Control 01f8 ; 0x00d1 Pop_Control Pop_Count_1 01f8 ; 0x00d2 Pop_Control Pop_Count_2 01f8 ; 0x00d3 Pop_Control Pop_Count_3 01f8 ; 0x00d4 Pop_Control Pop_Count_4 01f8 ; 0x00d5 Pop_Control Pop_Count_5 01f8 ; 0x00d6 Pop_Control Pop_Count_6 01f8 ; 0x00d7 Pop_Control Pop_Count_7 01f8 ; 0x00d8 Load_Top At_Offset_0 01f8 ; 0x00d9 Load_Top At_Offset_1 01f8 ; 0x00da Load_Top At_Offset_2 01f8 ; 0x00db Load_Top At_Offset_3 01f8 ; 0x00dc Load_Top At_Offset_4 01f8 ; 0x00dd Load_Top At_Offset_5 01f8 ; 0x00de Load_Top At_Offset_6 01f8 ; 0x00e0-0x00ff Load_Encached eon 01f8 ; 0x0106 Execute Exception,Address 01f8 ; 0x0107 Execute Exception,Get_Name 01f8 ; 0x0109 Execute Exception,Is_Instruction_Error 01f8 ; 0x010a Execute Exception,Is_Tasking_Error 01f8 ; 0x010b Execute Exception,Is_Storage_Error 01f8 ; 0x010c Execute Exception,Is_Program_Error 01f8 ; 0x010d Execute Exception,Is_Numeric_Error 01f8 ; 0x010e Execute Exception,Is_Constraint_Error 01f8 ; 0x010f Execute Exception,Equal 01f8 ; 0x0114 Execute Access,Size 01f8 ; 0x0115 Execute Any,Structure_Clear 01f8 ; 0x0116 Execute Any,Address_Of_Type 01f8 ; 0x0117 Execute Any,Structure_Query 01f8 ; 0x0118 Execute Any,Write_Unchecked 01f8 ; 0x0119 Execute Any,Check_In_Formal_Type 01f8 ; 0x011a Execute Any,Not_In_Type 01f8 ; 0x011b Execute Any,In_Type 01f8 ; 0x011c Execute Any,Convert_Unchecked 01f8 ; 0x011d Execute Any,Convert_To_Formal 01f8 ; 0x011e Execute Any,Convert 01f8 ; 0x011f Execute Any,Is_Scalar 01f8 ; 0x0123 Execute Any,Make_Aligned 01f8 ; 0x0124 Execute Any,Is_Constrained 01f8 ; 0x0125 Execute Any,Set_Constraint 01f8 ; 0x0126 Execute Any,Has_Default_Initialization 01f8 ; 0x0127 Execute Any,Run_Initialization_Utility 01f8 ; 0x0129 Execute Any,Make_Visible 01f8 ; 0x012a Execute Any,Change_Utility 01f8 ; 0x012b Execute Any,Spare14 01f8 ; 0x012c Execute Any,Size 01f8 ; 0x012d Execute Any,Address 01f8 ; 0x012e Execute Any,Not_Equal 01f8 ; 0x012f Execute Any,Equal 01f8 ; 0x0132 Execute Family,Count 01f8 ; 0x0133 Execute Family,Rendezvous 01f8 ; 0x0136 Execute Entry,Count 01f8 ; 0x0137 Execute Entry,Rendezvous 01f8 ; 0x013c Execute Select,Terminate_Guard_Write 01f8 ; 0x013d Execute Select,Timed_Duration_Write 01f8 ; 0x013e Execute Select,Timed_Guard_Write 01f8 ; 0x013f Execute Select,Rendezvous 01f8 ; 0x0140 Execute Discrete,Divide_And_Scale 01f8 ; 0x0141 Execute Discrete,Multiply_And_Scale 01f8 ; 0x0142 Execute Heap_Access,Diana_Find_Permanent_Attribute 01f8 ; 0x0143 Execute Heap_Access,Adaptive_Balanced_Tree_Lookup 01f8 ; 0x0144 Execute Heap_Access,Get_Name 01f8 ; 0x0145 Execute Heap_Access,Diana_Tree_Kind 01f8 ; 0x0146 Execute Heap_Access,Hash 01f8 ; 0x0147 Execute Heap_Access,Construct_Segment 01f8 ; 0x0148 Execute Heap_Access,Get_Offset 01f8 ; 0x0149 Execute Float,Less_Equal_Zero 01f8 ; 0x014a Execute Float,Greater_Equal_Zero 01f8 ; 0x014b Execute Float,Less_Zero 01f8 ; 0x014c Execute Float,Greater_Zero 01f8 ; 0x014d Execute Float,Not_Equal_Zero 01f8 ; 0x014e Execute Float,Equal_Zero 01f8 ; 0x014f Execute Float,Not_In_Range 01f8 ; 0x015b Execute Variant_Record,Make_Constrained 01f8 ; 0x015c Execute Variant_Record,Is_Constrained_Object 01f8 ; 0x015d Execute Variant_Record,Field_Type_Dynamic 01f8 ; 0x015e Execute Variant_Record,Field_Reference_Dynamic 01f8 ; 0x015f Execute Variant_Record,Field_Write_Dynamic 01f8 ; 0x0160 Execute Variant_Record,Field_Read_Dynamic 01f8 ; 0x0161 Execute Variant_Record,Check_In_Formal_Type 01f8 ; 0x0162 Execute Variant_Record,Check_In_Type 01f8 ; 0x0163 Execute Variant_Record,Not_In_Type 01f8 ; 0x0164 Execute Variant_Record,In_Type 01f8 ; 0x0165 Execute Variant_Record,Convert 01f8 ; 0x0166 Execute Variant_Record,Component_Offset 01f8 ; 0x0167 Execute Variant_Record,Structure_Query 01f8 ; 0x0168 Execute Variant_Record,Reference_Makes_Copy 01f8 ; 0x0169 Execute Variant_Record,Read_Discriminant_Constraint 01f8 ; 0x016a Execute Variant_Record,Indirects_Appended 01f8 ; 0x016b Execute Variant_Record,Read_Variant 01f8 ; 0x016c Execute Variant_Record,Is_Constrained 01f8 ; 0x016d Execute Variant_Record,Structure_Write 01f8 ; 0x016e Execute Variant_Record,Not_Equal 01f8 ; 0x016f Execute Variant_Record,Equal 01f8 ; 0x0177 Execute Record,Field_Type_Dynamic 01f8 ; 0x0178 Execute Record,Field_Reference_Dynamic 01f8 ; 0x0179 Execute Record,Field_Write_Dynamic 01f8 ; 0x017a Execute Record,Field_Read_Dynamic 01f8 ; 0x017b Execute Record,Convert 01f8 ; 0x017c Execute Record,Component_Offset 01f8 ; 0x017d Execute Record,Structure_Write 01f8 ; 0x017e Execute Record,Not_Equal 01f8 ; 0x017f Execute Record,Equal 01f8 ; 0x0189 Execute Subvector,Field_Reference 01f8 ; 0x018a Execute Subvector,Field_Write 01f8 ; 0x018b Execute Subvector,Field_Read 01f8 ; 0x018d Execute Subarray,Field_Reference 01f8 ; 0x018e Execute Subarray,Field_Write 01f8 ; 0x018f Execute Subarray,Field_Read 01f8 ; 0x019b Execute Matrix,Check_In_Type 01f8 ; 0x019c Execute Matrix,Not_In_Type 01f8 ; 0x019d Execute Matrix,In_Type 01f8 ; 0x019e Execute Matrix,Convert_To_Formal 01f8 ; 0x019f Execute Matrix,Convert 01f8 ; 0x01a3 Execute Matrix,Subarray 01f8 ; 0x01a4 Execute Matrix,Structure_Write 01f8 ; 0x01a5 Execute Matrix,Field_Reference 01f8 ; 0x01a6 Execute Matrix,Field_Write 01f8 ; 0x01a7 Execute Matrix,Field_Read 01f8 ; 0x01a8 Execute Matrix,Element_Type 01f8 ; 0x01a9 Execute Matrix,Reverse_Bounds 01f8 ; 0x01aa Execute Matrix,Bounds 01f8 ; 0x01ab Execute Matrix,Length 01f8 ; 0x01ac Execute Matrix,Last 01f8 ; 0x01ad Execute Matrix,First 01f8 ; 0x01ae Execute Matrix,Not_Equal 01f8 ; 0x01af Execute Matrix,Equal 01f8 ; 0x01be Execute Vector,Hash 01f8 ; 0x01bf Execute Vector,Less_Equal 01f8 ; 0x01c3 Execute Vector,Check_In_Type 01f8 ; 0x01c4 Execute Vector,Not_In_Type 01f8 ; 0x01c5 Execute Vector,In_Type 01f8 ; 0x01c6 Execute Vector,Convert_To_Formal 01f8 ; 0x01c7 Execute Vector,Convert 01f8 ; 0x01ca Execute Vector,Prepend 01f8 ; 0x01cb Execute Vector,Append 01f8 ; 0x01cc Execute Vector,Catenate 01f8 ; 0x01cd Execute Vector,Slice_Reference 01f8 ; 0x01ce Execute Vector,Slice_Write 01f8 ; 0x01cf Execute Vector,Slice_Read 01f8 ; 0x01d3 Execute Vector,And 01f8 ; 0x01d4 Execute Vector,Structure_Write 01f8 ; 0x01d5 Execute Vector,Field_Reference 01f8 ; 0x01d6 Execute Vector,Field_Write 01f8 ; 0x01d7 Execute Vector,Field_Read 01f8 ; 0x01d8 Execute Vector,Element_Type 01f8 ; 0x01d9 Execute Vector,Reverse_Bounds 01f8 ; 0x01da Execute Vector,Bounds 01f8 ; 0x01db Execute Vector,Length 01f8 ; 0x01dc Execute Vector,Last 01f8 ; 0x01dd Execute Vector,First 01f8 ; 0x01de Execute Vector,Not_Equal 01f8 ; 0x01df Execute Vector,Equal 01f8 ; 0x01eb Execute Array,Check_In_Type 01f8 ; 0x01ec Execute Array,Not_In_Type 01f8 ; 0x01ed Execute Array,In_Type 01f8 ; 0x01ee Execute Array,Convert_To_Formal 01f8 ; 0x01ef Execute Array,Convert 01f8 ; 0x01f3 Execute Array,Subarray 01f8 ; 0x01f4 Execute Array,Structure_Write 01f8 ; 0x01f5 Execute Array,Field_Reference 01f8 ; 0x01f6 Execute Array,Field_Write 01f8 ; 0x01f7 Execute Array,Field_Read 01f8 ; 0x01f8 Execute Array,Element_Type 01f8 ; 0x01f9 Execute Array,Reverse_Bounds 01f8 ; 0x01fa Execute Array,Bounds 01f8 ; 0x01fb Execute Array,Length 01f8 ; 0x01fc Execute Array,Last 01f8 ; 0x01fd Execute Array,First 01f8 ; 0x01fe Execute Array,Not_Equal 01f8 ; 0x01ff Execute Array,Equal 01f8 ; 0x0206 Execute Module,Check_Elaborated 01f8 ; 0x0208 Execute Task,Abort_Multiple 01f8 ; 0x0209 Execute Task,Abort 01f8 ; 0x020a Execute Module,Get_Name 01f8 ; 0x020b Execute Module,Is_Terminated 01f8 ; 0x020c Execute Module,Is_Callable 01f8 ; 0x020d Execute Module,Elaborate 01f8 ; 0x020e Execute Module,Augment_Imports 01f8 ; 0x020f Execute Module,Activate 01f8 ; 0x0213 Execute Heap_Access,Check_In_Type 01f8 ; 0x0214 Execute Heap_Access,Not_In_Type 01f8 ; 0x0215 Execute Heap_Access,In_Type 01f8 ; 0x0216 Execute Heap_Access,Convert 01f8 ; 0x0217 Execute Heap_Access,All_Reference 01f8 ; 0x0218 Execute Heap_Access,All_Write 01f8 ; 0x0219 Execute Heap_Access,All_Read 01f8 ; 0x021a Execute Heap_Access,Element_Type 01f8 ; 0x021b Execute Heap_Access,Set_Null 01f8 ; 0x021c Execute Heap_Access,Not_Null 01f8 ; 0x021d Execute Heap_Access,Is_Null 01f8 ; 0x021e Execute Heap_Access,Maximum 01f8 ; 0x021f Execute Heap_Access,Equal 01f8 ; 0x0220 Execute Access,Deallocate 01f8 ; 0x0221 Execute Access,Allow_Deallocate 01f8 ; 0x0222 Execute Access,Convert_Reference 01f8 ; 0x0223 Execute Access,Check_In_Type 01f8 ; 0x0224 Execute Access,Not_In_Type 01f8 ; 0x0225 Execute Access,In_Type 01f8 ; 0x0226 Execute Access,Convert 01f8 ; 0x0227 Execute Access,All_Reference 01f8 ; 0x0228 Execute Access,All_Write 01f8 ; 0x0229 Execute Access,All_Read 01f8 ; 0x022a Execute Access,Element_Type 01f8 ; 0x022b Execute Access,Set_Null 01f8 ; 0x022c Execute Access,Not_Null 01f8 ; 0x022d Execute Access,Is_Null 01f8 ; 0x022e Execute Access,Not_Equal 01f8 ; 0x022f Execute Access,Equal 01f8 ; 0x0230 Execute Float,In_Range 01f8 ; 0x0231 Execute Float,Write_Unchecked 01f8 ; 0x0232 Execute Float,Check_In_Type 01f8 ; 0x0233 Execute Float,Not_In_Type 01f8 ; 0x0234 Execute Float,In_Type 01f8 ; 0x0235 Execute Float,Round_To_Discrete 01f8 ; 0x0236 Execute Float,Truncate_To_Discrete 01f8 ; 0x0237 Execute Float,Convert_From_Discrete 01f8 ; 0x0238 Execute Float,Convert 01f8 ; 0x0239 Execute Float,Exponentiate 01f8 ; 0x023a Execute Float,Divide 01f8 ; 0x023b Execute Float,Times 01f8 ; 0x023c Execute Float,Minus 01f8 ; 0x023d Execute Float,Plus 01f8 ; 0x023e Execute Float,Absolute_Value 01f8 ; 0x023f Execute Float,Unary_Minus 01f8 ; 0x0240 Execute Float,Last 01f8 ; 0x0241 Execute Float,First 01f8 ; 0x0242 Execute Float,Less_Equal 01f8 ; 0x0243 Execute Float,Greater_Equal 01f8 ; 0x0244 Execute Float,Less 01f8 ; 0x0245 Execute Float,Greater 01f8 ; 0x0246 Execute Float,Not_Equal 01f8 ; 0x0247 Execute Float,Equal 01f8 ; 0x0248 Execute Discrete,Check_In_Integer 01f8 ; 0x0249 Execute Discrete,Case_In_Range 01f8 ; 0x024a Execute Discrete,Is_Unsigned 01f8 ; 0x024b Execute Discrete,Count_Trailing_Zeros 01f8 ; 0x024c Execute Discrete,Count_Leading_Zeros 01f8 ; 0x024d Execute Discrete,Count_Nonzero_Bits 01f8 ; 0x024e Execute Discrete,Extract_Bits 01f8 ; 0x024f Execute Discrete,Insert_Bits 01f8 ; 0x0250 Execute Discrete,Rotate 01f8 ; 0x0251 Execute Discrete,Logical_Shift 01f8 ; 0x0252 Execute Discrete,Arithmetic_Shift 01f8 ; 0x0253 Execute Discrete,Binary_Scale 01f8 ; 0x0254 Execute Discrete,Partial_Minus 01f8 ; 0x0255 Execute Discrete,Partial_Plus 01f8 ; 0x0256 Execute Discrete,Instruction_Read 01f8 ; 0x0257 Execute Discrete,Raise,>R 01f8 ; 0x0258 Execute Discrete,Test_And_Set_Next 01f8 ; 0x0259 Execute Discrete,Test_And_Set_Previous 01f8 ; 0x025a Execute Discrete,Write_Unchecked 01f8 ; 0x025b Execute Discrete,Check_In_Type 01f8 ; 0x025c Execute Discrete,ReverseBounds_Check 01f8 ; 0x025d Execute Discrete,Bounds_Check 01f8 ; 0x025e Execute Discrete,Convert 01f8 ; 0x025f Execute Discrete,Not_In_Type 01f8 ; 0x0263 Execute Discrete,Above_Bound 01f8 ; 0x0264 Execute Discrete,Below_Bound 01f8 ; 0x0265 Execute Discrete,Reverse_Bounds 01f8 ; 0x0266 Execute Discrete,Bounds 01f8 ; 0x0267 Execute Discrete,Predecessor 01f8 ; 0x0268 Execute Discrete,Successor 01f8 ; 0x0269 Execute Discrete,Last 01f8 ; 0x026a Execute Discrete,First 01f8 ; 0x026b Execute Discrete,Maximum 01f8 ; 0x026c Execute Discrete,Minimum 01f8 ; 0x026d Execute Discrete,Exponentiate 01f8 ; 0x026e Execute Discrete,Modulo 01f8 ; 0x026f Execute Discrete,Remainder 01f8 ; 0x0273 Execute Discrete,Plus 01f8 ; 0x0274 Execute Discrete,Absolute_Value 01f8 ; 0x0275 Execute Discrete,Unary_Minus 01f8 ; 0x0276 Execute Discrete,Complement 01f8 ; 0x0277 Execute Discrete,Xor 01f8 ; 0x0278 Execute Discrete,Or 01f8 ; 0x0279 Execute Discrete,And 01f8 ; 0x027a Execute Discrete,Less_Equal 01f8 ; 0x027b Execute Discrete,Greater_Equal 01f8 ; 0x027c Execute Discrete,Less 01f8 ; 0x027d Execute Discrete,Greater 01f8 ; 0x027e Execute Discrete,Not_Equal 01f8 ; 0x027f Execute Discrete,Equal 01f8 ; 0x0299 Declare_Subprogram For_Accept,subp 01f8 ; 0x029a Declare_Subprogram For_Outer_Call,Visible,Unelaborated,subp 01f8 ; 0x029b Declare_Subprogram For_Outer_Call,Unelaborated,subp 01f8 ; 0x029c Declare_Subprogram For_Outer_Call,Visible,subp 01f8 ; 0x029d Declare_Subprogram For_Outer_Call,subp 01f8 ; 0x029e Declare_Subprogram For_Call,Unelaborated,subp 01f8 ; 0x029f Declare_Subprogram For_Call,subp 01f8 ; 0x02a4 Declare_Subprogram For_Outer_Call,Visible,With_Address 01f8 ; 0x02a5 Declare_Subprogram For_Outer_Call,With_Address 01f8 ; 0x02a8 Declare_Subprogram For_Call,Visible,Unelaborated,With_Address 01f8 ; 0x02a9 Declare_Subprogram For_Call,Unelaborated,With_Address 01f8 ; 0x02aa Declare_Subprogram For_Call,Visible,With_Address 01f8 ; 0x02ab Declare_Subprogram For_Call,With_Address 01f8 ; 0x02be Declare_Variable Float,Visible,With_Value,With_Constraint 01f8 ; 0x02bf Declare_Variable Float,With_Value,With_Constraint 01f8 ; 0x02c6 Declare_Variable Any,Visible 01f8 ; 0x02c7 Declare_Variable Any 01f8 ; 0x02c9 Declare_Variable Family 01f8 ; 0x02cb Declare_Variable Entry 01f8 ; 0x02ce Declare_Variable Select,Choice_Open 01f8 ; 0x02cf Declare_Variable Select 01f8 ; 0x02fb Declare_Variable Variant_Record,Visible,With_Constraint 01f8 ; 0x02fc Declare_Variable Variant_Record,With_Constraint 01f8 ; 0x02fd Declare_Variable Variant_Record,Duplicate 01f8 ; 0x02fe Declare_Variable Variant_Record,Visible 01f8 ; 0x02ff Declare_Variable Variant_Record 01f8 ; 0x0303 Complete_Type Variant_Record,By_Component_Completion 01f8 ; 0x0304 Complete_Type Variant_Record,By_Completing_Constraint 01f8 ; 0x0305 Complete_Type Variant_Record,By_Constraining_Incomplete 01f8 ; 0x0306 Complete_Type Variant_Record,By_Renaming 01f8 ; 0x0307 Complete_Type Variant_Record,By_Defining 01f8 ; 0x0311 Declare_Type Variant_Record,Constrained_Incomplete 01f8 ; 0x0312 Declare_Type Variant_Record,Constrained_Incomplete,Visible 01f8 ; 0x0315 Declare_Type Variant_Record,Defined_Incomplete 01f8 ; 0x0316 Declare_Type Variant_Record,Defined_Incomplete,Visible 01f8 ; 0x0318 Declare_Type Variant_Record,Incomplete 01f8 ; 0x0319 Declare_Type Variant_Record,Incomplete,Visible 01f8 ; 0x031b Declare_Type Variant_Record,Constrained 01f8 ; 0x031c Declare_Type Variant_Record,Constrained,Visible 01f8 ; 0x031d Declare_Type Variant_Record,Defined 01f8 ; 0x031e Declare_Type Variant_Record,Defined,Visible 01f8 ; 0x0320 Declare_Variable Record,Duplicate 01f8 ; 0x0321 Declare_Variable Record,Visible 01f8 ; 0x0322 Declare_Variable Record 01f8 ; 0x0324 Complete_Type Record,By_Component_Completion 01f8 ; 0x0325 Complete_Type Record,By_Renaming 01f8 ; 0x0326 Complete_Type Record,By_Defining 01f8 ; 0x0327 Declare_Type Record,Defined_Incomplete 01f8 ; 0x0328 Declare_Type Record,Defined_Incomplete,Visible 01f8 ; 0x032a Declare_Type Record,Incomplete 01f8 ; 0x032b Declare_Type Record,Incomplete,Visible 01f8 ; 0x032d Declare_Type Record,Defined 01f8 ; 0x032e Declare_Type Record,Defined,Visible 01f8 ; 0x0333 Declare_Variable Array,Visible,With_Constraint 01f8 ; 0x0334 Declare_Variable Array,With_Constraint 01f8 ; 0x0335 Declare_Variable Array,Duplicate 01f8 ; 0x0336 Declare_Variable Array,Visible 01f8 ; 0x0337 Declare_Variable Array 01f8 ; 0x0340 Complete_Type Array,By_Component_Completion 01f8 ; 0x0341 Complete_Type Array,By_Constraining 01f8 ; 0x0342 Complete_Type Array,By_Renaming 01f8 ; 0x0343 Complete_Type Array,By_Defining 01f8 ; 0x0346 Declare_Type Array,Constrained_Incomplete,Bounds_With_Object 01f8 ; 0x0347 Declare_Type Array,Constrained_Incomplete,Visible,Bounds_With_Object 01f8 ; 0x0348 Declare_Type Array,Defined_Incomplete,Bounds_With_Object 01f8 ; 0x0349 Declare_Type Array,Defined_Incomplete,Visible,Bounds_With_Object 01f8 ; 0x034b Declare_Type Array,Incomplete,Bounds_With_Object 01f8 ; 0x034c Declare_Type Array,Incomplete,Visible,Bounds_With_Object 01f8 ; 0x034e Declare_Type Array,Constrained,Bounds_With_Object 01f8 ; 0x034f Declare_Type Array,Constrained,Visible,Bounds_With_Object 01f8 ; 0x0353 Declare_Type Array,Constrained_Incomplete 01f8 ; 0x0354 Declare_Type Array,Constrained_Incomplete,Visible 01f8 ; 0x0355 Declare_Type Array,Defined_Incomplete 01f8 ; 0x0356 Declare_Type Array,Defined_Incomplete,Visible 01f8 ; 0x0358 Declare_Type Array,Incomplete 01f8 ; 0x0359 Declare_Type Array,Incomplete,Visible 01f8 ; 0x035b Declare_Type Array,Constrained 01f8 ; 0x035c Declare_Type Array,Constrained,Visible 01f8 ; 0x035d Declare_Type Array,Defined 01f8 ; 0x035e Declare_Type Array,Defined,Visible 01f8 ; 0x036a Declare_Variable Task,On_Processor,As_Component 01f8 ; 0x036b Declare_Variable Task,As_Component 01f8 ; 0x036c Declare_Variable Task,Visible,On_Processor 01f8 ; 0x036d Declare_Variable Task,On_Processor 01f8 ; 0x036e Declare_Variable Task,Visible 01f8 ; 0x036f Declare_Variable Task 01f8 ; 0x0374 Complete_Type Task,By_Renaming 01f8 ; 0x0377 Declare_Type Task,Incomplete 01f8 ; 0x0378 Declare_Type Task,Incomplete,Visible 01f8 ; 0x037a Declare_Type Task,Defined,Not_Elaborated 01f8 ; 0x037b Declare_Type Task,Defined,Visible,Not_Elaborated 01f8 ; 0x037d Declare_Type Task,Defined 01f8 ; 0x037e Declare_Type Task,Defined,Visible 01f8 ; 0x0384 Declare_Variable Package,Visible,On_Processor 01f8 ; 0x0385 Declare_Variable Package,On_Processor 01f8 ; 0x0386 Declare_Variable Package,Visible 01f8 ; 0x0387 Declare_Variable Package 01f8 ; 0x038c Declare_Type Package,Defined,Not_Elaborated 01f8 ; 0x038d Declare_Type Package,Defined,Visible,Not_Elaborated 01f8 ; 0x038e Declare_Type Package,Defined 01f8 ; 0x038f Declare_Type Package,Defined,Visible 01f8 ; 0x0395 Declare_Variable Heap_Access,Visible,By_Allocation,With_Value 01f8 ; 0x0396 Declare_Variable Heap_Access,By_Allocation,With_Value 01f8 ; 0x0397 Declare_Variable Heap_Access,Visible,By_Allocation,With_Subtype 01f8 ; 0x0398 Declare_Variable Heap_Access,By_Allocation,With_Subtype 01f8 ; 0x0399 Declare_Variable Heap_Access,Visible,By_Allocation,With_Constraint 01f8 ; 0x039a Declare_Variable Heap_Access,By_Allocation,With_Constraint 01f8 ; 0x039b Declare_Variable Heap_Access,Visible,By_Allocation 01f8 ; 0x039c Declare_Variable Heap_Access,By_Allocation 01f8 ; 0x039d Declare_Variable Heap_Access,Duplicate 01f8 ; 0x039e Declare_Variable Heap_Access,Visible 01f8 ; 0x039f Declare_Variable Heap_Access 01f8 ; 0x03a0 Complete_Type Heap_Access,By_Component_Completion 01f8 ; 0x03a1 Complete_Type Heap_Access,By_Constraining 01f8 ; 0x03a2 Complete_Type Heap_Access,By_Renaming 01f8 ; 0x03a3 Complete_Type Heap_Access,By_Defining 01f8 ; 0x03a4 Declare_Type Heap_Access,Incomplete,Values_Relative,With_Size 01f8 ; 0x03a5 Declare_Type Heap_Access,Incomplete,Values_Relative 01f8 ; 0x03a6 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative 01f8 ; 0x03a7 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative,With_Size 01f8 ; 0x03a8 Declare_Type Heap_Access,Incomplete 01f8 ; 0x03a9 Declare_Type Heap_Access,Incomplete,Visible 01f8 ; 0x03ab Declare_Type Heap_Access,Constrained 01f8 ; 0x03ac Declare_Type Heap_Access,Constrained,Visible 01f8 ; 0x03ad Declare_Type Heap_Access,Defined 01f8 ; 0x03ae Declare_Type Heap_Access,Defined,Visible 01f8 ; 0x03b5 Declare_Variable Access,Visible,By_Allocation,With_Value 01f8 ; 0x03b6 Declare_Variable Access,By_Allocation,With_Value 01f8 ; 0x03b7 Declare_Variable Access,Visible,By_Allocation,With_Subtype 01f8 ; 0x03b8 Declare_Variable Access,By_Allocation,With_Subtype 01f8 ; 0x03b9 Declare_Variable Access,Visible,By_Allocation,With_Constraint 01f8 ; 0x03ba Declare_Variable Access,By_Allocation,With_Constraint 01f8 ; 0x03bb Declare_Variable Access,Visible,By_Allocation 01f8 ; 0x03bc Declare_Variable Access,By_Allocation 01f8 ; 0x03bd Declare_Variable Access,Duplicate 01f8 ; 0x03be Declare_Variable Access,Visible 01f8 ; 0x03bf Declare_Variable Access 01f8 ; 0x03c4 Complete_Type Access,By_Component_Completion 01f8 ; 0x03c5 Complete_Type Access,By_Constraining 01f8 ; 0x03c6 Complete_Type Access,By_Renaming 01f8 ; 0x03c7 Complete_Type Access,By_Defining 01f8 ; 0x03cc Declare_Type Access,Incomplete,Accesses_Protected 01f8 ; 0x03cd Declare_Type Access,Incomplete,Visible,Accesses_Protected 01f8 ; 0x03ce Declare_Type Access,Incomplete 01f8 ; 0x03cf Declare_Type Access,Incomplete,Visible 01f8 ; 0x03d1 Declare_Type Access,Constrained 01f8 ; 0x03d2 Declare_Type Access,Constrained,Visible 01f8 ; 0x03d3 Declare_Type Access,Defined,Accesses_Protected 01f8 ; 0x03d4 Declare_Type Access,Defined,Visible,Accesses_Protected 01f8 ; 0x03d5 Declare_Type Access,Defined 01f8 ; 0x03d6 Declare_Type Access,Defined,Visible 01f8 ; 0x03d8 Declare_Variable Float,Duplicate 01f8 ; 0x03d9 Declare_Variable Float,Visible 01f8 ; 0x03da Declare_Variable Float 01f8 ; 0x03db Declare_Variable Float,Visible,With_Value 01f8 ; 0x03dc Complete_Type Float,By_Constraining 01f8 ; 0x03dd Complete_Type Float,By_Renaming 01f8 ; 0x03de Complete_Type Float,By_Defining 01f8 ; 0x03df Declare_Variable Float,With_Value 01f8 ; 0x03e0 Declare_Type Float,Incomplete 01f8 ; 0x03e1 Declare_Type Float,Incomplete,Visible 01f8 ; 0x03e3 Declare_Type Float,Constrained 01f8 ; 0x03e4 Declare_Type Float,Constrained,Visible 01f8 ; 0x03e5 Declare_Type Float,Defined 01f8 ; 0x03e6 Declare_Type Float,Defined,Visible 01f8 ; 0x03e8 Declare_Variable Discrete,Visible,With_Value,With_Constraint 01f8 ; 0x03e9 Declare_Variable Discrete,Duplicate 01f8 ; 0x03ea Declare_Variable Discrete,Visible 01f8 ; 0x03eb Declare_Variable Discrete 01f8 ; 0x03ec Declare_Variable Discrete,With_Value,With_Constraint 01f8 ; 0x03ed Complete_Type Discrete,By_Constraining 01f8 ; 0x03ee Complete_Type Discrete,By_Renaming 01f8 ; 0x03ef Complete_Type Discrete,By_Defining 01f8 ; 0x03f0 Declare_Variable Discrete,Visible,With_Value 01f8 ; 0x03f1 Declare_Variable Discrete,With_Value 01f8 ; 0x03f2 Declare_Variable Discrete,Incomplete,Unsigned 01f8 ; 0x03f3 Declare_Variable Discrete,Incomplete,Visible,Unsigned 01f8 ; 0x03f5 Declare_Variable Discrete,Incomplete 01f8 ; 0x03f6 Declare_Variable Discrete,Incomplete,Visible 01f8 ; 0x03f7 Declare_Type InMicrocode,Discrete 01f8 ; 0x03fc Declare_Type InMicrocode,Discrete 01f8 ; 0x03f8 Declare_Type Discrete,Constrained 01f8 ; 0x03f9 Declare_Type Discrete,Constrained,Visible 01f8 ; 0x03fa Declare_Type Discrete,Defined,With_Size 01f8 ; 0x03fb Declare_Type Discrete,Defined,Visible,With_Size 01f8 ; 0x03fd Declare_Type Discrete,Defined 01f8 ; 0x03fe Declare_Type Discrete,Defined,Visible 01f8 ; 0x0800-0x08ff Execute_Immediate Raise,uimmediate,>R 01f8 ; 0x0900-0x093f Execute_Immediate Binary_Scale,limitedpos 01f8 ; 0x0940-0x097f Execute_Immediate Logical_Shift,limitedneg 01f8 ; 0x0980-0x09bf Execute_Immediate Logical_Shift,limitedpos 01f8 ; 0x09c0-0x09ff Execute_Immediate Binary_Scale,limitedneg 01f8 ; 0x0a00-0x0aff Execute_Immediate Plus,s8 01f8 ; 0x0b00-0x0bff Execute_Immediate Case_Compare,uimmediate 01f8 ; 0x0c00-0x0cff Execute_Immediate Greater_Equal,uimmediate 01f8 ; 0x0d00-0x0dff Execute_Immediate Less,uimmediate 01f8 ; 0x0e00-0x0eff Execute_Immediate Not_Equal,uimmediate 01f8 ; 0x0f00-0x0fbf Execute_Immediate Equal,uimmediate 01f8 ; 0x1000-0x10ff Execute Select,Guard_Write,fieldnum 01f8 ; 0x1100-0x11ff Execute Select,Member_Write,fieldnum 01f8 ; 0x1200-0x12ff Execute Task,Family_Timed,fieldnum 01f8 ; 0x1300-0x13ff Execute Task,Family_Cond,fieldnum 01f8 ; 0x1400-0x14ff Execute Task,Family_Call,fieldnum 01f8 ; 0x1500-0x15ff Execute Task,Timed_Call,fieldnum 01f8 ; 0x1600-0x16ff Execute Task,Conditional_Call,fieldnum 01f8 ; 0x1700-0x17ff Execute Task,Entry_Call,fieldnum 01f8 ; 0x1800-0x18ff Execute Package,Field_Execute,fieldnum 01f8 ; 0x1900-0x19ff Execute Package,Field_Reference,fieldnum 01f8 ; 0x1a00-0x1aff Execute Package,Field_Write,fieldnum 01f8 ; 0x1b00-0x1bff Execute Package,Field_Read,fieldnum 01f8 ; 0x1c00-0x1cff Execute_Immediate Run_Utility,uimmediate 01f8 ; 0x1d00-0x1dff Execute_Immediate Reference_Lex_1,uimmediate 01f8 ; 0x2000-0x20ff Execute Variant_Record,Set_Variant,fieldnum 01f8 ; 0x2100-0x21ff Execute Variant_Record,Set_Bounds,fieldnum 01f8 ; 0x2200-0x22ff Execute Variant_Record,Field_Constrain,fieldnum 01f8 ; 0x2300-0x23ff Execute Variant_Record,Field_Type,fieldnum 01f8 ; 0x2400-0x24ff Execute Variant_Record,Field_Reference,Fixed,Direct,fieldnum 01f8 ; 0x2500-0x25ff Execute Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 01f8 ; 0x2600-0x26ff Execute Variant_Record,Field_Reference,Variant,Direct,fieldnum 01f8 ; 0x2700-0x27ff Execute Variant_Record,Field_Reference,Variant,Indirect,fieldnum 01f8 ; 0x2800-0x28ff Execute Variant_Record,Field_Write,Fixed,Direct,fieldnum 01f8 ; 0x2900-0x29ff Execute Variant_Record,Field_Write,Fixed,Indirect,fieldnum 01f8 ; 0x2a00-0x2aff Execute Variant_Record,Field_Write,Variant,Direct,fieldnum 01f8 ; 0x2b00-0x2bff Execute Variant_Record,Field_Write,Variant,Indirect,fieldnum 01f8 ; 0x2c00-0x2cff Execute Variant_Record,Field_Read,Fixed,Direct,fieldnum 01f8 ; 0x2d00-0x2dff Execute Variant_Record,Field_Append,Fixed,Indirect,fieldnum 01f8 ; 0x2e00-0x2eff Execute Variant_Record,Field_Read,Variant,Direct,fieldnum 01f8 ; 0x2f00-0x2fff Execute Variant_Record,Field_Append,Variant,Indirect,fieldnum 01f8 ; 0x3000-0x30ff Execute Record,Field_Type,fieldnum 01f8 ; 0x3400-0x34ff Execute Record,Field_Reference,fieldnum 01f8 ; 0x3600-0x37ff Loop_Decreasing pcrelneg,>JC 01f8 ; 0x3800-0x38ff Execute Record,Field_Write,fieldnum 01f8 ; 0x3c00-0x3cff Execute Record,Field_Read,fieldnum 01f8 ; 0x3e00-0x3fff Loop_Increasing pcrelneg,>JC 01f8 ; 0x4100-0x41ff End_Rendezvous >R,parmcnt 01f8 ; 0x4200-0x42ff Exit_Subprogram From_Utility,With_Result,>R,topoffset 01f8 ; 0x4300-0x43ff Exit_Subprogram From_Utility,>R,topoffset 01f8 ; 0x4400-0x44ff Exit_Subprogram With_Result,>R,topoffset 01f8 ; 0x4500-0x45ff Exit_Subprogram topoffset,>R 01f8 ; 0x4600-0x47ff Jump_Case case_max 01f8 ; 0x4800-0x4fff Short_Literal slit 01f8 ; 0x5000-0x57ff Indirect_Literal Any,pcrel,literal 01f8 ; 0x5800-0x5fff Indirect_Literal Float,pcrel,dbl 01f8 ; 0x6000-0x67ff Indirect_Literal Discrete,pcrel,literal 01f8 ; 0x6800-0x6fff Jump_Zero pcrel,>JC 01f8 ; 0x7000-0x77ff Jump_Nonzero pcrel,>JC 01f8 ; 0x7800-0x7fff Jump pcrel,>J 01f8 ; 0x8040-0x81ff Call llvl,ldelta 01f8 ; 0x8240-0x83ff Call llvl,ldelta 01f8 ; 0x8440-0x85ff Call llvl,ldelta 01f8 ; 0x8640-0x9fff Call llvl,ldelta 01f8 ; 0xa040-0xa1ff Reference zdelta 01f8 ; 0xa240-0xa3ff Store_Unchecked llvl,ldelta 01f8 ; 0xa440-0xa5ff Store_Unchecked llvl,ldelta 01f8 ; 0xa640-0xbfff Store_Unchecked llvl,ldelta 01f8 ; 0xc000-0xcfff Store llvl,ldelta 01f8 ; 0xd040-0xdfff Store llvl,ldelta 01f8 ; 0xfe40-0xffff Load llvl,ldelta 01f8 ; -------------------------------------------------------------------------------------- 01f8 MACRO_01f8_QQUnknown_InMicrocode: 01f8 MACRO_Action_Accept_Activation: 01f8 MACRO_Action_Activate_Heap_Tasks: 01f8 MACRO_Action_Activate_Tasks: 01f8 MACRO_Action_Alter_Break_Mask: 01f8 MACRO_Action_Break_Optional: 01f8 MACRO_Action_Break_Unconditional: 01f8 MACRO_Action_Call_Dynamic: 01f8 MACRO_Action_Check_Subprogram_Elaborated: 01f8 MACRO_Action_Elaborate_Subprogram: 01f8 MACRO_Action_Establish_Frame: 01f8 MACRO_Action_Exit_Break: 01f8 MACRO_Action_Exit_Nullary_Function,>R: 01f8 MACRO_Action_Get_Priority: 01f8 MACRO_Action_Idle: 01f8 MACRO_Action_InMicrocode,Package,Field_Execute_Dynamic: 01f8 MACRO_Action_Increase_Priority: 01f8 MACRO_Action_Initiate_Delay: 01f8 MACRO_Action_Jump_Dynamic: 01f8 MACRO_Action_Jump_Extended,abs,>J: 01f8 MACRO_Action_Jump_Nonzero_Dynamic: 01f8 MACRO_Action_Jump_Nonzero_Extended,abs,>JC: 01f8 MACRO_Action_Jump_Zero_Dynamic: 01f8 MACRO_Action_Jump_Zero_Extended,abs,>JC: 01f8 MACRO_Action_Load_Dynamic: 01f8 MACRO_Action_Loop_Decreasing_Extended,abs,>JC: 01f8 MACRO_Action_Loop_Increasing_Extended,abs,>JC: 01f8 MACRO_Action_Make_Default: 01f8 MACRO_Action_Make_Parent: 01f8 MACRO_Action_Make_Scope: 01f8 MACRO_Action_Make_Self: 01f8 MACRO_Action_Mark_Auxiliary: 01f8 MACRO_Action_Name_Partner: 01f8 MACRO_Action_Pop_Auxiliary: 01f8 MACRO_Action_Pop_Auxiliary_Loop: 01f8 MACRO_Action_Pop_Auxiliary_Range: 01f8 MACRO_Action_Pop_Block: 01f8 MACRO_Action_Pop_Block_With_Result: 01f8 MACRO_Action_Push_Discrete_Extended: 01f8 MACRO_Action_Push_Float_Extended: 01f8 MACRO_Action_Push_String_Extended,pse: 01f8 MACRO_Action_Push_String_Extended_Indexed,pse: 01f8 MACRO_Action_Push_Structure_Extended,abs,mark: 01f8 MACRO_Action_Query_Break_Address: 01f8 MACRO_Action_Query_Break_Cause: 01f8 MACRO_Action_Query_Break_Mask: 01f8 MACRO_Action_Query_Frame: 01f8 MACRO_Action_Reference_Dynamic: 01f8 MACRO_Action_Set_Block_Start: 01f8 MACRO_Action_Set_Priority: 01f8 MACRO_Action_Signal_Activated: 01f8 MACRO_Action_Signal_Completion,>R: 01f8 MACRO_Action_Spare6_Action: 01f8 MACRO_Action_Store_Dynamic: 01f8 MACRO_Action_Store_String_Extended,pse: 01f8 MACRO_Action_Swap_Control: 01f8 MACRO_Call_llvl,ldelta: 01f8 MACRO_Complete_Type_Access,By_Component_Completion: 01f8 MACRO_Complete_Type_Access,By_Constraining: 01f8 MACRO_Complete_Type_Access,By_Defining: 01f8 MACRO_Complete_Type_Access,By_Renaming: 01f8 MACRO_Complete_Type_Array,By_Component_Completion: 01f8 MACRO_Complete_Type_Array,By_Constraining: 01f8 MACRO_Complete_Type_Array,By_Defining: 01f8 MACRO_Complete_Type_Array,By_Renaming: 01f8 MACRO_Complete_Type_Discrete,By_Constraining: 01f8 MACRO_Complete_Type_Discrete,By_Defining: 01f8 MACRO_Complete_Type_Discrete,By_Renaming: 01f8 MACRO_Complete_Type_Float,By_Constraining: 01f8 MACRO_Complete_Type_Float,By_Defining: 01f8 MACRO_Complete_Type_Float,By_Renaming: 01f8 MACRO_Complete_Type_Heap_Access,By_Component_Completion: 01f8 MACRO_Complete_Type_Heap_Access,By_Constraining: 01f8 MACRO_Complete_Type_Heap_Access,By_Defining: 01f8 MACRO_Complete_Type_Heap_Access,By_Renaming: 01f8 MACRO_Complete_Type_Record,By_Component_Completion: 01f8 MACRO_Complete_Type_Record,By_Defining: 01f8 MACRO_Complete_Type_Record,By_Renaming: 01f8 MACRO_Complete_Type_Task,By_Renaming: 01f8 MACRO_Complete_Type_Variant_Record,By_Completing_Constraint: 01f8 MACRO_Complete_Type_Variant_Record,By_Component_Completion: 01f8 MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete: 01f8 MACRO_Complete_Type_Variant_Record,By_Defining: 01f8 MACRO_Complete_Type_Variant_Record,By_Renaming: 01f8 MACRO_Declare_Subprogram_For_Accept,subp: 01f8 MACRO_Declare_Subprogram_For_Call,Unelaborated,With_Address: 01f8 MACRO_Declare_Subprogram_For_Call,Unelaborated,subp: 01f8 MACRO_Declare_Subprogram_For_Call,Visible,Unelaborated,With_Address: 01f8 MACRO_Declare_Subprogram_For_Call,Visible,With_Address: 01f8 MACRO_Declare_Subprogram_For_Call,With_Address: 01f8 MACRO_Declare_Subprogram_For_Call,subp: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,Unelaborated,subp: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,Unelaborated,subp: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,With_Address: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,subp: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,With_Address: 01f8 MACRO_Declare_Subprogram_For_Outer_Call,subp: 01f8 MACRO_Declare_Type_Access,Constrained: 01f8 MACRO_Declare_Type_Access,Constrained,Visible: 01f8 MACRO_Declare_Type_Access,Defined: 01f8 MACRO_Declare_Type_Access,Defined,Accesses_Protected: 01f8 MACRO_Declare_Type_Access,Defined,Visible: 01f8 MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected: 01f8 MACRO_Declare_Type_Access,Incomplete: 01f8 MACRO_Declare_Type_Access,Incomplete,Accesses_Protected: 01f8 MACRO_Declare_Type_Access,Incomplete,Visible: 01f8 MACRO_Declare_Type_Access,Incomplete,Visible,Accesses_Protected: 01f8 MACRO_Declare_Type_Array,Constrained: 01f8 MACRO_Declare_Type_Array,Constrained,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Constrained,Visible: 01f8 MACRO_Declare_Type_Array,Constrained,Visible,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Constrained_Incomplete: 01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible: 01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Defined: 01f8 MACRO_Declare_Type_Array,Defined,Visible: 01f8 MACRO_Declare_Type_Array,Defined_Incomplete: 01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Visible: 01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Incomplete: 01f8 MACRO_Declare_Type_Array,Incomplete,Bounds_With_Object: 01f8 MACRO_Declare_Type_Array,Incomplete,Visible: 01f8 MACRO_Declare_Type_Array,Incomplete,Visible,Bounds_With_Object: 01f8 MACRO_Declare_Type_Discrete,Constrained: 01f8 MACRO_Declare_Type_Discrete,Constrained,Visible: 01f8 MACRO_Declare_Type_Discrete,Defined: 01f8 MACRO_Declare_Type_Discrete,Defined,Visible: 01f8 MACRO_Declare_Type_Discrete,Defined,Visible,With_Size: 01f8 MACRO_Declare_Type_Discrete,Defined,With_Size: 01f8 MACRO_Declare_Type_Float,Constrained: 01f8 MACRO_Declare_Type_Float,Constrained,Visible: 01f8 MACRO_Declare_Type_Float,Defined: 01f8 MACRO_Declare_Type_Float,Defined,Visible: 01f8 MACRO_Declare_Type_Float,Incomplete: 01f8 MACRO_Declare_Type_Float,Incomplete,Visible: 01f8 MACRO_Declare_Type_Heap_Access,Constrained: 01f8 MACRO_Declare_Type_Heap_Access,Constrained,Visible: 01f8 MACRO_Declare_Type_Heap_Access,Defined: 01f8 MACRO_Declare_Type_Heap_Access,Defined,Visible: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative,With_Size: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative: 01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative,With_Size: 01f8 MACRO_Declare_Type_InMicrocode,Discrete: 01f8 MACRO_Declare_Type_Package,Defined: 01f8 MACRO_Declare_Type_Package,Defined,Not_Elaborated: 01f8 MACRO_Declare_Type_Package,Defined,Visible: 01f8 MACRO_Declare_Type_Package,Defined,Visible,Not_Elaborated: 01f8 MACRO_Declare_Type_Record,Defined: 01f8 MACRO_Declare_Type_Record,Defined,Visible: 01f8 MACRO_Declare_Type_Record,Defined_Incomplete: 01f8 MACRO_Declare_Type_Record,Defined_Incomplete,Visible: 01f8 MACRO_Declare_Type_Record,Incomplete: 01f8 MACRO_Declare_Type_Record,Incomplete,Visible: 01f8 MACRO_Declare_Type_Task,Defined: 01f8 MACRO_Declare_Type_Task,Defined,Not_Elaborated: 01f8 MACRO_Declare_Type_Task,Defined,Visible: 01f8 MACRO_Declare_Type_Task,Defined,Visible,Not_Elaborated: 01f8 MACRO_Declare_Type_Task,Incomplete: 01f8 MACRO_Declare_Type_Task,Incomplete,Visible: 01f8 MACRO_Declare_Type_Variant_Record,Constrained: 01f8 MACRO_Declare_Type_Variant_Record,Constrained,Visible: 01f8 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete: 01f8 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete,Visible: 01f8 MACRO_Declare_Type_Variant_Record,Defined: 01f8 MACRO_Declare_Type_Variant_Record,Defined,Visible: 01f8 MACRO_Declare_Type_Variant_Record,Defined_Incomplete: 01f8 MACRO_Declare_Type_Variant_Record,Defined_Incomplete,Visible: 01f8 MACRO_Declare_Type_Variant_Record,Incomplete: 01f8 MACRO_Declare_Type_Variant_Record,Incomplete,Visible: 01f8 MACRO_Declare_Variable_Access: 01f8 MACRO_Declare_Variable_Access,By_Allocation: 01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Constraint: 01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Subtype: 01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Value: 01f8 MACRO_Declare_Variable_Access,Duplicate: 01f8 MACRO_Declare_Variable_Access,Visible: 01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation: 01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint: 01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype: 01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value: 01f8 MACRO_Declare_Variable_Any: 01f8 MACRO_Declare_Variable_Any,Visible: 01f8 MACRO_Declare_Variable_Array: 01f8 MACRO_Declare_Variable_Array,Duplicate: 01f8 MACRO_Declare_Variable_Array,Visible: 01f8 MACRO_Declare_Variable_Array,Visible,With_Constraint: 01f8 MACRO_Declare_Variable_Array,With_Constraint: 01f8 MACRO_Declare_Variable_Discrete: 01f8 MACRO_Declare_Variable_Discrete,Duplicate: 01f8 MACRO_Declare_Variable_Discrete,Incomplete: 01f8 MACRO_Declare_Variable_Discrete,Incomplete,Unsigned: 01f8 MACRO_Declare_Variable_Discrete,Incomplete,Visible: 01f8 MACRO_Declare_Variable_Discrete,Incomplete,Visible,Unsigned: 01f8 MACRO_Declare_Variable_Discrete,Visible: 01f8 MACRO_Declare_Variable_Discrete,Visible,With_Value: 01f8 MACRO_Declare_Variable_Discrete,Visible,With_Value,With_Constraint: 01f8 MACRO_Declare_Variable_Discrete,With_Value: 01f8 MACRO_Declare_Variable_Discrete,With_Value,With_Constraint: 01f8 MACRO_Declare_Variable_Entry: 01f8 MACRO_Declare_Variable_Family: 01f8 MACRO_Declare_Variable_Float: 01f8 MACRO_Declare_Variable_Float,Duplicate: 01f8 MACRO_Declare_Variable_Float,Visible: 01f8 MACRO_Declare_Variable_Float,Visible,With_Value: 01f8 MACRO_Declare_Variable_Float,Visible,With_Value,With_Constraint: 01f8 MACRO_Declare_Variable_Float,With_Value: 01f8 MACRO_Declare_Variable_Float,With_Value,With_Constraint: 01f8 MACRO_Declare_Variable_Heap_Access: 01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation: 01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint: 01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype: 01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value: 01f8 MACRO_Declare_Variable_Heap_Access,Duplicate: 01f8 MACRO_Declare_Variable_Heap_Access,Visible: 01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation: 01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint: 01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype: 01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value: 01f8 MACRO_Declare_Variable_Package: 01f8 MACRO_Declare_Variable_Package,On_Processor: 01f8 MACRO_Declare_Variable_Package,Visible: 01f8 MACRO_Declare_Variable_Package,Visible,On_Processor: 01f8 MACRO_Declare_Variable_Record: 01f8 MACRO_Declare_Variable_Record,Duplicate: 01f8 MACRO_Declare_Variable_Record,Visible: 01f8 MACRO_Declare_Variable_Select: 01f8 MACRO_Declare_Variable_Select,Choice_Open: 01f8 MACRO_Declare_Variable_Task: 01f8 MACRO_Declare_Variable_Task,As_Component: 01f8 MACRO_Declare_Variable_Task,On_Processor: 01f8 MACRO_Declare_Variable_Task,On_Processor,As_Component: 01f8 MACRO_Declare_Variable_Task,Visible: 01f8 MACRO_Declare_Variable_Task,Visible,On_Processor: 01f8 MACRO_Declare_Variable_Variant_Record: 01f8 MACRO_Declare_Variable_Variant_Record,Duplicate: 01f8 MACRO_Declare_Variable_Variant_Record,Visible: 01f8 MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint: 01f8 MACRO_Declare_Variable_Variant_Record,With_Constraint: 01f8 MACRO_End_Rendezvous_>R,parmcnt: 01f8 MACRO_Execute_Access,All_Read: 01f8 MACRO_Execute_Access,All_Reference: 01f8 MACRO_Execute_Access,All_Write: 01f8 MACRO_Execute_Access,Allow_Deallocate: 01f8 MACRO_Execute_Access,Check_In_Type: 01f8 MACRO_Execute_Access,Convert: 01f8 MACRO_Execute_Access,Convert_Reference: 01f8 MACRO_Execute_Access,Deallocate: 01f8 MACRO_Execute_Access,Element_Type: 01f8 MACRO_Execute_Access,Equal: 01f8 MACRO_Execute_Access,In_Type: 01f8 MACRO_Execute_Access,Is_Null: 01f8 MACRO_Execute_Access,Not_Equal: 01f8 MACRO_Execute_Access,Not_In_Type: 01f8 MACRO_Execute_Access,Not_Null: 01f8 MACRO_Execute_Access,Set_Null: 01f8 MACRO_Execute_Access,Size: 01f8 MACRO_Execute_Any,Address: 01f8 MACRO_Execute_Any,Address_Of_Type: 01f8 MACRO_Execute_Any,Change_Utility: 01f8 MACRO_Execute_Any,Check_In_Formal_Type: 01f8 MACRO_Execute_Any,Convert: 01f8 MACRO_Execute_Any,Convert_To_Formal: 01f8 MACRO_Execute_Any,Convert_Unchecked: 01f8 MACRO_Execute_Any,Equal: 01f8 MACRO_Execute_Any,Has_Default_Initialization: 01f8 MACRO_Execute_Any,In_Type: 01f8 MACRO_Execute_Any,Is_Constrained: 01f8 MACRO_Execute_Any,Is_Scalar: 01f8 MACRO_Execute_Any,Make_Aligned: 01f8 MACRO_Execute_Any,Make_Visible: 01f8 MACRO_Execute_Any,Not_Equal: 01f8 MACRO_Execute_Any,Not_In_Type: 01f8 MACRO_Execute_Any,Run_Initialization_Utility: 01f8 MACRO_Execute_Any,Set_Constraint: 01f8 MACRO_Execute_Any,Size: 01f8 MACRO_Execute_Any,Spare14: 01f8 MACRO_Execute_Any,Structure_Clear: 01f8 MACRO_Execute_Any,Structure_Query: 01f8 MACRO_Execute_Any,Write_Unchecked: 01f8 MACRO_Execute_Array,Bounds: 01f8 MACRO_Execute_Array,Check_In_Type: 01f8 MACRO_Execute_Array,Convert: 01f8 MACRO_Execute_Array,Convert_To_Formal: 01f8 MACRO_Execute_Array,Element_Type: 01f8 MACRO_Execute_Array,Equal: 01f8 MACRO_Execute_Array,Field_Read: 01f8 MACRO_Execute_Array,Field_Reference: 01f8 MACRO_Execute_Array,Field_Write: 01f8 MACRO_Execute_Array,First: 01f8 MACRO_Execute_Array,In_Type: 01f8 MACRO_Execute_Array,Last: 01f8 MACRO_Execute_Array,Length: 01f8 MACRO_Execute_Array,Not_Equal: 01f8 MACRO_Execute_Array,Not_In_Type: 01f8 MACRO_Execute_Array,Reverse_Bounds: 01f8 MACRO_Execute_Array,Structure_Write: 01f8 MACRO_Execute_Array,Subarray: 01f8 MACRO_Execute_Discrete,Above_Bound: 01f8 MACRO_Execute_Discrete,Absolute_Value: 01f8 MACRO_Execute_Discrete,And: 01f8 MACRO_Execute_Discrete,Arithmetic_Shift: 01f8 MACRO_Execute_Discrete,Below_Bound: 01f8 MACRO_Execute_Discrete,Binary_Scale: 01f8 MACRO_Execute_Discrete,Bounds: 01f8 MACRO_Execute_Discrete,Bounds_Check: 01f8 MACRO_Execute_Discrete,Case_In_Range: 01f8 MACRO_Execute_Discrete,Check_In_Integer: 01f8 MACRO_Execute_Discrete,Check_In_Type: 01f8 MACRO_Execute_Discrete,Complement: 01f8 MACRO_Execute_Discrete,Convert: 01f8 MACRO_Execute_Discrete,Count_Leading_Zeros: 01f8 MACRO_Execute_Discrete,Count_Nonzero_Bits: 01f8 MACRO_Execute_Discrete,Count_Trailing_Zeros: 01f8 MACRO_Execute_Discrete,Diana_Arity_For_Kind: 01f8 MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci: 01f8 MACRO_Execute_Discrete,Diana_Spare0: 01f8 MACRO_Execute_Discrete,Diana_Spare1: 01f8 MACRO_Execute_Discrete,Diana_Spare2: 01f8 MACRO_Execute_Discrete,Divide_And_Scale: 01f8 MACRO_Execute_Discrete,Equal: 01f8 MACRO_Execute_Discrete,Exponentiate: 01f8 MACRO_Execute_Discrete,Extract_Bits: 01f8 MACRO_Execute_Discrete,First: 01f8 MACRO_Execute_Discrete,Greater: 01f8 MACRO_Execute_Discrete,Greater_Equal: 01f8 MACRO_Execute_Discrete,Insert_Bits: 01f8 MACRO_Execute_Discrete,Instruction_Read: 01f8 MACRO_Execute_Discrete,Is_Unsigned: 01f8 MACRO_Execute_Discrete,Last: 01f8 MACRO_Execute_Discrete,Less: 01f8 MACRO_Execute_Discrete,Less_Equal: 01f8 MACRO_Execute_Discrete,Logical_Shift: 01f8 MACRO_Execute_Discrete,Maximum: 01f8 MACRO_Execute_Discrete,Minimum: 01f8 MACRO_Execute_Discrete,Modulo: 01f8 MACRO_Execute_Discrete,Multiply_And_Scale: 01f8 MACRO_Execute_Discrete,Not_Equal: 01f8 MACRO_Execute_Discrete,Not_In_Type: 01f8 MACRO_Execute_Discrete,Or: 01f8 MACRO_Execute_Discrete,Partial_Minus: 01f8 MACRO_Execute_Discrete,Partial_Plus: 01f8 MACRO_Execute_Discrete,Plus: 01f8 MACRO_Execute_Discrete,Predecessor: 01f8 MACRO_Execute_Discrete,Raise,>R: 01f8 MACRO_Execute_Discrete,Remainder: 01f8 MACRO_Execute_Discrete,ReverseBounds_Check: 01f8 MACRO_Execute_Discrete,Reverse_Bounds: 01f8 MACRO_Execute_Discrete,Rotate: 01f8 MACRO_Execute_Discrete,Successor: 01f8 MACRO_Execute_Discrete,Test_And_Set_Next: 01f8 MACRO_Execute_Discrete,Test_And_Set_Previous: 01f8 MACRO_Execute_Discrete,Unary_Minus: 01f8 MACRO_Execute_Discrete,Write_Unchecked: 01f8 MACRO_Execute_Discrete,Xor: 01f8 MACRO_Execute_Entry,Count: 01f8 MACRO_Execute_Entry,Rendezvous: 01f8 MACRO_Execute_Exception,Address: 01f8 MACRO_Execute_Exception,Equal: 01f8 MACRO_Execute_Exception,Get_Name: 01f8 MACRO_Execute_Exception,Is_Constraint_Error: 01f8 MACRO_Execute_Exception,Is_Instruction_Error: 01f8 MACRO_Execute_Exception,Is_Numeric_Error: 01f8 MACRO_Execute_Exception,Is_Program_Error: 01f8 MACRO_Execute_Exception,Is_Storage_Error: 01f8 MACRO_Execute_Exception,Is_Tasking_Error: 01f8 MACRO_Execute_Family,Count: 01f8 MACRO_Execute_Family,Rendezvous: 01f8 MACRO_Execute_Float,Absolute_Value: 01f8 MACRO_Execute_Float,Check_In_Type: 01f8 MACRO_Execute_Float,Convert: 01f8 MACRO_Execute_Float,Convert_From_Discrete: 01f8 MACRO_Execute_Float,Divide: 01f8 MACRO_Execute_Float,Equal: 01f8 MACRO_Execute_Float,Equal_Zero: 01f8 MACRO_Execute_Float,Exponentiate: 01f8 MACRO_Execute_Float,First: 01f8 MACRO_Execute_Float,Greater: 01f8 MACRO_Execute_Float,Greater_Equal: 01f8 MACRO_Execute_Float,Greater_Equal_Zero: 01f8 MACRO_Execute_Float,Greater_Zero: 01f8 MACRO_Execute_Float,In_Range: 01f8 MACRO_Execute_Float,In_Type: 01f8 MACRO_Execute_Float,Last: 01f8 MACRO_Execute_Float,Less: 01f8 MACRO_Execute_Float,Less_Equal: 01f8 MACRO_Execute_Float,Less_Equal_Zero: 01f8 MACRO_Execute_Float,Less_Zero: 01f8 MACRO_Execute_Float,Minus: 01f8 MACRO_Execute_Float,Not_Equal: 01f8 MACRO_Execute_Float,Not_Equal_Zero: 01f8 MACRO_Execute_Float,Not_In_Range: 01f8 MACRO_Execute_Float,Not_In_Type: 01f8 MACRO_Execute_Float,Plus: 01f8 MACRO_Execute_Float,Round_To_Discrete: 01f8 MACRO_Execute_Float,Times: 01f8 MACRO_Execute_Float,Truncate_To_Discrete: 01f8 MACRO_Execute_Float,Unary_Minus: 01f8 MACRO_Execute_Float,Write_Unchecked: 01f8 MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup: 01f8 MACRO_Execute_Heap_Access,All_Read: 01f8 MACRO_Execute_Heap_Access,All_Reference: 01f8 MACRO_Execute_Heap_Access,All_Write: 01f8 MACRO_Execute_Heap_Access,Check_In_Type: 01f8 MACRO_Execute_Heap_Access,Construct_Segment: 01f8 MACRO_Execute_Heap_Access,Convert: 01f8 MACRO_Execute_Heap_Access,Diana_Allocate_Tree_Node: 01f8 MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute: 01f8 MACRO_Execute_Heap_Access,Diana_Put_Node_On_Seq_Type: 01f8 MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head: 01f8 MACRO_Execute_Heap_Access,Diana_Spare2: 01f8 MACRO_Execute_Heap_Access,Diana_Tree_Kind: 01f8 MACRO_Execute_Heap_Access,Element_Type: 01f8 MACRO_Execute_Heap_Access,Equal: 01f8 MACRO_Execute_Heap_Access,Get_Name: 01f8 MACRO_Execute_Heap_Access,Get_Offset: 01f8 MACRO_Execute_Heap_Access,Hash: 01f8 MACRO_Execute_Heap_Access,In_Type: 01f8 MACRO_Execute_Heap_Access,Is_Null: 01f8 MACRO_Execute_Heap_Access,Maximum: 01f8 MACRO_Execute_Heap_Access,Not_In_Type: 01f8 MACRO_Execute_Heap_Access,Not_Null: 01f8 MACRO_Execute_Heap_Access,Set_Null: 01f8 MACRO_Execute_Immediate_Binary_Scale,limitedneg: 01f8 MACRO_Execute_Immediate_Binary_Scale,limitedpos: 01f8 MACRO_Execute_Immediate_Case_Compare,uimmediate: 01f8 MACRO_Execute_Immediate_Equal,uimmediate: 01f8 MACRO_Execute_Immediate_Greater_Equal,uimmediate: 01f8 MACRO_Execute_Immediate_Less,uimmediate: 01f8 MACRO_Execute_Immediate_Logical_Shift,limitedneg: 01f8 MACRO_Execute_Immediate_Logical_Shift,limitedpos: 01f8 MACRO_Execute_Immediate_Not_Equal,uimmediate: 01f8 MACRO_Execute_Immediate_Plus,s8: 01f8 MACRO_Execute_Immediate_Raise,uimmediate,>R: 01f8 MACRO_Execute_Immediate_Reference_Lex_1,uimmediate: 01f8 MACRO_Execute_Immediate_Run_Utility,uimmediate: 01f8 MACRO_Execute_Matrix,Bounds: 01f8 MACRO_Execute_Matrix,Check_In_Type: 01f8 MACRO_Execute_Matrix,Convert: 01f8 MACRO_Execute_Matrix,Convert_To_Formal: 01f8 MACRO_Execute_Matrix,Element_Type: 01f8 MACRO_Execute_Matrix,Equal: 01f8 MACRO_Execute_Matrix,Field_Read: 01f8 MACRO_Execute_Matrix,Field_Reference: 01f8 MACRO_Execute_Matrix,Field_Write: 01f8 MACRO_Execute_Matrix,First: 01f8 MACRO_Execute_Matrix,In_Type: 01f8 MACRO_Execute_Matrix,Last: 01f8 MACRO_Execute_Matrix,Length: 01f8 MACRO_Execute_Matrix,Not_Equal: 01f8 MACRO_Execute_Matrix,Not_In_Type: 01f8 MACRO_Execute_Matrix,Reverse_Bounds: 01f8 MACRO_Execute_Matrix,Structure_Write: 01f8 MACRO_Execute_Matrix,Subarray: 01f8 MACRO_Execute_Module,Activate: 01f8 MACRO_Execute_Module,Augment_Imports: 01f8 MACRO_Execute_Module,Check_Elaborated: 01f8 MACRO_Execute_Module,Elaborate: 01f8 MACRO_Execute_Module,Get_Name: 01f8 MACRO_Execute_Module,Is_Callable: 01f8 MACRO_Execute_Module,Is_Terminated: 01f8 MACRO_Execute_Package,Field_Execute,fieldnum: 01f8 MACRO_Execute_Package,Field_Execute_Dynamic: 01f8 MACRO_Execute_Package,Field_Read,fieldnum: 01f8 MACRO_Execute_Package,Field_Read_Dynamic: 01f8 MACRO_Execute_Package,Field_Reference,fieldnum: 01f8 MACRO_Execute_Package,Field_Reference_Dynamic: 01f8 MACRO_Execute_Package,Field_Write,fieldnum: 01f8 MACRO_Execute_Package,Field_Write_Dynamic: 01f8 MACRO_Execute_Record,Component_Offset: 01f8 MACRO_Execute_Record,Convert: 01f8 MACRO_Execute_Record,Equal: 01f8 MACRO_Execute_Record,Field_Read,fieldnum: 01f8 MACRO_Execute_Record,Field_Read_Dynamic: 01f8 MACRO_Execute_Record,Field_Reference,fieldnum: 01f8 MACRO_Execute_Record,Field_Reference_Dynamic: 01f8 MACRO_Execute_Record,Field_Type,fieldnum: 01f8 MACRO_Execute_Record,Field_Type_Dynamic: 01f8 MACRO_Execute_Record,Field_Write,fieldnum: 01f8 MACRO_Execute_Record,Field_Write_Dynamic: 01f8 MACRO_Execute_Record,Not_Equal: 01f8 MACRO_Execute_Record,Structure_Write: 01f8 MACRO_Execute_Select,Guard_Write,fieldnum: 01f8 MACRO_Execute_Select,Member_Write,fieldnum: 01f8 MACRO_Execute_Select,Rendezvous: 01f8 MACRO_Execute_Select,Terminate_Guard_Write: 01f8 MACRO_Execute_Select,Timed_Duration_Write: 01f8 MACRO_Execute_Select,Timed_Guard_Write: 01f8 MACRO_Execute_Subarray,Field_Read: 01f8 MACRO_Execute_Subarray,Field_Reference: 01f8 MACRO_Execute_Subarray,Field_Write: 01f8 MACRO_Execute_Subvector,Field_Read: 01f8 MACRO_Execute_Subvector,Field_Reference: 01f8 MACRO_Execute_Subvector,Field_Write: 01f8 MACRO_Execute_Task,Abort: 01f8 MACRO_Execute_Task,Abort_Multiple: 01f8 MACRO_Execute_Task,Conditional_Call,fieldnum: 01f8 MACRO_Execute_Task,Entry_Call,fieldnum: 01f8 MACRO_Execute_Task,Family_Call,fieldnum: 01f8 MACRO_Execute_Task,Family_Cond,fieldnum: 01f8 MACRO_Execute_Task,Family_Timed,fieldnum: 01f8 MACRO_Execute_Task,Timed_Call,fieldnum: 01f8 MACRO_Execute_Variant_Record,Check_In_Formal_Type: 01f8 MACRO_Execute_Variant_Record,Check_In_Type: 01f8 MACRO_Execute_Variant_Record,Component_Offset: 01f8 MACRO_Execute_Variant_Record,Convert: 01f8 MACRO_Execute_Variant_Record,Equal: 01f8 MACRO_Execute_Variant_Record,Field_Append,Fixed,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Append,Variant,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Constrain,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Read_Dynamic: 01f8 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Reference_Dynamic: 01f8 MACRO_Execute_Variant_Record,Field_Type,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Type_Dynamic: 01f8 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum: 01f8 MACRO_Execute_Variant_Record,Field_Write_Dynamic: 01f8 MACRO_Execute_Variant_Record,In_Type: 01f8 MACRO_Execute_Variant_Record,Indirects_Appended: 01f8 MACRO_Execute_Variant_Record,Is_Constrained: 01f8 MACRO_Execute_Variant_Record,Is_Constrained_Object: 01f8 MACRO_Execute_Variant_Record,Make_Constrained: 01f8 MACRO_Execute_Variant_Record,Not_Equal: 01f8 MACRO_Execute_Variant_Record,Not_In_Type: 01f8 MACRO_Execute_Variant_Record,Read_Discriminant_Constraint: 01f8 MACRO_Execute_Variant_Record,Read_Variant: 01f8 MACRO_Execute_Variant_Record,Reference_Makes_Copy: 01f8 MACRO_Execute_Variant_Record,Set_Bounds,fieldnum: 01f8 MACRO_Execute_Variant_Record,Set_Variant,fieldnum: 01f8 MACRO_Execute_Variant_Record,Structure_Query: 01f8 MACRO_Execute_Variant_Record,Structure_Write: 01f8 MACRO_Execute_Vector,And: 01f8 MACRO_Execute_Vector,Append: 01f8 MACRO_Execute_Vector,Bounds: 01f8 MACRO_Execute_Vector,Catenate: 01f8 MACRO_Execute_Vector,Check_In_Type: 01f8 MACRO_Execute_Vector,Convert: 01f8 MACRO_Execute_Vector,Convert_To_Formal: 01f8 MACRO_Execute_Vector,Element_Type: 01f8 MACRO_Execute_Vector,Equal: 01f8 MACRO_Execute_Vector,Field_Read: 01f8 MACRO_Execute_Vector,Field_Reference: 01f8 MACRO_Execute_Vector,Field_Write: 01f8 MACRO_Execute_Vector,First: 01f8 MACRO_Execute_Vector,Hash: 01f8 MACRO_Execute_Vector,In_Type: 01f8 MACRO_Execute_Vector,Last: 01f8 MACRO_Execute_Vector,Length: 01f8 MACRO_Execute_Vector,Less_Equal: 01f8 MACRO_Execute_Vector,Not_Equal: 01f8 MACRO_Execute_Vector,Not_In_Type: 01f8 MACRO_Execute_Vector,Prepend: 01f8 MACRO_Execute_Vector,Reverse_Bounds: 01f8 MACRO_Execute_Vector,Slice_Read: 01f8 MACRO_Execute_Vector,Slice_Reference: 01f8 MACRO_Execute_Vector,Slice_Write: 01f8 MACRO_Execute_Vector,Structure_Write: 01f8 MACRO_Exit_Subprogram_From_Utility,>R,topoffset: 01f8 MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset: 01f8 MACRO_Exit_Subprogram_With_Result,>R,topoffset: 01f8 MACRO_Exit_Subprogram_topoffset,>R: 01f8 MACRO_Illegal_-: 01f8 MACRO_Indirect_Literal_Any,pcrel,literal: 01f8 MACRO_Indirect_Literal_Discrete,pcrel,literal: 01f8 MACRO_Indirect_Literal_Float,pcrel,dbl: 01f8 MACRO_Jump_Case_case_max: 01f8 MACRO_Jump_Nonzero_pcrel,>JC: 01f8 MACRO_Jump_Zero_pcrel,>JC: 01f8 MACRO_Jump_pcrel,>J: 01f8 MACRO_Load_Encached_eon: 01f8 MACRO_Load_Top_At_Offset_0: 01f8 MACRO_Load_Top_At_Offset_1: 01f8 MACRO_Load_Top_At_Offset_2: 01f8 MACRO_Load_Top_At_Offset_3: 01f8 MACRO_Load_Top_At_Offset_4: 01f8 MACRO_Load_Top_At_Offset_5: 01f8 MACRO_Load_Top_At_Offset_6: 01f8 MACRO_Load_llvl,ldelta: 01f8 MACRO_Loop_Decreasing_pcrelneg,>JC: 01f8 MACRO_Loop_Increasing_pcrelneg,>JC: 01f8 MACRO_Pop_Control_Pop_Count_1: 01f8 MACRO_Pop_Control_Pop_Count_2: 01f8 MACRO_Pop_Control_Pop_Count_3: 01f8 MACRO_Pop_Control_Pop_Count_4: 01f8 MACRO_Pop_Control_Pop_Count_5: 01f8 MACRO_Pop_Control_Pop_Count_6: 01f8 MACRO_Pop_Control_Pop_Count_7: 01f8 MACRO_PushFullAddress_InMicrocode,caddr: 01f8 MACRO_Reference_zdelta: 01f8 MACRO_Short_Literal_slit: 01f8 MACRO_Store_Top_Access,At_Offset_1: 01f8 MACRO_Store_Top_Access,At_Offset_2: 01f8 MACRO_Store_Top_Access,At_Offset_3: 01f8 MACRO_Store_Top_Access,At_Offset_4: 01f8 MACRO_Store_Top_Access,At_Offset_5: 01f8 MACRO_Store_Top_Access,At_Offset_6: 01f8 MACRO_Store_Top_Discrete,At_Offset_1: 01f8 MACRO_Store_Top_Discrete,At_Offset_2: 01f8 MACRO_Store_Top_Discrete,At_Offset_3: 01f8 MACRO_Store_Top_Discrete,At_Offset_4: 01f8 MACRO_Store_Top_Discrete,At_Offset_5: 01f8 MACRO_Store_Top_Discrete,At_Offset_6: 01f8 MACRO_Store_Top_Float,At_Offset_1: 01f8 MACRO_Store_Top_Float,At_Offset_2: 01f8 MACRO_Store_Top_Float,At_Offset_3: 01f8 MACRO_Store_Top_Float,At_Offset_4: 01f8 MACRO_Store_Top_Float,At_Offset_5: 01f8 MACRO_Store_Top_Float,At_Offset_6: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_1: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_2: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_3: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_4: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_5: 01f8 MACRO_Store_Top_Heap_Access,At_Offset_6: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_1: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_2: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_3: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_4: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_5: 01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_6: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_1: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_2: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_3: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_4: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_5: 01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_6: 01f8 MACRO_Store_Unchecked_llvl,ldelta: 01f8 MACRO_Store_llvl,ldelta: 01f8 01f8 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_uadr 01f8 ioc_random 14 clear cpu running seq_en_micro 0 seq_random 01 Halt+? typ_a_adr 3f TR19:1f typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 19 01f9 01f9 seq_br_type a Unconditional Return; Flow R 01fa 01fa <halt> ; Flow R 01fb 01fb <halt> ; Flow R 01fc 01fc <halt> ; Flow R 01fd 01fd <halt> ; Flow R 01fe 01fe <halt> ; Flow R 01ff 01ff <halt> ; Flow R 0200 0200 <halt> ; Flow R 0201 0201 <halt> ; Flow R 0202 ; -------------------------------------------------------------------------------------- 0202 ; Comes from: 0202 ; 0e23 C from color 0x0800 0202 ; 0e48 C from color 0x0e03 0202 ; -------------------------------------------------------------------------------------- 0202 0202 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 1d VR05:02 val_c_mux_sel 2 ALU val_frame 5 0203 0203 typ_c_adr 1d TR05:02 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0204 0204 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 06 GP06 val_alu_func 0 PASS_A 0205 0205 <default> 0206 0206 seq_br_type 0 Branch False; Flow J cc=False 0x208 seq_branch_adr 0208 0x0208 seq_cond_sel 6b CACHE_MISS~ 0207 0207 typ_a_adr 22 TR05:02 typ_alu_func 7 INC_A typ_c_adr 1d TR05:02 typ_c_mux_sel 0 ALU typ_frame 5 0208 0208 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 30 VR1a:10 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1a 0209 0209 seq_br_type 1 Branch True; Flow J cc=True 0x204 seq_branch_adr 0204 0x0204 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR19:10 val_frame 19 020a 020a typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 020b 020b typ_a_adr 30 TR1a:10 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 2d VR19:0d val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 020c 020c ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 020d 020d typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 020e 020e typ_a_adr 22 TR05:02 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 020f 020f fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 06 GP06 val_alu_func 0 PASS_A 0210 0210 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 30 VR1a:10 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1a 0211 0211 seq_b_timing 0 Early Condition; Flow J cc=False 0x20f seq_br_type 0 Branch False seq_branch_adr 020f 0x020f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 0212 0212 typ_c_adr 3e GP01 val_c_adr 3e GP01 0213 0213 seq_br_type 1 Branch True; Flow J cc=True 0x215 seq_branch_adr 0215 0x0215 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 1a TR05:05 typ_c_mux_sel 0 ALU typ_frame 5 0214 0214 typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 0215 0215 seq_br_type 1 Branch True; Flow J cc=True 0x217 seq_branch_adr 0217 0x0217 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 1a VR05:05 val_c_mux_sel 2 ALU val_frame 5 0216 0216 typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 0217 0217 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x221 seq_br_type 1 Branch True seq_branch_adr 0221 0x0221 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A 0218 0218 typ_a_adr 2f TR1a:0f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 2e VR19:0e val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 0219 0219 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x21b seq_br_type 1 Branch True seq_branch_adr 021b 0x021b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 021a 021a ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 021b 021b fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_mar_cntl f LOAD_MAR_RESERVED 021c 021c <default> 021d 021d fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_mar_cntl f LOAD_MAR_RESERVED 021e 021e <default> 021f 021f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x223 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0223 0x0223 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0220 0220 seq_br_type a Unconditional Return; Flow R val_c_adr 1d VR05:02 val_c_mux_sel 2 ALU val_frame 5 0221 0221 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 0222 0222 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 0223 0223 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0224 0224 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 0225 0225 seq_en_micro 0 val_a_adr 31 VR1a:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0226 0226 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 0227 0227 <halt> ; Flow R 0228 0228 <halt> ; Flow R 0229 0229 <halt> ; Flow R 022a 022a <halt> ; Flow R 022b 022b <halt> ; Flow R 022c 022c <halt> ; Flow R 022d 022d <halt> ; Flow R 022e 022e <halt> ; Flow R 022f 022f <halt> ; Flow R 0230 0230 <halt> ; Flow R 0231 0231 <halt> ; Flow R 0232 0232 <halt> ; Flow R 0233 0233 <halt> ; Flow R 0234 0234 <halt> ; Flow R 0235 0235 <halt> ; Flow R 0236 0236 <halt> ; Flow R 0237 0237 <halt> ; Flow R 0238 0238 <halt> ; Flow R 0239 0239 <halt> ; Flow R 023a 023a <halt> ; Flow R 023b 023b <halt> ; Flow R 023c 023c <halt> ; Flow R 023d 023d <halt> ; Flow R 023e 023e <halt> ; Flow R 023f 023f <halt> ; Flow R 0240 0240 <halt> ; Flow R 0241 0241 <halt> ; Flow R 0242 0242 <halt> ; Flow R 0243 0243 <halt> ; Flow R 0244 0244 <halt> ; Flow R 0245 0245 <halt> ; Flow R 0246 0246 <halt> ; Flow R 0247 0247 <halt> ; Flow R 0248 0248 <halt> ; Flow R 0249 0249 <halt> ; Flow R 024a 024a <halt> ; Flow R 024b 024b <halt> ; Flow R 024c 024c <halt> ; Flow R 024d 024d <halt> ; Flow R 024e 024e <halt> ; Flow R 024f 024f <halt> ; Flow R 0250 0250 <halt> ; Flow R 0251 0251 <halt> ; Flow R 0252 0252 <halt> ; Flow R 0253 0253 <halt> ; Flow R 0254 0254 <halt> ; Flow R 0255 0255 <halt> ; Flow R 0256 0256 <halt> ; Flow R 0257 0257 <halt> ; Flow R 0258 0258 <halt> ; Flow R 0259 0259 <halt> ; Flow R 025a 025a <halt> ; Flow R 025b 025b <halt> ; Flow R 025c 025c <halt> ; Flow R 025d 025d <halt> ; Flow R 025e 025e <halt> ; Flow R 025f 025f <halt> ; Flow R 0260 0260 <halt> ; Flow R 0261 0261 <halt> ; Flow R 0262 0262 <halt> ; Flow R 0263 0263 <halt> ; Flow R 0264 0264 <halt> ; Flow R 0265 0265 <halt> ; Flow R 0266 0266 <halt> ; Flow R 0267 0267 <halt> ; Flow R 0268 0268 <halt> ; Flow R 0269 0269 <halt> ; Flow R 026a 026a <halt> ; Flow R 026b 026b <halt> ; Flow R 026c 026c <halt> ; Flow R 026d 026d <halt> ; Flow R 026e 026e <halt> ; Flow R 026f 026f <halt> ; Flow R 0270 0270 <halt> ; Flow R 0271 0271 <halt> ; Flow R 0272 0272 <halt> ; Flow R 0273 0273 <halt> ; Flow R 0274 0274 <halt> ; Flow R 0275 0275 <halt> ; Flow R 0276 0276 <halt> ; Flow R 0277 0277 <halt> ; Flow R 0278 0278 <halt> ; Flow R 0279 0279 <halt> ; Flow R 027a 027a <halt> ; Flow R 027b 027b <halt> ; Flow R 027c 027c <halt> ; Flow R 027d 027d <halt> ; Flow R 027e 027e <halt> ; Flow R 027f 027f <halt> ; Flow R 0280 0280 <halt> ; Flow R 0281 0281 <halt> ; Flow R 0282 0282 <halt> ; Flow R 0283 0283 <halt> ; Flow R 0284 0284 <halt> ; Flow R 0285 0285 <halt> ; Flow R 0286 0286 <halt> ; Flow R 0287 0287 <halt> ; Flow R 0288 0288 <halt> ; Flow R 0289 0289 <halt> ; Flow R 028a 028a <halt> ; Flow R 028b 028b <halt> ; Flow R 028c 028c <halt> ; Flow R 028d 028d <halt> ; Flow R 028e 028e <halt> ; Flow R 028f 028f <halt> ; Flow R 0290 0290 <halt> ; Flow R 0291 0291 <halt> ; Flow R 0292 0292 <halt> ; Flow R 0293 0293 <halt> ; Flow R 0294 0294 <halt> ; Flow R 0295 0295 <halt> ; Flow R 0296 0296 <halt> ; Flow R 0297 0297 <halt> ; Flow R 0298 0298 <halt> ; Flow R 0299 0299 <halt> ; Flow R 029a 029a <halt> ; Flow R 029b 029b <halt> ; Flow R 029c 029c <halt> ; Flow R 029d 029d <halt> ; Flow R 029e 029e <halt> ; Flow R 029f 029f <halt> ; Flow R 02a0 02a0 <halt> ; Flow R 02a1 02a1 <halt> ; Flow R 02a2 02a2 <halt> ; Flow R 02a3 02a3 <halt> ; Flow R 02a4 02a4 <halt> ; Flow R 02a5 02a5 <halt> ; Flow R 02a6 02a6 <halt> ; Flow R 02a7 02a7 <halt> ; Flow R 02a8 02a8 <halt> ; Flow R 02a9 02a9 <halt> ; Flow R 02aa 02aa <halt> ; Flow R 02ab 02ab <halt> ; Flow R 02ac 02ac <halt> ; Flow R 02ad 02ad <halt> ; Flow R 02ae 02ae <halt> ; Flow R 02af 02af <halt> ; Flow R 02b0 02b0 <halt> ; Flow R 02b1 02b1 <halt> ; Flow R 02b2 02b2 <halt> ; Flow R 02b3 02b3 <halt> ; Flow R 02b4 02b4 <halt> ; Flow R 02b5 02b5 <halt> ; Flow R 02b6 02b6 <halt> ; Flow R 02b7 02b7 <halt> ; Flow R 02b8 02b8 <halt> ; Flow R 02b9 02b9 <halt> ; Flow R 02ba 02ba <halt> ; Flow R 02bb 02bb <halt> ; Flow R 02bc 02bc <halt> ; Flow R 02bd 02bd <halt> ; Flow R 02be 02be <halt> ; Flow R 02bf 02bf <halt> ; Flow R 02c0 02c0 <halt> ; Flow R 02c1 02c1 <halt> ; Flow R 02c2 02c2 <halt> ; Flow R 02c3 02c3 <halt> ; Flow R 02c4 02c4 <halt> ; Flow R 02c5 02c5 <halt> ; Flow R 02c6 02c6 <halt> ; Flow R 02c7 02c7 <halt> ; Flow R 02c8 02c8 <halt> ; Flow R 02c9 02c9 <halt> ; Flow R 02ca 02ca <halt> ; Flow R 02cb 02cb <halt> ; Flow R 02cc 02cc <halt> ; Flow R 02cd 02cd <halt> ; Flow R 02ce 02ce <halt> ; Flow R 02cf 02cf <halt> ; Flow R 02d0 02d0 <halt> ; Flow R 02d1 02d1 <halt> ; Flow R 02d2 02d2 <halt> ; Flow R 02d3 02d3 <halt> ; Flow R 02d4 02d4 <halt> ; Flow R 02d5 02d5 <halt> ; Flow R 02d6 02d6 <halt> ; Flow R 02d7 02d7 <halt> ; Flow R 02d8 02d8 <halt> ; Flow R 02d9 02d9 <halt> ; Flow R 02da 02da <halt> ; Flow R 02db 02db <halt> ; Flow R 02dc 02dc <halt> ; Flow R 02dd 02dd <halt> ; Flow R 02de 02de <halt> ; Flow R 02df 02df <halt> ; Flow R 02e0 02e0 <halt> ; Flow R 02e1 02e1 <halt> ; Flow R 02e2 02e2 <halt> ; Flow R 02e3 02e3 <halt> ; Flow R 02e4 02e4 <halt> ; Flow R 02e5 02e5 <halt> ; Flow R 02e6 02e6 <halt> ; Flow R 02e7 02e7 <halt> ; Flow R 02e8 02e8 <halt> ; Flow R 02e9 02e9 <halt> ; Flow R 02ea 02ea <halt> ; Flow R 02eb 02eb <halt> ; Flow R 02ec 02ec <halt> ; Flow R 02ed 02ed <halt> ; Flow R 02ee 02ee <halt> ; Flow R 02ef 02ef <halt> ; Flow R 02f0 02f0 <halt> ; Flow R 02f1 02f1 <halt> ; Flow R 02f2 02f2 <halt> ; Flow R 02f3 02f3 <halt> ; Flow R 02f4 02f4 <halt> ; Flow R 02f5 02f5 <halt> ; Flow R 02f6 02f6 <halt> ; Flow R 02f7 02f7 <halt> ; Flow R 02f8 02f8 <halt> ; Flow R 02f9 02f9 <halt> ; Flow R 02fa 02fa <halt> ; Flow R 02fb 02fb <halt> ; Flow R 02fc 02fc <halt> ; Flow R 02fd 02fd <halt> ; Flow R 02fe 02fe <halt> ; Flow R 02ff 02ff <halt> ; Flow R 0300 0300 <halt> ; Flow R 0301 0301 <halt> ; Flow R 0302 0302 <halt> ; Flow R 0303 0303 <halt> ; Flow R 0304 0304 <halt> ; Flow R 0305 0305 <halt> ; Flow R 0306 0306 <halt> ; Flow R 0307 0307 <halt> ; Flow R 0308 0308 <halt> ; Flow R 0309 0309 <halt> ; Flow R 030a 030a <halt> ; Flow R 030b 030b <halt> ; Flow R 030c 030c <halt> ; Flow R 030d 030d <halt> ; Flow R 030e 030e <halt> ; Flow R 030f 030f <halt> ; Flow R 0310 0310 <halt> ; Flow R 0311 0311 <halt> ; Flow R 0312 0312 <halt> ; Flow R 0313 0313 <halt> ; Flow R 0314 0314 <halt> ; Flow R 0315 0315 <halt> ; Flow R 0316 0316 <halt> ; Flow R 0317 0317 <halt> ; Flow R 0318 0318 <halt> ; Flow R 0319 0319 <halt> ; Flow R 031a 031a <halt> ; Flow R 031b 031b <halt> ; Flow R 031c 031c <halt> ; Flow R 031d 031d <halt> ; Flow R 031e 031e <halt> ; Flow R 031f 031f <halt> ; Flow R 0320 0320 <halt> ; Flow R 0321 0321 <halt> ; Flow R 0322 0322 <halt> ; Flow R 0323 0323 <halt> ; Flow R 0324 0324 <halt> ; Flow R 0325 0325 <halt> ; Flow R 0326 0326 <halt> ; Flow R 0327 0327 <halt> ; Flow R 0328 0328 <halt> ; Flow R 0329 0329 <halt> ; Flow R 032a 032a <halt> ; Flow R 032b 032b <halt> ; Flow R 032c 032c <halt> ; Flow R 032d 032d <halt> ; Flow R 032e 032e <halt> ; Flow R 032f 032f <halt> ; Flow R 0330 0330 <halt> ; Flow R 0331 0331 <halt> ; Flow R 0332 0332 <halt> ; Flow R 0333 0333 <halt> ; Flow R 0334 0334 <halt> ; Flow R 0335 0335 <halt> ; Flow R 0336 0336 <halt> ; Flow R 0337 0337 <halt> ; Flow R 0338 0338 <halt> ; Flow R 0339 0339 <halt> ; Flow R 033a 033a <halt> ; Flow R 033b 033b <halt> ; Flow R 033c 033c <halt> ; Flow R 033d 033d <halt> ; Flow R 033e 033e <halt> ; Flow R 033f 033f <halt> ; Flow R 0340 0340 <halt> ; Flow R 0341 0341 <halt> ; Flow R 0342 0342 <halt> ; Flow R 0343 0343 <halt> ; Flow R 0344 0344 <halt> ; Flow R 0345 0345 <halt> ; Flow R 0346 0346 <halt> ; Flow R 0347 0347 <halt> ; Flow R 0348 0348 <halt> ; Flow R 0349 0349 <halt> ; Flow R 034a 034a <halt> ; Flow R 034b 034b <halt> ; Flow R 034c 034c <halt> ; Flow R 034d 034d <halt> ; Flow R 034e 034e <halt> ; Flow R 034f 034f <halt> ; Flow R 0350 0350 <halt> ; Flow R 0351 0351 <halt> ; Flow R 0352 0352 <halt> ; Flow R 0353 0353 <halt> ; Flow R 0354 0354 <halt> ; Flow R 0355 0355 <halt> ; Flow R 0356 0356 <halt> ; Flow R 0357 0357 <halt> ; Flow R 0358 0358 <halt> ; Flow R 0359 0359 <halt> ; Flow R 035a 035a <halt> ; Flow R 035b 035b <halt> ; Flow R 035c 035c <halt> ; Flow R 035d 035d <halt> ; Flow R 035e 035e <halt> ; Flow R 035f 035f <halt> ; Flow R 0360 0360 <halt> ; Flow R 0361 0361 <halt> ; Flow R 0362 0362 <halt> ; Flow R 0363 0363 <halt> ; Flow R 0364 0364 <halt> ; Flow R 0365 0365 <halt> ; Flow R 0366 0366 <halt> ; Flow R 0367 0367 <halt> ; Flow R 0368 0368 <halt> ; Flow R 0369 0369 <halt> ; Flow R 036a 036a <halt> ; Flow R 036b 036b <halt> ; Flow R 036c 036c <halt> ; Flow R 036d 036d <halt> ; Flow R 036e 036e <halt> ; Flow R 036f 036f <halt> ; Flow R 0370 0370 <halt> ; Flow R 0371 0371 <halt> ; Flow R 0372 0372 <halt> ; Flow R 0373 0373 <halt> ; Flow R 0374 0374 <halt> ; Flow R 0375 0375 <halt> ; Flow R 0376 0376 <halt> ; Flow R 0377 0377 <halt> ; Flow R 0378 0378 <halt> ; Flow R 0379 0379 <halt> ; Flow R 037a 037a <halt> ; Flow R 037b 037b <halt> ; Flow R 037c 037c <halt> ; Flow R 037d 037d <halt> ; Flow R 037e 037e <halt> ; Flow R 037f 037f <halt> ; Flow R 0380 0380 <halt> ; Flow R 0381 0381 <halt> ; Flow R 0382 0382 <halt> ; Flow R 0383 0383 <halt> ; Flow R 0384 0384 <halt> ; Flow R 0385 0385 <halt> ; Flow R 0386 0386 <halt> ; Flow R 0387 0387 <halt> ; Flow R 0388 0388 <halt> ; Flow R 0389 0389 <halt> ; Flow R 038a 038a <halt> ; Flow R 038b 038b <halt> ; Flow R 038c 038c <halt> ; Flow R 038d 038d <halt> ; Flow R 038e 038e <halt> ; Flow R 038f 038f <halt> ; Flow R 0390 0390 <halt> ; Flow R 0391 0391 <halt> ; Flow R 0392 0392 <halt> ; Flow R 0393 0393 <halt> ; Flow R 0394 0394 <halt> ; Flow R 0395 0395 <halt> ; Flow R 0396 0396 <halt> ; Flow R 0397 0397 <halt> ; Flow R 0398 0398 <halt> ; Flow R 0399 0399 <halt> ; Flow R 039a 039a <halt> ; Flow R 039b 039b <halt> ; Flow R 039c 039c <halt> ; Flow R 039d 039d <halt> ; Flow R 039e 039e <halt> ; Flow R 039f 039f <halt> ; Flow R 03a0 03a0 <halt> ; Flow R 03a1 03a1 <halt> ; Flow R 03a2 03a2 <halt> ; Flow R 03a3 03a3 <halt> ; Flow R 03a4 03a4 <halt> ; Flow R 03a5 03a5 <halt> ; Flow R 03a6 03a6 <halt> ; Flow R 03a7 03a7 <halt> ; Flow R 03a8 03a8 <halt> ; Flow R 03a9 03a9 <halt> ; Flow R 03aa 03aa <halt> ; Flow R 03ab 03ab <halt> ; Flow R 03ac 03ac <halt> ; Flow R 03ad 03ad <halt> ; Flow R 03ae 03ae <halt> ; Flow R 03af 03af <halt> ; Flow R 03b0 03b0 <halt> ; Flow R 03b1 03b1 <halt> ; Flow R 03b2 03b2 <halt> ; Flow R 03b3 03b3 <halt> ; Flow R 03b4 03b4 <halt> ; Flow R 03b5 03b5 <halt> ; Flow R 03b6 03b6 <halt> ; Flow R 03b7 03b7 <halt> ; Flow R 03b8 03b8 <halt> ; Flow R 03b9 03b9 <halt> ; Flow R 03ba 03ba <halt> ; Flow R 03bb 03bb <halt> ; Flow R 03bc 03bc <halt> ; Flow R 03bd 03bd <halt> ; Flow R 03be 03be <halt> ; Flow R 03bf 03bf <halt> ; Flow R 03c0 03c0 <halt> ; Flow R 03c1 03c1 <halt> ; Flow R 03c2 03c2 <halt> ; Flow R 03c3 03c3 <halt> ; Flow R 03c4 03c4 <halt> ; Flow R 03c5 03c5 <halt> ; Flow R 03c6 03c6 <halt> ; Flow R 03c7 03c7 <halt> ; Flow R 03c8 03c8 <halt> ; Flow R 03c9 03c9 <halt> ; Flow R 03ca 03ca <halt> ; Flow R 03cb 03cb <halt> ; Flow R 03cc 03cc <halt> ; Flow R 03cd 03cd <halt> ; Flow R 03ce 03ce <halt> ; Flow R 03cf 03cf <halt> ; Flow R 03d0 03d0 <halt> ; Flow R 03d1 03d1 <halt> ; Flow R 03d2 03d2 <halt> ; Flow R 03d3 03d3 <halt> ; Flow R 03d4 03d4 <halt> ; Flow R 03d5 03d5 <halt> ; Flow R 03d6 03d6 <halt> ; Flow R 03d7 03d7 <halt> ; Flow R 03d8 03d8 <halt> ; Flow R 03d9 03d9 <halt> ; Flow R 03da 03da <halt> ; Flow R 03db 03db <halt> ; Flow R 03dc 03dc <halt> ; Flow R 03dd 03dd <halt> ; Flow R 03de 03de <halt> ; Flow R 03df 03df <halt> ; Flow R 03e0 03e0 <halt> ; Flow R 03e1 03e1 <halt> ; Flow R 03e2 03e2 <halt> ; Flow R 03e3 03e3 <halt> ; Flow R 03e4 03e4 <halt> ; Flow R 03e5 03e5 <halt> ; Flow R 03e6 03e6 <halt> ; Flow R 03e7 03e7 <halt> ; Flow R 03e8 03e8 <halt> ; Flow R 03e9 03e9 <halt> ; Flow R 03ea 03ea <halt> ; Flow R 03eb 03eb <halt> ; Flow R 03ec 03ec <halt> ; Flow R 03ed 03ed <halt> ; Flow R 03ee 03ee <halt> ; Flow R 03ef 03ef <halt> ; Flow R 03f0 03f0 <halt> ; Flow R 03f1 03f1 <halt> ; Flow R 03f2 03f2 <halt> ; Flow R 03f3 03f3 <halt> ; Flow R 03f4 03f4 <halt> ; Flow R 03f5 03f5 <halt> ; Flow R 03f6 03f6 <halt> ; Flow R 03f7 03f7 <halt> ; Flow R 03f8 03f8 <halt> ; Flow R 03f9 03f9 <halt> ; Flow R 03fa 03fa <halt> ; Flow R 03fb 03fb <halt> ; Flow R 03fc 03fc <halt> ; Flow R 03fd 03fd <halt> ; Flow R 03fe 03fe <halt> ; Flow R 03ff 03ff <halt> ; Flow R 0400 ; -------------------------------------------------------------------------------------- 0400 ; Comes from: 0400 ; 0e24 C from color 0x0800 0400 ; 0e4b C from color 0x0e04 0400 ; -------------------------------------------------------------------------------------- 0400 0400 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0401 0401 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 17 VAL.FALSE(early) typ_rand e CHECK_CLASS_SYSTEM_B 0402 0402 seq_b_timing 0 Early Condition; Flow J cc=False 0x404 seq_br_type 0 Branch False seq_branch_adr 0404 0x0404 seq_cond_sel 17 VAL.FALSE(early) 0403 0403 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0404 0404 seq_b_timing 0 Early Condition; Flow J cc=True 0x406 seq_br_type 1 Branch True seq_branch_adr 0406 0x0406 seq_cond_sel 16 VAL.TRUE(early) 0405 0405 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0406 0406 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 16 VAL.TRUE(early) 0407 0407 typ_rand e CHECK_CLASS_SYSTEM_B 0408 0408 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 0409 0409 seq_b_timing 0 Early Condition; Flow J cc=False 0x40b seq_br_type 0 Branch False seq_branch_adr 040b 0x040b seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 040a 040a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 040b 040b val_alu_func 13 ONES 040c 040c seq_b_timing 0 Early Condition; Flow J cc=True 0x40e seq_br_type 1 Branch True seq_branch_adr 040e 0x040e seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 13 ONES 040d 040d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 040e 040e seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 13 ONES 040f 040f seq_b_timing 0 Early Condition; Flow J cc=True 0x411 seq_br_type 1 Branch True seq_branch_adr 0411 0x0411 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 0410 0410 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0411 0411 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 13 ONES 0412 0412 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 0413 0413 seq_b_timing 0 Early Condition; Flow J cc=False 0x415 seq_br_type 0 Branch False seq_branch_adr 0415 0x0415 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 13 ONES 0414 0414 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0415 0415 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0416 0416 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0417 0417 seq_b_timing 0 Early Condition; Flow J cc=False 0x419 seq_br_type 0 Branch False seq_branch_adr 0419 0x0419 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0418 0418 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0419 0419 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 041a 041a seq_b_timing 0 Early Condition; Flow J cc=True 0x41c seq_br_type 1 Branch True seq_branch_adr 041c 0x041c seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 041b 041b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 041c 041c seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 041d 041d seq_b_timing 0 Early Condition; Flow J cc=True 0x41f seq_br_type 1 Branch True seq_branch_adr 041f 0x041f seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 041e 041e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 041f 041f seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0420 0420 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0421 0421 seq_b_timing 0 Early Condition; Flow J cc=False 0x423 seq_br_type 0 Branch False seq_branch_adr 0423 0x0423 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0422 0422 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0423 0423 seq_br_type 1 Branch True; Flow J cc=True 0x425 seq_branch_adr 0425 0x0425 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_rand e CHECK_CLASS_SYSTEM_B 0424 0424 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0425 0425 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) 0426 0426 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 13 ONES 0427 0427 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x429 seq_br_type 0 Branch False seq_branch_adr 0429 0x0429 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 13 ONES 0428 0428 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0429 0429 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x42b seq_br_type 1 Branch True seq_branch_adr 042b 0x042b seq_cond_sel 00 VAL.ALU_ZERO(late) 042a 042a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 042b 042b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) 042c 042c seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 13 ONES 042d 042d seq_br_type 0 Branch False; Flow J cc=False 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 13 ONES 042e 042e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 042f 042f seq_br_type 1 Branch True; Flow J cc=True 0x431 seq_branch_adr 0431 0x0431 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0430 0430 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0431 0431 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0432 0432 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0433 0433 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x435 seq_br_type 0 Branch False seq_branch_adr 0435 0x0435 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0434 0434 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0435 0435 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x437 seq_br_type 1 Branch True seq_branch_adr 0437 0x0437 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0436 0436 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0437 0437 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0438 0438 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0439 0439 seq_br_type 0 Branch False; Flow J cc=False 0x43b seq_branch_adr 043b 0x043b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 043a 043a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 043b 043b seq_br_type 1 Branch True; Flow J cc=True 0x43d seq_branch_adr 043d 0x043d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 13 ONES 043c 043c seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 043d 043d seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 13 ONES 043e 043e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) 043f 043f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x441 seq_br_type 0 Branch False seq_branch_adr 0441 0x0441 seq_cond_sel 01 VAL.ALU_NONZERO(late) 0440 0440 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0441 0441 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x443 seq_br_type 1 Branch True seq_branch_adr 0443 0x0443 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 13 ONES 0442 0442 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0443 0443 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 13 ONES 0444 0444 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) 0445 0445 seq_br_type 0 Branch False; Flow J cc=False 0x447 seq_branch_adr 0447 0x0447 seq_cond_sel 01 VAL.ALU_NONZERO(late) 0446 0446 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0447 0447 seq_br_type 1 Branch True; Flow J cc=True 0x449 seq_branch_adr 0449 0x0449 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0448 0448 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0449 0449 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 044a 044a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 044b 044b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x44d seq_br_type 0 Branch False seq_branch_adr 044d 0x044d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 044c 044c seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 044d 044d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x44f seq_br_type 1 Branch True seq_branch_adr 044f 0x044f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 044e 044e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 044f 044f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0450 0450 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0451 0451 seq_br_type 0 Branch False; Flow J cc=False 0x453 seq_branch_adr 0453 0x0453 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0452 0452 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0453 0453 typ_rand e CHECK_CLASS_SYSTEM_B val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0454 0454 seq_b_timing 0 Early Condition; Flow J cc=True 0x456 seq_br_type 1 Branch True seq_branch_adr 0456 0x0456 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 0455 0455 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0456 0456 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 0457 0457 val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0458 0458 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 0459 0459 seq_b_timing 0 Early Condition; Flow J cc=False 0x45b seq_br_type 0 Branch False seq_branch_adr 045b 0x045b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 045a 045a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 045b 045b seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 045c 045c seq_b_timing 0 Early Condition; Flow J cc=True 0x45e seq_br_type 1 Branch True seq_branch_adr 045e 0x045e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 045d 045d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 045e 045e seq_b_timing 0 Early Condition; Flow J cc=False 0x460 seq_br_type 0 Branch False seq_branch_adr 0460 0x0460 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 045f 045f seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0460 0460 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0461 0461 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 0462 0462 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0463 0463 seq_b_timing 0 Early Condition; Flow J cc=True 0x465 seq_br_type 1 Branch True seq_branch_adr 0465 0x0465 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0464 0464 seq_br_type 3 Unconditional Branch; Flow J 0x463 seq_branch_adr 0463 0x0463 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0465 0465 seq_br_type 1 Branch True; Flow J cc=True 0x467 seq_branch_adr 0467 0x0467 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3f VR19:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 0466 0466 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0467 0467 typ_rand e CHECK_CLASS_SYSTEM_B 0468 0468 seq_br_type 1 Branch True; Flow J cc=True 0x46a seq_branch_adr 046a 0x046a seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 30 VR14:10 val_b_adr 30 VR14:10 val_frame 14 0469 0469 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 046a 046a seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 30 VR14:10 val_b_adr 30 VR14:10 val_frame 14 046b 046b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x46d seq_br_type 1 Branch True seq_branch_adr 046d 0x046d seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 30 VR14:10 val_b_adr 30 VR14:10 val_frame 14 046c 046c seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 046d 046d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 30 VR14:10 val_b_adr 30 VR14:10 val_frame 14 046e 046e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 3a VR19:1a val_b_adr 32 VR19:12 val_frame 19 046f 046f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x471 seq_br_type 0 Branch False seq_branch_adr 0471 0x0471 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 3a VR19:1a val_b_adr 32 VR19:12 val_frame 19 0470 0470 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0471 0471 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 3a VR19:1a val_b_adr 32 VR19:12 val_frame 19 0472 0472 seq_br_type 0 Branch False; Flow J cc=False 0x474 seq_branch_adr 0474 0x0474 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 3a VR19:1a val_b_adr 32 VR19:12 val_frame 19 0473 0473 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0474 0474 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 3a VR19:1a val_frame 19 0475 0475 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x477 seq_br_type 0 Branch False seq_branch_adr 0477 0x0477 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 3a VR19:1a val_frame 19 0476 0476 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0477 0477 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 3a VR19:1a val_frame 19 0478 0478 seq_br_type 0 Branch False; Flow J cc=False 0x47a seq_branch_adr 047a 0x047a seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 3a VR19:1a val_frame 19 0479 0479 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 047a 047a seq_br_type 1 Branch True; Flow J cc=True 0x47c seq_branch_adr 047c 0x047c seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 32 VR19:12 val_frame 19 047b 047b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 047c 047c seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 32 VR19:12 val_frame 19 047d 047d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x47f seq_br_type 1 Branch True seq_branch_adr 047f 0x047f seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 32 VR19:12 val_frame 19 047e 047e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 047f 047f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 32 VR19:12 val_b_adr 32 VR19:12 val_frame 19 0480 0480 typ_rand e CHECK_CLASS_SYSTEM_B 0481 0481 seq_br_type 1 Branch True; Flow J cc=True 0x483 seq_branch_adr 0483 0x0483 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_alu_func 13 ONES 0482 0482 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0483 0483 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_alu_func 13 ONES 0484 0484 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) 0485 0485 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x487 seq_br_type 0 Branch False seq_branch_adr 0487 0x0487 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) 0486 0486 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0487 0487 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x489 seq_br_type 1 Branch True seq_branch_adr 0489 0x0489 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_alu_func 13 ONES 0488 0488 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0489 0489 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_alu_func 13 ONES 048a 048a seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) 048b 048b seq_br_type 0 Branch False; Flow J cc=False 0x48d seq_branch_adr 048d 0x048d seq_cond_sel 0a VAL.ALU_LT_ZERO(late) 048c 048c seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 048d 048d seq_br_type 1 Branch True; Flow J cc=True 0x48f seq_branch_adr 048f 0x048f seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 048e 048e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 048f 048f seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0490 0490 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0491 0491 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x493 seq_br_type 0 Branch False seq_branch_adr 0493 0x0493 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0492 0492 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0493 0493 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x495 seq_br_type 1 Branch True seq_branch_adr 0495 0x0495 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0494 0494 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0495 0495 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 0496 0496 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0497 0497 seq_br_type 0 Branch False; Flow J cc=False 0x499 seq_branch_adr 0499 0x0499 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 0498 0498 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0499 0499 typ_rand e CHECK_CLASS_SYSTEM_B 049a 049a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x49c seq_br_type 0 Branch False seq_branch_adr 049c 0x049c seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 13 ONES 049b 049b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 049c 049c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 13 ONES 049d 049d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x49f seq_br_type 0 Branch False seq_branch_adr 049f 0x049f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) 049e 049e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 049f 049f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) 04a0 04a0 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 04a1 04a1 seq_br_type 1 Branch True; Flow J cc=True 0x4a3 seq_branch_adr 04a3 0x04a3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 04a2 04a2 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04a3 04a3 seq_br_type 0 Branch False; Flow J cc=False 0x4a5 seq_branch_adr 04a5 0x04a5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 13 ONES 04a4 04a4 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04a5 04a5 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 13 ONES 04a6 04a6 seq_br_type 0 Branch False; Flow J cc=False 0x4a8 seq_branch_adr 04a8 0x04a8 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) 04a7 04a7 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04a8 04a8 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) 04a9 04a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 04aa 04aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4ac seq_br_type 1 Branch True seq_branch_adr 04ac 0x04ac seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 04ab 04ab seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04ac 04ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4ae seq_br_type 0 Branch False seq_branch_adr 04ae 0x04ae seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 04ad 04ad seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04ae 04ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 04af 04af seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4b1 seq_br_type 0 Branch False seq_branch_adr 04b1 0x04b1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04b0 04b0 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04b1 04b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04b2 04b2 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 31 VR19:11 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04b3 04b3 seq_br_type 1 Branch True; Flow J cc=True 0x4b5 seq_branch_adr 04b5 0x04b5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 31 VR19:11 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04b4 04b4 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04b5 04b5 seq_br_type 0 Branch False; Flow J cc=False 0x4b7 seq_branch_adr 04b7 0x04b7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 04b6 04b6 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04b7 04b7 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_frame 14 04b8 04b8 seq_br_type 0 Branch False; Flow J cc=False 0x4ba seq_branch_adr 04ba 0x04ba seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04b9 04b9 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04ba 04ba seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04bb 04bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 31 VR19:11 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04bc 04bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4be seq_br_type 1 Branch True seq_branch_adr 04be 0x04be seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 31 VR19:11 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04bd 04bd seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04be 04be typ_rand e CHECK_CLASS_SYSTEM_B 04bf 04bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04c0 04c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4c2 seq_br_type 0 Branch False seq_branch_adr 04c2 0x04c2 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04c1 04c1 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04c2 04c2 seq_br_type 1 Branch True; Flow J cc=True 0x4c4 seq_branch_adr 04c4 0x04c4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04c3 04c3 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04c4 04c4 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04c5 04c5 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04c6 04c6 seq_br_type 0 Branch False; Flow J cc=False 0x4c8 seq_branch_adr 04c8 0x04c8 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04c7 04c7 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04c8 04c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4ca seq_br_type 1 Branch True seq_branch_adr 04ca 0x04ca seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04c9 04c9 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04ca 04ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04cb 04cb typ_rand e CHECK_CLASS_SYSTEM_B 04cc 04cc seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04cd 04cd seq_br_type 1 Branch True; Flow J cc=True 0x4cf seq_branch_adr 04cf 0x04cf seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04ce 04ce seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04cf 04cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4d1 seq_br_type 0 Branch False seq_branch_adr 04d1 0x04d1 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04d0 04d0 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04d1 04d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04d2 04d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04d3 04d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4d5 seq_br_type 1 Branch True seq_branch_adr 04d5 0x04d5 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 04d4 04d4 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04d5 04d5 seq_br_type 0 Branch False; Flow J cc=False 0x4d7 seq_branch_adr 04d7 0x04d7 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04d6 04d6 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04d7 04d7 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 04d8 04d8 seq_br_type 0 Branch False; Flow J cc=False 0x4da seq_branch_adr 04da 0x04da seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 25 VR17:05 val_alu_func 7 INC_A val_frame 17 04d9 04d9 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04da 04da seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 3d VR19:1d val_alu_func 7 INC_A val_frame 19 04db 04db typ_rand e CHECK_CLASS_SYSTEM_B 04dc 04dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 1 A_PLUS_B val_b_adr 3b VR19:1b val_frame 19 04dd 04dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4df seq_br_type 0 Branch False seq_branch_adr 04df 0x04df seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 1 A_PLUS_B val_b_adr 3b VR19:1b val_frame 19 04de 04de seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04df 04df seq_br_type 1 Branch True; Flow J cc=True 0x4e1 seq_branch_adr 04e1 0x04e1 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04e0 04e0 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04e1 04e1 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04e2 04e2 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 1 A_PLUS_B val_b_adr 3b VR19:1b val_frame 19 04e3 04e3 seq_br_type 0 Branch False; Flow J cc=False 0x4e5 seq_branch_adr 04e5 0x04e5 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 1 A_PLUS_B val_b_adr 3b VR19:1b val_frame 19 04e4 04e4 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04e5 04e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4e7 seq_br_type 1 Branch True seq_branch_adr 04e7 0x04e7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04e6 04e6 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04e7 04e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04e8 04e8 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 3b VR19:1b val_frame 19 04e9 04e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 4 LEFT_I_A_INC val_b_adr 3b VR19:1b val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 04ea 04ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 03 GP03 val_alu_func 4 LEFT_I_A_INC val_b_adr 3b VR19:1b val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 04eb 04eb seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 04ec 04ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04ed 04ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 04ee 04ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04ef 04ef typ_rand e CHECK_CLASS_SYSTEM_B 04f0 04f0 seq_br_type 1 Branch True; Flow J cc=True 0x4f2 seq_branch_adr 04f2 0x04f2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 04f1 04f1 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04f2 04f2 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 04f3 04f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04f4 04f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4f6 seq_br_type 0 Branch False seq_branch_adr 04f6 0x04f6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04f5 04f5 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04f6 04f6 seq_br_type 1 Branch True; Flow J cc=True 0x4f8 seq_branch_adr 04f8 0x04f8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 04f7 04f7 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04f8 04f8 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 04f9 04f9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04fa 04fa seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4fc seq_br_type 0 Branch False seq_branch_adr 04fc 0x04fc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 04fb 04fb seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04fc 04fc seq_br_type 1 Branch True; Flow J cc=True 0x4fe seq_branch_adr 04fe 0x04fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04fd 04fd seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 04fe 04fe seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 04ff 04ff seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 0500 0500 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x502 seq_br_type 0 Branch False seq_branch_adr 0502 0x0502 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 0501 0501 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0502 0502 seq_br_type 1 Branch True; Flow J cc=True 0x504 seq_branch_adr 0504 0x0504 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0503 0503 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0504 0504 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0505 0505 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0506 0506 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x508 seq_br_type 0 Branch False seq_branch_adr 0508 0x0508 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0507 0507 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0508 0508 seq_br_type 1 Branch True; Flow J cc=True 0x50a seq_branch_adr 050a 0x050a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 0509 0509 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 050a 050a seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 050b 050b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 050c 050c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x50e seq_br_type 0 Branch False seq_branch_adr 050e 0x050e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 050d 050d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 050e 050e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 050f 050f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x511 seq_br_type 0 Branch False seq_branch_adr 0511 0x0511 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 0510 0510 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0511 0511 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0512 0512 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x514 seq_br_type 0 Branch False seq_branch_adr 0514 0x0514 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0513 0513 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0514 0514 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x516 seq_br_type 1 Branch True seq_branch_adr 0516 0x0516 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 0515 0515 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0516 0516 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 0517 0517 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0518 0518 seq_br_type 0 Branch False; Flow J cc=False 0x51a seq_branch_adr 051a 0x051a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0519 0519 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 051a 051a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x51c seq_br_type 1 Branch True seq_branch_adr 051c 0x051c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 051b 051b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 051c 051c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 051d 051d seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 051e 051e seq_br_type 0 Branch False; Flow J cc=False 0x520 seq_branch_adr 0520 0x0520 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 051f 051f seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0520 0520 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x522 seq_br_type 1 Branch True seq_branch_adr 0522 0x0522 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0521 0521 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0522 0522 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0523 0523 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 0524 0524 seq_br_type 0 Branch False; Flow J cc=False 0x526 seq_branch_adr 0526 0x0526 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 0525 0525 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0526 0526 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x528 seq_br_type 1 Branch True seq_branch_adr 0528 0x0528 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0527 0527 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0528 0528 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_frame 19 0529 0529 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 052a 052a seq_br_type 0 Branch False; Flow J cc=False 0x52c seq_branch_adr 052c 0x052c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 052b 052b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 052c 052c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x52e seq_br_type 1 Branch True seq_branch_adr 052e 0x052e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 052d 052d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 052e 052e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_frame 19 052f 052f seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0530 0530 seq_br_type 0 Branch False; Flow J cc=False 0x532 seq_branch_adr 0532 0x0532 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0531 0531 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0532 0532 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 0533 0533 seq_br_type 0 Branch False; Flow J cc=False 0x535 seq_branch_adr 0535 0x0535 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3c VR19:1c val_alu_func 6 A_MINUS_B val_b_adr 3c VR19:1c val_frame 19 0534 0534 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0535 0535 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0536 0536 seq_br_type 0 Branch False; Flow J cc=False 0x538 seq_branch_adr 0538 0x0538 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3b VR19:1b val_alu_func 6 A_MINUS_B val_b_adr 3b VR19:1b val_frame 19 0537 0537 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0538 0538 typ_rand e CHECK_CLASS_SYSTEM_B 0539 0539 seq_br_type 1 Branch True; Flow J cc=True 0x53b seq_branch_adr 053b 0x053b seq_cond_sel 10 VAL.ALU_32_ZERO(late) 053a 053a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 053b 053b seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) 053c 053c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_alu_func 13 ONES 053d 053d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x53f seq_br_type 0 Branch False seq_branch_adr 053f 0x053f seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_alu_func 13 ONES 053e 053e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 053f 053f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 0 PASS_A val_frame 19 0540 0540 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x542 seq_br_type 0 Branch False seq_branch_adr 0542 0x0542 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 0 PASS_A val_frame 19 0541 0541 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0542 0542 seq_br_type 1 Branch True; Flow J cc=True 0x544 seq_branch_adr 0544 0x0544 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 10 NOT_A val_frame 19 0543 0543 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0544 0544 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 10 NOT_A val_frame 19 0545 0545 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x547 seq_br_type 1 Branch True seq_branch_adr 0547 0x0547 seq_cond_sel 10 VAL.ALU_32_ZERO(late) 0546 0546 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0547 0547 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) 0548 0548 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_alu_func 13 ONES 0549 0549 seq_br_type 0 Branch False; Flow J cc=False 0x54b seq_branch_adr 054b 0x054b seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_alu_func 13 ONES 054a 054a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 054b 054b seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 0 PASS_A val_frame 19 054c 054c seq_br_type 0 Branch False; Flow J cc=False 0x54e seq_branch_adr 054e 0x054e seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 0 PASS_A val_frame 19 054d 054d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 054e 054e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x550 seq_br_type 1 Branch True seq_branch_adr 0550 0x0550 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 10 NOT_A val_frame 19 054f 054f seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0550 0550 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 38 VR19:18 val_alu_func 10 NOT_A val_frame 19 0551 0551 val_a_adr 35 VR19:15 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 0552 0552 val_a_adr 2f VR1a:0f val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 1a 0553 0553 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 0554 0554 seq_b_timing 0 Early Condition; Flow J cc=False 0x553 seq_br_type 0 Branch False seq_branch_adr 0553 0x0553 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0555 0555 typ_rand e CHECK_CLASS_SYSTEM_B 0556 0556 seq_br_type 1 Branch True; Flow J cc=True 0x558 seq_branch_adr 0558 0x0558 seq_cond_sel 11 VAL.ALU_40_ZERO(late) 0557 0557 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0558 0558 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) 0559 0559 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_alu_func 13 ONES 055a 055a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x55c seq_br_type 0 Branch False seq_branch_adr 055c 0x055c seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_alu_func 13 ONES 055b 055b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 055c 055c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 0 PASS_A val_frame 19 055d 055d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x55f seq_br_type 0 Branch False seq_branch_adr 055f 0x055f seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 0 PASS_A val_frame 19 055e 055e seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 055f 055f seq_br_type 1 Branch True; Flow J cc=True 0x561 seq_branch_adr 0561 0x0561 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 10 NOT_A val_frame 19 0560 0560 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0561 0561 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 10 NOT_A val_frame 19 0562 0562 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x564 seq_br_type 1 Branch True seq_branch_adr 0564 0x0564 seq_cond_sel 11 VAL.ALU_40_ZERO(late) 0563 0563 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0564 0564 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) 0565 0565 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_alu_func 13 ONES 0566 0566 seq_br_type 0 Branch False; Flow J cc=False 0x568 seq_branch_adr 0568 0x0568 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_alu_func 13 ONES 0567 0567 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0568 0568 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 0 PASS_A val_frame 19 0569 0569 seq_br_type 0 Branch False; Flow J cc=False 0x56b seq_branch_adr 056b 0x056b seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 0 PASS_A val_frame 19 056a 056a seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 056b 056b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x56d seq_br_type 1 Branch True seq_branch_adr 056d 0x056d seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 10 NOT_A val_frame 19 056c 056c seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 056d 056d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 37 VR19:17 val_alu_func 10 NOT_A val_frame 19 056e 056e val_a_adr 34 VR19:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 056f 056f val_a_adr 28 VR14:08 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 0570 0570 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 0571 0571 seq_b_timing 0 Early Condition; Flow J cc=False 0x570 seq_br_type 0 Branch False seq_branch_adr 0570 0x0570 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0572 0572 typ_rand e CHECK_CLASS_SYSTEM_B 0573 0573 seq_br_type 1 Branch True; Flow J cc=True 0x575 seq_branch_adr 0575 0x0575 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) 0574 0574 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0575 0575 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) 0576 0576 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_alu_func 13 ONES 0577 0577 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x579 seq_br_type 0 Branch False seq_branch_adr 0579 0x0579 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_alu_func 13 ONES 0578 0578 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0579 0579 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 0 PASS_A val_frame 19 057a 057a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x57c seq_br_type 0 Branch False seq_branch_adr 057c 0x057c seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 0 PASS_A val_frame 19 057b 057b seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 057c 057c seq_br_type 1 Branch True; Flow J cc=True 0x57e seq_branch_adr 057e 0x057e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 10 NOT_A val_frame 19 057d 057d seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 057e 057e seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 10 NOT_A val_frame 19 057f 057f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x581 seq_br_type 1 Branch True seq_branch_adr 0581 0x0581 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) 0580 0580 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0581 0581 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) 0582 0582 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_alu_func 13 ONES 0583 0583 seq_br_type 0 Branch False; Flow J cc=False 0x585 seq_branch_adr 0585 0x0585 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_alu_func 13 ONES 0584 0584 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0585 0585 seq_br_type 1 Branch True; Flow J cc=True 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 0 PASS_A val_frame 19 0586 0586 seq_br_type 0 Branch False; Flow J cc=False 0x588 seq_branch_adr 0588 0x0588 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 0 PASS_A val_frame 19 0587 0587 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0588 0588 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x58a seq_br_type 1 Branch True seq_branch_adr 058a 0x058a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 10 NOT_A val_frame 19 0589 0589 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 058a 058a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 33 VR19:13 val_alu_func 10 NOT_A val_frame 19 058b 058b val_a_adr 36 VR19:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 058c 058c val_a_adr 28 VR14:08 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 058d 058d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 058e 058e seq_b_timing 0 Early Condition; Flow J cc=False 0x58d seq_br_type 0 Branch False seq_branch_adr 058d 0x058d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 058f 058f seq_cond_sel 17 VAL.FALSE(early) typ_rand e CHECK_CLASS_SYSTEM_B 0590 0590 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 0591 0591 seq_cond_sel 17 VAL.FALSE(early) 0592 0592 seq_b_timing 0 Early Condition; Flow J cc=False 0x594 seq_br_type 0 Branch False seq_branch_adr 0594 0x0594 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 0593 0593 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0594 0594 seq_cond_sel 16 VAL.TRUE(early) 0595 0595 seq_b_timing 0 Early Condition; Flow J cc=True 0x597 seq_br_type 1 Branch True seq_branch_adr 0597 0x0597 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 0596 0596 seq_br_type 3 Unconditional Branch; Flow J 0x5f4 seq_branch_adr 05f4 0x05f4 0597 0597 seq_cond_sel 16 VAL.TRUE(early) 0598 0598 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 0599 0599 seq_cond_sel 25 TYP.FALSE (early) 059a 059a seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 059b 059b seq_cond_sel 17 VAL.FALSE(early) 059c 059c seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 059d 059d seq_cond_sel 00 VAL.ALU_ZERO(late) 059e 059e seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 059f 059f seq_cond_sel 17 VAL.FALSE(early) 05a0 05a0 seq_b_timing 0 Early Condition; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 05a1 05a1 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) val_a_adr 31 VR19:11 val_b_adr 31 VR19:11 val_frame 19 05a2 05a2 seq_b_timing 0 Early Condition; Flow J cc=False 0x5f4 seq_br_type 0 Branch False seq_branch_adr 05f4 0x05f4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 05a3 05a3 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 05a4 05a4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 05a5 05a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 05a6 05a6 val_alu_func 13 ONES val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05a7 05a7 seq_br_type 0 Branch False; Flow J cc=False 0x5f4 seq_branch_adr 05f4 0x05f4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 03 GP03 val_alu_func 7 INC_A 05a8 05a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05a9 05a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05aa 05aa val_alu_func 13 ONES val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05ab 05ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05ac 05ac val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 05ad 05ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 05ae 05ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 1c DEC_A 05af 05af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 05b0 05b0 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 05b1 05b1 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05b2 05b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 05b3 05b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 05b4 05b4 seq_b_timing 0 Early Condition; Flow J cc=False 0x5af seq_br_type 0 Branch False seq_branch_adr 05af 0x05af seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 05b5 05b5 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 05b6 05b6 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 val_rand 2 DEC_LOOP_COUNTER 05b7 05b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 05b8 05b8 val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 05b9 05b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 05ba 05ba val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 05bb 05bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 05bc 05bc val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05bd 05bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 0 PASS_A 05be 05be seq_b_timing 0 Early Condition; Flow J cc=False 0x5b8 seq_br_type 0 Branch False seq_branch_adr 05b8 0x05b8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 05bf 05bf typ_rand e CHECK_CLASS_SYSTEM_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 05c0 05c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 05c1 05c1 typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU 05c2 05c2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 05c3 05c3 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR15:00 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05c4 05c4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05c5 05c5 val_a_adr 21 VR15:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05c6 05c6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05c7 05c7 val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05c8 05c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05c9 05c9 val_a_adr 23 VR15:03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05ca 05ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05cb 05cb val_a_adr 24 VR15:04 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05cc 05cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05cd 05cd val_a_adr 25 VR15:05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05ce 05ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05cf 05cf typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1a PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05d0 05d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05d1 05d1 val_alu_func 1a PASS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05d2 05d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05d3 05d3 val_alu_func 1a PASS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05d4 05d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05d5 05d5 val_alu_func 1a PASS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05d6 05d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05d7 05d7 val_alu_func 1a PASS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05d8 05d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05d9 05d9 val_alu_func 1a PASS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05da 05da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05db 05db typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR15:00 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05dc 05dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05dd 05dd val_a_adr 21 VR15:01 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05de 05de seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05df 05df val_a_adr 22 VR15:02 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05e0 05e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05e1 05e1 val_a_adr 23 VR15:03 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05e2 05e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05e3 05e3 val_a_adr 24 VR15:04 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05e4 05e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05e5 05e5 val_a_adr 25 VR15:05 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05e6 05e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05e7 05e7 typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 15 NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05e8 05e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05e9 05e9 val_alu_func 15 NOT_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05ea 05ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05eb 05eb val_alu_func 15 NOT_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05ec 05ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05ed 05ed val_alu_func 15 NOT_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05ee 05ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05ef 05ef val_alu_func 15 NOT_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05f0 05f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05f1 05f1 val_alu_func 15 NOT_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 05f2 05f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f4 seq_br_type 1 Branch True seq_branch_adr 05f4 0x05f4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 05f3 05f3 seq_br_type 3 Unconditional Branch; Flow J 0x1000 seq_branch_adr 1000 0x1000 05f4 05f4 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU 05f5 05f5 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 05f6 05f6 <halt> ; Flow R 05f7 05f7 <halt> ; Flow R 05f8 05f8 <halt> ; Flow R 05f9 05f9 <halt> ; Flow R 05fa 05fa <halt> ; Flow R 05fb 05fb <halt> ; Flow R 05fc 05fc <halt> ; Flow R 05fd 05fd <halt> ; Flow R 05fe 05fe <halt> ; Flow R 05ff 05ff <halt> ; Flow R 0600 ; -------------------------------------------------------------------------------------- 0600 ; Comes from: 0600 ; 0e25 C from color 0x0800 0600 ; 0e4e C from color 0x0e05 0600 ; -------------------------------------------------------------------------------------- 0600 0600 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0601 0601 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 25 TYP.FALSE (early) val_rand 1 INC_LOOP_COUNTER 0602 0602 seq_b_timing 0 Early Condition; Flow J cc=False 0x604 seq_br_type 0 Branch False seq_branch_adr 0604 0x0604 seq_cond_sel 25 TYP.FALSE (early) 0603 0603 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0604 0604 seq_b_timing 0 Early Condition; Flow J cc=True 0x606 seq_br_type 1 Branch True seq_branch_adr 0606 0x0606 seq_cond_sel 26 TYP.TRUE (early) 0605 0605 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0606 0606 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 26 TYP.TRUE (early) 0607 0607 seq_br_type 1 Branch True; Flow J cc=True 0x609 seq_branch_adr 0609 0x0609 seq_cond_sel 18 TYP.ALU_ZERO(late) val_rand 1 INC_LOOP_COUNTER 0608 0608 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0609 0609 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) 060a 060a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 13 ONES 060b 060b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x60d seq_br_type 0 Branch False seq_branch_adr 060d 0x060d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 13 ONES 060c 060c seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 060d 060d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x60f seq_br_type 1 Branch True seq_branch_adr 060f 0x060f seq_cond_sel 18 TYP.ALU_ZERO(late) 060e 060e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 060f 060f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) 0610 0610 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 13 ONES 0611 0611 seq_br_type 0 Branch False; Flow J cc=False 0x613 seq_branch_adr 0613 0x0613 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 13 ONES 0612 0612 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0613 0613 seq_br_type 1 Branch True; Flow J cc=True 0x615 seq_branch_adr 0615 0x0615 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0614 0614 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0615 0615 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0616 0616 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0617 0617 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x619 seq_br_type 0 Branch False seq_branch_adr 0619 0x0619 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0618 0618 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0619 0619 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x61b seq_br_type 1 Branch True seq_branch_adr 061b 0x061b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 061a 061a seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 061b 061b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 061c 061c seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 061d 061d seq_br_type 0 Branch False; Flow J cc=False 0x61f seq_branch_adr 061f 0x061f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 061e 061e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 061f 061f typ_a_adr 3c TR14:1c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 14 0620 0620 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0621 0621 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A 0622 0622 seq_b_timing 0 Early Condition; Flow J cc=False 0x621 seq_br_type 0 Branch False seq_branch_adr 0621 0x0621 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 0623 0623 seq_br_type 1 Branch True; Flow J cc=True 0x625 seq_branch_adr 0625 0x0625 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 13 ONES val_rand 1 INC_LOOP_COUNTER 0624 0624 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0625 0625 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 13 ONES 0626 0626 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) 0627 0627 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x629 seq_br_type 0 Branch False seq_branch_adr 0629 0x0629 seq_cond_sel 19 TYP.ALU_NONZERO(late) 0628 0628 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0629 0629 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x62b seq_br_type 1 Branch True seq_branch_adr 062b 0x062b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 13 ONES 062a 062a seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 062b 062b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 13 ONES 062c 062c seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) 062d 062d seq_br_type 0 Branch False; Flow J cc=False 0x62f seq_branch_adr 062f 0x062f seq_cond_sel 19 TYP.ALU_NONZERO(late) 062e 062e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 062f 062f seq_br_type 1 Branch True; Flow J cc=True 0x631 seq_branch_adr 0631 0x0631 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0630 0630 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0631 0631 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0632 0632 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0633 0633 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x635 seq_br_type 0 Branch False seq_branch_adr 0635 0x0635 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0634 0634 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0635 0635 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x637 seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0636 0636 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0637 0637 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0638 0638 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0639 0639 seq_br_type 0 Branch False; Flow J cc=False 0x63b seq_branch_adr 063b 0x063b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 063a 063a seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 063b 063b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 063c 063c seq_b_timing 0 Early Condition; Flow J cc=True 0x63e seq_br_type 1 Branch True seq_branch_adr 063e 0x063e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 063d 063d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 063e 063e seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 063f 063f typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0640 0640 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 0641 0641 seq_b_timing 0 Early Condition; Flow J cc=False 0x643 seq_br_type 0 Branch False seq_branch_adr 0643 0x0643 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 0642 0642 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0643 0643 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0644 0644 seq_b_timing 0 Early Condition; Flow J cc=True 0x646 seq_br_type 1 Branch True seq_branch_adr 0646 0x0646 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0645 0645 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0646 0646 seq_b_timing 0 Early Condition; Flow J cc=False 0x648 seq_br_type 0 Branch False seq_branch_adr 0648 0x0648 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0647 0647 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0648 0648 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0649 0649 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 064a 064a typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 064b 064b seq_b_timing 0 Early Condition; Flow J cc=True 0x64d seq_br_type 1 Branch True seq_branch_adr 064d 0x064d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 064c 064c seq_br_type 3 Unconditional Branch; Flow J 0x64b seq_branch_adr 064b 0x064b typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 064d 064d seq_br_type 1 Branch True; Flow J cc=True 0x64f seq_branch_adr 064f 0x064f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR12:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 064e 064e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 064f 064f seq_br_type 1 Branch True; Flow J cc=True 0x651 seq_branch_adr 0651 0x0651 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 0650 0650 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0651 0651 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 0652 0652 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x654 seq_br_type 1 Branch True seq_branch_adr 0654 0x0654 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 0653 0653 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0654 0654 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 0655 0655 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 20 TR18:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0656 0656 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x658 seq_br_type 0 Branch False seq_branch_adr 0658 0x0658 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 20 TR18:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0657 0657 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0658 0658 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 20 TR18:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0659 0659 seq_br_type 0 Branch False; Flow J cc=False 0x65b seq_branch_adr 065b 0x065b seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 20 TR18:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 065a 065a seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 065b 065b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR18:00 typ_frame 18 065c 065c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x65e seq_br_type 0 Branch False seq_branch_adr 065e 0x065e seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR18:00 typ_frame 18 065d 065d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 065e 065e seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR18:00 typ_frame 18 065f 065f seq_br_type 0 Branch False; Flow J cc=False 0x661 seq_branch_adr 0661 0x0661 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR18:00 typ_frame 18 0660 0660 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0661 0661 seq_br_type 1 Branch True; Flow J cc=True 0x663 seq_branch_adr 0663 0x0663 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0662 0662 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0663 0663 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0664 0664 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x666 seq_br_type 1 Branch True seq_branch_adr 0666 0x0666 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0665 0665 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0666 0666 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 22 TR18:02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_frame 18 0667 0667 seq_br_type 1 Branch True; Flow J cc=True 0x669 seq_branch_adr 0669 0x0669 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_alu_func 13 ONES val_rand 1 INC_LOOP_COUNTER 0668 0668 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0669 0669 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_alu_func 13 ONES 066a 066a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) 066b 066b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x66d seq_br_type 0 Branch False seq_branch_adr 066d 0x066d seq_cond_sel 22 TYP.ALU_LT_ZERO(late) 066c 066c seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 066d 066d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x66f seq_br_type 1 Branch True seq_branch_adr 066f 0x066f seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_alu_func 13 ONES 066e 066e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 066f 066f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_alu_func 13 ONES 0670 0670 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) 0671 0671 seq_br_type 0 Branch False; Flow J cc=False 0x673 seq_branch_adr 0673 0x0673 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) 0672 0672 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0673 0673 seq_br_type 1 Branch True; Flow J cc=True 0x675 seq_branch_adr 0675 0x0675 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0674 0674 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0675 0675 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0676 0676 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0677 0677 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x679 seq_br_type 0 Branch False seq_branch_adr 0679 0x0679 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0678 0678 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0679 0679 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x67b seq_br_type 1 Branch True seq_branch_adr 067b 0x067b seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 067a 067a seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 067b 067b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 067c 067c seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 067d 067d seq_br_type 0 Branch False; Flow J cc=False 0x67f seq_branch_adr 067f 0x067f seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 067e 067e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 067f 067f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x681 seq_br_type 0 Branch False seq_branch_adr 0681 0x0681 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 13 ONES val_rand 1 INC_LOOP_COUNTER 0680 0680 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0681 0681 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 13 ONES 0682 0682 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x684 seq_br_type 0 Branch False seq_branch_adr 0684 0x0684 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) 0683 0683 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0684 0684 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) 0685 0685 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 0686 0686 seq_br_type 1 Branch True; Flow J cc=True 0x688 seq_branch_adr 0688 0x0688 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 0687 0687 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0688 0688 seq_br_type 0 Branch False; Flow J cc=False 0x68a seq_branch_adr 068a 0x068a seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 13 ONES 0689 0689 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 068a 068a seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 13 ONES 068b 068b seq_br_type 0 Branch False; Flow J cc=False 0x68d seq_branch_adr 068d 0x068d seq_cond_sel 23 TYP.ALU_LE_ZERO(late) 068c 068c seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 068d 068d seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) 068e 068e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 068f 068f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x691 seq_br_type 1 Branch True seq_branch_adr 0691 0x0691 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 0690 0690 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0691 0691 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x693 seq_br_type 0 Branch False seq_branch_adr 0693 0x0693 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0692 0692 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0693 0693 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 0694 0694 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x696 seq_br_type 0 Branch False seq_branch_adr 0696 0x0696 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0695 0695 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0696 0696 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 0697 0697 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 21 TR18:01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 0698 0698 seq_br_type 1 Branch True; Flow J cc=True 0x69a seq_branch_adr 069a 0x069a seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 21 TR18:01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 0699 0699 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 069a 069a seq_br_type 0 Branch False; Flow J cc=False 0x69c seq_branch_adr 069c 0x069c seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 069b 069b seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 069c 069c seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_frame 12 069d 069d seq_br_type 0 Branch False; Flow J cc=False 0x69f seq_branch_adr 069f 0x069f seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 069e 069e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 069f 069f seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06a0 06a0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 21 TR18:01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06a1 06a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x6a3 seq_br_type 1 Branch True seq_branch_adr 06a3 0x06a3 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 21 TR18:01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06a2 06a2 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06a3 06a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 06a4 06a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6a6 seq_br_type 0 Branch False seq_branch_adr 06a6 0x06a6 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06a5 06a5 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06a6 06a6 seq_br_type 1 Branch True; Flow J cc=True 0x6a8 seq_branch_adr 06a8 0x06a8 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06a7 06a7 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06a8 06a8 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06a9 06a9 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06aa 06aa seq_br_type 0 Branch False; Flow J cc=False 0x6ac seq_branch_adr 06ac 0x06ac seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06ab 06ab seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06ac 06ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x6ae seq_br_type 1 Branch True seq_branch_adr 06ae 0x06ae seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06ad 06ad seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06ae 06ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06af 06af seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 06b0 06b0 seq_br_type 1 Branch True; Flow J cc=True 0x6b2 seq_branch_adr 06b2 0x06b2 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b1 06b1 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06b2 06b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6b4 seq_br_type 0 Branch False seq_branch_adr 06b4 0x06b4 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b3 06b3 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06b4 06b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b5 06b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b6 06b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x6b8 seq_br_type 1 Branch True seq_branch_adr 06b8 0x06b8 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b7 06b7 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06b8 06b8 seq_br_type 0 Branch False; Flow J cc=False 0x6ba seq_branch_adr 06ba 0x06ba seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06b9 06b9 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06ba 06ba seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 06bb 06bb seq_br_type 0 Branch False; Flow J cc=False 0x6bd seq_branch_adr 06bd 0x06bd seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 25 TR15:05 typ_alu_func 7 INC_A typ_frame 15 06bc 06bc seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06bd 06bd seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 24 TR13:04 typ_alu_func 7 INC_A typ_frame 13 06be 06be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR18:07 typ_frame 18 val_rand 1 INC_LOOP_COUNTER 06bf 06bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6c1 seq_br_type 0 Branch False seq_branch_adr 06c1 0x06c1 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c0 06c0 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06c1 06c1 seq_br_type 1 Branch True; Flow J cc=True 0x6c3 seq_branch_adr 06c3 0x06c3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c2 06c2 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06c3 06c3 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c4 06c4 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c5 06c5 seq_br_type 0 Branch False; Flow J cc=False 0x6c7 seq_branch_adr 06c7 0x06c7 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c6 06c6 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06c7 06c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x6c9 seq_br_type 1 Branch True seq_branch_adr 06c9 0x06c9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06c8 06c8 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06c9 06c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06ca 06ca seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 27 TR18:07 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR18:07 typ_frame 18 06cb 06cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 27 TR18:07 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 06cc 06cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 27 TR18:07 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 06cd 06cd seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 06ce 06ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 06cf 06cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 06d0 06d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 06d1 06d1 val_rand 1 INC_LOOP_COUNTER 06d2 06d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6d4 seq_br_type 0 Branch False seq_branch_adr 06d4 0x06d4 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06d3 06d3 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06d4 06d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06d5 06d5 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06d6 06d6 seq_br_type 1 Branch True; Flow J cc=True 0x6d8 seq_branch_adr 06d8 0x06d8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06d7 06d7 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06d8 06d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6da seq_br_type 0 Branch False seq_branch_adr 06da 0x06da seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06d9 06d9 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06da 06da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06db 06db seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06dc 06dc seq_br_type 1 Branch True; Flow J cc=True 0x6de seq_branch_adr 06de 0x06de seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06dd 06dd seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06de 06de seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6e0 seq_br_type 0 Branch False seq_branch_adr 06e0 0x06e0 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06df 06df seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06e0 06e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06e1 06e1 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 06e2 06e2 seq_br_type 1 Branch True; Flow J cc=True 0x6e4 seq_branch_adr 06e4 0x06e4 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 06e3 06e3 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06e4 06e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6e6 seq_br_type 0 Branch False seq_branch_adr 06e6 0x06e6 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06e5 06e5 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06e6 06e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06e7 06e7 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06e8 06e8 seq_br_type 1 Branch True; Flow J cc=True 0x6ea seq_branch_adr 06ea 0x06ea seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06e9 06e9 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06ea 06ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6ec seq_br_type 0 Branch False seq_branch_adr 06ec 0x06ec seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 06eb 06eb seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06ec 06ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 06ed 06ed seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06ee 06ee seq_br_type 1 Branch True; Flow J cc=True 0x6f0 seq_branch_adr 06f0 0x06f0 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06ef 06ef seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06f0 06f0 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06f1 06f1 seq_br_type 1 Branch True; Flow J cc=True 0x6f3 seq_branch_adr 06f3 0x06f3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06f2 06f2 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06f3 06f3 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06f4 06f4 seq_br_type 1 Branch True; Flow J cc=True 0x6f6 seq_branch_adr 06f6 0x06f6 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 06f5 06f5 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06f6 06f6 seq_br_type 0 Branch False; Flow J cc=False 0x6f8 seq_branch_adr 06f8 0x06f8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06f7 06f7 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06f8 06f8 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06f9 06f9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06fa 06fa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x6fc seq_br_type 1 Branch True seq_branch_adr 06fc 0x06fc seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 06fb 06fb seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06fc 06fc seq_br_type 0 Branch False; Flow J cc=False 0x6fe seq_branch_adr 06fe 0x06fe seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06fd 06fd seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 06fe 06fe seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 06ff 06ff seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0700 0700 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x702 seq_br_type 1 Branch True seq_branch_adr 0702 0x0702 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0701 0701 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0702 0702 seq_br_type 0 Branch False; Flow J cc=False 0x704 seq_branch_adr 0704 0x0704 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 0703 0703 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0704 0704 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 0705 0705 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 0706 0706 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x708 seq_br_type 1 Branch True seq_branch_adr 0708 0x0708 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 0707 0707 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0708 0708 seq_br_type 0 Branch False; Flow J cc=False 0x70a seq_branch_adr 070a 0x070a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 0709 0709 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 070a 070a seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR18:00 typ_frame 18 070b 070b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 070c 070c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x70e seq_br_type 1 Branch True seq_branch_adr 070e 0x070e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 20 TR18:00 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 070d 070d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 070e 070e seq_br_type 0 Branch False; Flow J cc=False 0x710 seq_branch_adr 0710 0x0710 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 070f 070f seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0710 0710 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR18:02 typ_frame 18 0711 0711 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0712 0712 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x714 seq_br_type 1 Branch True seq_branch_adr 0714 0x0714 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 22 TR18:02 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0713 0713 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0714 0714 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 0715 0715 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x717 seq_br_type 1 Branch True seq_branch_adr 0717 0x0717 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 23 TR18:03 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR18:03 typ_frame 18 0716 0716 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0717 0717 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0718 0718 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x71a seq_br_type 1 Branch True seq_branch_adr 071a 0x071a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 27 TR18:07 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR18:07 typ_frame 18 0719 0719 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 071a 071a seq_br_type 1 Branch True; Flow J cc=True 0x71c seq_branch_adr 071c 0x071c seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3e TR12:1e typ_frame 12 val_rand 1 INC_LOOP_COUNTER 071b 071b seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 071c 071c seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3e TR12:1e typ_frame 12 071d 071d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3d TR13:1d typ_frame 13 071e 071e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x720 seq_br_type 0 Branch False seq_branch_adr 0720 0x0720 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3d TR13:1d typ_frame 13 071f 071f seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0720 0720 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x722 seq_br_type 1 Branch True seq_branch_adr 0722 0x0722 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3e TR12:1e typ_frame 12 0721 0721 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0722 0722 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3e TR12:1e typ_frame 12 0723 0723 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3d TR13:1d typ_frame 13 0724 0724 seq_br_type 0 Branch False; Flow J cc=False 0x726 seq_branch_adr 0726 0x0726 seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late) typ_b_adr 3d TR13:1d typ_frame 13 0725 0725 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0726 0726 seq_br_type 1 Branch True; Flow J cc=True 0x728 seq_branch_adr 0728 0x0728 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 3d TR12:1d typ_frame 12 val_rand 1 INC_LOOP_COUNTER 0727 0727 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0728 0728 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 3d TR12:1d typ_frame 12 0729 0729 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 21 TR13:01 typ_frame 13 072a 072a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x72c seq_br_type 0 Branch False seq_branch_adr 072c 0x072c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 21 TR13:01 typ_frame 13 072b 072b seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 072c 072c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x72e seq_br_type 1 Branch True seq_branch_adr 072e 0x072e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 3d TR12:1d typ_frame 12 072d 072d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 072e 072e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 3d TR12:1d typ_frame 12 072f 072f seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 21 TR13:01 typ_frame 13 0730 0730 seq_br_type 0 Branch False; Flow J cc=False 0x732 seq_branch_adr 0732 0x0732 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 21 TR13:01 typ_frame 13 0731 0731 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0732 0732 seq_br_type 1 Branch True; Flow J cc=True 0x734 seq_branch_adr 0734 0x0734 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 val_rand 1 INC_LOOP_COUNTER 0733 0733 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0734 0734 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 0735 0735 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR13:02 typ_frame 13 0736 0736 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x738 seq_br_type 0 Branch False seq_branch_adr 0738 0x0738 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR13:02 typ_frame 13 0737 0737 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0738 0738 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x73a seq_br_type 1 Branch True seq_branch_adr 073a 0x073a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 0739 0739 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 073a 073a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 073b 073b seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR13:02 typ_frame 13 073c 073c seq_br_type 0 Branch False; Flow J cc=False 0x73e seq_branch_adr 073e 0x073e seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR13:02 typ_frame 13 073d 073d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 073e 073e seq_br_type 1 Branch True; Flow J cc=True 0x740 seq_branch_adr 0740 0x0740 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 073f 073f seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0740 0740 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 0741 0741 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 23 TR13:03 typ_frame 13 0742 0742 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x744 seq_br_type 0 Branch False seq_branch_adr 0744 0x0744 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 23 TR13:03 typ_frame 13 0743 0743 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0744 0744 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x746 seq_br_type 1 Branch True seq_branch_adr 0746 0x0746 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 0745 0745 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0746 0746 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 0747 0747 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 23 TR13:03 typ_frame 13 0748 0748 seq_br_type 0 Branch False; Flow J cc=False 0x74a seq_branch_adr 074a 0x074a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 23 TR13:03 typ_frame 13 0749 0749 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 074a 074a seq_br_type 1 Branch True; Flow J cc=True 0x74c seq_branch_adr 074c 0x074c seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 23 TR12:03 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 074b 074b seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 074c 074c seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 23 TR12:03 typ_frame 12 074d 074d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 24 TR13:04 typ_frame 13 074e 074e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x750 seq_br_type 0 Branch False seq_branch_adr 0750 0x0750 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 24 TR13:04 typ_frame 13 074f 074f seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0750 0750 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x752 seq_br_type 1 Branch True seq_branch_adr 0752 0x0752 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 23 TR12:03 typ_frame 12 0751 0751 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0752 0752 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 23 TR12:03 typ_frame 12 0753 0753 seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 24 TR13:04 typ_frame 13 0754 0754 seq_br_type 0 Branch False; Flow J cc=False 0x756 seq_branch_adr 0756 0x0756 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 24 TR13:04 typ_frame 13 0755 0755 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0756 0756 seq_br_type 1 Branch True; Flow J cc=True 0x758 seq_branch_adr 0758 0x0758 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 val_rand 1 INC_LOOP_COUNTER 0757 0757 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0758 0758 seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 0759 0759 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 25 TR13:05 typ_frame 13 075a 075a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x75c seq_br_type 0 Branch False seq_branch_adr 075c 0x075c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 25 TR13:05 typ_frame 13 075b 075b seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 075c 075c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x75e seq_br_type 1 Branch True seq_branch_adr 075e 0x075e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 075d 075d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 075e 075e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 075f 075f seq_br_type 1 Branch True; Flow J cc=True 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 25 TR13:05 typ_frame 13 0760 0760 seq_br_type 0 Branch False; Flow J cc=False 0x762 seq_branch_adr 0762 0x0762 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 25 TR13:05 typ_frame 13 0761 0761 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0762 0762 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x764 seq_br_type 0 Branch False seq_branch_adr 0764 0x0764 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 val_rand 1 INC_LOOP_COUNTER 0763 0763 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0764 0764 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 3c TR12:1c typ_frame 12 0765 0765 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x767 seq_br_type 0 Branch False seq_branch_adr 0767 0x0767 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 0766 0766 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0767 0767 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 24 TR12:04 typ_frame 12 0768 0768 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x76a seq_br_type 0 Branch False seq_branch_adr 076a 0x076a seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 0769 0769 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 076a 076a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 3a TR12:1a typ_frame 12 076b 076b seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 29 TR12:09 typ_frame 12 076c 076c seq_br_type 1 Branch True; Flow J cc=True 0x76e seq_branch_adr 076e 0x076e seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 29 TR12:09 typ_frame 12 076d 076d seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 076e 076e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x770 seq_br_type 0 Branch False seq_branch_adr 0770 0x0770 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 22 TR18:02 typ_frame 18 076f 076f seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0770 0770 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 22 TR18:02 typ_frame 18 0771 0771 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x773 seq_br_type 0 Branch False seq_branch_adr 0773 0x0773 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 26 TR13:06 typ_frame 13 0772 0772 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0773 0773 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x775 seq_br_type 0 Branch False seq_branch_adr 0775 0x0775 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 27 TR13:07 typ_frame 13 0774 0774 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0775 0775 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x777 seq_br_type 0 Branch False seq_branch_adr 0777 0x0777 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) typ_b_adr 28 TR13:08 typ_frame 13 0776 0776 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 0777 0777 typ_a_adr 2f TR18:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 val_rand 1 INC_LOOP_COUNTER 0778 0778 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0779 0779 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077a 077a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077b 077b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077c 077c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077d 077d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077e 077e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 077f 077f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 0780 0780 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 0781 0781 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0782 0782 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0783 0783 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0784 0784 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0785 0785 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0786 0786 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0787 0787 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0788 0788 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0789 0789 typ_a_adr 2f TR18:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 078a 078a typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 078b 078b typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 078c 078c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 078d 078d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 078e 078e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 078f 078f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0790 0790 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0791 0791 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0792 0792 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 0793 0793 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 0794 0794 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0795 0795 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0796 0796 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0797 0797 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0798 0798 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0799 0799 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 079a 079a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 079b 079b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 079c 079c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 079d 079d seq_br_type 1 Branch True; Flow J cc=True 0x79f seq_branch_adr 079f 0x079f seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 079e 079e seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 079f 079f typ_a_adr 04 GP04 typ_alu_func 3 LEFT_I_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07a0 07a0 seq_br_type 1 Branch True; Flow J cc=True 0x7a2 seq_branch_adr 07a2 0x07a2 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07a1 07a1 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07a2 07a2 typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07a3 07a3 seq_br_type 1 Branch True; Flow J cc=True 0x7a5 seq_branch_adr 07a5 0x07a5 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07a4 07a4 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07a5 07a5 typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07a6 07a6 seq_br_type 1 Branch True; Flow J cc=True 0x7a8 seq_branch_adr 07a8 0x07a8 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07a7 07a7 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07a8 07a8 typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07a9 07a9 seq_br_type 1 Branch True; Flow J cc=True 0x7ab seq_branch_adr 07ab 0x07ab seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07aa 07aa seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07ab 07ab typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07ac 07ac seq_br_type 1 Branch True; Flow J cc=True 0x7ae seq_branch_adr 07ae 0x07ae seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07ad 07ad seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07ae 07ae typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07af 07af seq_br_type 1 Branch True; Flow J cc=True 0x7b1 seq_branch_adr 07b1 0x07b1 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07b0 07b0 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07b1 07b1 typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07b2 07b2 seq_br_type 1 Branch True; Flow J cc=True 0x7b4 seq_branch_adr 07b4 0x07b4 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 07b3 07b3 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07b4 07b4 seq_cond_sel 25 TYP.FALSE (early) val_rand 1 INC_LOOP_COUNTER 07b5 07b5 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07b6 07b6 seq_cond_sel 25 TYP.FALSE (early) 07b7 07b7 seq_b_timing 0 Early Condition; Flow J cc=False 0x7b9 seq_br_type 0 Branch False seq_branch_adr 07b9 0x07b9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07b8 07b8 seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07b9 07b9 seq_cond_sel 26 TYP.TRUE (early) 07ba 07ba seq_b_timing 0 Early Condition; Flow J cc=True 0x7bc seq_br_type 1 Branch True seq_branch_adr 07bc 0x07bc seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07bb 07bb seq_br_type 3 Unconditional Branch; Flow J 0x7f5 seq_branch_adr 07f5 0x07f5 07bc 07bc seq_cond_sel 26 TYP.TRUE (early) 07bd 07bd seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07be 07be seq_cond_sel 17 VAL.FALSE(early) 07bf 07bf seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07c0 07c0 seq_cond_sel 25 TYP.FALSE (early) 07c1 07c1 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07c2 07c2 seq_cond_sel 18 TYP.ALU_ZERO(late) 07c3 07c3 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07c4 07c4 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 13 ONES 07c5 07c5 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07c6 07c6 seq_cond_sel 25 TYP.FALSE (early) 07c7 07c7 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07c8 07c8 seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 21 TR18:01 typ_b_adr 21 TR18:01 typ_frame 18 07c9 07c9 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07ca 07ca seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late) typ_a_adr 27 TR18:07 typ_b_adr 21 TR18:01 typ_frame 18 07cb 07cb seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07cc 07cc seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 29 TR12:09 typ_b_adr 29 TR12:09 typ_frame 12 07cd 07cd seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07ce 07ce seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 20 TR18:00 typ_b_adr 21 TR18:01 typ_frame 18 07cf 07cf seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07d0 07d0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 29 TR12:09 typ_frame 12 07d1 07d1 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07d2 07d2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR18:02 typ_frame 18 07d3 07d3 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07d4 07d4 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 29 TR12:09 typ_frame 12 07d5 07d5 seq_b_timing 0 Early Condition; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07d6 07d6 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 22 TR18:02 typ_frame 18 07d7 07d7 seq_b_timing 0 Early Condition; Flow J cc=False 0x7f5 seq_br_type 0 Branch False seq_branch_adr 07f5 0x07f5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 07d8 07d8 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_rand 1 INC_LOOP_COUNTER 07d9 07d9 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 07da 07da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_rand d SET_PASS_PRIVACY_BIT 07db 07db typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07dc 07dc seq_br_type 0 Branch False; Flow J cc=False 0x7f5 seq_branch_adr 07f5 0x07f5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A 07dd 07dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07de 07de seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07df 07df typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07e0 07e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07e1 07e1 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 07e2 07e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A 07e3 07e3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A 07e4 07e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 07e5 07e5 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07e6 07e6 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07e7 07e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A 07e8 07e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 07e9 07e9 seq_b_timing 0 Early Condition; Flow J cc=False 0x7e4 seq_br_type 0 Branch False seq_branch_adr 07e4 0x07e4 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 07ea 07ea typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 07eb 07eb typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand d SET_PASS_PRIVACY_BIT 07ec 07ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_rand d SET_PASS_PRIVACY_BIT 07ed 07ed typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 07ee 07ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 07ef 07ef typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 07f0 07f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 07f1 07f1 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 07f2 07f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x7f5 seq_br_type 1 Branch True seq_branch_adr 07f5 0x07f5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A 07f3 07f3 seq_b_timing 0 Early Condition; Flow J cc=False 0x7ed seq_br_type 0 Branch False seq_branch_adr 07ed 0x07ed seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 07f4 07f4 seq_br_type 3 Unconditional Branch; Flow J 0x1800 seq_branch_adr 1800 0x1800 07f5 07f5 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 07f6 07f6 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 07f7 07f7 <halt> ; Flow R 07f8 07f8 <halt> ; Flow R 07f9 07f9 <halt> ; Flow R 07fa 07fa <halt> ; Flow R 07fb 07fb <halt> ; Flow R 07fc 07fc <halt> ; Flow R 07fd 07fd <halt> ; Flow R 07fe 07fe <halt> ; Flow R 07ff 07ff <halt> ; Flow R 0800 0800 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 0801 0801 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 0802 0802 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 0803 0803 seq_b_timing 0 Early Condition; Flow J cc=True 0x806 seq_br_type 1 Branch True seq_branch_adr 0806 0x0806 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0804 0804 seq_b_timing 0 Early Condition; Flow J cc=False 0x803 seq_br_type 0 Branch False seq_branch_adr 0803 0x0803 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? val_rand 2 DEC_LOOP_COUNTER 0805 0805 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0806 0806 seq_br_type 2 Push (branch address); Flow J 0x807 seq_branch_adr 0806 0x0806 0807 0807 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0808 0808 seq_random 06 Pop_stack+? 0809 0809 seq_b_timing 0 Early Condition; Flow J cc=True 0x80b seq_br_type 1 Branch True seq_branch_adr 080b 0x080b seq_cond_sel 47 SEQ.#_entries_in_stack_zero 080a 080a seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 080b 080b val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 080c 080c seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 080d 080d seq_br_type 2 Push (branch address); Flow J 0x80e seq_branch_adr 080c 0x080c val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 080e 080e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 080f 0x080f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 080f 080f seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0810 0x0810 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0810 0810 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0811 0811 seq_br_type 5 Call True; Flow C cc=True 0x80c seq_branch_adr 080c 0x080c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0812 0812 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0813 0813 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x80c seq_br_type 5 Call True seq_branch_adr 080c 0x080c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0814 0814 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0815 0815 seq_random 06 Pop_stack+? 0816 0816 seq_b_timing 0 Early Condition; Flow J cc=True 0x818 seq_br_type 1 Branch True seq_branch_adr 0818 0x0818 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0817 0817 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0818 0818 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0819 0819 seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 081a 081a seq_br_type 2 Push (branch address); Flow J 0x81b seq_branch_adr 0819 0x0819 val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 081b 081b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x81d seq_br_type 1 Branch True seq_branch_adr 081d 0x081d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 081c 081c seq_random 06 Pop_stack+? 081d 081d seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 081e 081e seq_br_type 5 Call True; Flow C cc=True 0x821 seq_branch_adr 0821 0x0821 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 081f 081f seq_b_timing 0 Early Condition; Flow J cc=False 0x822 seq_br_type 0 Branch False seq_branch_adr 0822 0x0822 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0820 0820 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0821 0821 seq_random 06 Pop_stack+? 0822 0822 seq_random 06 Pop_stack+? 0823 0823 seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0824 0824 seq_br_type 2 Push (branch address); Flow J 0x825 seq_branch_adr 0819 0x0819 0825 0825 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x827 seq_br_type 1 Branch True seq_branch_adr 0827 0x0827 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0826 0826 seq_br_type a Unconditional Return; Flow R 0827 0827 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0828 0828 seq_br_type 5 Call True; Flow C cc=True 0x82b seq_branch_adr 082b 0x082b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0829 0829 seq_b_timing 0 Early Condition; Flow J cc=False 0x82c seq_br_type 0 Branch False seq_branch_adr 082c 0x082c seq_cond_sel 47 SEQ.#_entries_in_stack_zero 082a 082a seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 082b 082b seq_br_type a Unconditional Return; Flow R 082c 082c seq_random 06 Pop_stack+? 082d 082d seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 082e 082e seq_br_type 2 Push (branch address); Flow J 0x82f seq_branch_adr 0819 0x0819 082f 082f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x831 seq_br_type 1 Branch True seq_branch_adr 0831 0x0831 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0830 0830 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 20 Clear_stack+Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0831 0831 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0832 0832 seq_br_type 5 Call True; Flow C cc=True 0x835 seq_branch_adr 0835 0x0835 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0833 0833 seq_b_timing 0 Early Condition; Flow J cc=False 0x836 seq_br_type 0 Branch False seq_branch_adr 0836 0x0836 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0834 0834 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0835 0835 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 20 Clear_stack+Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0836 0836 seq_random 06 Pop_stack+? 0837 0837 seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0838 0838 seq_br_type 2 Push (branch address); Flow J 0x839 seq_branch_adr 0819 0x0819 0839 0839 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x83b seq_br_type 1 Branch True seq_branch_adr 083b 0x083b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 083a 083a seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 083b 083b seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 083c 083c seq_br_type 5 Call True; Flow C cc=True 0x83f seq_branch_adr 083f 0x083f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 083d 083d seq_b_timing 0 Early Condition; Flow J cc=False 0x840 seq_br_type 0 Branch False seq_branch_adr 0840 0x0840 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 083e 083e seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 083f 083f seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0840 0840 seq_random 06 Pop_stack+? 0841 0841 seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0842 0842 seq_br_type 2 Push (branch address); Flow J 0x843 seq_branch_adr 0819 0x0819 0843 0843 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x845 seq_br_type 1 Branch True seq_branch_adr 0845 0x0845 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0844 0844 seq_br_type 2 Push (branch address); Flow J 0x845 seq_branch_adr 0819 0x0819 0845 0845 seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0846 0846 seq_br_type 5 Call True; Flow C cc=True 0x849 seq_branch_adr 0849 0x0849 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0847 0847 seq_b_timing 0 Early Condition; Flow J cc=False 0x84a seq_br_type 0 Branch False seq_branch_adr 084a 0x084a seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0848 0848 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0849 0849 seq_br_type 2 Push (branch address); Flow J 0x84a seq_branch_adr 0819 0x0819 084a 084a seq_random 06 Pop_stack+? 084b 084b seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 084c 084c seq_br_type 2 Push (branch address); Flow J 0x84d seq_branch_adr 0819 0x0819 084d 084d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x84f seq_br_type 1 Branch True seq_branch_adr 084f 0x084f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 084e 084e ioc_fiubs 2 typ ; Flow C cc=#0x0 0x819 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0819 0x0819 typ_a_adr 14 ZEROS 084f 084f seq_b_timing 0 Early Condition; Flow C cc=True 0x21b7 seq_br_type 5 Call True seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0850 0850 seq_br_type 5 Call True; Flow C cc=True 0x853 seq_branch_adr 0853 0x0853 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_frame 14 0851 0851 seq_b_timing 0 Early Condition; Flow J cc=False 0x856 seq_br_type 0 Branch False seq_branch_adr 0856 0x0856 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0852 0852 seq_br_type 7 Unconditional Call; Flow C 0x21b7 seq_branch_adr 21b7 0x21b7 0853 0853 ioc_fiubs 2 typ ; Flow C cc=#0x0 0x819 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0819 0x0819 typ_a_adr 14 ZEROS 0854 0854 seq_br_type 1 Branch True; Flow J cc=True 0xe28 seq_branch_adr 0e28 0x0e28 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 0e GP0e val_alu_func 0 PASS_A 0855 0855 seq_br_type 3 Unconditional Branch; Flow J 0xe55 seq_branch_adr 0e55 0x0e55 0856 0856 seq_random 06 Pop_stack+? 0857 0857 seq_b_timing 0 Early Condition; Flow C cc=False 0x21b7 seq_br_type 4 Call False seq_branch_adr 21b7 0x21b7 seq_cond_sel 47 SEQ.#_entries_in_stack_zero 0858 0858 seq_br_type 2 Push (branch address); Flow J 0x859 seq_branch_adr 0819 0x0819 0859 0859 ioc_adrbs 1 val typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES 085a 085a typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 085b 085b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 085c 085c typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 085d 085d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 085e 085e seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 085f 085f seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 0860 0860 seq_b_timing 0 Early Condition; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 0861 0861 seq_b_timing 0 Early Condition; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 0862 0862 seq_b_timing 1 Latch Condition; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_en_micro 0 0863 0863 seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 0864 0864 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 0865 0865 seq_b_timing 0 Early Condition; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 0866 0866 seq_b_timing 0 Early Condition; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 0867 0867 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x869 seq_br_type 1 Branch True seq_branch_adr 0869 0x0869 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0868 0868 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0869 0869 seq_br_type 5 Call True; Flow C cc=True 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 086a 086a seq_b_timing 0 Early Condition; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 086b 086b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 086c 086c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x86e seq_br_type 0 Branch False seq_branch_adr 086e 0x086e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 086d 086d seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 086e 086e seq_br_type 5 Call True; Flow C cc=True 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) val_rand 1 INC_LOOP_COUNTER 086f 086f seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0870 0870 seq_br_type 1 Branch True; Flow J cc=True 0x872 seq_branch_adr 0872 0x0872 seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0871 0871 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0872 0872 typ_rand e CHECK_CLASS_SYSTEM_B 0873 0873 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0874 0874 seq_br_type 1 Branch True; Flow J cc=True 0x876 seq_branch_adr 0876 0x0876 seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0875 0875 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0876 0876 val_rand 2 DEC_LOOP_COUNTER 0877 0877 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0878 0878 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) 0879 0879 seq_br_type 0 Branch False; Flow J cc=False 0x87b seq_branch_adr 087b 0x087b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 087a 087a seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 087b 087b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 087c 087c seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 087d 087d seq_br_type 1 Branch True; Flow J cc=True 0x87f seq_branch_adr 087f 0x087f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 087e 087e seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 087f 087f seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0880 0880 seq_br_type 1 Branch True; Flow J cc=True 0x882 seq_branch_adr 0882 0x0882 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0881 0881 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0882 0882 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0883 0883 seq_br_type 1 Branch True; Flow J cc=True 0x885 seq_branch_adr 0885 0x0885 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0884 0884 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0885 0885 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x887 seq_br_type 1 Branch True seq_branch_adr 0887 0x0887 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0886 0886 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0887 0887 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0888 0888 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0889 0889 seq_br_type 1 Branch True; Flow J cc=True 0x88b seq_branch_adr 088b 0x088b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 088a 088a seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 088b 088b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 088c 088c seq_br_type 1 Branch True; Flow J cc=True 0x88e seq_branch_adr 088e 0x088e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 088d 088d seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 088e 088e seq_br_type 5 Call True; Flow C cc=True 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 088f 088f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x891 seq_br_type 0 Branch False seq_branch_adr 0891 0x0891 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0890 0890 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0891 0891 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x893 seq_br_type 1 Branch True seq_branch_adr 0893 0x0893 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0892 0892 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0893 0893 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0894 0894 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0895 0895 seq_br_type 1 Branch True; Flow J cc=True 0x897 seq_branch_adr 0897 0x0897 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 0896 0896 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 0897 0897 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0898 0898 seq_br_type 1 Branch True; Flow J cc=True 0x89a seq_branch_adr 089a 0x089a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 0899 0899 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 089a 089a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 089b 089b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x89d seq_br_type 0 Branch False seq_branch_adr 089d 0x089d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 089c 089c seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 089d 089d seq_br_type 0 Branch False; Flow J cc=False 0x89f seq_branch_adr 089f 0x089f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 089e 089e seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 089f 089f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08a0 08a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08a1 08a1 seq_br_type 1 Branch True; Flow J cc=True 0x8a3 seq_branch_adr 08a3 0x08a3 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08a2 08a2 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08a3 08a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08a4 08a4 seq_br_type 1 Branch True; Flow J cc=True 0x8a6 seq_branch_adr 08a6 0x08a6 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08a5 08a5 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08a6 08a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08a7 08a7 seq_br_type 1 Branch True; Flow J cc=True 0x8a9 seq_branch_adr 08a9 0x08a9 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08a8 08a8 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08a9 08a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ab seq_br_type 1 Branch True seq_branch_adr 08ab 0x08ab seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08aa 08aa seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08ab 08ab seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08ac 08ac seq_br_type 5 Call True; Flow C cc=True 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08ad 08ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x8af seq_br_type 0 Branch False seq_branch_adr 08af 0x08af seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08ae 08ae seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08af 08af seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08b0 08b0 seq_br_type 1 Branch True; Flow J cc=True 0x8b2 seq_branch_adr 08b2 0x08b2 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08b1 08b1 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08b2 08b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08b3 08b3 seq_br_type 1 Branch True; Flow J cc=True 0x8b5 seq_branch_adr 08b5 0x08b5 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08b4 08b4 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08b5 08b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8b7 seq_br_type 1 Branch True seq_branch_adr 08b7 0x08b7 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08b6 08b6 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08b7 08b7 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08b8 08b8 seq_br_type 5 Call True; Flow C cc=True 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08b9 08b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x8bb seq_br_type 0 Branch False seq_branch_adr 08bb 0x08bb seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08ba 08ba seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08bb 08bb seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08bc 08bc seq_br_type 1 Branch True; Flow J cc=True 0x8be seq_branch_adr 08be 0x08be seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08bd 08bd seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08be 08be seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08bf 08bf seq_br_type 1 Branch True; Flow J cc=True 0x8c1 seq_branch_adr 08c1 0x08c1 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 08c0 08c0 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08c1 08c1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08c2 08c2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x8c4 seq_br_type 0 Branch False seq_branch_adr 08c4 0x08c4 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08c3 08c3 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08c4 08c4 seq_br_type 1 Branch True; Flow J cc=True 0x8c6 seq_branch_adr 08c6 0x08c6 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08c5 08c5 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08c6 08c6 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08c7 08c7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08c8 08c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ca seq_br_type 1 Branch True seq_branch_adr 08ca 0x08ca seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08c9 08c9 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08ca 08ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8cc seq_br_type 1 Branch True seq_branch_adr 08cc 0x08cc seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08cb 08cb seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08cc 08cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08cd 08cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8cf seq_br_type 1 Branch True seq_branch_adr 08cf 0x08cf seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 25 VR17:05 val_alu_func 7 INC_A val_frame 17 08ce 08ce seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08cf 08cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 3d VR19:1d val_alu_func 7 INC_A val_frame 19 08d0 08d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8d2 seq_br_type 1 Branch True seq_branch_adr 08d2 0x08d2 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 25 TR15:05 typ_alu_func 7 INC_A typ_frame 15 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08d1 08d1 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08d2 08d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 24 TR13:04 typ_alu_func 7 INC_A typ_frame 13 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08d3 08d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08d4 08d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x8d6 seq_br_type 0 Branch False seq_branch_adr 08d6 0x08d6 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08d5 08d5 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08d6 08d6 seq_br_type 1 Branch True; Flow J cc=True 0x8d8 seq_branch_adr 08d8 0x08d8 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08d7 08d7 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08d8 08d8 seq_br_type 4 Call False; Flow C cc=False 0x217e seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08d9 08d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08da 08da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8dc seq_br_type 1 Branch True seq_branch_adr 08dc 0x08dc seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08db 08db seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08dc 08dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8de seq_br_type 1 Branch True seq_branch_adr 08de 0x08de seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 08dd 08dd seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08de 08de seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x217e seq_br_type 4 Call False seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 6 A_MINUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08df 08df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8e1 seq_br_type 1 Branch True seq_branch_adr 08e1 0x08e1 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 25 VR17:05 val_alu_func 7 INC_A val_frame 17 08e0 08e0 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08e1 08e1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 3d VR19:1d val_alu_func 7 INC_A val_frame 19 08e2 08e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8e4 seq_br_type 1 Branch True seq_branch_adr 08e4 0x08e4 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 25 TR15:05 typ_alu_func 7 INC_A typ_frame 15 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08e3 08e3 seq_br_type 7 Unconditional Call; Flow C 0x217e seq_branch_adr 217e 0x217e 08e4 08e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217e seq_br_type 5 Call True seq_branch_adr 217e 0x217e seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 24 TR13:04 typ_alu_func 7 INC_A typ_frame 13 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 08e5 08e5 seq_br_type 1 Branch True; Flow J cc=True 0xe28 seq_branch_adr 0e28 0x0e28 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 0e GP0e val_alu_func 0 PASS_A 08e6 08e6 seq_br_type 3 Unconditional Branch; Flow J 0xe55 seq_branch_adr 0e55 0x0e55 08e7 ; -------------------------------------------------------------------------------------- 08e7 ; Comes from: 08e7 ; 0e28 C from color 0x0800 08e7 ; 0e55 C from color 0x0800 08e7 ; -------------------------------------------------------------------------------------- 08e7 08e7 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 08e8 08e8 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 32 VR19:12 val_frame 19 08e9 08e9 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 22 VR13:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08ea 08ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2180 seq_br_type 5 Call True seq_branch_adr 2180 0x2180 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR13:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08eb 08eb ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08ec 08ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2181 seq_br_type 5 Call True seq_branch_adr 2181 0x2181 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR13:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08ed 08ed ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 31 VR13:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08ee 08ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2182 seq_br_type 5 Call True seq_branch_adr 2182 0x2182 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR13:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08ef 08ef seq_random 55 ? 08f0 08f0 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_a_adr 22 VR13:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08f1 08f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2180 seq_br_type 5 Call True seq_branch_adr 2180 0x2180 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR13:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08f2 08f2 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08f3 08f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2187 seq_br_type 5 Call True seq_branch_adr 2187 0x2187 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR13:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08f4 08f4 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_a_adr 31 VR13:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 08f5 08f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2188 seq_br_type 5 Call True seq_branch_adr 2188 0x2188 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR13:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 08f6 08f6 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 08f7 08f7 val_a_adr 27 VR1a:07 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 08f8 08f8 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 08f9 08f9 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 55 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 08fa 08fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08fb 08fb ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 08fc 08fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08fd 08fd seq_b_timing 0 Early Condition; Flow J cc=False 0x8f8 seq_br_type 0 Branch False seq_branch_adr 08f8 0x08f8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 3 LEFT_I_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 08fe 08fe val_a_adr 2f VR1a:0f val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 08ff 08ff val_a_adr 30 VR13:10 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 0900 0900 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 0901 0901 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 55 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0902 0902 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0903 0903 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0904 0904 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0905 0905 seq_b_timing 0 Early Condition; Flow J cc=False 0x900 seq_br_type 0 Branch False seq_branch_adr 0900 0x0900 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 3 LEFT_I_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0906 0906 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0907 0907 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2183 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2183 0x2183 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 4 SAVE OFFSET seq_random 55 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0908 0908 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2189 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2189 0x2189 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0909 0909 val_a_adr 31 VR19:11 val_alu_func 10 NOT_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 090a 090a val_a_adr 27 VR1a:07 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 090b 090b seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 090c 090c ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 55 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 090d 090d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1d A_AND_NOT_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 090e 090e val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR13:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 090f 090f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0910 0910 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0911 0911 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1d A_AND_NOT_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0912 0912 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR13:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0913 0913 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0914 0914 seq_b_timing 0 Early Condition; Flow J cc=False 0x90b seq_br_type 0 Branch False seq_branch_adr 090b 0x090b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 4 LEFT_I_A_INC val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0915 0915 val_a_adr 2f VR1a:0f val_alu_func 10 NOT_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0916 0916 val_a_adr 30 VR13:10 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 0917 0917 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 0918 0918 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 55 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0919 0919 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1d A_AND_NOT_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 091a 091a val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR13:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 091b 091b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217f seq_br_type 5 Call True seq_branch_adr 217f 0x217f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 091c 091c ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 5b ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 091d 091d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1d A_AND_NOT_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 091e 091e val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR13:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 091f 091f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2186 seq_br_type 5 Call True seq_branch_adr 2186 0x2186 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0920 0920 seq_b_timing 0 Early Condition; Flow J cc=False 0x917 seq_br_type 0 Branch False seq_branch_adr 0917 0x0917 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 4 LEFT_I_A_INC val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0921 0921 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0922 0922 typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0923 0923 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0924 0924 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2183 seq_br_type 5 Call True seq_branch_adr 2183 0x2183 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0925 0925 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0926 0926 seq_random 16 ? 0927 0927 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0928 0928 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2184 seq_br_type 5 Call True seq_branch_adr 2184 0x2184 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0929 0929 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 092a 092a seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 092b 092b ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 092c 092c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 092d 092d seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 092e 092e ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 092f 092f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 0930 0930 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 32 VR19:12 val_frame 19 0931 0931 ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 0932 0932 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 0933 0933 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 32 VR19:12 val_frame 19 0934 0934 ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 0935 0935 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 0936 0936 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 0937 0937 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 29 VR1a:09 val_alu_func 0 PASS_A val_b_adr 3f VR1a:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0938 0938 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 0939 0939 ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 093a 093a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 093b 093b seq_b_timing 0 Early Condition; Flow J cc=False 0x938 seq_br_type 0 Branch False seq_branch_adr 0938 0x0938 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 3 LEFT_I_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 093c 093c val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 093d 093d val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 093e 093e seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 093f 093f ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 0940 0940 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0941 0941 seq_b_timing 0 Early Condition; Flow J cc=False 0x93e seq_br_type 0 Branch False seq_branch_adr 093e 0x093e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 3 LEFT_I_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0942 0942 val_a_adr 31 VR19:11 val_alu_func 10 NOT_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 0943 0943 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 0944 0944 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 0d GP0d 0945 0945 ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 0946 0946 val_a_adr 01 GP01 val_alu_func 17 A_OR_NOT_B val_b_adr 2f VR14:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 0947 0947 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0948 0948 seq_b_timing 0 Early Condition; Flow J cc=False 0x944 seq_br_type 0 Branch False seq_branch_adr 0944 0x0944 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 4 LEFT_I_A_INC val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0949 0949 val_a_adr 31 VR19:11 val_alu_func 10 NOT_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 094a 094a val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 094b 094b seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 0d GP0d 094c 094c ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 094d 094d val_a_adr 01 GP01 val_alu_func 17 A_OR_NOT_B val_b_adr 2f VR14:0f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 094e 094e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2197 seq_br_type 5 Call True seq_branch_adr 2197 0x2197 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 0d GP0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU 094f 094f seq_b_timing 0 Early Condition; Flow J cc=False 0x94b seq_br_type 0 Branch False seq_branch_adr 094b 0x094b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 4 LEFT_I_A_INC val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0950 0950 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 0951 0951 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0952 0952 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0953 0953 seq_random 36 Load_ibuff+? 0954 0954 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0955 0955 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2185 seq_br_type 5 Call True seq_branch_adr 2185 0x2185 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 0956 0956 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 32 VR19:12 val_frame 19 0957 0957 seq_random 36 Load_ibuff+? 0958 0958 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0959 0959 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2185 seq_br_type 5 Call True seq_branch_adr 2185 0x2185 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR13:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 095a 095a val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 095b 095b val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 095c 095c val_a_adr 2e VR13:0e val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 095d 095d seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 095e 095e seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 095f 095f seq_random 36 Load_ibuff+? 0960 0960 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0961 0961 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2185 seq_br_type 5 Call True seq_branch_adr 2185 0x2185 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0962 0962 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0963 0963 seq_b_timing 0 Early Condition; Flow J cc=False 0x95d seq_br_type 0 Branch False seq_branch_adr 095d 0x095d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 0d GP0d val_alu_func 3 LEFT_I_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0964 0964 seq_int_reads 0 TYP VAL BUS seq_random 52 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0965 0965 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0d GP0d 0966 0966 seq_random 36 Load_ibuff+? 0967 0967 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 32 VR13:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0968 0968 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2185 seq_br_type 5 Call True seq_branch_adr 2185 0x2185 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR13:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0969 0969 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 096a 096a seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 096b 096b ioc_tvbs 5 seq+seq; Flow C cc=True 0x218a seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 096c 096c ioc_tvbs 5 seq+seq; Flow C cc=True 0x218b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 096d 096d seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 096e 096e ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 096f 096f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218a seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 0970 0970 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0971 0971 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218b seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 0972 0972 seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0973 0973 ioc_tvbs 5 seq+seq; Flow C cc=True 0x218a seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0974 0974 ioc_tvbs 5 seq+seq; Flow C cc=True 0x218b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0975 0975 typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 1a 0976 0976 typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 0977 0977 seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 0d GP0d val_b_adr 30 VR14:10 val_frame 14 0978 0978 ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0979 0979 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218a seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 097a 097a ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 097b 097b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218b seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 097c 097c seq_b_timing 0 Early Condition; Flow J cc=False 0x977 seq_br_type 0 Branch False seq_branch_adr 0977 0x0977 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 0d GP0d typ_alu_func 3 LEFT_I_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 097d 097d typ_a_adr 3c TR1a:1c typ_alu_func 10 NOT_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 1a 097e 097e typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 097f 097f seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 0d GP0d val_b_adr 30 VR14:10 val_frame 14 0980 0980 ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0981 0981 typ_a_adr 01 GP01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 27 TR14:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0982 0982 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218a seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0983 0983 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0984 0984 typ_a_adr 01 GP01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 27 TR14:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0985 0985 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218b seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0986 0986 seq_b_timing 0 Early Condition; Flow J cc=False 0x97f seq_br_type 0 Branch False seq_branch_adr 097f 0x097f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 0d GP0d typ_alu_func 4 LEFT_I_A_INC typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 0987 0987 seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0988 0988 seq_int_reads 6 CONTROL TOP seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0989 0989 ioc_tvbs 5 seq+seq; Flow C cc=True 0x218c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218c 0x218c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 098a 098a val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 098b 098b ioc_fiubs 1 val seq_random 58 Load_control_pred+Load_control_pred+? val_a_adr 30 VR14:10 val_frame 14 098c 098c ioc_tvbs 5 seq+seq; Flow C cc=True 0x218d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218d 0x218d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 14 098d 098d ioc_tvbs 5 seq+seq; Flow C cc=True 0x218e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218e 0x218e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 14 098e 098e ioc_fiubs 1 val seq_random 58 Load_control_pred+Load_control_pred+? val_a_adr 32 VR19:12 val_frame 19 098f 098f ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0990 0990 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218d seq_br_type 5 Call True seq_branch_adr 218d 0x218d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 0991 0991 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0992 0992 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218e seq_br_type 5 Call True seq_branch_adr 218e 0x218e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 0993 0993 typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 1a 0994 0994 typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 0995 0995 ioc_fiubs 2 typ seq_random 58 Load_control_pred+Load_control_pred+? typ_a_adr 0d GP0d 0996 0996 ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0997 0997 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218a seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0998 0998 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 0999 0999 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218b seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 099a 099a seq_b_timing 0 Early Condition; Flow J cc=False 0x995 seq_br_type 0 Branch False seq_branch_adr 0995 0x0995 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 0d GP0d typ_alu_func 3 LEFT_I_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 099b 099b typ_a_adr 3c TR1a:1c typ_alu_func 10 NOT_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 1a 099c 099c typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 099d 099d ioc_fiubs 2 typ seq_random 58 Load_control_pred+Load_control_pred+? typ_a_adr 0d GP0d 099e 099e ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 099f 099f typ_a_adr 01 GP01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 27 TR14:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09a0 09a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218a seq_br_type 5 Call True seq_branch_adr 218a 0x218a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09a1 09a1 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09a2 09a2 typ_a_adr 01 GP01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 27 TR14:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09a3 09a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218b seq_br_type 5 Call True seq_branch_adr 218b 0x218b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0d GP0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09a4 09a4 seq_b_timing 0 Early Condition; Flow J cc=False 0x99d seq_br_type 0 Branch False seq_branch_adr 099d 0x099d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 0d GP0d typ_alu_func 4 LEFT_I_A_INC typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 09a5 09a5 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 09a6 09a6 seq_int_reads 0 TYP VAL BUS seq_random 56 Load_control_pred+Load_control_pred+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 09a7 09a7 typ_csa_cntl 2 PUSH_CSA 09a8 09a8 ioc_tvbs 5 seq+seq; Flow C cc=True 0x218f seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 218f 0x218f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09a9 09a9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x218f seq_br_type 5 Call True seq_branch_adr 218f 0x218f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3c TR1a:1c typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 1a val_b_adr 30 VR14:10 val_frame 14 09aa 09aa typ_csa_cntl 3 POP_CSA 09ab 09ab ioc_tvbs 5 seq+seq; Flow C cc=True 0x2190 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2190 0x2190 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09ac 09ac ioc_tvbs 5 seq+seq; Flow C cc=True 0x21a0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21a0 0x21a0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2a TR14:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09ad 09ad ioc_tvbs 5 seq+seq; Flow C cc=True 0x21a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21a1 0x21a1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2a TR14:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 14 09ae 09ae ioc_tvbs 5 seq+seq; Flow C cc=True 0x21a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21a2 0x21a2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2a TR14:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 14 09af 09af ioc_tvbs 5 seq+seq; Flow C cc=True 0x21a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21a3 0x21a3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2a TR14:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 14 09b0 09b0 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 09b1 09b1 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09b2 09b2 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09b3 09b3 seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 09b4 09b4 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2195 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2195 0x2195 seq_cond_sel 43 SEQ.loop_counter_zero seq_int_reads 5 RESOLVE RAM 09b5 09b5 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09b6 09b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2191 seq_br_type 5 Call True seq_branch_adr 2191 0x2191 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09b7 09b7 seq_br_type 1 Branch True; Flow J cc=True 0x9b2 seq_branch_adr 09b2 0x09b2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09b8 09b8 seq_random 0a ? 09b9 09b9 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09ba 09ba seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09bb 09bb seq_br_type 4 Call False; Flow C cc=False 0x2196 seq_branch_adr 2196 0x2196 seq_cond_sel 43 SEQ.loop_counter_zero 09bc 09bc seq_br_type 1 Branch True; Flow J cc=True 0x9ba seq_branch_adr 09ba 0x09ba seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09bd 09bd val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09be 09be seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09bf 09bf seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 09c0 09c0 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2195 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2195 0x2195 seq_cond_sel 43 SEQ.loop_counter_zero seq_int_reads 5 RESOLVE RAM 09c1 09c1 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09c2 09c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2193 seq_br_type 5 Call True seq_branch_adr 2193 0x2193 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR14:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 09c3 09c3 seq_br_type 1 Branch True; Flow J cc=True 0x9be seq_branch_adr 09be 0x09be seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09c4 09c4 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09c5 09c5 typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 09c6 09c6 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09c7 09c7 seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 0d GP0d val_b_adr 30 VR14:10 val_frame 14 09c8 09c8 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09c9 09c9 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09ca 09ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2193 seq_br_type 5 Call True seq_branch_adr 2193 0x2193 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09cb 09cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x9c6 seq_br_type 0 Branch False seq_branch_adr 09c6 0x09c6 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 0d GP0d typ_alu_func 3 LEFT_I_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU 09cc 09cc seq_br_type 1 Branch True; Flow J cc=True 0x9c5 seq_branch_adr 09c5 0x09c5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09cd 09cd val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09ce 09ce typ_a_adr 21 TR18:01 typ_alu_func 10 NOT_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 18 09cf 09cf seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09d0 09d0 seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 0d GP0d val_b_adr 32 VR19:12 val_frame 19 09d1 09d1 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09d2 09d2 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09d3 09d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2193 seq_br_type 5 Call True seq_branch_adr 2193 0x2193 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09d4 09d4 seq_br_type 1 Branch True; Flow J cc=True 0x9cf seq_branch_adr 09cf 0x09cf seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 0d GP0d typ_alu_func 4 LEFT_I_A_INC typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU 09d5 09d5 seq_br_type 1 Branch True; Flow J cc=True 0x9ce seq_branch_adr 09ce 0x09ce seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09d6 09d6 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09d7 09d7 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09d8 09d8 seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_b_adr 03 GP03 val_b_adr 32 VR19:12 val_frame 19 09d9 09d9 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09da 09da typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09db 09db seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2193 seq_br_type 5 Call True seq_branch_adr 2193 0x2193 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09dc 09dc seq_br_type 1 Branch True; Flow J cc=True 0x9d7 seq_branch_adr 09d7 0x09d7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 28 TR1a:08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09dd 09dd val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 09de 09de typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 09df 09df ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09e0 09e0 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09e1 09e1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2194 seq_br_type 5 Call True seq_branch_adr 2194 0x2194 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09e2 09e2 typ_a_adr 28 TR1a:08 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 09e3 09e3 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09e4 09e4 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09e5 09e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2194 seq_br_type 5 Call True seq_branch_adr 2194 0x2194 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09e6 09e6 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09e7 09e7 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09e8 09e8 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09e9 09e9 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09ea 09ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2194 seq_br_type 5 Call True seq_branch_adr 2194 0x2194 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09eb 09eb seq_br_type 1 Branch True; Flow J cc=True 0x9e7 seq_branch_adr 09e7 0x09e7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 28 TR1a:08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09ec 09ec typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 31 VR19:11 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 19 09ed 09ed seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 3e ? typ_b_adr 03 GP03 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09ee 09ee seq_br_type 1 Branch True; Flow J cc=True 0x9ed seq_branch_adr 09ed 0x09ed seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 28 TR1a:08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3c VR14:1c val_frame 14 09ef 09ef typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 09f0 09f0 seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 09 GP09 val_alu_func 7 INC_A val_b_adr 09 GP09 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 09f1 09f1 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 09f2 09f2 typ_a_adr 29 TR14:09 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 09f3 09f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2194 seq_br_type 5 Call True seq_branch_adr 2194 0x2194 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 09f4 09f4 seq_br_type 1 Branch True; Flow J cc=True 0x9f0 seq_branch_adr 09f0 0x09f0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 28 TR1a:08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 09f5 09f5 seq_br_type 3 Unconditional Branch; Flow J 0x1e00 seq_branch_adr 1e00 0x1e00 09f6 09f6 <halt> ; Flow R 09f7 09f7 <halt> ; Flow R 09f8 09f8 <halt> ; Flow R 09f9 09f9 <halt> ; Flow R 09fa 09fa <halt> ; Flow R 09fb 09fb <halt> ; Flow R 09fc 09fc <halt> ; Flow R 09fd 09fd <halt> ; Flow R 09fe 09fe <halt> ; Flow R 09ff 09ff <halt> ; Flow R 0a00 ; -------------------------------------------------------------------------------------- 0a00 ; Comes from: 0a00 ; 0e29 C from color 0x0800 0a00 ; 0e58 C from color 0x0e07 0a00 ; -------------------------------------------------------------------------------------- 0a00 0a00 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a01 0a01 val_a_adr 3b VR1a:1b val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a02 0a02 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 0a03 0a03 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_a_adr 3a VR1a:1a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 1a 0a04 0a04 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb35 seq_br_type 5 Call True seq_branch_adr 0b35 0x0b35 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a05 0a05 seq_b_timing 0 Early Condition; Flow J cc=False 0xa02 seq_br_type 0 Branch False seq_branch_adr 0a02 0x0a02 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0a06 0a06 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a07 0a07 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg 0a08 0a08 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a09 0a09 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a0a 0a0a fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a0b 0a0b fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a0c 0a0c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a0d 0a0d seq_b_timing 0 Early Condition; Flow C cc=False 0xb37 seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a0e 0a0e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f 0a0f 0a0f fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a10 0a10 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a11 0a11 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a12 0a12 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a13 0a13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a14 0a14 seq_b_timing 0 Early Condition; Flow C cc=False 0xb37 seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a15 0a15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 0a16 0a16 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a17 0a17 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a18 0a18 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a19 0a19 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a1a 0a1a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a1b 0a1b seq_b_timing 0 Early Condition; Flow C cc=False 0xb37 seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a1c 0a1c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 0a1d 0a1d fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a1e 0a1e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a1f 0a1f fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a20 0a20 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a21 0a21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a22 0a22 seq_b_timing 0 Early Condition; Flow C cc=True 0xb37 seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a23 0a23 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 0a24 0a24 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a25 0a25 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a26 0a26 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a27 0a27 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a28 0a28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 42 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a29 0a29 seq_b_timing 0 Early Condition; Flow C cc=True 0xb37 seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a2a 0a2a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e 0a2b 0a2b fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a2c 0a2c fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a2d 0a2d fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a2e 0a2e fiu_len_fill_lit 01 sign-fill 0x1; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a2f 0a2f fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a30 0a30 fiu_len_fill_lit 02 sign-fill 0x2; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a31 0a31 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a32 0a32 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a33 0a33 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a34 0a34 seq_b_timing 0 Early Condition; Flow C cc=True 0xb37 seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a35 0a35 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f 0a36 0a36 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a37 0a37 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a38 0a38 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a39 0a39 fiu_len_fill_lit 01 sign-fill 0x1; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a3a 0a3a fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a3b 0a3b fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a3c 0a3c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xb37 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a3d 0a3d seq_b_timing 0 Early Condition; Flow C cc=True 0xb37 seq_br_type 5 Call True seq_branch_adr 0b37 0x0b37 seq_cond_sel 65 CROSS_WORD_FIELD~ 0a3e 0a3e val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a3f 0a3f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 39 VR1a:19 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a40 0a40 typ_a_adr 3d TR1a:1d typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1a 0a41 0a41 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0a42 0a42 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa44 seq_br_type 0 Branch False seq_branch_adr 0a44 0x0a44 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0a43 0a43 seq_br_type 7 Unconditional Call; Flow C 0xb39 seq_branch_adr 0b39 0x0b39 0a44 0a44 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0a45 0a45 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa47 seq_br_type 0 Branch False seq_branch_adr 0a47 0x0a47 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0a46 0a46 seq_br_type 7 Unconditional Call; Flow C 0xb39 seq_branch_adr 0b39 0x0b39 0a47 0a47 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 3c TR1a:1c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 0a48 0a48 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3c TR1a:1c typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1a 0a49 0a49 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0a4a 0a4a seq_br_type 4 Call False; Flow C cc=False 0xb39 seq_branch_adr 0b39 0x0b39 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0a4b 0a4b fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0a4c 0a4c seq_br_type 4 Call False; Flow C cc=False 0xb39 seq_branch_adr 0b39 0x0b39 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0a4d 0a4d seq_b_timing 0 Early Condition; Flow J cc=False 0xa47 seq_br_type 0 Branch False seq_branch_adr 0a47 0x0a47 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0a4e 0a4e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_mar_cntl b LOAD_MAR_DATA 0a4f 0a4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb39 seq_br_type 5 Call True seq_branch_adr 0b39 0x0b39 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_mar_cntl 6 INCREMENT_MAR 0a50 0a50 seq_br_type 4 Call False; Flow C cc=False 0xb39 seq_branch_adr 0b39 0x0b39 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0a51 0a51 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a52 0a52 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a53 0a53 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a54 0a54 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3b 0x0b3b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a55 0a55 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 04 GP04 0a56 0a56 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a57 0a57 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3b 0x0b3b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a58 0a58 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a59 0a59 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3b 0x0b3b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a5a 0a5a fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 04 GP04 0a5b 0a5b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a5c 0a5c ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3b 0x0b3b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a5d 0a5d fiu_load_var 1 hold_var; Flow J cc=True 0xa59 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0a59 0x0a59 val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a5e 0a5e val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a5f 0a5f fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a60 0a60 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 03 GP03 val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a61 0a61 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3d 0x0b3d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a62 0a62 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 04 GP04 0a63 0a63 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a64 0a64 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3d 0x0b3d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a65 0a65 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a66 0a66 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3d 0x0b3d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a67 0a67 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 04 GP04 0a68 0a68 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a69 0a69 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb3d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3d 0x0b3d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a6a 0a6a fiu_load_var 1 hold_var; Flow J cc=True 0xa66 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0a66 0x0a66 val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0a6b 0a6b val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a6c 0a6c fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc typ_a_adr 3a TR1a:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 38 VR1a:18 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a6d 0a6d fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_tivi_src 8 type_var typ_alu_func 1a PASS_B typ_b_adr 2a TR18:0a typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0a6e 0a6e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 32 VR19:12 val_frame 19 0a6f 0a6f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_tivi_src 9 type_val typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0a70 0a70 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb3f seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3f 0x0b3f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a71 0a71 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 35 TR12:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 30 VR14:10 val_frame 14 0a72 0a72 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_tivi_src 9 type_val typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0a73 0a73 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb3f seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b3f 0x0b3f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 16 A_XNOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 16 A_XNOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a74 0a74 fiu_len_fill_reg_ctl 2 fiu_tivi_src 8 type_var typ_b_adr 03 GP03 typ_rand d SET_PASS_PRIVACY_BIT val_rand 2 DEC_LOOP_COUNTER 0a75 0a75 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa6e seq_br_type 0 Branch False seq_branch_adr 0a6e 0x0a6e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 37 VR1a:17 val_frame 1a 0a76 0a76 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a77 0a77 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg typ_a_adr 38 TR1a:18 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a78 0a78 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 32 VR19:12 val_frame 19 0a79 0a79 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0a7a 0a7a ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb43 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b43 0x0b43 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 16 A_XNOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 32 VR19:12 val_alu_func 16 A_XNOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 0a7b 0a7b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 30 VR14:10 val_frame 14 0a7c 0a7c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0a7d 0a7d ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb43 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b43 0x0b43 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 0a7e 0a7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xa79 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0a79 0x0a79 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 32 VR19:12 val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0a7f 0a7f val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a80 0a80 typ_a_adr 3a TR1a:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 38 VR1a:18 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a81 0a81 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 0a82 0a82 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 32 VR19:12 val_frame 19 0a83 0a83 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0a84 0a84 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb41 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b41 0x0b41 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a85 0a85 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 30 VR14:10 val_frame 14 0a86 0a86 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0a87 0a87 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb41 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b41 0x0b41 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 16 A_XNOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 16 A_XNOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a88 0a88 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 32 VR19:12 val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0a89 0a89 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa83 seq_br_type 0 Branch False seq_branch_adr 0a83 0x0a83 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 37 VR1a:17 val_frame 1a 0a8a 0a8a val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0a8b 0a8b typ_a_adr 3a TR1a:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 38 VR1a:18 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0a8c 0a8c typ_a_adr 2a TR18:0a typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 0a8d 0a8d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_b_adr 06 GP06 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_b_adr 32 VR19:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 19 0a8e 0a8e typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a8f 0a8f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 0a90 0a90 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0a91 0a91 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb45 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b45 0x0b45 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a92 0a92 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 0a93 0a93 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0xa91 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a91 0x0a91 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0a94 0a94 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb45 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b45 0x0b45 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a95 0a95 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val val_a_adr 06 GP06 val_alu_func 0 PASS_A val_b_adr 30 VR14:10 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 14 0a96 0a96 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0a97 0a97 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 0a98 0a98 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0a99 0a99 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb45 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b45 0x0b45 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 16 A_XNOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 16 A_XNOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a9a 0a9a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 22 TR18:02 typ_frame 18 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_b_adr 32 VR19:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 0a9b 0a9b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0xa99 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a99 0x0a99 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0a9c 0a9c ioc_tvbs 3 fiu+fiu; Flow C cc=True 0xb45 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b45 0x0b45 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 16 A_XNOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 16 A_XNOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0a9d 0a9d typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 35 TR12:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 7 INC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0a9e 0a9e fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0xa8d fiu_tivi_src c mar_0xc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a8d 0x0a8d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 37 VR1a:17 val_frame 1a 0a9f 0a9f val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0aa0 0aa0 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0aa1 0aa1 val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0aa2 0aa2 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 31 VR19:11 val_alu_func 1a PASS_B val_b_adr 31 VR19:11 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 0aa3 0aa3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 06 GP06 val_alu_func 0 PASS_A 0aa4 0aa4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 30 VR14:10 val_frame 14 0aa5 0aa5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0aa6 0aa6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb47 seq_br_type 5 Call True seq_branch_adr 0b47 0x0b47 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0aa7 0aa7 val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0aa8 0aa8 seq_b_timing 0 Early Condition; Flow J cc=False 0xaa3 seq_br_type 0 Branch False seq_branch_adr 0aa3 0x0aa3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0aa9 0aa9 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 30 VR14:10 val_frame 14 0aaa 0aaa val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0aab 0aab val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 0aac 0aac fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 06 GP06 val_alu_func 0 PASS_A 0aad 0aad fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 31 VR19:11 val_frame 19 0aae 0aae fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0aaf 0aaf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb47 seq_br_type 5 Call True seq_branch_adr 0b47 0x0b47 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ab0 0ab0 val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0ab1 0ab1 seq_b_timing 0 Early Condition; Flow J cc=False 0xaac seq_br_type 0 Branch False seq_branch_adr 0aac 0x0aac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0ab2 0ab2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0ab3 0ab3 val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0ab4 0ab4 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 33 VR1a:13 val_alu_func 1a PASS_B val_b_adr 33 VR1a:13 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 0ab5 0ab5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 06 GP06 val_alu_func 0 PASS_A 0ab6 0ab6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 32 VR19:12 val_frame 19 0ab7 0ab7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ab8 0ab8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb47 seq_br_type 5 Call True seq_branch_adr 0b47 0x0b47 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ab9 0ab9 val_a_adr 05 GP05 val_alu_func 4 LEFT_I_A_INC val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0aba 0aba seq_b_timing 0 Early Condition; Flow J cc=False 0xab5 seq_br_type 0 Branch False seq_branch_adr 0ab5 0x0ab5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0abb 0abb fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 32 VR19:12 val_frame 19 0abc 0abc val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0abd 0abd val_a_adr 33 VR1a:13 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 0abe 0abe fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 06 GP06 val_alu_func 0 PASS_A 0abf 0abf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 33 VR1a:13 val_frame 1a 0ac0 0ac0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ac1 0ac1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb47 seq_br_type 5 Call True seq_branch_adr 0b47 0x0b47 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ac2 0ac2 val_a_adr 05 GP05 val_alu_func 4 LEFT_I_A_INC val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0ac3 0ac3 seq_b_timing 0 Early Condition; Flow J cc=False 0xabe seq_br_type 0 Branch False seq_branch_adr 0abe 0x0abe seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 val_rand 2 DEC_LOOP_COUNTER 0ac4 0ac4 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0ac5 0ac5 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 0ac6 0ac6 val_a_adr 36 VR1a:16 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0ac7 0ac7 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 3b VR1a:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 1a 0ac8 0ac8 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 0ac9 0ac9 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0aca 0aca typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1c DEC_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0acb 0acb typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 0acc 0acc val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0acd 0acd fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val typ_b_adr 06 GP06 val_a_adr 06 GP06 val_alu_func 0 PASS_A 0ace 0ace fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value typ_b_adr 04 GP04 val_b_adr 04 GP04 0acf 0acf ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb4b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b4b 0x0b4b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ad0 0ad0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value typ_b_adr 04 GP04 val_b_adr 04 GP04 0ad1 0ad1 ioc_tvbs 1 typ+fiu; Flow C cc=True 0xb4b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b4b 0x0b4b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 0ad2 0ad2 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0ad3 0ad3 seq_b_timing 0 Early Condition; Flow J cc=False 0xacd seq_br_type 0 Branch False seq_branch_adr 0acd 0x0acd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ad4 0ad4 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0xac9 fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ac9 0x0ac9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 35 TR12:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 03 GP03 val_alu_func 4 LEFT_I_A_INC val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0ad5 0ad5 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0ad6 0ad6 val_a_adr 3a VR1a:1a val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 1a 0ad7 0ad7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_b_adr 20 TR18:00 typ_c_adr 35 GP0a typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 0ad8 0ad8 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 30 VR1a:10 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0ad9 0ad9 typ_a_adr 0a GP0a typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0a GP0a val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0ada 0ada fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_b_adr 22 TR18:02 typ_frame 18 val_a_adr 0b GP0b val_alu_func 0 PASS_A val_b_adr 0d GP0d 0adb 0adb typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0adc 0adc val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 0add 0add seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xaf5 seq_br_type 1 Branch True seq_branch_adr 0af5 0x0af5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_a_adr 36 VR1a:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 0ade 0ade fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0adf 0adf fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ae0 0ae0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ae1 0ae1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0ae2 0ae2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ae3 0ae3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ae4 0ae4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xae9 seq_br_type 1 Branch True seq_branch_adr 0ae9 0x0ae9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 0b GP0b typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0ae5 0ae5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xae7 seq_br_type 0 Branch False seq_branch_adr 0ae7 0x0ae7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0ae6 0ae6 seq_br_type 3 Unconditional Branch; Flow J 0xafe seq_branch_adr 0afe 0x0afe val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 14 0ae7 0ae7 seq_b_timing 0 Early Condition; Flow J cc=False 0xade seq_br_type 0 Branch False seq_branch_adr 0ade 0x0ade seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0ae8 0ae8 seq_br_type 3 Unconditional Branch; Flow J 0xb0b seq_branch_adr 0b0b 0x0b0b 0ae9 0ae9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xafc seq_br_type 1 Branch True seq_branch_adr 0afc 0x0afc seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 31 VR1a:11 val_frame 1a 0aea 0aea seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xaec seq_br_type 0 Branch False seq_branch_adr 0aec 0x0aec seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0aeb 0aeb seq_br_type 3 Unconditional Branch; Flow J 0xb03 seq_branch_adr 0b03 0x0b03 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 14 0aec 0aec fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0aed 0aed fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0aee 0aee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0aef 0aef fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0af0 0af0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0af1 0af1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0af2 0af2 typ_a_adr 0b GP0b typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0af3 0af3 seq_b_timing 0 Early Condition; Flow J cc=False 0xae9 seq_br_type 0 Branch False seq_branch_adr 0ae9 0x0ae9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0af4 0af4 seq_br_type 3 Unconditional Branch; Flow J 0xb0b seq_branch_adr 0b0b 0x0b0b 0af5 0af5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0af6 0af6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0af7 0af7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0af8 0af8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0af9 0af9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0afa 0afa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0afb 0afb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xb00 seq_br_type 1 Branch True seq_branch_adr 0b00 0x0b00 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 0b GP0b typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0afc 0afc seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xafe seq_br_type 0 Branch False seq_branch_adr 0afe 0x0afe seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0afd 0afd seq_br_type 3 Unconditional Branch; Flow J 0xae7 seq_branch_adr 0ae7 0x0ae7 val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 14 0afe 0afe seq_b_timing 0 Early Condition; Flow J cc=False 0xaf5 seq_br_type 0 Branch False seq_branch_adr 0af5 0x0af5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0aff 0aff seq_br_type 3 Unconditional Branch; Flow J 0xb0b seq_branch_adr 0b0b 0x0b0b 0b00 0b00 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xae5 seq_br_type 1 Branch True seq_branch_adr 0ae5 0x0ae5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 31 VR1a:11 val_frame 1a 0b01 0b01 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb03 seq_br_type 0 Branch False seq_branch_adr 0b03 0x0b03 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b02 0b02 seq_br_type 3 Unconditional Branch; Flow J 0xaec seq_branch_adr 0aec 0x0aec val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 14 0b03 0b03 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0b04 0b04 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0b05 0b05 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0b06 0b06 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0b07 0b07 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0b08 0b08 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0b09 0b09 typ_a_adr 0b GP0b typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0b0a 0b0a seq_b_timing 0 Early Condition; Flow J cc=False 0xb00 seq_br_type 0 Branch False seq_branch_adr 0b00 0x0b00 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 0b0b 0b0b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb0d seq_br_type 0 Branch False seq_branch_adr 0b0d 0x0b0d seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 09 GP09 val_alu_func 3 LEFT_I_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0b0c 0b0c typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 19 0b0d 0b0d fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0xada fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0ada 0x0ada seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0c GP0c typ_alu_func 1c DEC_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 2f VR1a:0f val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0b0e 0b0e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb10 seq_br_type 0 Branch False seq_branch_adr 0b10 0x0b10 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 0a GP0a val_alu_func 3 LEFT_I_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU 0b0f 0b0f typ_a_adr 0a GP0a typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 35 GP0a typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 19 0b10 0b10 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0xad8 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0ad8 0x0ad8 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0b GP0b val_alu_func 1c DEC_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0b11 0b11 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 29 TR12:09 typ_frame 12 0b12 0b12 typ_a_adr 3c TR1a:1c typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 1a 0b13 0b13 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 19 0b14 0b14 typ_a_adr 28 TR18:08 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 0a GP0a val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0b15 0b15 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 30 VR1a:10 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0b16 0b16 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 19 0b17 0b17 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 0b18 0b18 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 0d GP0d 0b19 0b19 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0b1a 0b1a fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0b1b 0b1b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0b1c 0b1c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0b1d 0b1d fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0b1e 0b1e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0b1f 0b1f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb21 seq_br_type 0 Branch False seq_branch_adr 0b21 0x0b21 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0b20 0b20 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 0b21 0b21 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xb2c seq_br_type 1 Branch True seq_branch_adr 0b2c 0x0b2c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 09 GP09 0b22 0b22 seq_b_timing 0 Early Condition; Flow J cc=False 0xb19 seq_br_type 0 Branch False seq_branch_adr 0b19 0x0b19 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 0b23 0b23 seq_br_type 3 Unconditional Branch; Flow J 0xb2d seq_branch_adr 0b2d 0x0b2d 0b24 0b24 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 0c GP0c 0b25 0b25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0b26 0b26 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0b27 0b27 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 0c GP0c 0b28 0b28 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0b29 0b29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb49 seq_br_type 5 Call True seq_branch_adr 0b49 0x0b49 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0b2a 0b2a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb2c seq_br_type 0 Branch False seq_branch_adr 0b2c 0x0b2c seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 3 LEFT_I_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 0b2b 0b2b typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 0b2c 0b2c seq_b_timing 0 Early Condition; Flow J cc=False 0xb24 seq_br_type 0 Branch False seq_branch_adr 0b24 0x0b24 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 0b2d 0b2d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb2f seq_br_type 0 Branch False seq_branch_adr 0b2f 0x0b2f seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 3 LEFT_I_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 7 INC_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0b2e 0b2e typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 0b2f 0b2f val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 2f VR1a:0f val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 0b30 0b30 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0xb16 fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0b16 0x0b16 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 31 VR1a:11 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 1a 0b31 0b31 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xb33 seq_br_type 0 Branch False seq_branch_adr 0b33 0x0b33 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 0a GP0a val_alu_func 7 INC_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU 0b32 0b32 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 0b33 0b33 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0xb14 fiu_tivi_src c mar_0xc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0b14 0x0b14 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 0b GP0b typ_alu_func 1c DEC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0a GP0a val_alu_func 1e A_AND_B val_b_adr 31 VR1a:11 val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 0b34 0b34 seq_br_type a Unconditional Return; Flow R val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 0b35 ; -------------------------------------------------------------------------------------- 0b35 ; Comes from: 0b35 ; 0a04 C True from color 0x0a00 0b35 ; -------------------------------------------------------------------------------------- 0b35 0b35 <halt> ; Flow R 0b36 0b36 seq_br_type a Unconditional Return; Flow R 0b37 ; -------------------------------------------------------------------------------------- 0b37 ; Comes from: 0b37 ; 0a08 C False from color 0x0a00 0b37 ; 0a09 C False from color 0x0a00 0b37 ; 0a0a C False from color 0x0a00 0b37 ; 0a0b C False from color 0x0a00 0b37 ; 0a0c C False from color 0x0a00 0b37 ; 0a0d C False from color 0x0a00 0b37 ; 0a0f C False from color 0x0a00 0b37 ; 0a10 C False from color 0x0a00 0b37 ; 0a11 C False from color 0x0a00 0b37 ; 0a12 C False from color 0x0a00 0b37 ; 0a13 C False from color 0x0a00 0b37 ; 0a14 C False from color 0x0a00 0b37 ; 0a16 C False from color 0x0a00 0b37 ; 0a17 C False from color 0x0a00 0b37 ; 0a18 C False from color 0x0a00 0b37 ; 0a19 C False from color 0x0a00 0b37 ; 0a1a C False from color 0x0a00 0b37 ; 0a1b C False from color 0x0a00 0b37 ; 0a1d C False from color 0x0a00 0b37 ; 0a1e C False from color 0x0a00 0b37 ; 0a1f C False from color 0x0a00 0b37 ; 0a20 C False from color 0x0a00 0b37 ; 0a21 C False from color 0x0a00 0b37 ; 0a22 C True from color 0x0a00 0b37 ; 0a24 C False from color 0x0a00 0b37 ; 0a25 C False from color 0x0a00 0b37 ; 0a26 C False from color 0x0a00 0b37 ; 0a27 C True from color 0x0a00 0b37 ; 0a28 C True from color 0x0a00 0b37 ; 0a29 C True from color 0x0a00 0b37 ; 0a2b C False from color 0x0a00 0b37 ; 0a2c C False from color 0x0a00 0b37 ; 0a2d C False from color 0x0a00 0b37 ; 0a2e C False from color 0x0a00 0b37 ; 0a2f C False from color 0x0a00 0b37 ; 0a30 C True from color 0x0a00 0b37 ; 0a31 C True from color 0x0a00 0b37 ; 0a32 C True from color 0x0a00 0b37 ; 0a33 C True from color 0x0a00 0b37 ; 0a34 C True from color 0x0a00 0b37 ; 0a36 C False from color 0x0a00 0b37 ; 0a37 C False from color 0x0a00 0b37 ; 0a38 C False from color 0x0a00 0b37 ; 0a39 C True from color 0x0a00 0b37 ; 0a3a C True from color 0x0a00 0b37 ; 0a3b C True from color 0x0a00 0b37 ; 0a3c C True from color 0x0a00 0b37 ; 0a3d C True from color 0x0a00 0b37 ; -------------------------------------------------------------------------------------- 0b37 0b37 <halt> ; Flow R 0b38 0b38 seq_br_type a Unconditional Return; Flow R 0b39 ; -------------------------------------------------------------------------------------- 0b39 ; Comes from: 0b39 ; 0a43 C from color 0x0a00 0b39 ; 0a46 C from color 0x0a00 0b39 ; 0a4a C False from color 0x0a00 0b39 ; 0a4c C False from color 0x0a00 0b39 ; 0a4f C True from color 0x0a00 0b39 ; 0a50 C False from color 0x0a00 0b39 ; -------------------------------------------------------------------------------------- 0b39 0b39 <halt> ; Flow R 0b3a 0b3a seq_br_type a Unconditional Return; Flow R 0b3b ; -------------------------------------------------------------------------------------- 0b3b ; Comes from: 0b3b ; 0a54 C True from color 0x0a00 0b3b ; 0a57 C True from color 0x0a00 0b3b ; 0a59 C True from color 0x0a00 0b3b ; 0a5c C True from color 0x0a00 0b3b ; -------------------------------------------------------------------------------------- 0b3b 0b3b <halt> ; Flow R 0b3c 0b3c seq_br_type a Unconditional Return; Flow R 0b3d ; -------------------------------------------------------------------------------------- 0b3d ; Comes from: 0b3d ; 0a61 C True from color 0x0a00 0b3d ; 0a64 C True from color 0x0a00 0b3d ; 0a66 C True from color 0x0a00 0b3d ; 0a69 C True from color 0x0a00 0b3d ; -------------------------------------------------------------------------------------- 0b3d 0b3d <halt> ; Flow R 0b3e 0b3e seq_br_type a Unconditional Return; Flow R 0b3f ; -------------------------------------------------------------------------------------- 0b3f ; Comes from: 0b3f ; 0a70 C True from color 0x0a00 0b3f ; 0a73 C True from color 0x0a00 0b3f ; -------------------------------------------------------------------------------------- 0b3f 0b3f <halt> ; Flow R 0b40 0b40 seq_br_type a Unconditional Return; Flow R 0b41 ; -------------------------------------------------------------------------------------- 0b41 ; Comes from: 0b41 ; 0a84 C True from color 0x0a00 0b41 ; 0a87 C True from color 0x0a00 0b41 ; -------------------------------------------------------------------------------------- 0b41 0b41 <halt> ; Flow R 0b42 0b42 seq_br_type a Unconditional Return; Flow R 0b43 ; -------------------------------------------------------------------------------------- 0b43 ; Comes from: 0b43 ; 0a7a C True from color 0x0a00 0b43 ; 0a7d C True from color 0x0a00 0b43 ; -------------------------------------------------------------------------------------- 0b43 0b43 <halt> ; Flow R 0b44 0b44 seq_br_type a Unconditional Return; Flow R 0b45 ; -------------------------------------------------------------------------------------- 0b45 ; Comes from: 0b45 ; 0a91 C True from color 0x0a00 0b45 ; 0a94 C True from color 0x0a00 0b45 ; 0a99 C True from color 0x0a00 0b45 ; 0a9c C True from color 0x0a00 0b45 ; -------------------------------------------------------------------------------------- 0b45 0b45 <halt> ; Flow R 0b46 0b46 seq_br_type a Unconditional Return; Flow R 0b47 ; -------------------------------------------------------------------------------------- 0b47 ; Comes from: 0b47 ; 0aa6 C True from color 0x0a00 0b47 ; 0aaf C True from color 0x0a00 0b47 ; 0ab8 C True from color 0x0a00 0b47 ; 0ac1 C True from color 0x0a00 0b47 ; -------------------------------------------------------------------------------------- 0b47 0b47 <halt> ; Flow R 0b48 0b48 seq_br_type a Unconditional Return; Flow R 0b49 ; -------------------------------------------------------------------------------------- 0b49 ; Comes from: 0b49 ; 0ae0 C True from color 0x0a00 0b49 ; 0ae3 C True from color 0x0a00 0b49 ; 0aee C True from color 0x0a00 0b49 ; 0af1 C True from color 0x0a00 0b49 ; 0af7 C True from color 0x0a00 0b49 ; 0afa C True from color 0x0a00 0b49 ; 0b05 C True from color 0x0a00 0b49 ; 0b08 C True from color 0x0a00 0b49 ; 0b1b C True from color 0x0a00 0b49 ; 0b1e C True from color 0x0a00 0b49 ; 0b26 C True from color 0x0a00 0b49 ; 0b29 C True from color 0x0a00 0b49 ; -------------------------------------------------------------------------------------- 0b49 0b49 <halt> ; Flow R 0b4a 0b4a seq_br_type a Unconditional Return; Flow R 0b4b ; -------------------------------------------------------------------------------------- 0b4b ; Comes from: 0b4b ; 0acf C True from color 0x0a00 0b4b ; 0ad1 C True from color 0x0a00 0b4b ; -------------------------------------------------------------------------------------- 0b4b 0b4b <halt> ; Flow R 0b4c 0b4c seq_br_type a Unconditional Return; Flow R 0b4d 0b4d <halt> ; Flow R 0b4e 0b4e seq_br_type a Unconditional Return; Flow R 0b4f 0b4f <halt> ; Flow R 0b50 0b50 <halt> ; Flow R 0b51 0b51 <halt> ; Flow R 0b52 0b52 <halt> ; Flow R 0b53 0b53 <halt> ; Flow R 0b54 0b54 <halt> ; Flow R 0b55 0b55 <halt> ; Flow R 0b56 0b56 <halt> ; Flow R 0b57 0b57 <halt> ; Flow R 0b58 0b58 <halt> ; Flow R 0b59 0b59 <halt> ; Flow R 0b5a 0b5a <halt> ; Flow R 0b5b 0b5b <halt> ; Flow R 0b5c 0b5c <halt> ; Flow R 0b5d 0b5d <halt> ; Flow R 0b5e 0b5e <halt> ; Flow R 0b5f 0b5f <halt> ; Flow R 0b60 0b60 <halt> ; Flow R 0b61 0b61 <halt> ; Flow R 0b62 0b62 <halt> ; Flow R 0b63 0b63 <halt> ; Flow R 0b64 0b64 <halt> ; Flow R 0b65 0b65 <halt> ; Flow R 0b66 0b66 <halt> ; Flow R 0b67 0b67 <halt> ; Flow R 0b68 0b68 <halt> ; Flow R 0b69 0b69 <halt> ; Flow R 0b6a 0b6a <halt> ; Flow R 0b6b 0b6b <halt> ; Flow R 0b6c 0b6c <halt> ; Flow R 0b6d 0b6d <halt> ; Flow R 0b6e 0b6e <halt> ; Flow R 0b6f 0b6f <halt> ; Flow R 0b70 0b70 <halt> ; Flow R 0b71 0b71 <halt> ; Flow R 0b72 0b72 <halt> ; Flow R 0b73 0b73 <halt> ; Flow R 0b74 0b74 <halt> ; Flow R 0b75 0b75 <halt> ; Flow R 0b76 0b76 <halt> ; Flow R 0b77 0b77 <halt> ; Flow R 0b78 0b78 <halt> ; Flow R 0b79 0b79 <halt> ; Flow R 0b7a 0b7a <halt> ; Flow R 0b7b 0b7b <halt> ; Flow R 0b7c 0b7c <halt> ; Flow R 0b7d 0b7d <halt> ; Flow R 0b7e 0b7e <halt> ; Flow R 0b7f 0b7f <halt> ; Flow R 0b80 0b80 <halt> ; Flow R 0b81 0b81 <halt> ; Flow R 0b82 0b82 <halt> ; Flow R 0b83 0b83 <halt> ; Flow R 0b84 0b84 <halt> ; Flow R 0b85 0b85 <halt> ; Flow R 0b86 0b86 <halt> ; Flow R 0b87 0b87 <halt> ; Flow R 0b88 0b88 <halt> ; Flow R 0b89 0b89 <halt> ; Flow R 0b8a 0b8a <halt> ; Flow R 0b8b 0b8b <halt> ; Flow R 0b8c 0b8c <halt> ; Flow R 0b8d 0b8d <halt> ; Flow R 0b8e 0b8e <halt> ; Flow R 0b8f 0b8f <halt> ; Flow R 0b90 0b90 <halt> ; Flow R 0b91 0b91 <halt> ; Flow R 0b92 0b92 <halt> ; Flow R 0b93 0b93 <halt> ; Flow R 0b94 0b94 <halt> ; Flow R 0b95 0b95 <halt> ; Flow R 0b96 0b96 <halt> ; Flow R 0b97 0b97 <halt> ; Flow R 0b98 0b98 <halt> ; Flow R 0b99 0b99 <halt> ; Flow R 0b9a 0b9a <halt> ; Flow R 0b9b 0b9b <halt> ; Flow R 0b9c 0b9c <halt> ; Flow R 0b9d 0b9d <halt> ; Flow R 0b9e 0b9e <halt> ; Flow R 0b9f 0b9f <halt> ; Flow R 0ba0 0ba0 <halt> ; Flow R 0ba1 0ba1 <halt> ; Flow R 0ba2 0ba2 <halt> ; Flow R 0ba3 0ba3 <halt> ; Flow R 0ba4 0ba4 <halt> ; Flow R 0ba5 0ba5 <halt> ; Flow R 0ba6 0ba6 <halt> ; Flow R 0ba7 0ba7 <halt> ; Flow R 0ba8 0ba8 <halt> ; Flow R 0ba9 0ba9 <halt> ; Flow R 0baa 0baa <halt> ; Flow R 0bab 0bab <halt> ; Flow R 0bac 0bac <halt> ; Flow R 0bad 0bad <halt> ; Flow R 0bae 0bae <halt> ; Flow R 0baf 0baf <halt> ; Flow R 0bb0 0bb0 <halt> ; Flow R 0bb1 0bb1 <halt> ; Flow R 0bb2 0bb2 <halt> ; Flow R 0bb3 0bb3 <halt> ; Flow R 0bb4 0bb4 <halt> ; Flow R 0bb5 0bb5 <halt> ; Flow R 0bb6 0bb6 <halt> ; Flow R 0bb7 0bb7 <halt> ; Flow R 0bb8 0bb8 <halt> ; Flow R 0bb9 0bb9 <halt> ; Flow R 0bba 0bba <halt> ; Flow R 0bbb 0bbb <halt> ; Flow R 0bbc 0bbc <halt> ; Flow R 0bbd 0bbd <halt> ; Flow R 0bbe 0bbe <halt> ; Flow R 0bbf 0bbf <halt> ; Flow R 0bc0 0bc0 <halt> ; Flow R 0bc1 0bc1 <halt> ; Flow R 0bc2 0bc2 <halt> ; Flow R 0bc3 0bc3 <halt> ; Flow R 0bc4 0bc4 <halt> ; Flow R 0bc5 0bc5 <halt> ; Flow R 0bc6 0bc6 <halt> ; Flow R 0bc7 0bc7 <halt> ; Flow R 0bc8 0bc8 <halt> ; Flow R 0bc9 0bc9 <halt> ; Flow R 0bca 0bca <halt> ; Flow R 0bcb 0bcb <halt> ; Flow R 0bcc 0bcc <halt> ; Flow R 0bcd 0bcd <halt> ; Flow R 0bce 0bce <halt> ; Flow R 0bcf 0bcf <halt> ; Flow R 0bd0 0bd0 <halt> ; Flow R 0bd1 0bd1 <halt> ; Flow R 0bd2 0bd2 <halt> ; Flow R 0bd3 0bd3 <halt> ; Flow R 0bd4 0bd4 <halt> ; Flow R 0bd5 0bd5 <halt> ; Flow R 0bd6 0bd6 <halt> ; Flow R 0bd7 0bd7 <halt> ; Flow R 0bd8 0bd8 <halt> ; Flow R 0bd9 0bd9 <halt> ; Flow R 0bda 0bda <halt> ; Flow R 0bdb 0bdb <halt> ; Flow R 0bdc 0bdc <halt> ; Flow R 0bdd 0bdd <halt> ; Flow R 0bde 0bde <halt> ; Flow R 0bdf 0bdf <halt> ; Flow R 0be0 0be0 <halt> ; Flow R 0be1 0be1 <halt> ; Flow R 0be2 0be2 <halt> ; Flow R 0be3 0be3 <halt> ; Flow R 0be4 0be4 <halt> ; Flow R 0be5 0be5 <halt> ; Flow R 0be6 0be6 <halt> ; Flow R 0be7 0be7 <halt> ; Flow R 0be8 0be8 <halt> ; Flow R 0be9 0be9 <halt> ; Flow R 0bea 0bea <halt> ; Flow R 0beb 0beb <halt> ; Flow R 0bec 0bec <halt> ; Flow R 0bed 0bed <halt> ; Flow R 0bee 0bee <halt> ; Flow R 0bef 0bef <halt> ; Flow R 0bf0 0bf0 <halt> ; Flow R 0bf1 0bf1 <halt> ; Flow R 0bf2 0bf2 <halt> ; Flow R 0bf3 0bf3 <halt> ; Flow R 0bf4 0bf4 <halt> ; Flow R 0bf5 0bf5 <halt> ; Flow R 0bf6 0bf6 <halt> ; Flow R 0bf7 0bf7 <halt> ; Flow R 0bf8 0bf8 <halt> ; Flow R 0bf9 0bf9 <halt> ; Flow R 0bfa 0bfa <halt> ; Flow R 0bfb 0bfb <halt> ; Flow R 0bfc 0bfc <halt> ; Flow R 0bfd 0bfd <halt> ; Flow R 0bfe 0bfe <halt> ; Flow R 0bff 0bff <halt> ; Flow R 0c00 0c00 <halt> ; Flow R 0c01 0c01 <halt> ; Flow R 0c02 0c02 <halt> ; Flow R 0c03 0c03 <halt> ; Flow R 0c04 0c04 <halt> ; Flow R 0c05 0c05 <halt> ; Flow R 0c06 0c06 <halt> ; Flow R 0c07 0c07 <halt> ; Flow R 0c08 0c08 <halt> ; Flow R 0c09 0c09 <halt> ; Flow R 0c0a 0c0a <halt> ; Flow R 0c0b 0c0b <halt> ; Flow R 0c0c 0c0c <halt> ; Flow R 0c0d 0c0d <halt> ; Flow R 0c0e 0c0e <halt> ; Flow R 0c0f 0c0f <halt> ; Flow R 0c10 0c10 <halt> ; Flow R 0c11 0c11 <halt> ; Flow R 0c12 0c12 <halt> ; Flow R 0c13 0c13 <halt> ; Flow R 0c14 0c14 <halt> ; Flow R 0c15 0c15 <halt> ; Flow R 0c16 0c16 <halt> ; Flow R 0c17 0c17 <halt> ; Flow R 0c18 0c18 <halt> ; Flow R 0c19 0c19 <halt> ; Flow R 0c1a 0c1a <halt> ; Flow R 0c1b 0c1b <halt> ; Flow R 0c1c 0c1c <halt> ; Flow R 0c1d 0c1d <halt> ; Flow R 0c1e 0c1e <halt> ; Flow R 0c1f 0c1f <halt> ; Flow R 0c20 0c20 <halt> ; Flow R 0c21 0c21 <halt> ; Flow R 0c22 0c22 <halt> ; Flow R 0c23 0c23 <halt> ; Flow R 0c24 0c24 <halt> ; Flow R 0c25 0c25 <halt> ; Flow R 0c26 0c26 <halt> ; Flow R 0c27 0c27 <halt> ; Flow R 0c28 0c28 <halt> ; Flow R 0c29 0c29 <halt> ; Flow R 0c2a 0c2a <halt> ; Flow R 0c2b 0c2b <halt> ; Flow R 0c2c 0c2c <halt> ; Flow R 0c2d 0c2d <halt> ; Flow R 0c2e 0c2e <halt> ; Flow R 0c2f 0c2f <halt> ; Flow R 0c30 0c30 <halt> ; Flow R 0c31 0c31 <halt> ; Flow R 0c32 0c32 <halt> ; Flow R 0c33 0c33 <halt> ; Flow R 0c34 0c34 <halt> ; Flow R 0c35 0c35 <halt> ; Flow R 0c36 0c36 <halt> ; Flow R 0c37 0c37 <halt> ; Flow R 0c38 0c38 <halt> ; Flow R 0c39 0c39 <halt> ; Flow R 0c3a 0c3a <halt> ; Flow R 0c3b 0c3b <halt> ; Flow R 0c3c 0c3c <halt> ; Flow R 0c3d 0c3d <halt> ; Flow R 0c3e 0c3e <halt> ; Flow R 0c3f 0c3f <halt> ; Flow R 0c40 0c40 <halt> ; Flow R 0c41 0c41 <halt> ; Flow R 0c42 0c42 <halt> ; Flow R 0c43 0c43 <halt> ; Flow R 0c44 0c44 <halt> ; Flow R 0c45 0c45 <halt> ; Flow R 0c46 0c46 <halt> ; Flow R 0c47 0c47 <halt> ; Flow R 0c48 0c48 <halt> ; Flow R 0c49 0c49 <halt> ; Flow R 0c4a 0c4a <halt> ; Flow R 0c4b 0c4b <halt> ; Flow R 0c4c 0c4c <halt> ; Flow R 0c4d 0c4d <halt> ; Flow R 0c4e 0c4e <halt> ; Flow R 0c4f 0c4f <halt> ; Flow R 0c50 0c50 <halt> ; Flow R 0c51 0c51 <halt> ; Flow R 0c52 0c52 <halt> ; Flow R 0c53 0c53 <halt> ; Flow R 0c54 0c54 <halt> ; Flow R 0c55 0c55 <halt> ; Flow R 0c56 0c56 <halt> ; Flow R 0c57 0c57 <halt> ; Flow R 0c58 0c58 <halt> ; Flow R 0c59 0c59 <halt> ; Flow R 0c5a 0c5a <halt> ; Flow R 0c5b 0c5b <halt> ; Flow R 0c5c 0c5c <halt> ; Flow R 0c5d 0c5d <halt> ; Flow R 0c5e 0c5e <halt> ; Flow R 0c5f 0c5f <halt> ; Flow R 0c60 0c60 <halt> ; Flow R 0c61 0c61 <halt> ; Flow R 0c62 0c62 <halt> ; Flow R 0c63 0c63 <halt> ; Flow R 0c64 0c64 <halt> ; Flow R 0c65 0c65 <halt> ; Flow R 0c66 0c66 <halt> ; Flow R 0c67 0c67 <halt> ; Flow R 0c68 0c68 <halt> ; Flow R 0c69 0c69 <halt> ; Flow R 0c6a 0c6a <halt> ; Flow R 0c6b 0c6b <halt> ; Flow R 0c6c 0c6c <halt> ; Flow R 0c6d 0c6d <halt> ; Flow R 0c6e 0c6e <halt> ; Flow R 0c6f 0c6f <halt> ; Flow R 0c70 0c70 <halt> ; Flow R 0c71 0c71 <halt> ; Flow R 0c72 0c72 <halt> ; Flow R 0c73 0c73 <halt> ; Flow R 0c74 0c74 <halt> ; Flow R 0c75 0c75 <halt> ; Flow R 0c76 0c76 <halt> ; Flow R 0c77 0c77 <halt> ; Flow R 0c78 0c78 <halt> ; Flow R 0c79 0c79 <halt> ; Flow R 0c7a 0c7a <halt> ; Flow R 0c7b 0c7b <halt> ; Flow R 0c7c 0c7c <halt> ; Flow R 0c7d 0c7d <halt> ; Flow R 0c7e 0c7e <halt> ; Flow R 0c7f 0c7f <halt> ; Flow R 0c80 0c80 <halt> ; Flow R 0c81 0c81 <halt> ; Flow R 0c82 0c82 <halt> ; Flow R 0c83 0c83 <halt> ; Flow R 0c84 0c84 <halt> ; Flow R 0c85 0c85 <halt> ; Flow R 0c86 0c86 <halt> ; Flow R 0c87 0c87 <halt> ; Flow R 0c88 0c88 <halt> ; Flow R 0c89 0c89 <halt> ; Flow R 0c8a 0c8a <halt> ; Flow R 0c8b 0c8b <halt> ; Flow R 0c8c 0c8c <halt> ; Flow R 0c8d 0c8d <halt> ; Flow R 0c8e 0c8e <halt> ; Flow R 0c8f 0c8f <halt> ; Flow R 0c90 0c90 <halt> ; Flow R 0c91 0c91 <halt> ; Flow R 0c92 0c92 <halt> ; Flow R 0c93 0c93 <halt> ; Flow R 0c94 0c94 <halt> ; Flow R 0c95 0c95 <halt> ; Flow R 0c96 0c96 <halt> ; Flow R 0c97 0c97 <halt> ; Flow R 0c98 0c98 <halt> ; Flow R 0c99 0c99 <halt> ; Flow R 0c9a 0c9a <halt> ; Flow R 0c9b 0c9b <halt> ; Flow R 0c9c 0c9c <halt> ; Flow R 0c9d 0c9d <halt> ; Flow R 0c9e 0c9e <halt> ; Flow R 0c9f 0c9f <halt> ; Flow R 0ca0 0ca0 <halt> ; Flow R 0ca1 0ca1 <halt> ; Flow R 0ca2 0ca2 <halt> ; Flow R 0ca3 0ca3 <halt> ; Flow R 0ca4 0ca4 <halt> ; Flow R 0ca5 0ca5 <halt> ; Flow R 0ca6 0ca6 <halt> ; Flow R 0ca7 0ca7 <halt> ; Flow R 0ca8 0ca8 <halt> ; Flow R 0ca9 0ca9 <halt> ; Flow R 0caa 0caa <halt> ; Flow R 0cab 0cab <halt> ; Flow R 0cac 0cac <halt> ; Flow R 0cad 0cad <halt> ; Flow R 0cae 0cae <halt> ; Flow R 0caf 0caf <halt> ; Flow R 0cb0 0cb0 <halt> ; Flow R 0cb1 0cb1 <halt> ; Flow R 0cb2 0cb2 <halt> ; Flow R 0cb3 0cb3 <halt> ; Flow R 0cb4 0cb4 <halt> ; Flow R 0cb5 0cb5 <halt> ; Flow R 0cb6 0cb6 <halt> ; Flow R 0cb7 0cb7 <halt> ; Flow R 0cb8 0cb8 <halt> ; Flow R 0cb9 0cb9 <halt> ; Flow R 0cba 0cba <halt> ; Flow R 0cbb 0cbb <halt> ; Flow R 0cbc 0cbc <halt> ; Flow R 0cbd 0cbd <halt> ; Flow R 0cbe 0cbe <halt> ; Flow R 0cbf 0cbf <halt> ; Flow R 0cc0 0cc0 <halt> ; Flow R 0cc1 0cc1 <halt> ; Flow R 0cc2 0cc2 <halt> ; Flow R 0cc3 0cc3 <halt> ; Flow R 0cc4 0cc4 <halt> ; Flow R 0cc5 0cc5 <halt> ; Flow R 0cc6 0cc6 <halt> ; Flow R 0cc7 0cc7 <halt> ; Flow R 0cc8 0cc8 <halt> ; Flow R 0cc9 0cc9 <halt> ; Flow R 0cca 0cca <halt> ; Flow R 0ccb 0ccb <halt> ; Flow R 0ccc 0ccc <halt> ; Flow R 0ccd 0ccd <halt> ; Flow R 0cce 0cce <halt> ; Flow R 0ccf 0ccf <halt> ; Flow R 0cd0 0cd0 <halt> ; Flow R 0cd1 0cd1 <halt> ; Flow R 0cd2 0cd2 <halt> ; Flow R 0cd3 0cd3 <halt> ; Flow R 0cd4 0cd4 <halt> ; Flow R 0cd5 0cd5 <halt> ; Flow R 0cd6 0cd6 <halt> ; Flow R 0cd7 0cd7 <halt> ; Flow R 0cd8 0cd8 <halt> ; Flow R 0cd9 0cd9 <halt> ; Flow R 0cda 0cda <halt> ; Flow R 0cdb 0cdb <halt> ; Flow R 0cdc 0cdc <halt> ; Flow R 0cdd 0cdd <halt> ; Flow R 0cde 0cde <halt> ; Flow R 0cdf 0cdf <halt> ; Flow R 0ce0 0ce0 <halt> ; Flow R 0ce1 0ce1 <halt> ; Flow R 0ce2 0ce2 <halt> ; Flow R 0ce3 0ce3 <halt> ; Flow R 0ce4 0ce4 <halt> ; Flow R 0ce5 0ce5 <halt> ; Flow R 0ce6 0ce6 <halt> ; Flow R 0ce7 0ce7 <halt> ; Flow R 0ce8 0ce8 <halt> ; Flow R 0ce9 0ce9 <halt> ; Flow R 0cea 0cea <halt> ; Flow R 0ceb 0ceb <halt> ; Flow R 0cec 0cec <halt> ; Flow R 0ced 0ced <halt> ; Flow R 0cee 0cee <halt> ; Flow R 0cef 0cef <halt> ; Flow R 0cf0 0cf0 <halt> ; Flow R 0cf1 0cf1 <halt> ; Flow R 0cf2 0cf2 <halt> ; Flow R 0cf3 0cf3 <halt> ; Flow R 0cf4 0cf4 <halt> ; Flow R 0cf5 0cf5 <halt> ; Flow R 0cf6 0cf6 <halt> ; Flow R 0cf7 0cf7 <halt> ; Flow R 0cf8 0cf8 <halt> ; Flow R 0cf9 0cf9 <halt> ; Flow R 0cfa 0cfa <halt> ; Flow R 0cfb 0cfb <halt> ; Flow R 0cfc 0cfc <halt> ; Flow R 0cfd 0cfd <halt> ; Flow R 0cfe 0cfe <halt> ; Flow R 0cff 0cff <halt> ; Flow R 0d00 0d00 <halt> ; Flow R 0d01 0d01 <halt> ; Flow R 0d02 0d02 <halt> ; Flow R 0d03 0d03 <halt> ; Flow R 0d04 0d04 <halt> ; Flow R 0d05 0d05 <halt> ; Flow R 0d06 0d06 <halt> ; Flow R 0d07 0d07 <halt> ; Flow R 0d08 0d08 <halt> ; Flow R 0d09 0d09 <halt> ; Flow R 0d0a 0d0a <halt> ; Flow R 0d0b 0d0b <halt> ; Flow R 0d0c 0d0c <halt> ; Flow R 0d0d 0d0d <halt> ; Flow R 0d0e 0d0e <halt> ; Flow R 0d0f 0d0f <halt> ; Flow R 0d10 0d10 <halt> ; Flow R 0d11 0d11 <halt> ; Flow R 0d12 0d12 <halt> ; Flow R 0d13 0d13 <halt> ; Flow R 0d14 0d14 <halt> ; Flow R 0d15 0d15 <halt> ; Flow R 0d16 0d16 <halt> ; Flow R 0d17 0d17 <halt> ; Flow R 0d18 0d18 <halt> ; Flow R 0d19 0d19 <halt> ; Flow R 0d1a 0d1a <halt> ; Flow R 0d1b 0d1b <halt> ; Flow R 0d1c 0d1c <halt> ; Flow R 0d1d 0d1d <halt> ; Flow R 0d1e 0d1e <halt> ; Flow R 0d1f 0d1f <halt> ; Flow R 0d20 0d20 <halt> ; Flow R 0d21 0d21 <halt> ; Flow R 0d22 0d22 <halt> ; Flow R 0d23 0d23 <halt> ; Flow R 0d24 0d24 <halt> ; Flow R 0d25 0d25 <halt> ; Flow R 0d26 0d26 <halt> ; Flow R 0d27 0d27 <halt> ; Flow R 0d28 0d28 <halt> ; Flow R 0d29 0d29 <halt> ; Flow R 0d2a 0d2a <halt> ; Flow R 0d2b 0d2b <halt> ; Flow R 0d2c 0d2c <halt> ; Flow R 0d2d 0d2d <halt> ; Flow R 0d2e 0d2e <halt> ; Flow R 0d2f 0d2f <halt> ; Flow R 0d30 0d30 <halt> ; Flow R 0d31 0d31 <halt> ; Flow R 0d32 0d32 <halt> ; Flow R 0d33 0d33 <halt> ; Flow R 0d34 0d34 <halt> ; Flow R 0d35 0d35 <halt> ; Flow R 0d36 0d36 <halt> ; Flow R 0d37 0d37 <halt> ; Flow R 0d38 0d38 <halt> ; Flow R 0d39 0d39 <halt> ; Flow R 0d3a 0d3a <halt> ; Flow R 0d3b 0d3b <halt> ; Flow R 0d3c 0d3c <halt> ; Flow R 0d3d 0d3d <halt> ; Flow R 0d3e 0d3e <halt> ; Flow R 0d3f 0d3f <halt> ; Flow R 0d40 0d40 <halt> ; Flow R 0d41 0d41 <halt> ; Flow R 0d42 0d42 <halt> ; Flow R 0d43 0d43 <halt> ; Flow R 0d44 0d44 <halt> ; Flow R 0d45 0d45 <halt> ; Flow R 0d46 0d46 <halt> ; Flow R 0d47 0d47 <halt> ; Flow R 0d48 0d48 <halt> ; Flow R 0d49 0d49 <halt> ; Flow R 0d4a 0d4a <halt> ; Flow R 0d4b 0d4b <halt> ; Flow R 0d4c 0d4c <halt> ; Flow R 0d4d 0d4d <halt> ; Flow R 0d4e 0d4e <halt> ; Flow R 0d4f 0d4f <halt> ; Flow R 0d50 0d50 <halt> ; Flow R 0d51 0d51 <halt> ; Flow R 0d52 0d52 <halt> ; Flow R 0d53 0d53 <halt> ; Flow R 0d54 0d54 <halt> ; Flow R 0d55 0d55 <halt> ; Flow R 0d56 0d56 <halt> ; Flow R 0d57 0d57 <halt> ; Flow R 0d58 0d58 <halt> ; Flow R 0d59 0d59 <halt> ; Flow R 0d5a 0d5a <halt> ; Flow R 0d5b 0d5b <halt> ; Flow R 0d5c 0d5c <halt> ; Flow R 0d5d 0d5d <halt> ; Flow R 0d5e 0d5e <halt> ; Flow R 0d5f 0d5f <halt> ; Flow R 0d60 0d60 <halt> ; Flow R 0d61 0d61 <halt> ; Flow R 0d62 0d62 <halt> ; Flow R 0d63 0d63 <halt> ; Flow R 0d64 0d64 <halt> ; Flow R 0d65 0d65 <halt> ; Flow R 0d66 0d66 <halt> ; Flow R 0d67 0d67 <halt> ; Flow R 0d68 0d68 <halt> ; Flow R 0d69 0d69 <halt> ; Flow R 0d6a 0d6a <halt> ; Flow R 0d6b 0d6b <halt> ; Flow R 0d6c 0d6c <halt> ; Flow R 0d6d 0d6d <halt> ; Flow R 0d6e 0d6e <halt> ; Flow R 0d6f 0d6f <halt> ; Flow R 0d70 0d70 <halt> ; Flow R 0d71 0d71 <halt> ; Flow R 0d72 0d72 <halt> ; Flow R 0d73 0d73 <halt> ; Flow R 0d74 0d74 <halt> ; Flow R 0d75 0d75 <halt> ; Flow R 0d76 0d76 <halt> ; Flow R 0d77 0d77 <halt> ; Flow R 0d78 0d78 <halt> ; Flow R 0d79 0d79 <halt> ; Flow R 0d7a 0d7a <halt> ; Flow R 0d7b 0d7b <halt> ; Flow R 0d7c 0d7c <halt> ; Flow R 0d7d 0d7d <halt> ; Flow R 0d7e 0d7e <halt> ; Flow R 0d7f 0d7f <halt> ; Flow R 0d80 0d80 <halt> ; Flow R 0d81 0d81 <halt> ; Flow R 0d82 0d82 <halt> ; Flow R 0d83 0d83 <halt> ; Flow R 0d84 0d84 <halt> ; Flow R 0d85 0d85 <halt> ; Flow R 0d86 0d86 <halt> ; Flow R 0d87 0d87 <halt> ; Flow R 0d88 0d88 <halt> ; Flow R 0d89 0d89 <halt> ; Flow R 0d8a 0d8a <halt> ; Flow R 0d8b 0d8b <halt> ; Flow R 0d8c 0d8c <halt> ; Flow R 0d8d 0d8d <halt> ; Flow R 0d8e 0d8e <halt> ; Flow R 0d8f 0d8f <halt> ; Flow R 0d90 0d90 <halt> ; Flow R 0d91 0d91 <halt> ; Flow R 0d92 0d92 <halt> ; Flow R 0d93 0d93 <halt> ; Flow R 0d94 0d94 <halt> ; Flow R 0d95 0d95 <halt> ; Flow R 0d96 0d96 <halt> ; Flow R 0d97 0d97 <halt> ; Flow R 0d98 0d98 <halt> ; Flow R 0d99 0d99 <halt> ; Flow R 0d9a 0d9a <halt> ; Flow R 0d9b 0d9b <halt> ; Flow R 0d9c 0d9c <halt> ; Flow R 0d9d 0d9d <halt> ; Flow R 0d9e 0d9e <halt> ; Flow R 0d9f 0d9f <halt> ; Flow R 0da0 0da0 <halt> ; Flow R 0da1 0da1 <halt> ; Flow R 0da2 0da2 <halt> ; Flow R 0da3 0da3 <halt> ; Flow R 0da4 0da4 <halt> ; Flow R 0da5 0da5 <halt> ; Flow R 0da6 0da6 <halt> ; Flow R 0da7 0da7 <halt> ; Flow R 0da8 0da8 <halt> ; Flow R 0da9 0da9 <halt> ; Flow R 0daa 0daa <halt> ; Flow R 0dab 0dab <halt> ; Flow R 0dac 0dac <halt> ; Flow R 0dad 0dad <halt> ; Flow R 0dae 0dae <halt> ; Flow R 0daf 0daf <halt> ; Flow R 0db0 0db0 <halt> ; Flow R 0db1 0db1 <halt> ; Flow R 0db2 0db2 <halt> ; Flow R 0db3 0db3 <halt> ; Flow R 0db4 0db4 <halt> ; Flow R 0db5 0db5 <halt> ; Flow R 0db6 0db6 <halt> ; Flow R 0db7 0db7 <halt> ; Flow R 0db8 0db8 <halt> ; Flow R 0db9 0db9 <halt> ; Flow R 0dba 0dba <halt> ; Flow R 0dbb 0dbb <halt> ; Flow R 0dbc 0dbc <halt> ; Flow R 0dbd 0dbd <halt> ; Flow R 0dbe 0dbe <halt> ; Flow R 0dbf 0dbf <halt> ; Flow R 0dc0 0dc0 <halt> ; Flow R 0dc1 0dc1 <halt> ; Flow R 0dc2 0dc2 <halt> ; Flow R 0dc3 0dc3 <halt> ; Flow R 0dc4 0dc4 <halt> ; Flow R 0dc5 0dc5 <halt> ; Flow R 0dc6 0dc6 <halt> ; Flow R 0dc7 0dc7 <halt> ; Flow R 0dc8 0dc8 <halt> ; Flow R 0dc9 0dc9 <halt> ; Flow R 0dca 0dca <halt> ; Flow R 0dcb 0dcb <halt> ; Flow R 0dcc 0dcc <halt> ; Flow R 0dcd 0dcd <halt> ; Flow R 0dce 0dce <halt> ; Flow R 0dcf 0dcf <halt> ; Flow R 0dd0 0dd0 <halt> ; Flow R 0dd1 0dd1 <halt> ; Flow R 0dd2 0dd2 <halt> ; Flow R 0dd3 0dd3 <halt> ; Flow R 0dd4 0dd4 <halt> ; Flow R 0dd5 0dd5 <halt> ; Flow R 0dd6 0dd6 <halt> ; Flow R 0dd7 0dd7 <halt> ; Flow R 0dd8 0dd8 <halt> ; Flow R 0dd9 0dd9 <halt> ; Flow R 0dda 0dda <halt> ; Flow R 0ddb 0ddb <halt> ; Flow R 0ddc 0ddc <halt> ; Flow R 0ddd 0ddd <halt> ; Flow R 0dde 0dde <halt> ; Flow R 0ddf 0ddf <halt> ; Flow R 0de0 0de0 <halt> ; Flow R 0de1 0de1 <halt> ; Flow R 0de2 0de2 <halt> ; Flow R 0de3 0de3 <halt> ; Flow R 0de4 0de4 <halt> ; Flow R 0de5 0de5 <halt> ; Flow R 0de6 0de6 <halt> ; Flow R 0de7 0de7 <halt> ; Flow R 0de8 0de8 <halt> ; Flow R 0de9 0de9 <halt> ; Flow R 0dea 0dea <halt> ; Flow R 0deb 0deb <halt> ; Flow R 0dec 0dec <halt> ; Flow R 0ded 0ded <halt> ; Flow R 0dee 0dee <halt> ; Flow R 0def 0def <halt> ; Flow R 0df0 0df0 <halt> ; Flow R 0df1 0df1 <halt> ; Flow R 0df2 0df2 <halt> ; Flow R 0df3 0df3 <halt> ; Flow R 0df4 0df4 <halt> ; Flow R 0df5 0df5 <halt> ; Flow R 0df6 0df6 <halt> ; Flow R 0df7 0df7 <halt> ; Flow R 0df8 0df8 <halt> ; Flow R 0df9 0df9 <halt> ; Flow R 0dfa 0dfa <halt> ; Flow R 0dfb 0dfb <halt> ; Flow R 0dfc 0dfc <halt> ; Flow R 0dfd 0dfd <halt> ; Flow R 0dfe 0dfe <halt> ; Flow R 0dff 0dff <halt> ; Flow R 0e00 0e00 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 19 0e01 0e01 seq_br_type 3 Unconditional Branch; Flow J 0xe21 seq_branch_adr 0e21 0x0e21 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e02 0e02 seq_br_type 3 Unconditional Branch; Flow J 0xe44 seq_branch_adr 0e44 0x0e44 0e03 0e03 seq_br_type 3 Unconditional Branch; Flow J 0xe47 seq_branch_adr 0e47 0x0e47 0e04 0e04 seq_br_type 3 Unconditional Branch; Flow J 0xe4a seq_branch_adr 0e4a 0x0e4a 0e05 0e05 seq_br_type 3 Unconditional Branch; Flow J 0xe4d seq_branch_adr 0e4d 0x0e4d 0e06 0e06 seq_br_type 3 Unconditional Branch; Flow J 0xe52 seq_branch_adr 0e52 0x0e52 0e07 0e07 seq_br_type 3 Unconditional Branch; Flow J 0xe57 seq_branch_adr 0e57 0x0e57 0e08 0e08 seq_br_type 3 Unconditional Branch; Flow J 0xe5a seq_branch_adr 0e5a 0x0e5a 0e09 0e09 seq_br_type 3 Unconditional Branch; Flow J 0xe5d seq_branch_adr 0e5d 0x0e5d 0e0a 0e0a seq_br_type 3 Unconditional Branch; Flow J 0xe60 seq_branch_adr 0e60 0x0e60 0e0b 0e0b seq_br_type 3 Unconditional Branch; Flow J 0xe63 seq_branch_adr 0e63 0x0e63 0e0c 0e0c seq_br_type 3 Unconditional Branch; Flow J 0xe66 seq_branch_adr 0e66 0x0e66 0e0d 0e0d seq_br_type 3 Unconditional Branch; Flow J 0xe69 seq_branch_adr 0e69 0x0e69 0e0e 0e0e seq_br_type 3 Unconditional Branch; Flow J 0xe6c seq_branch_adr 0e6c 0x0e6c 0e0f 0e0f seq_br_type 3 Unconditional Branch; Flow J 0xe6f seq_branch_adr 0e6f 0x0e6f 0e10 0e10 seq_br_type 3 Unconditional Branch; Flow J 0xe72 seq_branch_adr 0e72 0x0e72 0e11 0e11 seq_br_type 3 Unconditional Branch; Flow J 0xe75 seq_branch_adr 0e75 0x0e75 0e12 0e12 seq_br_type 3 Unconditional Branch; Flow J 0xe78 seq_branch_adr 0e78 0x0e78 0e13 0e13 seq_br_type 3 Unconditional Branch; Flow J 0xe7b seq_branch_adr 0e7b 0x0e7b 0e14 0e14 seq_br_type 3 Unconditional Branch; Flow J 0xe7e seq_branch_adr 0e7e 0x0e7e 0e15 0e15 seq_br_type 3 Unconditional Branch; Flow J 0xe81 seq_branch_adr 0e81 0x0e81 0e16 0e16 seq_br_type 3 Unconditional Branch; Flow J 0xe84 seq_branch_adr 0e84 0x0e84 0e17 0e17 seq_br_type 3 Unconditional Branch; Flow J 0xe87 seq_branch_adr 0e87 0x0e87 0e18 0e18 seq_br_type 3 Unconditional Branch; Flow J 0xe8a seq_branch_adr 0e8a 0x0e8a 0e19 0e19 seq_br_type 3 Unconditional Branch; Flow J 0xe8d seq_branch_adr 0e8d 0x0e8d 0e1a 0e1a seq_br_type 3 Unconditional Branch; Flow J 0xe90 seq_branch_adr 0e90 0x0e90 0e1b 0e1b seq_br_type 3 Unconditional Branch; Flow J 0xe93 seq_branch_adr 0e93 0x0e93 0e1c 0e1c seq_br_type 3 Unconditional Branch; Flow J 0xe96 seq_branch_adr 0e96 0x0e96 0e1d 0e1d seq_br_type 3 Unconditional Branch; Flow J 0xe99 seq_branch_adr 0e99 0x0e99 0e1e 0e1e seq_br_type 3 Unconditional Branch; Flow J 0xe9c seq_branch_adr 0e9c 0x0e9c 0e1f 0e1f seq_br_type 3 Unconditional Branch; Flow J 0xe9f seq_branch_adr 0e9f 0x0e9f 0e20 0e20 seq_br_type 3 Unconditional Branch; Flow J 0xea2 seq_branch_adr 0ea2 0x0ea2 0e21 0e21 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e22 0e22 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e23 0e23 fiu_mem_start 18 acknowledge_refresh; Flow C 0x202 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0202 0x0202 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e24 0e24 fiu_mem_start 18 acknowledge_refresh; Flow C 0x400 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0400 0x0400 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e25 0e25 fiu_mem_start 18 acknowledge_refresh; Flow C 0x600 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0600 0x0600 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e26 0e26 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e27 0e27 seq_br_type 3 Unconditional Branch; Flow J 0x800 seq_branch_adr 0800 0x0800 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 0e28 0e28 seq_br_type 7 Unconditional Call; Flow C 0x8e7 seq_branch_adr 08e7 0x08e7 0e29 0e29 fiu_mem_start 18 acknowledge_refresh; Flow C 0xa00 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0a00 0x0a00 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2a 0e2a fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2b 0e2b fiu_mem_start 18 acknowledge_refresh; Flow C 0x1c00 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 1c00 0x1c00 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2c 0e2c fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2d 0e2d fiu_mem_start 18 acknowledge_refresh; Flow C 0x2600 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2600 0x2600 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2e 0e2e fiu_mem_start 18 acknowledge_refresh; Flow C 0x2800 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2800 0x2800 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e2f 0e2f fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e30 0e30 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e31 0e31 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e32 0e32 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e33 0e33 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e34 0e34 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e35 0e35 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e36 0e36 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e37 0e37 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e38 0e38 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e39 0e39 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3a 0e3a fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3b 0e3b fiu_mem_start 18 acknowledge_refresh; Flow C 0x2400 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2400 0x2400 val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3c 0e3c fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3d 0e3d fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3e 0e3e fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e3f 0e3f fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e40 0e40 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e41 0e41 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e42 0e42 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 0f GP0f val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e43 0e43 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e44 0e44 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e45 0e45 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 19 0e46 0e46 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e47 0e47 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e48 0e48 fiu_mem_start 18 acknowledge_refresh; Flow C 0x202 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0202 0x0202 val_a_adr 31 VR19:11 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 19 0e49 0e49 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e4a 0e4a seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e4b 0e4b fiu_mem_start 18 acknowledge_refresh; Flow C 0x400 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0400 0x0400 val_a_adr 31 VR1a:11 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e4c 0e4c ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e4d 0e4d seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e4e 0e4e fiu_mem_start 18 acknowledge_refresh; Flow C 0x600 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0600 0x0600 val_a_adr 31 VR1a:11 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e4f 0e4f fiu_mem_start 18 acknowledge_refresh; Flow C 0x2600 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2600 0x2600 val_a_adr 2c VR1a:0c val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e50 0e50 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2800 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2800 0x2800 val_a_adr 2b VR1a:0b val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e51 0e51 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e52 0e52 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e53 0e53 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 34 VR14:14 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 14 0e54 0e54 seq_br_type 3 Unconditional Branch; Flow J 0x800 seq_branch_adr 0800 0x0800 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 19 0e55 0e55 seq_br_type 7 Unconditional Call; Flow C 0x8e7 seq_branch_adr 08e7 0x08e7 0e56 0e56 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e57 0e57 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e58 0e58 fiu_mem_start 18 acknowledge_refresh; Flow C 0xa00 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0a00 0x0a00 val_a_adr 34 VR14:14 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 14 0e59 0e59 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e5a 0e5a seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e5b 0e5b fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e5c 0e5c ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e5d 0e5d seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e5e 0e5e fiu_mem_start 18 acknowledge_refresh; Flow C 0x1c00 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 1c00 0x1c00 val_a_adr 2d VR1a:0d val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e5f 0e5f ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e60 0e60 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e61 0e61 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 2c VR1a:0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e62 0e62 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e63 0e63 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e64 0e64 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2600 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2600 0x2600 val_a_adr 2c VR1a:0c val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e65 0e65 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e66 0e66 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e67 0e67 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2800 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2800 0x2800 val_a_adr 2b VR1a:0b val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e68 0e68 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e69 0e69 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e6a 0e6a fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 2b VR1a:0b val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e6b 0e6b ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e6c 0e6c seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e6d 0e6d fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e6e 0e6e ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e6f 0e6f seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e70 0e70 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 2a VR1a:0a val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e71 0e71 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e72 0e72 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e73 0e73 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0e74 0e74 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e75 0e75 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e76 0e76 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 22 VR13:02 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0e77 0e77 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e78 0e78 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e79 0e79 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 28 VR1a:08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e7a 0e7a ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e7b 0e7b seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e7c 0e7c fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 28 VR1a:08 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e7d 0e7d ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e7e 0e7e seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e7f 0e7f fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 27 VR1a:07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e80 0e80 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e81 0e81 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e82 0e82 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 27 VR1a:07 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e83 0e83 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e84 0e84 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e85 0e85 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 26 VR1a:06 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e86 0e86 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e87 0e87 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e88 0e88 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 26 VR1a:06 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e89 0e89 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e8a 0e8a seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e8b 0e8b fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 25 VR1a:05 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e8c 0e8c ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e8d 0e8d seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e8e 0e8e fiu_mem_start 18 acknowledge_refresh; Flow C 0x2400 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2400 0x2400 val_a_adr 25 VR1a:05 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e8f 0e8f ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e90 0e90 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e91 0e91 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 3a VR13:1a val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0e92 0e92 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e93 0e93 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e94 0e94 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 3a VR13:1a val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0e95 0e95 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e96 0e96 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e97 0e97 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 23 VR1a:03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e98 0e98 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e99 0e99 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e9a 0e9a fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 23 VR1a:03 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e9b 0e9b ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e9c 0e9c seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0e9d 0e9d fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 22 VR1a:02 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0e9e 0e9e ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0e9f 0e9f seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0ea0 0ea0 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 22 VR1a:02 val_alu_func 7 INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0ea1 0ea1 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0ea2 0ea2 seq_br_type 7 Unconditional Call; Flow C 0x2200 seq_branch_adr 2200 0x2200 0ea3 0ea3 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 21 VR1a:01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 1a 0ea4 0ea4 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_alu_func 13 ONES val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0ea5 0ea5 <halt> ; Flow R 0ea6 0ea6 <halt> ; Flow R 0ea7 0ea7 <halt> ; Flow R 0ea8 0ea8 <halt> ; Flow R 0ea9 0ea9 <halt> ; Flow R 0eaa 0eaa <halt> ; Flow R 0eab 0eab <halt> ; Flow R 0eac 0eac <halt> ; Flow R 0ead 0ead <halt> ; Flow R 0eae 0eae <halt> ; Flow R 0eaf 0eaf <halt> ; Flow R 0eb0 0eb0 <halt> ; Flow R 0eb1 0eb1 <halt> ; Flow R 0eb2 0eb2 <halt> ; Flow R 0eb3 0eb3 <halt> ; Flow R 0eb4 0eb4 <halt> ; Flow R 0eb5 0eb5 <halt> ; Flow R 0eb6 0eb6 <halt> ; Flow R 0eb7 0eb7 <halt> ; Flow R 0eb8 0eb8 <halt> ; Flow R 0eb9 0eb9 <halt> ; Flow R 0eba 0eba <halt> ; Flow R 0ebb 0ebb <halt> ; Flow R 0ebc 0ebc <halt> ; Flow R 0ebd 0ebd <halt> ; Flow R 0ebe 0ebe <halt> ; Flow R 0ebf 0ebf <halt> ; Flow R 0ec0 0ec0 <halt> ; Flow R 0ec1 0ec1 <halt> ; Flow R 0ec2 0ec2 <halt> ; Flow R 0ec3 0ec3 <halt> ; Flow R 0ec4 0ec4 <halt> ; Flow R 0ec5 0ec5 <halt> ; Flow R 0ec6 0ec6 <halt> ; Flow R 0ec7 0ec7 <halt> ; Flow R 0ec8 0ec8 <halt> ; Flow R 0ec9 0ec9 <halt> ; Flow R 0eca 0eca <halt> ; Flow R 0ecb 0ecb <halt> ; Flow R 0ecc 0ecc <halt> ; Flow R 0ecd 0ecd <halt> ; Flow R 0ece 0ece <halt> ; Flow R 0ecf 0ecf <halt> ; Flow R 0ed0 0ed0 <halt> ; Flow R 0ed1 0ed1 <halt> ; Flow R 0ed2 0ed2 <halt> ; Flow R 0ed3 0ed3 <halt> ; Flow R 0ed4 0ed4 <halt> ; Flow R 0ed5 0ed5 <halt> ; Flow R 0ed6 0ed6 <halt> ; Flow R 0ed7 0ed7 <halt> ; Flow R 0ed8 0ed8 <halt> ; Flow R 0ed9 0ed9 <halt> ; Flow R 0eda 0eda <halt> ; Flow R 0edb 0edb <halt> ; Flow R 0edc 0edc <halt> ; Flow R 0edd 0edd <halt> ; Flow R 0ede 0ede <halt> ; Flow R 0edf 0edf <halt> ; Flow R 0ee0 0ee0 <halt> ; Flow R 0ee1 0ee1 <halt> ; Flow R 0ee2 0ee2 <halt> ; Flow R 0ee3 0ee3 <halt> ; Flow R 0ee4 0ee4 <halt> ; Flow R 0ee5 0ee5 <halt> ; Flow R 0ee6 0ee6 <halt> ; Flow R 0ee7 0ee7 <halt> ; Flow R 0ee8 0ee8 <halt> ; Flow R 0ee9 0ee9 <halt> ; Flow R 0eea 0eea <halt> ; Flow R 0eeb 0eeb <halt> ; Flow R 0eec 0eec <halt> ; Flow R 0eed 0eed <halt> ; Flow R 0eee 0eee <halt> ; Flow R 0eef 0eef <halt> ; Flow R 0ef0 0ef0 <halt> ; Flow R 0ef1 0ef1 <halt> ; Flow R 0ef2 0ef2 <halt> ; Flow R 0ef3 0ef3 <halt> ; Flow R 0ef4 0ef4 <halt> ; Flow R 0ef5 0ef5 <halt> ; Flow R 0ef6 0ef6 <halt> ; Flow R 0ef7 0ef7 <halt> ; Flow R 0ef8 0ef8 <halt> ; Flow R 0ef9 0ef9 <halt> ; Flow R 0efa 0efa <halt> ; Flow R 0efb 0efb <halt> ; Flow R 0efc 0efc <halt> ; Flow R 0efd 0efd <halt> ; Flow R 0efe 0efe <halt> ; Flow R 0eff 0eff <halt> ; Flow R 0f00 0f00 <halt> ; Flow R 0f01 0f01 <halt> ; Flow R 0f02 0f02 <halt> ; Flow R 0f03 0f03 <halt> ; Flow R 0f04 0f04 <halt> ; Flow R 0f05 0f05 <halt> ; Flow R 0f06 0f06 <halt> ; Flow R 0f07 0f07 <halt> ; Flow R 0f08 0f08 <halt> ; Flow R 0f09 0f09 <halt> ; Flow R 0f0a 0f0a <halt> ; Flow R 0f0b 0f0b <halt> ; Flow R 0f0c 0f0c <halt> ; Flow R 0f0d 0f0d <halt> ; Flow R 0f0e 0f0e <halt> ; Flow R 0f0f 0f0f <halt> ; Flow R 0f10 0f10 <halt> ; Flow R 0f11 0f11 <halt> ; Flow R 0f12 0f12 <halt> ; Flow R 0f13 0f13 <halt> ; Flow R 0f14 0f14 <halt> ; Flow R 0f15 0f15 <halt> ; Flow R 0f16 0f16 <halt> ; Flow R 0f17 0f17 <halt> ; Flow R 0f18 0f18 <halt> ; Flow R 0f19 0f19 <halt> ; Flow R 0f1a 0f1a <halt> ; Flow R 0f1b 0f1b <halt> ; Flow R 0f1c 0f1c <halt> ; Flow R 0f1d 0f1d <halt> ; Flow R 0f1e 0f1e <halt> ; Flow R 0f1f 0f1f <halt> ; Flow R 0f20 0f20 <halt> ; Flow R 0f21 0f21 <halt> ; Flow R 0f22 0f22 <halt> ; Flow R 0f23 0f23 <halt> ; Flow R 0f24 0f24 <halt> ; Flow R 0f25 0f25 <halt> ; Flow R 0f26 0f26 <halt> ; Flow R 0f27 0f27 <halt> ; Flow R 0f28 0f28 <halt> ; Flow R 0f29 0f29 <halt> ; Flow R 0f2a 0f2a <halt> ; Flow R 0f2b 0f2b <halt> ; Flow R 0f2c 0f2c <halt> ; Flow R 0f2d 0f2d <halt> ; Flow R 0f2e 0f2e <halt> ; Flow R 0f2f 0f2f <halt> ; Flow R 0f30 0f30 <halt> ; Flow R 0f31 0f31 <halt> ; Flow R 0f32 0f32 <halt> ; Flow R 0f33 0f33 <halt> ; Flow R 0f34 0f34 <halt> ; Flow R 0f35 0f35 <halt> ; Flow R 0f36 0f36 <halt> ; Flow R 0f37 0f37 <halt> ; Flow R 0f38 0f38 <halt> ; Flow R 0f39 0f39 <halt> ; Flow R 0f3a 0f3a <halt> ; Flow R 0f3b 0f3b <halt> ; Flow R 0f3c 0f3c <halt> ; Flow R 0f3d 0f3d <halt> ; Flow R 0f3e 0f3e <halt> ; Flow R 0f3f 0f3f <halt> ; Flow R 0f40 0f40 <halt> ; Flow R 0f41 0f41 <halt> ; Flow R 0f42 0f42 <halt> ; Flow R 0f43 0f43 <halt> ; Flow R 0f44 0f44 <halt> ; Flow R 0f45 0f45 <halt> ; Flow R 0f46 0f46 <halt> ; Flow R 0f47 0f47 <halt> ; Flow R 0f48 0f48 <halt> ; Flow R 0f49 0f49 <halt> ; Flow R 0f4a 0f4a <halt> ; Flow R 0f4b 0f4b <halt> ; Flow R 0f4c 0f4c <halt> ; Flow R 0f4d 0f4d <halt> ; Flow R 0f4e 0f4e <halt> ; Flow R 0f4f 0f4f <halt> ; Flow R 0f50 0f50 <halt> ; Flow R 0f51 0f51 <halt> ; Flow R 0f52 0f52 <halt> ; Flow R 0f53 0f53 <halt> ; Flow R 0f54 0f54 <halt> ; Flow R 0f55 0f55 <halt> ; Flow R 0f56 0f56 <halt> ; Flow R 0f57 0f57 <halt> ; Flow R 0f58 0f58 <halt> ; Flow R 0f59 0f59 <halt> ; Flow R 0f5a 0f5a <halt> ; Flow R 0f5b 0f5b <halt> ; Flow R 0f5c 0f5c <halt> ; Flow R 0f5d 0f5d <halt> ; Flow R 0f5e 0f5e <halt> ; Flow R 0f5f 0f5f <halt> ; Flow R 0f60 0f60 <halt> ; Flow R 0f61 0f61 <halt> ; Flow R 0f62 0f62 <halt> ; Flow R 0f63 0f63 <halt> ; Flow R 0f64 0f64 <halt> ; Flow R 0f65 0f65 <halt> ; Flow R 0f66 0f66 <halt> ; Flow R 0f67 0f67 <halt> ; Flow R 0f68 0f68 <halt> ; Flow R 0f69 0f69 <halt> ; Flow R 0f6a 0f6a <halt> ; Flow R 0f6b 0f6b <halt> ; Flow R 0f6c 0f6c <halt> ; Flow R 0f6d 0f6d <halt> ; Flow R 0f6e 0f6e <halt> ; Flow R 0f6f 0f6f <halt> ; Flow R 0f70 0f70 <halt> ; Flow R 0f71 0f71 <halt> ; Flow R 0f72 0f72 <halt> ; Flow R 0f73 0f73 <halt> ; Flow R 0f74 0f74 <halt> ; Flow R 0f75 0f75 <halt> ; Flow R 0f76 0f76 <halt> ; Flow R 0f77 0f77 <halt> ; Flow R 0f78 0f78 <halt> ; Flow R 0f79 0f79 <halt> ; Flow R 0f7a 0f7a <halt> ; Flow R 0f7b 0f7b <halt> ; Flow R 0f7c 0f7c <halt> ; Flow R 0f7d 0f7d <halt> ; Flow R 0f7e 0f7e <halt> ; Flow R 0f7f 0f7f <halt> ; Flow R 0f80 0f80 <halt> ; Flow R 0f81 0f81 <halt> ; Flow R 0f82 0f82 <halt> ; Flow R 0f83 0f83 <halt> ; Flow R 0f84 0f84 <halt> ; Flow R 0f85 0f85 <halt> ; Flow R 0f86 0f86 <halt> ; Flow R 0f87 0f87 <halt> ; Flow R 0f88 0f88 <halt> ; Flow R 0f89 0f89 <halt> ; Flow R 0f8a 0f8a <halt> ; Flow R 0f8b 0f8b <halt> ; Flow R 0f8c 0f8c <halt> ; Flow R 0f8d 0f8d <halt> ; Flow R 0f8e 0f8e <halt> ; Flow R 0f8f 0f8f <halt> ; Flow R 0f90 0f90 <halt> ; Flow R 0f91 0f91 <halt> ; Flow R 0f92 0f92 <halt> ; Flow R 0f93 0f93 <halt> ; Flow R 0f94 0f94 <halt> ; Flow R 0f95 0f95 <halt> ; Flow R 0f96 0f96 <halt> ; Flow R 0f97 0f97 <halt> ; Flow R 0f98 0f98 <halt> ; Flow R 0f99 0f99 <halt> ; Flow R 0f9a 0f9a <halt> ; Flow R 0f9b 0f9b <halt> ; Flow R 0f9c 0f9c <halt> ; Flow R 0f9d 0f9d <halt> ; Flow R 0f9e 0f9e <halt> ; Flow R 0f9f 0f9f <halt> ; Flow R 0fa0 0fa0 <halt> ; Flow R 0fa1 0fa1 <halt> ; Flow R 0fa2 0fa2 <halt> ; Flow R 0fa3 0fa3 <halt> ; Flow R 0fa4 0fa4 <halt> ; Flow R 0fa5 0fa5 <halt> ; Flow R 0fa6 0fa6 <halt> ; Flow R 0fa7 0fa7 <halt> ; Flow R 0fa8 0fa8 <halt> ; Flow R 0fa9 0fa9 <halt> ; Flow R 0faa 0faa <halt> ; Flow R 0fab 0fab <halt> ; Flow R 0fac 0fac <halt> ; Flow R 0fad 0fad <halt> ; Flow R 0fae 0fae <halt> ; Flow R 0faf 0faf <halt> ; Flow R 0fb0 0fb0 <halt> ; Flow R 0fb1 0fb1 <halt> ; Flow R 0fb2 0fb2 <halt> ; Flow R 0fb3 0fb3 <halt> ; Flow R 0fb4 0fb4 <halt> ; Flow R 0fb5 0fb5 <halt> ; Flow R 0fb6 0fb6 <halt> ; Flow R 0fb7 0fb7 <halt> ; Flow R 0fb8 0fb8 <halt> ; Flow R 0fb9 0fb9 <halt> ; Flow R 0fba 0fba <halt> ; Flow R 0fbb 0fbb <halt> ; Flow R 0fbc 0fbc <halt> ; Flow R 0fbd 0fbd <halt> ; Flow R 0fbe 0fbe <halt> ; Flow R 0fbf 0fbf <halt> ; Flow R 0fc0 0fc0 <halt> ; Flow R 0fc1 0fc1 <halt> ; Flow R 0fc2 0fc2 <halt> ; Flow R 0fc3 0fc3 <halt> ; Flow R 0fc4 0fc4 <halt> ; Flow R 0fc5 0fc5 <halt> ; Flow R 0fc6 0fc6 <halt> ; Flow R 0fc7 0fc7 <halt> ; Flow R 0fc8 0fc8 <halt> ; Flow R 0fc9 0fc9 <halt> ; Flow R 0fca 0fca <halt> ; Flow R 0fcb 0fcb <halt> ; Flow R 0fcc 0fcc <halt> ; Flow R 0fcd 0fcd <halt> ; Flow R 0fce 0fce <halt> ; Flow R 0fcf 0fcf <halt> ; Flow R 0fd0 0fd0 <halt> ; Flow R 0fd1 0fd1 <halt> ; Flow R 0fd2 0fd2 <halt> ; Flow R 0fd3 0fd3 <halt> ; Flow R 0fd4 0fd4 <halt> ; Flow R 0fd5 0fd5 <halt> ; Flow R 0fd6 0fd6 <halt> ; Flow R 0fd7 0fd7 <halt> ; Flow R 0fd8 0fd8 <halt> ; Flow R 0fd9 0fd9 <halt> ; Flow R 0fda 0fda <halt> ; Flow R 0fdb 0fdb <halt> ; Flow R 0fdc 0fdc <halt> ; Flow R 0fdd 0fdd <halt> ; Flow R 0fde 0fde <halt> ; Flow R 0fdf 0fdf <halt> ; Flow R 0fe0 0fe0 <halt> ; Flow R 0fe1 0fe1 <halt> ; Flow R 0fe2 0fe2 <halt> ; Flow R 0fe3 0fe3 <halt> ; Flow R 0fe4 0fe4 <halt> ; Flow R 0fe5 0fe5 <halt> ; Flow R 0fe6 0fe6 <halt> ; Flow R 0fe7 0fe7 <halt> ; Flow R 0fe8 0fe8 <halt> ; Flow R 0fe9 0fe9 <halt> ; Flow R 0fea 0fea <halt> ; Flow R 0feb 0feb <halt> ; Flow R 0fec 0fec <halt> ; Flow R 0fed 0fed <halt> ; Flow R 0fee 0fee <halt> ; Flow R 0fef 0fef <halt> ; Flow R 0ff0 0ff0 <halt> ; Flow R 0ff1 0ff1 <halt> ; Flow R 0ff2 0ff2 <halt> ; Flow R 0ff3 0ff3 <halt> ; Flow R 0ff4 0ff4 <halt> ; Flow R 0ff5 0ff5 <halt> ; Flow R 0ff6 0ff6 <halt> ; Flow R 0ff7 0ff7 <halt> ; Flow R 0ff8 0ff8 <halt> ; Flow R 0ff9 0ff9 <halt> ; Flow R 0ffa 0ffa <halt> ; Flow R 0ffb 0ffb <halt> ; Flow R 0ffc 0ffc <halt> ; Flow R 0ffd 0ffd <halt> ; Flow R 0ffe 0ffe <halt> ; Flow R 0fff 0fff <halt> ; Flow R 1000 1000 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 1e A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1001 1001 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1002 1002 val_a_adr 20 VR15:00 val_alu_func 1e A_AND_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1003 1003 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1004 1004 val_a_adr 23 VR15:03 val_alu_func 1e A_AND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1005 1005 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1006 1006 val_a_adr 21 VR15:01 val_alu_func 1e A_AND_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1007 1007 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1008 1008 val_a_adr 24 VR15:04 val_alu_func 1e A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1009 1009 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 100a 100a val_a_adr 20 VR15:00 val_alu_func 1e A_AND_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 100b 100b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 100c 100c val_a_adr 25 VR15:05 val_alu_func 1e A_AND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 100d 100d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 100e 100e val_a_adr 21 VR15:01 val_alu_func 1e A_AND_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 100f 100f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1010 1010 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 1b A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1011 1011 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1012 1012 val_a_adr 20 VR15:00 val_alu_func 1b A_OR_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1013 1013 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1014 1014 val_a_adr 23 VR15:03 val_alu_func 1b A_OR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1015 1015 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1016 1016 val_a_adr 21 VR15:01 val_alu_func 1b A_OR_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1017 1017 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1018 1018 val_a_adr 24 VR15:04 val_alu_func 1b A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1019 1019 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 101a 101a val_a_adr 20 VR15:00 val_alu_func 1b A_OR_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 101b 101b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 101c 101c val_a_adr 25 VR15:05 val_alu_func 1b A_OR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 101d 101d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 101e 101e val_a_adr 21 VR15:01 val_alu_func 1b A_OR_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 101f 101f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1020 1020 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1021 1021 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1022 1022 val_a_adr 20 VR15:00 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1023 1023 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1024 1024 val_a_adr 23 VR15:03 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1025 1025 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1026 1026 val_a_adr 21 VR15:01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1027 1027 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1028 1028 val_a_adr 24 VR15:04 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1029 1029 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 102a 102a val_a_adr 20 VR15:00 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 102b 102b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 102c 102c val_a_adr 25 VR15:05 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 102d 102d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 102e 102e val_a_adr 21 VR15:01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 102f 102f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1030 1030 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 11 A_NAND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1031 1031 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1032 1032 val_a_adr 20 VR15:00 val_alu_func 11 A_NAND_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1033 1033 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1034 1034 val_a_adr 23 VR15:03 val_alu_func 11 A_NAND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1035 1035 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1036 1036 val_a_adr 21 VR15:01 val_alu_func 11 A_NAND_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1037 1037 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1038 1038 val_a_adr 24 VR15:04 val_alu_func 11 A_NAND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1039 1039 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 103a 103a val_a_adr 20 VR15:00 val_alu_func 11 A_NAND_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 103b 103b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 103c 103c val_a_adr 25 VR15:05 val_alu_func 11 A_NAND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 103d 103d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 103e 103e val_a_adr 21 VR15:01 val_alu_func 11 A_NAND_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 103f 103f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1040 1040 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 14 A_NOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1041 1041 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1042 1042 val_a_adr 20 VR15:00 val_alu_func 14 A_NOR_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1043 1043 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1044 1044 val_a_adr 23 VR15:03 val_alu_func 14 A_NOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1045 1045 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1046 1046 val_a_adr 21 VR15:01 val_alu_func 14 A_NOR_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1047 1047 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1048 1048 val_a_adr 24 VR15:04 val_alu_func 14 A_NOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1049 1049 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 104a 104a val_a_adr 20 VR15:00 val_alu_func 14 A_NOR_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 104b 104b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 104c 104c val_a_adr 25 VR15:05 val_alu_func 14 A_NOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 104d 104d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 104e 104e val_a_adr 21 VR15:01 val_alu_func 14 A_NOR_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 104f 104f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1050 1050 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 16 A_XNOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1051 1051 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1052 1052 val_a_adr 20 VR15:00 val_alu_func 16 A_XNOR_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1053 1053 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1054 1054 val_a_adr 23 VR15:03 val_alu_func 16 A_XNOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1055 1055 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1056 1056 val_a_adr 21 VR15:01 val_alu_func 16 A_XNOR_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1057 1057 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1058 1058 val_a_adr 24 VR15:04 val_alu_func 16 A_XNOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1059 1059 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 105a 105a val_a_adr 20 VR15:00 val_alu_func 16 A_XNOR_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 105b 105b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 105c 105c val_a_adr 25 VR15:05 val_alu_func 16 A_XNOR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 105d 105d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 105e 105e val_a_adr 21 VR15:01 val_alu_func 16 A_XNOR_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 105f 105f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1060 1060 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 18 NOT_A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1061 1061 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1062 1062 val_a_adr 20 VR15:00 val_alu_func 18 NOT_A_AND_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1063 1063 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1064 1064 val_a_adr 23 VR15:03 val_alu_func 18 NOT_A_AND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1065 1065 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1066 1066 val_a_adr 21 VR15:01 val_alu_func 18 NOT_A_AND_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1067 1067 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1068 1068 val_a_adr 24 VR15:04 val_alu_func 18 NOT_A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1069 1069 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 106a 106a val_a_adr 20 VR15:00 val_alu_func 18 NOT_A_AND_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 106b 106b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 106c 106c val_a_adr 25 VR15:05 val_alu_func 18 NOT_A_AND_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 106d 106d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 106e 106e val_a_adr 21 VR15:01 val_alu_func 18 NOT_A_AND_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 106f 106f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1070 1070 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 1d A_AND_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1071 1071 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1072 1072 val_a_adr 20 VR15:00 val_alu_func 1d A_AND_NOT_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1073 1073 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1074 1074 val_a_adr 23 VR15:03 val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1075 1075 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR15:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1076 1076 val_a_adr 21 VR15:01 val_alu_func 1d A_AND_NOT_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1077 1077 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1078 1078 val_a_adr 24 VR15:04 val_alu_func 1d A_AND_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1079 1079 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR15:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 107a 107a val_a_adr 20 VR15:00 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 107b 107b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 107c 107c val_a_adr 25 VR15:05 val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 107d 107d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR15:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 107e 107e val_a_adr 21 VR15:01 val_alu_func 1d A_AND_NOT_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 107f 107f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR15:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1080 1080 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 12 NOT_A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1081 1081 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1082 1082 val_a_adr 20 VR15:00 val_alu_func 12 NOT_A_OR_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1083 1083 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1084 1084 val_a_adr 23 VR15:03 val_alu_func 12 NOT_A_OR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1085 1085 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1086 1086 val_a_adr 21 VR15:01 val_alu_func 12 NOT_A_OR_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1087 1087 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1088 1088 val_a_adr 24 VR15:04 val_alu_func 12 NOT_A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1089 1089 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 108a 108a val_a_adr 20 VR15:00 val_alu_func 12 NOT_A_OR_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 108b 108b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 108c 108c val_a_adr 25 VR15:05 val_alu_func 12 NOT_A_OR_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 108d 108d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 108e 108e val_a_adr 21 VR15:01 val_alu_func 12 NOT_A_OR_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 108f 108f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1090 1090 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 17 A_OR_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1091 1091 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1092 1092 val_a_adr 20 VR15:00 val_alu_func 17 A_OR_NOT_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1093 1093 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1094 1094 val_a_adr 23 VR15:03 val_alu_func 17 A_OR_NOT_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1095 1095 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1096 1096 val_a_adr 21 VR15:01 val_alu_func 17 A_OR_NOT_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1097 1097 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR15:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1098 1098 val_a_adr 24 VR15:04 val_alu_func 17 A_OR_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1099 1099 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 109a 109a val_a_adr 20 VR15:00 val_alu_func 17 A_OR_NOT_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 109b 109b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR15:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 109c 109c val_a_adr 25 VR15:05 val_alu_func 17 A_OR_NOT_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 109d 109d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR15:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 109e 109e val_a_adr 21 VR15:01 val_alu_func 17 A_OR_NOT_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 109f 109f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR15:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10a0 10a0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 10a1 10a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 10a2 10a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 10a3 10a3 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10a4 10a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10a5 10a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 10a6 10a6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 3c VR19:1c val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10a7 10a7 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3c VR19:1c val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10a8 10a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR19:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 10a9 10a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10aa 10aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ab 10ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR15:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10ac 10ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ad 10ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ae 10ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR15:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10af 10af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b0 10b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b1 10b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR15:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10b2 10b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b3 10b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b4 10b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR15:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10b5 10b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b6 10b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b7 10b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR15:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10b8 10b8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10b9 10b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ba 10ba seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR15:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10bb 10bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 10bc 10bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 10bd 10bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 10be 10be seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 31 VR19:11 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10bf 10bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 31 VR19:11 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10c0 10c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 10c1 10c1 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 3b VR19:1b val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10c2 10c2 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 3b VR19:1b val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 10c3 10c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR19:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 10c4 10c4 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10c5 10c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10c6 10c6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 34 VR15:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10c7 10c7 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10c8 10c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10c9 10c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 35 VR15:15 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10ca 10ca seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10cb 10cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10cc 10cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR15:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10cd 10cd seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ce 10ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10cf 10cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 37 VR15:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10d0 10d0 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d1 10d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d2 10d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR15:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10d3 10d3 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d4 10d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d5 10d5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR15:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10d6 10d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR15:00 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d7 10d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR16:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10d8 10d8 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10d9 10d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR16:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10da 10da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10db 10db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR16:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10dc 10dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10dd 10dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR16:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10de 10de seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10df 10df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR16:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10e0 10e0 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10e1 10e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 34 VR16:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10e2 10e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR15:00 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10e3 10e3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR16:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10e4 10e4 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10e5 10e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR16:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10e6 10e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10e7 10e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR16:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10e8 10e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10e9 10e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR16:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10ea 10ea seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10eb 10eb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR16:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10ec 10ec seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ed 10ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 35 VR16:15 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10ee 10ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ef 10ef seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f0 10f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10f1 10f1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f2 10f2 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f3 10f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10f4 10f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f5 10f5 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f6 10f6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR16:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10f7 10f7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f8 10f8 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10f9 10f9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR16:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 10fa 10fa seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10fb 10fb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10fc 10fc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR15:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 10fd 10fd seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10fe 10fe seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 10ff 10ff seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR15:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1100 1100 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1101 1101 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1102 1102 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR16:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1103 1103 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1104 1104 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 1 A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1105 1105 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR16:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1106 1106 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1107 1107 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1108 1108 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR16:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1109 1109 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 110a 110a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 110b 110b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR16:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 110c 110c seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 110d 110d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 110e 110e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR15:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 110f 110f seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1110 1110 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1111 1111 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR15:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1112 1112 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1113 1113 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1114 1114 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR16:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1115 1115 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1116 1116 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1117 1117 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR16:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1118 1118 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1119 1119 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 1 A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 111a 111a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR16:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 111b 111b seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 111c 111c seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 1 A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 111d 111d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR16:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 111e 111e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 111f 111f seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1120 1120 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR16:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1121 1121 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1122 1122 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1123 1123 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR16:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1124 1124 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1125 1125 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1126 1126 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR16:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1127 1127 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1128 1128 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1129 1129 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR16:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 112a 112a seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 112b 112b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 112c 112c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR15:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 112d 112d seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 112e 112e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 112f 112f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR15:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1130 1130 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1131 1131 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1132 1132 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR16:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1133 1133 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1134 1134 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1135 1135 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR16:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1136 1136 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1137 1137 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1138 1138 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1139 1139 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 113a 113a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 113b 113b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 113c 113c seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 113d 113d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 113e 113e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR15:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 113f 113f seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1140 1140 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1141 1141 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR15:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1142 1142 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1143 1143 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1144 1144 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR16:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1145 1145 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1146 1146 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1147 1147 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR16:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1148 1148 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1149 1149 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 2 INC_A_PLUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 114a 114a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR15:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 114b 114b seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 114c 114c seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 2 INC_A_PLUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 114d 114d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR15:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 114e 114e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 114f 114f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1150 1150 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1151 1151 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1152 1152 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1153 1153 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR15:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1154 1154 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1155 1155 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1156 1156 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR15:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1157 1157 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1158 1158 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1159 1159 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR16:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 115a 115a seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 115b 115b seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 115c 115c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR16:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 115d 115d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 115e 115e seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 115f 115f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR16:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1160 1160 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1161 1161 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1162 1162 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR15:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1163 1163 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1164 1164 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 6 A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1165 1165 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR16:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1166 1166 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1167 1167 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1168 1168 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR16:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1169 1169 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 116a 116a seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 116b 116b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR16:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 116c 116c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 116d 116d seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 116e 116e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR16:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 116f 116f seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1170 1170 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1171 1171 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR15:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1172 1172 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1173 1173 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1174 1174 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR15:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1175 1175 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1176 1176 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1177 1177 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1178 1178 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1179 1179 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 6 A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 117a 117a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR16:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 117b 117b seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 117c 117c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 6 A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 117d 117d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR15:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 117e 117e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 117f 117f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1180 1180 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR16:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1181 1181 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1182 1182 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1183 1183 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR15:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1184 1184 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1185 1185 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1186 1186 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR15:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1187 1187 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1188 1188 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1189 1189 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR16:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 118a 118a seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 118b 118b seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 118c 118c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR16:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 118d 118d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 118e 118e seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 118f 118f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1190 1190 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1191 1191 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1192 1192 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR16:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1193 1193 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1194 1194 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 20 VR15:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1195 1195 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR16:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1196 1196 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1197 1197 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1198 1198 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1199 1199 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 119a 119a seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 119b 119b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR16:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 119c 119c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 23 VR15:03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 119d 119d seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 23 VR15:03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 119e 119e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR16:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 119f 119f seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a0 11a0 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a1 11a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR16:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 11a2 11a2 seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 24 VR15:04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a3 11a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 24 VR15:04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a4 11a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR15:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11a5 11a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a6 11a6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a7 11a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR16:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 11a8 11a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 25 VR15:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11a9 11a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 25 VR15:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11aa 11aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR16:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 11ab 11ab seq_br_type 0 Branch False; Flow J cc=False 0x11f7 seq_branch_adr 11f7 0x11f7 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11ac 11ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) val_a_adr 21 VR15:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11ad 11ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR15:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11ae 11ae seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11af 11af seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11b0 11b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11b1 11b1 seq_cond_sel 16 VAL.TRUE(early) 11b2 11b2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11b3 11b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11b4 11b4 seq_cond_sel 17 VAL.FALSE(early) 11b5 11b5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11b6 11b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11b7 11b7 seq_cond_sel 17 VAL.FALSE(early) 11b8 11b8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11b9 11b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11ba 11ba seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11bb 11bb seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11bc 11bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11bd 11bd seq_cond_sel 16 VAL.TRUE(early) 11be 11be seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11bf 11bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11c0 11c0 seq_cond_sel 17 VAL.FALSE(early) 11c1 11c1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11c2 11c2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11c3 11c3 seq_cond_sel 17 VAL.FALSE(early) 11c4 11c4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 11c5 11c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 11c6 11c6 seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11c7 11c7 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11c8 11c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11c9 11c9 seq_cond_sel 16 VAL.TRUE(early) 11ca 11ca seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11cb 11cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11cc 11cc seq_cond_sel 17 VAL.FALSE(early) 11cd 11cd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11ce 11ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11cf 11cf seq_cond_sel 17 VAL.FALSE(early) 11d0 11d0 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11d1 11d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11d2 11d2 seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11d3 11d3 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11d4 11d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11d5 11d5 seq_cond_sel 16 VAL.TRUE(early) 11d6 11d6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11d7 11d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11d8 11d8 seq_cond_sel 17 VAL.FALSE(early) 11d9 11d9 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11da 11da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11db 11db seq_cond_sel 17 VAL.FALSE(early) 11dc 11dc seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 11dd 11dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11de 11de seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11df 11df seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11e0 11e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11e1 11e1 seq_cond_sel 16 VAL.TRUE(early) 11e2 11e2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11e3 11e3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11e4 11e4 seq_cond_sel 17 VAL.FALSE(early) 11e5 11e5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11e6 11e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11e7 11e7 seq_cond_sel 17 VAL.FALSE(early) 11e8 11e8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11e9 11e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11ea 11ea seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 11eb 11eb seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11ec 11ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11ed 11ed seq_cond_sel 16 VAL.TRUE(early) 11ee 11ee seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11ef 11ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 11f0 11f0 seq_cond_sel 17 VAL.FALSE(early) 11f1 11f1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11f2 11f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11f3 11f3 seq_cond_sel 17 VAL.FALSE(early) 11f4 11f4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 11f5 11f5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 11f6 11f6 seq_br_type 3 Unconditional Branch; Flow J 0x1200 seq_branch_adr 1200 0x1200 11f7 11f7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU 11f8 11f8 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 11f9 11f9 <halt> ; Flow R 11fa 11fa <halt> ; Flow R 11fb 11fb <halt> ; Flow R 11fc 11fc <halt> ; Flow R 11fd 11fd <halt> ; Flow R 11fe 11fe <halt> ; Flow R 11ff 11ff <halt> ; Flow R 1200 1200 seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 1201 1201 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1202 1202 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1203 1203 seq_cond_sel 16 VAL.TRUE(early) 1204 1204 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1205 1205 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1206 1206 seq_cond_sel 17 VAL.FALSE(early) 1207 1207 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1208 1208 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1209 1209 seq_cond_sel 17 VAL.FALSE(early) 120a 120a seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 120b 120b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 120c 120c seq_cond_sel 16 VAL.TRUE(early) typ_rand e CHECK_CLASS_SYSTEM_B 120d 120d seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 120e 120e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 120f 120f seq_cond_sel 16 VAL.TRUE(early) 1210 1210 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1211 1211 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR16:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1212 1212 seq_cond_sel 17 VAL.FALSE(early) 1213 1213 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1214 1214 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1215 1215 seq_cond_sel 17 VAL.FALSE(early) 1216 1216 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1217 1217 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR15:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1218 1218 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1219 1219 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR16:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 121a 121a val_a_adr 22 VR15:02 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 121b 121b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 37 VR16:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 121c 121c val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 121d 121d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 121e 121e val_a_adr 22 VR15:02 val_alu_func 1a PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 121f 121f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR16:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1220 1220 val_a_adr 22 VR15:02 val_alu_func 10 NOT_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1221 1221 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR16:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1222 1222 val_a_adr 22 VR15:02 val_alu_func 15 NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1223 1223 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR16:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1224 1224 val_a_adr 22 VR15:02 val_alu_func 1e A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1225 1225 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR16:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1226 1226 val_a_adr 22 VR15:02 val_alu_func 1b A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1227 1227 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR16:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1228 1228 val_a_adr 22 VR15:02 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1229 1229 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR16:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 122a 122a val_a_adr 22 VR15:02 val_alu_func 11 A_NAND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 122b 122b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR16:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 122c 122c val_a_adr 22 VR15:02 val_alu_func 14 A_NOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 122d 122d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR16:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 122e 122e val_a_adr 22 VR15:02 val_alu_func 16 A_XNOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 122f 122f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR17:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1230 1230 val_a_adr 22 VR15:02 val_alu_func 18 NOT_A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1231 1231 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR17:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1232 1232 val_a_adr 22 VR15:02 val_alu_func 1d A_AND_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1233 1233 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR17:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1234 1234 val_a_adr 22 VR15:02 val_alu_func 12 NOT_A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1235 1235 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR17:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1236 1236 val_a_adr 22 VR15:02 val_alu_func 17 A_OR_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1237 1237 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR17:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1238 1238 val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand 9 PASS_A_HIGH 1239 1239 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR19:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 123a 123a val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand 9 PASS_A_HIGH 123b 123b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR17:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 123c 123c val_a_adr 22 VR15:02 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 123d 123d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR17:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 123e 123e val_a_adr 22 VR15:02 val_alu_func 4 LEFT_I_A_INC val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 123f 123f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR17:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1240 1240 val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1241 1241 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR17:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1242 1242 val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1243 1243 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR17:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1244 1244 val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1245 1245 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR17:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1246 1246 val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1247 1247 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2b VR17:0b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1248 1248 seq_cond_sel 16 VAL.TRUE(early) 1249 1249 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 124a 124a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 124b 124b seq_cond_sel 17 VAL.FALSE(early) 124c 124c seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 124d 124d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR16:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 124e 124e seq_cond_sel 16 VAL.TRUE(early) 124f 124f seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1250 1250 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR16:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1251 1251 seq_cond_sel 17 VAL.FALSE(early) 1252 1252 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1253 1253 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1254 1254 seq_cond_sel 16 VAL.TRUE(early) 1255 1255 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1256 1256 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1257 1257 seq_cond_sel 17 VAL.FALSE(early) 1258 1258 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func c PASS_A_ELSE_INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1259 1259 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR15:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 125a 125a seq_cond_sel 16 VAL.TRUE(early) 125b 125b seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 125c 125c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR15:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 125d 125d seq_cond_sel 17 VAL.FALSE(early) 125e 125e seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func d INC_A_ELSE_PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 125f 125f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1260 1260 seq_cond_sel 16 VAL.TRUE(early) 1261 1261 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1262 1262 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1263 1263 seq_cond_sel 17 VAL.FALSE(early) 1264 1264 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func e PASS_A_ELSE_DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1265 1265 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR15:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1266 1266 seq_cond_sel 16 VAL.TRUE(early) 1267 1267 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1268 1268 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR15:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1269 1269 seq_cond_sel 17 VAL.FALSE(early) 126a 126a seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func f DEC_A_ELSE__PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 126b 126b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 126c 126c seq_cond_sel 16 VAL.TRUE(early) 126d 126d seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 126e 126e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR17:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 126f 126f seq_cond_sel 17 VAL.FALSE(early) 1270 1270 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1271 1271 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR17:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1272 1272 seq_cond_sel 16 VAL.TRUE(early) 1273 1273 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1274 1274 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR17:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1275 1275 seq_cond_sel 17 VAL.FALSE(early) 1276 1276 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 9 PASS_A_HIGH 1277 1277 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR17:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1278 1278 typ_rand e CHECK_CLASS_SYSTEM_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1279 1279 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR17:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 127a 127a val_alu_func 13 ONES val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 127b 127b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2d VR17:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 127c 127c val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 127d 127d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 127e 127e val_alu_func 1a PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 127f 127f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1280 1280 val_a_adr 22 VR15:02 val_alu_func 10 NOT_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1281 1281 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR17:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1282 1282 val_alu_func 15 NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1283 1283 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR17:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1284 1284 val_a_adr 22 VR15:02 val_alu_func 1e A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1285 1285 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR17:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1286 1286 val_a_adr 22 VR15:02 val_alu_func 1b A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1287 1287 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR17:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1288 1288 val_a_adr 22 VR15:02 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1289 1289 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR17:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 128a 128a val_a_adr 22 VR15:02 val_alu_func 11 A_NAND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 128b 128b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 34 VR17:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 128c 128c val_a_adr 22 VR15:02 val_alu_func 14 A_NOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 128d 128d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 35 VR17:15 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 128e 128e val_a_adr 22 VR15:02 val_alu_func 16 A_XNOR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 128f 128f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR17:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1290 1290 val_a_adr 22 VR15:02 val_alu_func 18 NOT_A_AND_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1291 1291 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 37 VR17:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1292 1292 val_a_adr 22 VR15:02 val_alu_func 1d A_AND_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1293 1293 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR17:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1294 1294 val_a_adr 22 VR15:02 val_alu_func 12 NOT_A_OR_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1295 1295 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR17:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1296 1296 val_a_adr 22 VR15:02 val_alu_func 17 A_OR_NOT_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 1297 1297 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR17:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1298 1298 val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand a PASS_B_HIGH 1299 1299 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR19:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 129a 129a val_a_adr 30 VR14:10 val_alu_func 1c DEC_A val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand a PASS_B_HIGH 129b 129b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR17:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 129c 129c val_a_adr 22 VR15:02 val_alu_func 3 LEFT_I_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 129d 129d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR17:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 129e 129e val_a_adr 22 VR15:02 val_alu_func 4 LEFT_I_A_INC val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 129f 129f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR17:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12a0 12a0 val_a_adr 22 VR15:02 val_alu_func 1 A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12a1 12a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR17:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12a2 12a2 val_a_adr 22 VR15:02 val_alu_func 2 INC_A_PLUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12a3 12a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR17:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12a4 12a4 val_a_adr 22 VR15:02 val_alu_func 6 A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12a5 12a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR17:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12a6 12a6 val_a_adr 22 VR15:02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12a7 12a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR18:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 12a8 12a8 seq_cond_sel 16 VAL.TRUE(early) 12a9 12a9 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12aa 12aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12ab 12ab seq_cond_sel 17 VAL.FALSE(early) 12ac 12ac seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12ad 12ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 12ae 12ae seq_cond_sel 16 VAL.TRUE(early) 12af 12af seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12b0 12b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 12b1 12b1 seq_cond_sel 17 VAL.FALSE(early) 12b2 12b2 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12b3 12b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12b4 12b4 seq_cond_sel 16 VAL.TRUE(early) 12b5 12b5 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func c PASS_A_ELSE_INC_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12b6 12b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12b7 12b7 seq_cond_sel 17 VAL.FALSE(early) 12b8 12b8 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func c PASS_A_ELSE_INC_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12b9 12b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR18:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 12ba 12ba seq_cond_sel 16 VAL.TRUE(early) 12bb 12bb seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func d INC_A_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12bc 12bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR18:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 12bd 12bd seq_cond_sel 17 VAL.FALSE(early) 12be 12be seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func d INC_A_ELSE_PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12bf 12bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12c0 12c0 seq_cond_sel 16 VAL.TRUE(early) 12c1 12c1 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func e PASS_A_ELSE_DEC_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12c2 12c2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12c3 12c3 seq_cond_sel 17 VAL.FALSE(early) 12c4 12c4 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func e PASS_A_ELSE_DEC_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12c5 12c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR18:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 12c6 12c6 seq_cond_sel 16 VAL.TRUE(early) 12c7 12c7 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func f DEC_A_ELSE__PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12c8 12c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR18:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 12c9 12c9 seq_cond_sel 17 VAL.FALSE(early) 12ca 12ca seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func f DEC_A_ELSE__PASS_A val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12cb 12cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12cc 12cc seq_cond_sel 16 VAL.TRUE(early) 12cd 12cd seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12ce 12ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR17:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12cf 12cf seq_cond_sel 17 VAL.FALSE(early) 12d0 12d0 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12d1 12d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR17:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12d2 12d2 seq_cond_sel 16 VAL.TRUE(early) 12d3 12d3 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12d4 12d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3f VR17:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12d5 12d5 seq_cond_sel 17 VAL.FALSE(early) 12d6 12d6 seq_en_micro 0 val_a_adr 22 VR15:02 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand a PASS_B_HIGH 12d7 12d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR17:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 12d8 12d8 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 12d9 12d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12da 12da ioc_fiubs 1 val val_a_adr 14 ZEROS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 12db 12db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12dc 12dc typ_rand e CHECK_CLASS_SYSTEM_B val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 12dd 12dd seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12de 12de seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12df 12df val_a_adr 3f VR14:1f val_alu_func 10 NOT_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12e0 12e0 seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12e1 12e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 12e2 12e2 val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12e3 12e3 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12e4 12e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3f VR14:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12e5 12e5 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 12e6 12e6 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12e7 12e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 12e8 12e8 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 12e9 12e9 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12ea 12ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 12eb 12eb val_a_adr 3e VR14:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12ec 12ec seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12ed 12ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3e VR14:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12ee 12ee val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12ef 12ef seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12f0 12f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3d VR14:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12f1 12f1 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12f2 12f2 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12f3 12f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR14:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12f4 12f4 val_a_adr 39 VR13:19 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 12f5 12f5 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12f6 12f6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 39 VR13:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 12f7 12f7 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 12f8 12f8 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12f9 12f9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 37 VR14:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 12fa 12fa val_a_adr 3b VR1a:1b val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 12fb 12fb seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12fc 12fc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3b VR1a:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 12fd 12fd val_a_adr 3d VR1a:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 12fe 12fe seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 12ff 12ff seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3d VR1a:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 1300 1300 val_a_adr 3a VR14:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1301 1301 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 1302 1302 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3a VR14:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1303 1303 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1304 1304 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1305 1305 seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1306 1306 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1307 1307 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1308 1308 seq_br_type 1 Branch True; Flow J cc=True 0x1307 seq_branch_adr 1307 0x1307 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1309 1309 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR14:19 val_frame 14 130a 130a seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 130b 130b val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 130c 130c seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 130d 130d val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 130e 130e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 130f 130f seq_b_timing 0 Early Condition; Flow J cc=False 0x130e seq_br_type 0 Branch False seq_branch_adr 130e 0x130e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1310 1310 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1311 1311 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1312 1312 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 38 VR14:18 val_frame 14 1313 1313 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1314 1314 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 30 VR14:10 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 30 VR14:10 val_frame 14 val_rand b DIVIDE 1315 1315 seq_b_timing 0 Early Condition; Flow J cc=False 0x13e7 seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 30 VR14:10 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 30 VR14:10 val_frame 14 val_rand b DIVIDE 1316 1316 seq_b_timing 0 Early Condition; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 1317 1317 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3f VR14:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1318 1318 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 1319 1319 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 131a 131a val_a_adr 32 VR19:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 131b 131b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 131c 131c val_a_adr 20 VR15:00 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 131d 131d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 131e 131e val_a_adr 21 VR15:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 131f 131f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1320 1320 val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1321 1321 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1322 1322 val_a_adr 23 VR15:03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1323 1323 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1324 1324 val_a_adr 24 VR15:04 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1325 1325 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1326 1326 val_a_adr 25 VR15:05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 1327 1327 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1328 1328 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 1329 1329 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 132a 132a val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 132b 132b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 132c 132c seq_b_timing 0 Early Condition; Flow J cc=False 0x132a seq_br_type 0 Branch False seq_branch_adr 132a 0x132a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 132d 132d typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 14 132e 132e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 132f 132f val_a_adr 32 VR19:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 19 1330 1330 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR1a:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 1331 1331 val_a_adr 20 VR15:00 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 1332 1332 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2a VR16:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1333 1333 val_a_adr 21 VR15:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 1334 1334 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2c VR16:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1335 1335 val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 1336 1336 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR16:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1337 1337 val_a_adr 23 VR15:03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 1338 1338 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR16:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1339 1339 val_a_adr 24 VR15:04 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 133a 133a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR16:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 133b 133b val_a_adr 25 VR15:05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_frame 15 133c 133c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 34 VR16:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 133d 133d val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 133e 133e val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 133f 133f val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 1340 1340 val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1341 1341 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1342 1342 seq_b_timing 0 Early Condition; Flow J cc=False 0x1340 seq_br_type 0 Branch False seq_branch_adr 1340 0x1340 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 1343 1343 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 14 1344 1344 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1345 1345 val_a_adr 32 VR19:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 19 1346 1346 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR18:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 1347 1347 val_a_adr 20 VR15:00 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 1348 1348 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR18:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 1349 1349 val_a_adr 21 VR15:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 134a 134a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR18:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 134b 134b val_a_adr 22 VR15:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 134c 134c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR18:06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 134d 134d val_a_adr 23 VR15:03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 134e 134e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 27 VR18:07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 134f 134f val_a_adr 24 VR15:04 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 1350 1350 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR18:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 1351 1351 val_a_adr 25 VR15:05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 val_frame 15 1352 1352 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 29 VR18:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 1353 1353 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 1354 1354 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1355 1355 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 1356 1356 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1357 1357 val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1358 1358 seq_b_timing 0 Early Condition; Flow J cc=False 0x1356 seq_br_type 0 Branch False seq_branch_adr 1356 0x1356 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 1359 1359 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 135a 135a val_a_adr 37 VR14:17 val_alu_func 6 A_MINUS_B val_b_adr 3c VR14:1c val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 135b 135b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 135c 135c val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 135d 135d val_a_adr 06 GP06 val_alu_func 3 LEFT_I_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 135e 135e seq_b_timing 0 Early Condition; Flow J cc=False 0x135b seq_br_type 0 Branch False seq_branch_adr 135b 0x135b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 1 ALU >> 16 135f 135f ioc_load_wdr 0 typ_rand e CHECK_CLASS_SYSTEM_B val_b_adr 30 VR14:10 val_frame 14 1360 1360 val_c_adr 3e GP01 1361 1361 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1362 1362 ioc_load_wdr 0 val_b_adr 32 VR19:12 val_frame 19 1363 1363 val_c_adr 3e GP01 1364 1364 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1365 1365 ioc_load_wdr 0 val_b_adr 20 VR15:00 val_frame 15 1366 1366 val_c_adr 3e GP01 1367 1367 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1368 1368 ioc_load_wdr 0 val_b_adr 21 VR15:01 val_frame 15 1369 1369 val_c_adr 3e GP01 136a 136a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 136b 136b ioc_load_wdr 0 val_b_adr 22 VR15:02 val_frame 15 136c 136c val_c_adr 3e GP01 136d 136d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 136e 136e ioc_load_wdr 0 val_b_adr 23 VR15:03 val_frame 15 136f 136f val_c_adr 3e GP01 1370 1370 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1371 1371 ioc_load_wdr 0 val_b_adr 24 VR15:04 val_frame 15 1372 1372 val_c_adr 3e GP01 1373 1373 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1374 1374 ioc_load_wdr 0 val_b_adr 25 VR15:05 val_frame 15 1375 1375 val_c_adr 3e GP01 1376 1376 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1377 1377 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 1378 1378 val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1379 1379 ioc_load_wdr 0 val_b_adr 05 GP05 137a 137a val_c_adr 3e GP01 137b 137b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 137c 137c seq_b_timing 0 Early Condition; Flow J cc=False 0x1379 seq_br_type 0 Branch False seq_branch_adr 1379 0x1379 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 137d 137d ioc_fiubs 1 val typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 137e 137e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 137f 137f ioc_fiubs 1 val val_a_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 1380 1380 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1381 1381 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 1382 1382 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR15:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1383 1383 ioc_fiubs 1 val val_a_adr 21 VR15:01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 1384 1384 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR15:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1385 1385 ioc_fiubs 1 val val_a_adr 22 VR15:02 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 1386 1386 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR15:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1387 1387 ioc_fiubs 1 val val_a_adr 23 VR15:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 1388 1388 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR15:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 1389 1389 ioc_fiubs 1 val val_a_adr 24 VR15:04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 138a 138a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 24 VR15:04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 138b 138b ioc_fiubs 1 val val_a_adr 25 VR15:05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 15 138c 138c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR15:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 15 138d 138d val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 138e 138e val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 138f 138f ioc_fiubs 1 val val_a_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1390 1390 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1391 1391 seq_b_timing 0 Early Condition; Flow J cc=False 0x138f seq_br_type 0 Branch False seq_branch_adr 138f 0x138f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1392 1392 ioc_fiubs 1 val typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 32 VR19:12 val_alu_func 1a PASS_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 19 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1393 1393 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR19:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1394 1394 ioc_fiubs 1 val val_a_adr 3a VR19:1a val_alu_func 1a PASS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 19 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1395 1395 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR17:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 1396 1396 ioc_fiubs 1 val val_a_adr 22 VR15:02 val_alu_func 1a PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1397 1397 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR16:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 1398 1398 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1399 1399 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 139a 139a ioc_fiubs 1 val val_a_adr 22 VR15:02 val_alu_func 1a PASS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 139b 139b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3a VR16:1a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 139c 139c ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 139d 139d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR17:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 139e 139e ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 139f 139f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR17:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 13a0 13a0 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a1 13a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 36 VR17:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 13a2 13a2 ioc_fiubs 1 val val_a_adr 36 VR14:16 val_alu_func 1a PASS_B val_b_adr 35 VR14:15 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 14 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a3 13a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 23 VR14:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13a4 13a4 ioc_fiubs 1 val val_a_adr 33 VR14:13 val_alu_func 1a PASS_B val_b_adr 34 VR14:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 14 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a5 13a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 22 VR14:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13a6 13a6 ioc_fiubs 1 val typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 32 VR19:12 val_alu_func 1a PASS_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a7 13a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 25 VR17:05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 13a8 13a8 ioc_fiubs 1 val val_a_adr 3a VR19:1a val_alu_func 1a PASS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a9 13a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR19:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13aa 13aa ioc_fiubs 1 val val_a_adr 22 VR15:02 val_alu_func 1a PASS_B val_b_adr 20 VR15:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13ab 13ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2e VR17:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 17 13ac 13ac ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 22 VR15:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13ad 13ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 38 VR16:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 16 13ae 13ae ioc_fiubs 1 val val_a_adr 22 VR15:02 val_alu_func 1a PASS_B val_b_adr 21 VR15:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13af 13af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3b VR18:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 13b0 13b0 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 23 VR15:03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13b1 13b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR18:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 13b2 13b2 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 24 VR15:04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13b3 13b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3d VR18:1d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 13b4 13b4 ioc_fiubs 1 val val_a_adr 20 VR15:00 val_alu_func 1a PASS_B val_b_adr 25 VR15:05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 15 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13b5 13b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3e VR18:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 13b6 13b6 ioc_fiubs 1 val val_a_adr 36 VR14:16 val_alu_func 1a PASS_B val_b_adr 32 VR14:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13b7 13b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR14:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13b8 13b8 ioc_fiubs 1 val val_a_adr 33 VR14:13 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13b9 13b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13ba 13ba seq_cond_sel 17 VAL.FALSE(early) typ_rand e CHECK_CLASS_SYSTEM_B 13bb 13bb ioc_fiubs 1 val seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13bc 13bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13bd 13bd seq_cond_sel 16 VAL.TRUE(early) 13be 13be ioc_fiubs 1 val seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13bf 13bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR1a:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 13c0 13c0 ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13c1 13c1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13c2 13c2 ioc_fiubs 1 val seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13c3 13c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR1a:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 13c4 13c4 ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13c5 13c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR1a:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 13c6 13c6 ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13c7 13c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13c8 13c8 ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13c9 13c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 33 VR1a:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 13ca 13ca ioc_fiubs 1 val seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 32 VR19:12 val_alu_func 19 X_XOR_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13cb 13cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13cc 13cc ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 6 A_MINUS_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13cd 13cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13ce 13ce ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 32 VR19:12 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR19:1a val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13cf 13cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13d0 13d0 ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3a VR19:1a val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13d1 13d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13d2 13d2 seq_cond_sel 17 VAL.FALSE(early) 13d3 13d3 ioc_fiubs 1 val seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13d4 13d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13d5 13d5 seq_cond_sel 16 VAL.TRUE(early) 13d6 13d6 ioc_fiubs 1 val seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13d7 13d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13d8 13d8 ioc_fiubs 1 val seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3a VR19:1a val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13d9 13d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13da 13da ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 6 A_MINUS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13db 13db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13dc 13dc ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3a VR19:1a val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 13dd 13dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13de 13de ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 30 VR14:10 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13df 13df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13e0 13e0 ioc_fiubs 1 val seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 30 VR14:10 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13e1 13e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13e2 13e2 ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13e3 13e3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 13e4 13e4 ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 30 VR14:10 val_alu_func 5 DEC_A_MINUS_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 14 val_rand 3 CONDITION_TO_FIU 13e5 13e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x13e7 seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 13e6 13e6 seq_br_type 3 Unconditional Branch; Flow J 0x1400 seq_branch_adr 1400 0x1400 13e7 13e7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU 13e8 13e8 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 13e9 13e9 <halt> ; Flow R 13ea 13ea <halt> ; Flow R 13eb 13eb <halt> ; Flow R 13ec 13ec <halt> ; Flow R 13ed 13ed <halt> ; Flow R 13ee 13ee <halt> ; Flow R 13ef 13ef <halt> ; Flow R 13f0 13f0 <halt> ; Flow R 13f1 13f1 <halt> ; Flow R 13f2 13f2 <halt> ; Flow R 13f3 13f3 <halt> ; Flow R 13f4 13f4 <halt> ; Flow R 13f5 13f5 <halt> ; Flow R 13f6 13f6 <halt> ; Flow R 13f7 13f7 <halt> ; Flow R 13f8 13f8 <halt> ; Flow R 13f9 13f9 <halt> ; Flow R 13fa 13fa <halt> ; Flow R 13fb 13fb <halt> ; Flow R 13fc 13fc <halt> ; Flow R 13fd 13fd <halt> ; Flow R 13fe 13fe <halt> ; Flow R 13ff 13ff <halt> ; Flow R 1400 1400 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 37 VR14:17 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1401 1401 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 1402 1402 seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A 1403 1403 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A 1404 1404 seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A 1405 1405 seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A 1406 1406 seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A 1407 1407 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1408 1408 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1409 1409 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 140a 140a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 140b 140b seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 140c 140c seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 140d 140d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 140e 140e seq_b_timing 0 Early Condition; Flow J cc=False 0x140a seq_br_type 0 Branch False seq_branch_adr 140a 0x140a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 140f 140f val_a_adr 37 VR14:17 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1410 1410 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 1411 1411 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1412 1412 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1413 1413 seq_b_timing 0 Early Condition; Flow J cc=False 0x1411 seq_br_type 0 Branch False seq_branch_adr 1411 0x1411 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 4 LEFT_I_A_INC val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 1414 1414 val_alu_func 13 ONES val_rand 5 COUNT_ZEROS 1415 1415 ioc_fiubs 1 val seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 19 val_rand 5 COUNT_ZEROS 1416 1416 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR1a:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 1417 1417 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1418 1418 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 1419 1419 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 141a 141a seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 141b 141b seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 141c 141c seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 141d 141d seq_b_timing 0 Early Condition; Flow J cc=False 0x141a seq_br_type 0 Branch False seq_branch_adr 141a 0x141a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 141e 141e val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 141f 141f seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 1420 1420 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 1421 1421 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 1422 1422 seq_b_timing 0 Early Condition; Flow J cc=False 0x141f seq_br_type 0 Branch False seq_branch_adr 141f 0x141f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1423 1423 val_a_adr 39 VR13:19 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1424 1424 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 1425 1425 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 11 VAL.ALU_40_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 1426 1426 seq_br_type 0 Branch False; Flow J cc=False 0x1532 seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 1427 1427 seq_b_timing 0 Early Condition; Flow J cc=False 0x1424 seq_br_type 0 Branch False seq_branch_adr 1424 0x1424 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1428 1428 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1429 1429 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG val_c_adr 3d GP02 val_c_mux_sel 2 ALU 142a 142a seq_b_timing 0 Early Condition; Flow J cc=False 0x1429 seq_br_type 0 Branch False seq_branch_adr 1429 0x1429 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 142b 142b typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 32 VR19:12 val_b_adr 3a VR19:1a val_frame 19 val_rand c START_MULTIPLY 142c 142c seq_en_micro 0 val_m_b_src 0 Bits 0…15 142d 142d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 1 Bits 16…31 142e 142e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 142f 142f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 1430 1430 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 1431 1431 val_a_adr 3a VR19:1a val_b_adr 32 VR19:12 val_frame 19 val_rand c START_MULTIPLY 1432 1432 seq_en_micro 0 val_m_a_src 0 Bits 0…15 1433 1433 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 1 Bits 16…31 1434 1434 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 1435 1435 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 1436 1436 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 1437 1437 val_a_adr 31 VR19:11 val_b_adr 32 VR19:12 val_frame 19 val_rand c START_MULTIPLY 1438 1438 seq_en_micro 0 val_m_b_src 0 Bits 0…15 1439 1439 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_m_b_src 1 Bits 16…31 143a 143a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_m_b_src 2 Bits 32…47 143b 143b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 143c 143c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 143d 143d val_a_adr 32 VR19:12 val_b_adr 31 VR19:11 val_frame 19 val_rand c START_MULTIPLY 143e 143e seq_en_micro 0 val_m_a_src 0 Bits 0…15 143f 143f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_m_a_src 1 Bits 16…31 1440 1440 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_m_a_src 2 Bits 32…47 1441 1441 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1442 1442 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1443 1443 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1444 1444 val_a_adr 37 VR19:17 val_b_adr 03 GP03 val_frame 19 val_rand c START_MULTIPLY 1445 1445 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1446 1446 val_a_adr 2e VR14:0e val_b_adr 03 GP03 val_frame 14 val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1447 1447 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1448 1448 val_a_adr 2d VR14:0d val_b_adr 03 GP03 val_frame 14 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 1449 1449 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 144a 144a val_a_adr 23 VR18:03 val_b_adr 03 GP03 val_frame 18 val_m_a_src 0 Bits 0…15 val_rand c START_MULTIPLY 144b 144b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 144c 144c val_a_adr 2f VR14:0f val_b_adr 03 GP03 val_frame 14 val_rand c START_MULTIPLY 144d 144d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 144e 144e val_a_adr 33 VR19:13 val_b_adr 03 GP03 val_frame 19 val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 144f 144f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1450 1450 val_a_adr 2c VR14:0c val_b_adr 03 GP03 val_frame 14 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 1451 1451 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1452 1452 val_a_adr 2b VR14:0b val_b_adr 03 GP03 val_frame 14 val_m_a_src 0 Bits 0…15 val_rand c START_MULTIPLY 1453 1453 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1454 1454 val_a_adr 2a VR14:0a val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1455 1455 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 1456 1456 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1457 1457 seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_a_src 0 Bits 0…15 val_rand c START_MULTIPLY 1458 1458 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1459 1459 seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 145a 145a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 145b 145b seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_b_adr 31 VR19:11 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 145c 145c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 145d 145d seq_en_micro 0 val_a_adr 06 GP06 val_b_adr 31 VR19:11 val_frame 19 val_rand c START_MULTIPLY 145e 145e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 145f 145f val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1460 1460 seq_b_timing 0 Early Condition; Flow J cc=False 0x1457 seq_br_type 0 Branch False seq_branch_adr 1457 0x1457 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1461 1461 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1462 1462 val_a_adr 03 GP03 val_b_adr 37 VR19:17 val_frame 19 val_rand c START_MULTIPLY 1463 1463 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1464 1464 val_a_adr 03 GP03 val_b_adr 2e VR14:0e val_frame 14 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 1465 1465 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1466 1466 val_a_adr 03 GP03 val_b_adr 2d VR14:0d val_frame 14 val_m_b_src 1 Bits 16…31 val_rand c START_MULTIPLY 1467 1467 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1468 1468 val_a_adr 03 GP03 val_b_adr 23 VR18:03 val_frame 18 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 1469 1469 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 146a 146a val_a_adr 03 GP03 val_b_adr 2f VR14:0f val_frame 14 val_rand c START_MULTIPLY 146b 146b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 146c 146c val_a_adr 03 GP03 val_b_adr 33 VR19:13 val_frame 19 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 146d 146d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 146e 146e val_a_adr 03 GP03 val_b_adr 2c VR14:0c val_frame 14 val_m_b_src 1 Bits 16…31 val_rand c START_MULTIPLY 146f 146f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1470 1470 val_a_adr 03 GP03 val_b_adr 2b VR14:0b val_frame 14 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 1471 1471 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1472 1472 val_a_adr 2a VR14:0a val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1473 1473 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 1474 1474 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1475 1475 seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 1476 1476 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1477 1477 seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_b_src 1 Bits 16…31 val_rand c START_MULTIPLY 1478 1478 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1479 1479 seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 1 ALU >> 16 val_frame 19 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 147a 147a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 147b 147b seq_en_micro 0 val_a_adr 31 VR19:11 val_b_adr 06 GP06 val_frame 19 val_rand c START_MULTIPLY 147c 147c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 147d 147d val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 147e 147e seq_b_timing 0 Early Condition; Flow J cc=False 0x1475 seq_br_type 0 Branch False seq_branch_adr 1475 0x1475 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 05 GP05 val_alu_func 3 LEFT_I_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 147f 147f seq_en_micro 0 val_a_adr 30 VR14:10 val_b_adr 30 VR14:10 val_frame 14 val_rand c START_MULTIPLY 1480 1480 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1481 1481 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_rand d PRODUCT_LEFT_16 1482 1482 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_rand e PRODUCT_LEFT_32 1483 1483 seq_en_micro 0 val_a_adr 31 VR19:11 val_b_adr 31 VR19:11 val_frame 19 val_rand c START_MULTIPLY 1484 1484 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1485 1485 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 28 VR14:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 val_rand d PRODUCT_LEFT_16 1486 1486 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2f VR1a:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a val_rand e PRODUCT_LEFT_32 1487 1487 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 19 1488 1488 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1a 1489 1489 val_a_adr 29 VR14:09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 148a 148a val_a_adr 3c VR14:1c val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 148b 148b seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 06 GP06 val_rand c START_MULTIPLY 148c 148c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 148d 148d seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 1 ALU >> 16 val_rand 2 DEC_LOOP_COUNTER 148e 148e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 148f 148f seq_en_micro 0 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 1 ALU >> 16 1490 1490 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1491 1491 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1492 1492 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1493 1493 seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 06 GP06 val_rand c START_MULTIPLY 1494 1494 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1495 1495 seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 1 ALU >> 16 1496 1496 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1497 1497 seq_en_micro 0 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 1 ALU >> 16 1498 1498 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1499 1499 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 149a 149a seq_b_timing 0 Early Condition; Flow J cc=False 0x148b seq_br_type 0 Branch False seq_branch_adr 148b 0x148b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 06 GP06 val_alu_func 3 LEFT_I_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 149b 149b seq_en_micro 0 val_a_adr 2a VR18:0a val_b_adr 2b VR18:0b val_frame 18 val_rand c START_MULTIPLY 149c 149c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2c VR18:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 149d 149d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2d VR18:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_rand d PRODUCT_LEFT_16 149e 149e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 2e VR18:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_rand e PRODUCT_LEFT_32 149f 149f seq_en_micro 0 val_a_adr 2f VR18:0f val_b_adr 30 VR18:10 val_frame 18 val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 14a0 14a0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 32 VR18:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 14a1 14a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 34 VR18:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 14a2 14a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 37 VR18:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_b_src 2 Bits 32…47 14a3 14a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 35 VR18:15 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 14a4 14a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 33 VR18:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 1 Bits 16…31 14a5 14a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 36 VR18:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 14a6 14a6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 39 VR18:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 14a7 14a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 38 VR18:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 14a8 14a8 seq_en_micro 0 val_a_adr 31 VR18:11 val_b_adr 2f VR18:0f val_frame 18 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 14a9 14a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 32 VR18:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_b_src 1 Bits 16…31 14aa 14aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 34 VR18:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 14ab 14ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 37 VR18:17 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 0 Bits 0…15 14ac 14ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 35 VR18:15 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 14ad 14ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 33 VR18:13 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 14ae 14ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 36 VR18:16 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 14af 14af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 39 VR18:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 val_m_a_src 2 Bits 32…47 14b0 14b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 38 VR18:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 18 14b1 14b1 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14b2 14b2 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 19 14b3 14b3 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 14b4 14b4 val_a_adr 39 VR13:19 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 14b5 14b5 seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 06 GP06 val_rand c START_MULTIPLY 14b6 14b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14b7 14b7 seq_en_micro 0 val_a_adr 06 GP06 val_b_adr 05 GP05 val_rand c START_MULTIPLY 14b8 14b8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14b9 14b9 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14ba 14ba val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14bb 14bb val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 14bc 14bc val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 14bd 14bd seq_b_timing 0 Early Condition; Flow J cc=False 0x14b5 seq_br_type 0 Branch False seq_branch_adr 14b5 0x14b5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 07 GP07 val_alu_func 4 LEFT_I_A_INC val_c_adr 39 GP06 val_c_mux_sel 2 ALU 14be 14be val_a_adr 2f VR1a:0f val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 14bf 14bf val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 27 VR14:07 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14c0 14c0 val_a_adr 26 VR14:06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 14c1 14c1 val_a_adr 25 VR14:05 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 14c2 14c2 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 25 VR14:05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14c3 14c3 val_a_adr 24 VR14:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 14c4 14c4 val_a_adr 26 VR14:06 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 14c5 14c5 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14c6 14c6 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x14ca fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 14ca 0x14ca seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_b_adr 04 GP04 val_rand c START_MULTIPLY 14c7 14c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14c8 14c8 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 3d VR1a:1d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 1a 14c9 14c9 seq_br_type 3 Unconditional Branch; Flow J 0x14c6 seq_branch_adr 14c6 0x14c6 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 14ca 14ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 14cb 14cb val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 3d VR1a:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1a 14cc 14cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x14c2 seq_br_type 0 Branch False seq_branch_adr 14c2 0x14c2 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 28 VR14:08 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 14cd 14cd val_a_adr 2f VR14:0f val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14ce 14ce val_a_adr 3a VR18:1a val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 18 14cf 14cf fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 14d0 14d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14d1 14d1 val_a_adr 05 GP05 val_alu_func 4 LEFT_I_A_INC val_c_adr 39 GP06 val_c_mux_sel 2 ALU 14d2 14d2 seq_br_type 1 Branch True; Flow J cc=True 0x14cf seq_branch_adr 14cf 0x14cf seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14d3 14d3 val_a_adr 26 VR14:06 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14d4 14d4 val_a_adr 24 VR14:04 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 14d5 14d5 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 24 VR14:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 14d6 14d6 val_a_adr 24 VR14:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 14d7 14d7 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14d8 14d8 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x14db fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 14db 0x14db seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 17 LOOP_COUNTER val_b_adr 04 GP04 val_rand c START_MULTIPLY 14d9 14d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14da 14da seq_br_type 3 Unconditional Branch; Flow J 0x14d8 seq_branch_adr 14d8 0x14d8 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 14db 14db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 14dc 14dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x14d5 seq_br_type 0 Branch False seq_branch_adr 14d5 0x14d5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 14dd 14dd typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 14de 14de val_a_adr 31 VR19:11 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14df 14df seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14e0 14e0 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 14e1 14e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 14e2 14e2 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 31 VR19:11 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14e3 14e3 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_frame 19 val_rand b DIVIDE 14e4 14e4 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 14e5 14e5 val_a_adr 31 VR19:11 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14e6 14e6 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14e7 14e7 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 14e8 14e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR19:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 14e9 14e9 val_a_adr 31 VR19:11 val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14ea 14ea seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14eb 14eb seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 14ec 14ec val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14ed 14ed seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14ee 14ee seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 14ef 14ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 14f0 14f0 val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14f1 14f1 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_frame 19 val_rand b DIVIDE 14f2 14f2 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 14f3 14f3 val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14f4 14f4 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14f5 14f5 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 14f6 14f6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR19:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 14f7 14f7 val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_frame 19 14f8 14f8 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14f9 14f9 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 14fa 14fa val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 14fb 14fb seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 14fc 14fc seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 14fd 14fd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 14fe 14fe val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 14ff 14ff seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 1500 1500 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 1501 1501 val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 1502 1502 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 1503 1503 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 1504 1504 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR19:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1505 1505 val_a_adr 3b VR19:1b val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 1506 1506 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 1507 1507 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 1508 1508 val_a_adr 32 VR19:12 val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 1509 1509 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 150a 150a seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 150b 150b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1a 150c 150c val_a_adr 32 VR19:12 val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 150d 150d seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 31 VR19:11 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 150e 150e seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 150f 150f val_a_adr 32 VR19:12 val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 1510 1510 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 1511 1511 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 1512 1512 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 3c VR19:1c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 1513 1513 val_a_adr 32 VR19:12 val_alu_func 1 A_PLUS_B val_b_adr 32 VR19:12 val_frame 19 1514 1514 seq_b_timing 0 Early Condition; Flow J cc=False 0x1532 seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_a_adr 3b VR19:1b val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 31 VR19:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand b DIVIDE 1515 1515 seq_b_timing 0 Early Condition; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 1516 1516 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val typ_rand e CHECK_CLASS_SYSTEM_B val_b_adr 30 VR14:10 val_frame 14 1517 1517 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1518 1518 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1519 1519 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_b_adr 32 VR19:12 val_frame 19 151a 151a ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 151b 151b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR19:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 151c 151c fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 16 VAL.TRUE(early) val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 6 IMMEDIATE_OP 151d 151d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 19 151e 151e fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 6 IMMEDIATE_OP 151f 151f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1520 1520 val_a_adr 3d VR1a:1d val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 1a 1521 1521 val_a_adr 3d VR1a:1d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 1522 1522 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_a_adr 3c VR1a:1c val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1a 1523 1523 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand 6 IMMEDIATE_OP 1524 1524 val_a_adr 17 LOOP_COUNTER val_alu_func 1b A_OR_B val_b_adr 30 VR14:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1525 1525 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1526 1526 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand 6 IMMEDIATE_OP 1527 1527 val_a_adr 17 LOOP_COUNTER val_alu_func 1b A_OR_B val_b_adr 3c VR1a:1c val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 1528 1528 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1529 1529 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_b_adr 04 GP04 152a 152a ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 val_rand 6 IMMEDIATE_OP 152b 152b val_a_adr 17 LOOP_COUNTER val_alu_func 1b A_OR_B val_b_adr 30 VR14:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 152c 152c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 152d 152d ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 32 VR19:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 19 val_rand 6 IMMEDIATE_OP 152e 152e val_a_adr 17 LOOP_COUNTER val_alu_func 1b A_OR_B val_b_adr 3c VR1a:1c val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 152f 152f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1532 seq_br_type 1 Branch True seq_branch_adr 1532 0x1532 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1530 1530 seq_b_timing 0 Early Condition; Flow J cc=False 0x1522 seq_br_type 0 Branch False seq_branch_adr 1522 0x1522 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1531 1531 seq_br_type a Unconditional Return; Flow R 1532 1532 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU 1533 1533 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 1534 1534 <halt> ; Flow R 1535 1535 <halt> ; Flow R 1536 1536 <halt> ; Flow R 1537 1537 <halt> ; Flow R 1538 1538 <halt> ; Flow R 1539 1539 <halt> ; Flow R 153a 153a <halt> ; Flow R 153b 153b <halt> ; Flow R 153c 153c <halt> ; Flow R 153d 153d <halt> ; Flow R 153e 153e <halt> ; Flow R 153f 153f <halt> ; Flow R 1540 1540 <halt> ; Flow R 1541 1541 <halt> ; Flow R 1542 1542 <halt> ; Flow R 1543 1543 <halt> ; Flow R 1544 1544 <halt> ; Flow R 1545 1545 <halt> ; Flow R 1546 1546 <halt> ; Flow R 1547 1547 <halt> ; Flow R 1548 1548 <halt> ; Flow R 1549 1549 <halt> ; Flow R 154a 154a <halt> ; Flow R 154b 154b <halt> ; Flow R 154c 154c <halt> ; Flow R 154d 154d <halt> ; Flow R 154e 154e <halt> ; Flow R 154f 154f <halt> ; Flow R 1550 1550 <halt> ; Flow R 1551 1551 <halt> ; Flow R 1552 1552 <halt> ; Flow R 1553 1553 <halt> ; Flow R 1554 1554 <halt> ; Flow R 1555 1555 <halt> ; Flow R 1556 1556 <halt> ; Flow R 1557 1557 <halt> ; Flow R 1558 1558 <halt> ; Flow R 1559 1559 <halt> ; Flow R 155a 155a <halt> ; Flow R 155b 155b <halt> ; Flow R 155c 155c <halt> ; Flow R 155d 155d <halt> ; Flow R 155e 155e <halt> ; Flow R 155f 155f <halt> ; Flow R 1560 1560 <halt> ; Flow R 1561 1561 <halt> ; Flow R 1562 1562 <halt> ; Flow R 1563 1563 <halt> ; Flow R 1564 1564 <halt> ; Flow R 1565 1565 <halt> ; Flow R 1566 1566 <halt> ; Flow R 1567 1567 <halt> ; Flow R 1568 1568 <halt> ; Flow R 1569 1569 <halt> ; Flow R 156a 156a <halt> ; Flow R 156b 156b <halt> ; Flow R 156c 156c <halt> ; Flow R 156d 156d <halt> ; Flow R 156e 156e <halt> ; Flow R 156f 156f <halt> ; Flow R 1570 1570 <halt> ; Flow R 1571 1571 <halt> ; Flow R 1572 1572 <halt> ; Flow R 1573 1573 <halt> ; Flow R 1574 1574 <halt> ; Flow R 1575 1575 <halt> ; Flow R 1576 1576 <halt> ; Flow R 1577 1577 <halt> ; Flow R 1578 1578 <halt> ; Flow R 1579 1579 <halt> ; Flow R 157a 157a <halt> ; Flow R 157b 157b <halt> ; Flow R 157c 157c <halt> ; Flow R 157d 157d <halt> ; Flow R 157e 157e <halt> ; Flow R 157f 157f <halt> ; Flow R 1580 1580 <halt> ; Flow R 1581 1581 <halt> ; Flow R 1582 1582 <halt> ; Flow R 1583 1583 <halt> ; Flow R 1584 1584 <halt> ; Flow R 1585 1585 <halt> ; Flow R 1586 1586 <halt> ; Flow R 1587 1587 <halt> ; Flow R 1588 1588 <halt> ; Flow R 1589 1589 <halt> ; Flow R 158a 158a <halt> ; Flow R 158b 158b <halt> ; Flow R 158c 158c <halt> ; Flow R 158d 158d <halt> ; Flow R 158e 158e <halt> ; Flow R 158f 158f <halt> ; Flow R 1590 1590 <halt> ; Flow R 1591 1591 <halt> ; Flow R 1592 1592 <halt> ; Flow R 1593 1593 <halt> ; Flow R 1594 1594 <halt> ; Flow R 1595 1595 <halt> ; Flow R 1596 1596 <halt> ; Flow R 1597 1597 <halt> ; Flow R 1598 1598 <halt> ; Flow R 1599 1599 <halt> ; Flow R 159a 159a <halt> ; Flow R 159b 159b <halt> ; Flow R 159c 159c <halt> ; Flow R 159d 159d <halt> ; Flow R 159e 159e <halt> ; Flow R 159f 159f <halt> ; Flow R 15a0 15a0 <halt> ; Flow R 15a1 15a1 <halt> ; Flow R 15a2 15a2 <halt> ; Flow R 15a3 15a3 <halt> ; Flow R 15a4 15a4 <halt> ; Flow R 15a5 15a5 <halt> ; Flow R 15a6 15a6 <halt> ; Flow R 15a7 15a7 <halt> ; Flow R 15a8 15a8 <halt> ; Flow R 15a9 15a9 <halt> ; Flow R 15aa 15aa <halt> ; Flow R 15ab 15ab <halt> ; Flow R 15ac 15ac <halt> ; Flow R 15ad 15ad <halt> ; Flow R 15ae 15ae <halt> ; Flow R 15af 15af <halt> ; Flow R 15b0 15b0 <halt> ; Flow R 15b1 15b1 <halt> ; Flow R 15b2 15b2 <halt> ; Flow R 15b3 15b3 <halt> ; Flow R 15b4 15b4 <halt> ; Flow R 15b5 15b5 <halt> ; Flow R 15b6 15b6 <halt> ; Flow R 15b7 15b7 <halt> ; Flow R 15b8 15b8 <halt> ; Flow R 15b9 15b9 <halt> ; Flow R 15ba 15ba <halt> ; Flow R 15bb 15bb <halt> ; Flow R 15bc 15bc <halt> ; Flow R 15bd 15bd <halt> ; Flow R 15be 15be <halt> ; Flow R 15bf 15bf <halt> ; Flow R 15c0 15c0 <halt> ; Flow R 15c1 15c1 <halt> ; Flow R 15c2 15c2 <halt> ; Flow R 15c3 15c3 <halt> ; Flow R 15c4 15c4 <halt> ; Flow R 15c5 15c5 <halt> ; Flow R 15c6 15c6 <halt> ; Flow R 15c7 15c7 <halt> ; Flow R 15c8 15c8 <halt> ; Flow R 15c9 15c9 <halt> ; Flow R 15ca 15ca <halt> ; Flow R 15cb 15cb <halt> ; Flow R 15cc 15cc <halt> ; Flow R 15cd 15cd <halt> ; Flow R 15ce 15ce <halt> ; Flow R 15cf 15cf <halt> ; Flow R 15d0 15d0 <halt> ; Flow R 15d1 15d1 <halt> ; Flow R 15d2 15d2 <halt> ; Flow R 15d3 15d3 <halt> ; Flow R 15d4 15d4 <halt> ; Flow R 15d5 15d5 <halt> ; Flow R 15d6 15d6 <halt> ; Flow R 15d7 15d7 <halt> ; Flow R 15d8 15d8 <halt> ; Flow R 15d9 15d9 <halt> ; Flow R 15da 15da <halt> ; Flow R 15db 15db <halt> ; Flow R 15dc 15dc <halt> ; Flow R 15dd 15dd <halt> ; Flow R 15de 15de <halt> ; Flow R 15df 15df <halt> ; Flow R 15e0 15e0 <halt> ; Flow R 15e1 15e1 <halt> ; Flow R 15e2 15e2 <halt> ; Flow R 15e3 15e3 <halt> ; Flow R 15e4 15e4 <halt> ; Flow R 15e5 15e5 <halt> ; Flow R 15e6 15e6 <halt> ; Flow R 15e7 15e7 <halt> ; Flow R 15e8 15e8 <halt> ; Flow R 15e9 15e9 <halt> ; Flow R 15ea 15ea <halt> ; Flow R 15eb 15eb <halt> ; Flow R 15ec 15ec <halt> ; Flow R 15ed 15ed <halt> ; Flow R 15ee 15ee <halt> ; Flow R 15ef 15ef <halt> ; Flow R 15f0 15f0 <halt> ; Flow R 15f1 15f1 <halt> ; Flow R 15f2 15f2 <halt> ; Flow R 15f3 15f3 <halt> ; Flow R 15f4 15f4 <halt> ; Flow R 15f5 15f5 <halt> ; Flow R 15f6 15f6 <halt> ; Flow R 15f7 15f7 <halt> ; Flow R 15f8 15f8 <halt> ; Flow R 15f9 15f9 <halt> ; Flow R 15fa 15fa <halt> ; Flow R 15fb 15fb <halt> ; Flow R 15fc 15fc <halt> ; Flow R 15fd 15fd <halt> ; Flow R 15fe 15fe <halt> ; Flow R 15ff 15ff <halt> ; Flow R 1600 1600 <default> 1601 1601 fiu_tivi_src c mar_0xc; Flow C cc=True 0x161f ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 161f 0x161f seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1602 1602 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 typ_b_adr 05 GP05 typ_mar_cntl 4 RESTORE_MAR val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1603 1603 seq_en_micro 0 typ_c_adr 38 GP07 val_c_adr 38 GP07 1604 1604 seq_en_micro 0 1605 1605 ioc_random 11 disable ecc event; Flow J cc=False 0x1615 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1615 0x1615 seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1606 1606 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1619 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1619 0x1619 seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 1607 1607 seq_en_micro 0 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1a 1608 1608 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS 1609 1609 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 160a 160a seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 10 NOT_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 160b 160b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 160c 160c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_en_micro 0 160d 160d ioc_tvbs 3 fiu+fiu typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 160e 160e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 08 GP08 val_b_adr 08 GP08 160f 160f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 1610 1610 seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 10 NOT_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 1611 1611 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 1612 1612 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_en_micro 0 1613 1613 ioc_tvbs 3 fiu+fiu typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1614 1614 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 08 GP08 typ_mar_cntl 1 RESTORE_RDR val_b_adr 08 GP08 1615 1615 seq_en_micro 0 typ_a_adr 32 TR14:12 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 14 1616 1616 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS 1617 1617 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 1618 1618 seq_br_type 3 Unconditional Branch; Flow J 0x1614 seq_branch_adr 1614 0x1614 seq_en_micro 0 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1619 1619 seq_en_micro 0 typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1a 161a 161a seq_br_type 3 Unconditional Branch; Flow J 0x1614 seq_branch_adr 1614 0x1614 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_mux_sel 2 ALU 161b 161b seq_en_micro 0 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1a 161c 161c seq_br_type 3 Unconditional Branch; Flow J 0x1614 seq_branch_adr 1614 0x1614 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_mux_sel 2 ALU 161d 161d seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 161e 161e seq_br_type 3 Unconditional Branch; Flow J 0x1614 seq_branch_adr 1614 0x1614 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_mux_sel 2 ALU 161f ; -------------------------------------------------------------------------------------- 161f ; Comes from: 161f ; 1601 C True from color UE_ECC 161f ; -------------------------------------------------------------------------------------- 161f 161f seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1620 0x1620 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 24 TR12:04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 3b VR1a:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 1620 1620 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR12:04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 3b VR1a:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 1621 1621 <halt> ; Flow R 1622 1622 <halt> ; Flow R 1623 1623 <halt> ; Flow R 1624 1624 <halt> ; Flow R 1625 1625 <halt> ; Flow R 1626 1626 <halt> ; Flow R 1627 1627 <halt> ; Flow R 1628 1628 <halt> ; Flow R 1629 1629 <halt> ; Flow R 162a 162a <halt> ; Flow R 162b 162b <halt> ; Flow R 162c 162c <halt> ; Flow R 162d 162d <halt> ; Flow R 162e 162e <halt> ; Flow R 162f 162f <halt> ; Flow R 1630 1630 <halt> ; Flow R 1631 1631 <halt> ; Flow R 1632 1632 <halt> ; Flow R 1633 1633 <halt> ; Flow R 1634 1634 <halt> ; Flow R 1635 1635 <halt> ; Flow R 1636 1636 <halt> ; Flow R 1637 1637 <halt> ; Flow R 1638 1638 <halt> ; Flow R 1639 1639 <halt> ; Flow R 163a 163a <halt> ; Flow R 163b 163b <halt> ; Flow R 163c 163c <halt> ; Flow R 163d 163d <halt> ; Flow R 163e 163e <halt> ; Flow R 163f 163f <halt> ; Flow R 1640 1640 <halt> ; Flow R 1641 1641 <halt> ; Flow R 1642 1642 <halt> ; Flow R 1643 1643 <halt> ; Flow R 1644 1644 <halt> ; Flow R 1645 1645 <halt> ; Flow R 1646 1646 <halt> ; Flow R 1647 1647 <halt> ; Flow R 1648 1648 <halt> ; Flow R 1649 1649 <halt> ; Flow R 164a 164a <halt> ; Flow R 164b 164b <halt> ; Flow R 164c 164c <halt> ; Flow R 164d 164d <halt> ; Flow R 164e 164e <halt> ; Flow R 164f 164f <halt> ; Flow R 1650 1650 <halt> ; Flow R 1651 1651 <halt> ; Flow R 1652 1652 <halt> ; Flow R 1653 1653 <halt> ; Flow R 1654 1654 <halt> ; Flow R 1655 1655 <halt> ; Flow R 1656 1656 <halt> ; Flow R 1657 1657 <halt> ; Flow R 1658 1658 <halt> ; Flow R 1659 1659 <halt> ; Flow R 165a 165a <halt> ; Flow R 165b 165b <halt> ; Flow R 165c 165c <halt> ; Flow R 165d 165d <halt> ; Flow R 165e 165e <halt> ; Flow R 165f 165f <halt> ; Flow R 1660 1660 <halt> ; Flow R 1661 1661 <halt> ; Flow R 1662 1662 <halt> ; Flow R 1663 1663 <halt> ; Flow R 1664 1664 <halt> ; Flow R 1665 1665 <halt> ; Flow R 1666 1666 <halt> ; Flow R 1667 1667 <halt> ; Flow R 1668 1668 <halt> ; Flow R 1669 1669 <halt> ; Flow R 166a 166a <halt> ; Flow R 166b 166b <halt> ; Flow R 166c 166c <halt> ; Flow R 166d 166d <halt> ; Flow R 166e 166e <halt> ; Flow R 166f 166f <halt> ; Flow R 1670 1670 <halt> ; Flow R 1671 1671 <halt> ; Flow R 1672 1672 <halt> ; Flow R 1673 1673 <halt> ; Flow R 1674 1674 <halt> ; Flow R 1675 1675 <halt> ; Flow R 1676 1676 <halt> ; Flow R 1677 1677 <halt> ; Flow R 1678 1678 <halt> ; Flow R 1679 1679 <halt> ; Flow R 167a 167a <halt> ; Flow R 167b 167b <halt> ; Flow R 167c 167c <halt> ; Flow R 167d 167d <halt> ; Flow R 167e 167e <halt> ; Flow R 167f 167f <halt> ; Flow R 1680 1680 <halt> ; Flow R 1681 1681 <halt> ; Flow R 1682 1682 <halt> ; Flow R 1683 1683 <halt> ; Flow R 1684 1684 <halt> ; Flow R 1685 1685 <halt> ; Flow R 1686 1686 <halt> ; Flow R 1687 1687 <halt> ; Flow R 1688 1688 <halt> ; Flow R 1689 1689 <halt> ; Flow R 168a 168a <halt> ; Flow R 168b 168b <halt> ; Flow R 168c 168c <halt> ; Flow R 168d 168d <halt> ; Flow R 168e 168e <halt> ; Flow R 168f 168f <halt> ; Flow R 1690 1690 <halt> ; Flow R 1691 1691 <halt> ; Flow R 1692 1692 <halt> ; Flow R 1693 1693 <halt> ; Flow R 1694 1694 <halt> ; Flow R 1695 1695 <halt> ; Flow R 1696 1696 <halt> ; Flow R 1697 1697 <halt> ; Flow R 1698 1698 <halt> ; Flow R 1699 1699 <halt> ; Flow R 169a 169a <halt> ; Flow R 169b 169b <halt> ; Flow R 169c 169c <halt> ; Flow R 169d 169d <halt> ; Flow R 169e 169e <halt> ; Flow R 169f 169f <halt> ; Flow R 16a0 16a0 <halt> ; Flow R 16a1 16a1 <halt> ; Flow R 16a2 16a2 <halt> ; Flow R 16a3 16a3 <halt> ; Flow R 16a4 16a4 <halt> ; Flow R 16a5 16a5 <halt> ; Flow R 16a6 16a6 <halt> ; Flow R 16a7 16a7 <halt> ; Flow R 16a8 16a8 <halt> ; Flow R 16a9 16a9 <halt> ; Flow R 16aa 16aa <halt> ; Flow R 16ab 16ab <halt> ; Flow R 16ac 16ac <halt> ; Flow R 16ad 16ad <halt> ; Flow R 16ae 16ae <halt> ; Flow R 16af 16af <halt> ; Flow R 16b0 16b0 <halt> ; Flow R 16b1 16b1 <halt> ; Flow R 16b2 16b2 <halt> ; Flow R 16b3 16b3 <halt> ; Flow R 16b4 16b4 <halt> ; Flow R 16b5 16b5 <halt> ; Flow R 16b6 16b6 <halt> ; Flow R 16b7 16b7 <halt> ; Flow R 16b8 16b8 <halt> ; Flow R 16b9 16b9 <halt> ; Flow R 16ba 16ba <halt> ; Flow R 16bb 16bb <halt> ; Flow R 16bc 16bc <halt> ; Flow R 16bd 16bd <halt> ; Flow R 16be 16be <halt> ; Flow R 16bf 16bf <halt> ; Flow R 16c0 16c0 <halt> ; Flow R 16c1 16c1 <halt> ; Flow R 16c2 16c2 <halt> ; Flow R 16c3 16c3 <halt> ; Flow R 16c4 16c4 <halt> ; Flow R 16c5 16c5 <halt> ; Flow R 16c6 16c6 <halt> ; Flow R 16c7 16c7 <halt> ; Flow R 16c8 16c8 <halt> ; Flow R 16c9 16c9 <halt> ; Flow R 16ca 16ca <halt> ; Flow R 16cb 16cb <halt> ; Flow R 16cc 16cc <halt> ; Flow R 16cd 16cd <halt> ; Flow R 16ce 16ce <halt> ; Flow R 16cf 16cf <halt> ; Flow R 16d0 16d0 <halt> ; Flow R 16d1 16d1 <halt> ; Flow R 16d2 16d2 <halt> ; Flow R 16d3 16d3 <halt> ; Flow R 16d4 16d4 <halt> ; Flow R 16d5 16d5 <halt> ; Flow R 16d6 16d6 <halt> ; Flow R 16d7 16d7 <halt> ; Flow R 16d8 16d8 <halt> ; Flow R 16d9 16d9 <halt> ; Flow R 16da 16da <halt> ; Flow R 16db 16db <halt> ; Flow R 16dc 16dc <halt> ; Flow R 16dd 16dd <halt> ; Flow R 16de 16de <halt> ; Flow R 16df 16df <halt> ; Flow R 16e0 16e0 <halt> ; Flow R 16e1 16e1 <halt> ; Flow R 16e2 16e2 <halt> ; Flow R 16e3 16e3 <halt> ; Flow R 16e4 16e4 <halt> ; Flow R 16e5 16e5 <halt> ; Flow R 16e6 16e6 <halt> ; Flow R 16e7 16e7 <halt> ; Flow R 16e8 16e8 <halt> ; Flow R 16e9 16e9 <halt> ; Flow R 16ea 16ea <halt> ; Flow R 16eb 16eb <halt> ; Flow R 16ec 16ec <halt> ; Flow R 16ed 16ed <halt> ; Flow R 16ee 16ee <halt> ; Flow R 16ef 16ef <halt> ; Flow R 16f0 16f0 <halt> ; Flow R 16f1 16f1 <halt> ; Flow R 16f2 16f2 <halt> ; Flow R 16f3 16f3 <halt> ; Flow R 16f4 16f4 <halt> ; Flow R 16f5 16f5 <halt> ; Flow R 16f6 16f6 <halt> ; Flow R 16f7 16f7 <halt> ; Flow R 16f8 16f8 <halt> ; Flow R 16f9 16f9 <halt> ; Flow R 16fa 16fa <halt> ; Flow R 16fb 16fb <halt> ; Flow R 16fc 16fc <halt> ; Flow R 16fd 16fd <halt> ; Flow R 16fe 16fe <halt> ; Flow R 16ff 16ff <halt> ; Flow R 1700 1700 <halt> ; Flow R 1701 1701 <halt> ; Flow R 1702 1702 <halt> ; Flow R 1703 1703 <halt> ; Flow R 1704 1704 <halt> ; Flow R 1705 1705 <halt> ; Flow R 1706 1706 <halt> ; Flow R 1707 1707 <halt> ; Flow R 1708 1708 <halt> ; Flow R 1709 1709 <halt> ; Flow R 170a 170a <halt> ; Flow R 170b 170b <halt> ; Flow R 170c 170c <halt> ; Flow R 170d 170d <halt> ; Flow R 170e 170e <halt> ; Flow R 170f 170f <halt> ; Flow R 1710 1710 <halt> ; Flow R 1711 1711 <halt> ; Flow R 1712 1712 <halt> ; Flow R 1713 1713 <halt> ; Flow R 1714 1714 <halt> ; Flow R 1715 1715 <halt> ; Flow R 1716 1716 <halt> ; Flow R 1717 1717 <halt> ; Flow R 1718 1718 <halt> ; Flow R 1719 1719 <halt> ; Flow R 171a 171a <halt> ; Flow R 171b 171b <halt> ; Flow R 171c 171c <halt> ; Flow R 171d 171d <halt> ; Flow R 171e 171e <halt> ; Flow R 171f 171f <halt> ; Flow R 1720 1720 <halt> ; Flow R 1721 1721 <halt> ; Flow R 1722 1722 <halt> ; Flow R 1723 1723 <halt> ; Flow R 1724 1724 <halt> ; Flow R 1725 1725 <halt> ; Flow R 1726 1726 <halt> ; Flow R 1727 1727 <halt> ; Flow R 1728 1728 <halt> ; Flow R 1729 1729 <halt> ; Flow R 172a 172a <halt> ; Flow R 172b 172b <halt> ; Flow R 172c 172c <halt> ; Flow R 172d 172d <halt> ; Flow R 172e 172e <halt> ; Flow R 172f 172f <halt> ; Flow R 1730 1730 <halt> ; Flow R 1731 1731 <halt> ; Flow R 1732 1732 <halt> ; Flow R 1733 1733 <halt> ; Flow R 1734 1734 <halt> ; Flow R 1735 1735 <halt> ; Flow R 1736 1736 <halt> ; Flow R 1737 1737 <halt> ; Flow R 1738 1738 <halt> ; Flow R 1739 1739 <halt> ; Flow R 173a 173a <halt> ; Flow R 173b 173b <halt> ; Flow R 173c 173c <halt> ; Flow R 173d 173d <halt> ; Flow R 173e 173e <halt> ; Flow R 173f 173f <halt> ; Flow R 1740 1740 <halt> ; Flow R 1741 1741 <halt> ; Flow R 1742 1742 <halt> ; Flow R 1743 1743 <halt> ; Flow R 1744 1744 <halt> ; Flow R 1745 1745 <halt> ; Flow R 1746 1746 <halt> ; Flow R 1747 1747 <halt> ; Flow R 1748 1748 <halt> ; Flow R 1749 1749 <halt> ; Flow R 174a 174a <halt> ; Flow R 174b 174b <halt> ; Flow R 174c 174c <halt> ; Flow R 174d 174d <halt> ; Flow R 174e 174e <halt> ; Flow R 174f 174f <halt> ; Flow R 1750 1750 <halt> ; Flow R 1751 1751 <halt> ; Flow R 1752 1752 <halt> ; Flow R 1753 1753 <halt> ; Flow R 1754 1754 <halt> ; Flow R 1755 1755 <halt> ; Flow R 1756 1756 <halt> ; Flow R 1757 1757 <halt> ; Flow R 1758 1758 <halt> ; Flow R 1759 1759 <halt> ; Flow R 175a 175a <halt> ; Flow R 175b 175b <halt> ; Flow R 175c 175c <halt> ; Flow R 175d 175d <halt> ; Flow R 175e 175e <halt> ; Flow R 175f 175f <halt> ; Flow R 1760 1760 <halt> ; Flow R 1761 1761 <halt> ; Flow R 1762 1762 <halt> ; Flow R 1763 1763 <halt> ; Flow R 1764 1764 <halt> ; Flow R 1765 1765 <halt> ; Flow R 1766 1766 <halt> ; Flow R 1767 1767 <halt> ; Flow R 1768 1768 <halt> ; Flow R 1769 1769 <halt> ; Flow R 176a 176a <halt> ; Flow R 176b 176b <halt> ; Flow R 176c 176c <halt> ; Flow R 176d 176d <halt> ; Flow R 176e 176e <halt> ; Flow R 176f 176f <halt> ; Flow R 1770 1770 <halt> ; Flow R 1771 1771 <halt> ; Flow R 1772 1772 <halt> ; Flow R 1773 1773 <halt> ; Flow R 1774 1774 <halt> ; Flow R 1775 1775 <halt> ; Flow R 1776 1776 <halt> ; Flow R 1777 1777 <halt> ; Flow R 1778 1778 <halt> ; Flow R 1779 1779 <halt> ; Flow R 177a 177a <halt> ; Flow R 177b 177b <halt> ; Flow R 177c 177c <halt> ; Flow R 177d 177d <halt> ; Flow R 177e 177e <halt> ; Flow R 177f 177f <halt> ; Flow R 1780 1780 <halt> ; Flow R 1781 1781 <halt> ; Flow R 1782 1782 <halt> ; Flow R 1783 1783 <halt> ; Flow R 1784 1784 <halt> ; Flow R 1785 1785 <halt> ; Flow R 1786 1786 <halt> ; Flow R 1787 1787 <halt> ; Flow R 1788 1788 <halt> ; Flow R 1789 1789 <halt> ; Flow R 178a 178a <halt> ; Flow R 178b 178b <halt> ; Flow R 178c 178c <halt> ; Flow R 178d 178d <halt> ; Flow R 178e 178e <halt> ; Flow R 178f 178f <halt> ; Flow R 1790 1790 <halt> ; Flow R 1791 1791 <halt> ; Flow R 1792 1792 <halt> ; Flow R 1793 1793 <halt> ; Flow R 1794 1794 <halt> ; Flow R 1795 1795 <halt> ; Flow R 1796 1796 <halt> ; Flow R 1797 1797 <halt> ; Flow R 1798 1798 <halt> ; Flow R 1799 1799 <halt> ; Flow R 179a 179a <halt> ; Flow R 179b 179b <halt> ; Flow R 179c 179c <halt> ; Flow R 179d 179d <halt> ; Flow R 179e 179e <halt> ; Flow R 179f 179f <halt> ; Flow R 17a0 17a0 <halt> ; Flow R 17a1 17a1 <halt> ; Flow R 17a2 17a2 <halt> ; Flow R 17a3 17a3 <halt> ; Flow R 17a4 17a4 <halt> ; Flow R 17a5 17a5 <halt> ; Flow R 17a6 17a6 <halt> ; Flow R 17a7 17a7 <halt> ; Flow R 17a8 17a8 <halt> ; Flow R 17a9 17a9 <halt> ; Flow R 17aa 17aa <halt> ; Flow R 17ab 17ab <halt> ; Flow R 17ac 17ac <halt> ; Flow R 17ad 17ad <halt> ; Flow R 17ae 17ae <halt> ; Flow R 17af 17af <halt> ; Flow R 17b0 17b0 <halt> ; Flow R 17b1 17b1 <halt> ; Flow R 17b2 17b2 <halt> ; Flow R 17b3 17b3 <halt> ; Flow R 17b4 17b4 <halt> ; Flow R 17b5 17b5 <halt> ; Flow R 17b6 17b6 <halt> ; Flow R 17b7 17b7 <halt> ; Flow R 17b8 17b8 <halt> ; Flow R 17b9 17b9 <halt> ; Flow R 17ba 17ba <halt> ; Flow R 17bb 17bb <halt> ; Flow R 17bc 17bc <halt> ; Flow R 17bd 17bd <halt> ; Flow R 17be 17be <halt> ; Flow R 17bf 17bf <halt> ; Flow R 17c0 17c0 <halt> ; Flow R 17c1 17c1 <halt> ; Flow R 17c2 17c2 <halt> ; Flow R 17c3 17c3 <halt> ; Flow R 17c4 17c4 <halt> ; Flow R 17c5 17c5 <halt> ; Flow R 17c6 17c6 <halt> ; Flow R 17c7 17c7 <halt> ; Flow R 17c8 17c8 <halt> ; Flow R 17c9 17c9 <halt> ; Flow R 17ca 17ca <halt> ; Flow R 17cb 17cb <halt> ; Flow R 17cc 17cc <halt> ; Flow R 17cd 17cd <halt> ; Flow R 17ce 17ce <halt> ; Flow R 17cf 17cf <halt> ; Flow R 17d0 17d0 <halt> ; Flow R 17d1 17d1 <halt> ; Flow R 17d2 17d2 <halt> ; Flow R 17d3 17d3 <halt> ; Flow R 17d4 17d4 <halt> ; Flow R 17d5 17d5 <halt> ; Flow R 17d6 17d6 <halt> ; Flow R 17d7 17d7 <halt> ; Flow R 17d8 17d8 <halt> ; Flow R 17d9 17d9 <halt> ; Flow R 17da 17da <halt> ; Flow R 17db 17db <halt> ; Flow R 17dc 17dc <halt> ; Flow R 17dd 17dd <halt> ; Flow R 17de 17de <halt> ; Flow R 17df 17df <halt> ; Flow R 17e0 17e0 <halt> ; Flow R 17e1 17e1 <halt> ; Flow R 17e2 17e2 <halt> ; Flow R 17e3 17e3 <halt> ; Flow R 17e4 17e4 <halt> ; Flow R 17e5 17e5 <halt> ; Flow R 17e6 17e6 <halt> ; Flow R 17e7 17e7 <halt> ; Flow R 17e8 17e8 <halt> ; Flow R 17e9 17e9 <halt> ; Flow R 17ea 17ea <halt> ; Flow R 17eb 17eb <halt> ; Flow R 17ec 17ec <halt> ; Flow R 17ed 17ed <halt> ; Flow R 17ee 17ee <halt> ; Flow R 17ef 17ef <halt> ; Flow R 17f0 17f0 <halt> ; Flow R 17f1 17f1 <halt> ; Flow R 17f2 17f2 <halt> ; Flow R 17f3 17f3 <halt> ; Flow R 17f4 17f4 <halt> ; Flow R 17f5 17f5 <halt> ; Flow R 17f6 17f6 <halt> ; Flow R 17f7 17f7 <halt> ; Flow R 17f8 17f8 <halt> ; Flow R 17f9 17f9 <halt> ; Flow R 17fa 17fa <halt> ; Flow R 17fb 17fb <halt> ; Flow R 17fc 17fc <halt> ; Flow R 17fd 17fd <halt> ; Flow R 17fe 17fe <halt> ; Flow R 17ff 17ff <halt> ; Flow R 1800 1800 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 1801 1801 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1802 1802 typ_alu_func 13 ONES typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 1803 1803 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1804 1804 typ_a_adr 20 TR17:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1805 1805 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1806 1806 typ_a_adr 21 TR17:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1807 1807 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1808 1808 typ_a_adr 22 TR17:02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1809 1809 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 180a 180a typ_a_adr 23 TR17:03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 180b 180b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 180c 180c typ_a_adr 24 TR17:04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 180d 180d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 180e 180e typ_a_adr 25 TR17:05 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 180f 180f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1810 1810 typ_alu_func 1a PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1811 1811 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1812 1812 typ_alu_func 1a PASS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1813 1813 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1814 1814 typ_alu_func 1a PASS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1815 1815 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1816 1816 typ_alu_func 1a PASS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1817 1817 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1818 1818 typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1819 1819 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 181a 181a typ_alu_func 1a PASS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 181b 181b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 181c 181c typ_a_adr 20 TR17:00 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 181d 181d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 181e 181e typ_a_adr 21 TR17:01 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 181f 181f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1820 1820 typ_a_adr 22 TR17:02 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1821 1821 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1822 1822 typ_a_adr 23 TR17:03 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1823 1823 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1824 1824 typ_a_adr 24 TR17:04 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1825 1825 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1826 1826 typ_a_adr 25 TR17:05 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1827 1827 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1828 1828 typ_alu_func 15 NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1829 1829 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 182a 182a typ_alu_func 15 NOT_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 182b 182b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 182c 182c typ_alu_func 15 NOT_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 182d 182d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 182e 182e typ_alu_func 15 NOT_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 182f 182f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1830 1830 typ_alu_func 15 NOT_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1831 1831 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1832 1832 typ_alu_func 15 NOT_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1833 1833 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1834 1834 typ_a_adr 22 TR17:02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1835 1835 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1836 1836 typ_a_adr 20 TR17:00 typ_alu_func 1e A_AND_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1837 1837 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1838 1838 typ_a_adr 23 TR17:03 typ_alu_func 1e A_AND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1839 1839 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 183a 183a typ_a_adr 21 TR17:01 typ_alu_func 1e A_AND_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 183b 183b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 183c 183c typ_a_adr 24 TR17:04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 183d 183d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 183e 183e typ_a_adr 20 TR17:00 typ_alu_func 1e A_AND_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 183f 183f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1840 1840 typ_a_adr 25 TR17:05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1841 1841 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1842 1842 typ_a_adr 21 TR17:01 typ_alu_func 1e A_AND_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1843 1843 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1844 1844 typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1845 1845 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1846 1846 typ_a_adr 20 TR17:00 typ_alu_func 1b A_OR_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1847 1847 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1848 1848 typ_a_adr 23 TR17:03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1849 1849 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 184a 184a typ_a_adr 21 TR17:01 typ_alu_func 1b A_OR_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 184b 184b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 184c 184c typ_a_adr 24 TR17:04 typ_alu_func 1b A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 184d 184d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 184e 184e typ_a_adr 20 TR17:00 typ_alu_func 1b A_OR_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 184f 184f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1850 1850 typ_a_adr 25 TR17:05 typ_alu_func 1b A_OR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1851 1851 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1852 1852 typ_a_adr 21 TR17:01 typ_alu_func 1b A_OR_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1853 1853 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1854 1854 typ_a_adr 22 TR17:02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1855 1855 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1856 1856 typ_a_adr 20 TR17:00 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1857 1857 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1858 1858 typ_a_adr 23 TR17:03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1859 1859 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 185a 185a typ_a_adr 21 TR17:01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 185b 185b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 185c 185c typ_a_adr 24 TR17:04 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 185d 185d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 185e 185e typ_a_adr 20 TR17:00 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 185f 185f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1860 1860 typ_a_adr 25 TR17:05 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1861 1861 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1862 1862 typ_a_adr 21 TR17:01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1863 1863 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1864 1864 typ_a_adr 22 TR17:02 typ_alu_func 11 A_NAND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1865 1865 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1866 1866 typ_a_adr 20 TR17:00 typ_alu_func 11 A_NAND_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1867 1867 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1868 1868 typ_a_adr 23 TR17:03 typ_alu_func 11 A_NAND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1869 1869 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 186a 186a typ_a_adr 21 TR17:01 typ_alu_func 11 A_NAND_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 186b 186b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 186c 186c typ_a_adr 24 TR17:04 typ_alu_func 11 A_NAND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 186d 186d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 186e 186e typ_a_adr 20 TR17:00 typ_alu_func 11 A_NAND_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 186f 186f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1870 1870 typ_a_adr 25 TR17:05 typ_alu_func 11 A_NAND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1871 1871 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1872 1872 typ_a_adr 21 TR17:01 typ_alu_func 11 A_NAND_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1873 1873 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1874 1874 typ_a_adr 22 TR17:02 typ_alu_func 14 A_NOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1875 1875 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1876 1876 typ_a_adr 20 TR17:00 typ_alu_func 14 A_NOR_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1877 1877 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1878 1878 typ_a_adr 23 TR17:03 typ_alu_func 14 A_NOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1879 1879 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 187a 187a typ_a_adr 21 TR17:01 typ_alu_func 14 A_NOR_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 187b 187b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 187c 187c typ_a_adr 24 TR17:04 typ_alu_func 14 A_NOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 187d 187d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 187e 187e typ_a_adr 20 TR17:00 typ_alu_func 14 A_NOR_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 187f 187f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1880 1880 typ_a_adr 25 TR17:05 typ_alu_func 14 A_NOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1881 1881 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1882 1882 typ_a_adr 21 TR17:01 typ_alu_func 14 A_NOR_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1883 1883 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1884 1884 typ_a_adr 22 TR17:02 typ_alu_func 16 A_XNOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1885 1885 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1886 1886 typ_a_adr 20 TR17:00 typ_alu_func 16 A_XNOR_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1887 1887 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1888 1888 typ_a_adr 23 TR17:03 typ_alu_func 16 A_XNOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1889 1889 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 188a 188a typ_a_adr 21 TR17:01 typ_alu_func 16 A_XNOR_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 188b 188b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 188c 188c typ_a_adr 24 TR17:04 typ_alu_func 16 A_XNOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 188d 188d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 188e 188e typ_a_adr 20 TR17:00 typ_alu_func 16 A_XNOR_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 188f 188f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1890 1890 typ_a_adr 25 TR17:05 typ_alu_func 16 A_XNOR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1891 1891 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1892 1892 typ_a_adr 21 TR17:01 typ_alu_func 16 A_XNOR_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1893 1893 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1894 1894 typ_a_adr 22 TR17:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1895 1895 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1896 1896 typ_a_adr 20 TR17:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1897 1897 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1898 1898 typ_a_adr 23 TR17:03 typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1899 1899 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 189a 189a typ_a_adr 21 TR17:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 189b 189b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 189c 189c typ_a_adr 24 TR17:04 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 189d 189d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 189e 189e typ_a_adr 20 TR17:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 189f 189f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18a0 18a0 typ_a_adr 25 TR17:05 typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18a1 18a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18a2 18a2 typ_a_adr 21 TR17:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18a3 18a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18a4 18a4 typ_a_adr 22 TR17:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 18a5 18a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18a6 18a6 typ_a_adr 20 TR17:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18a7 18a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18a8 18a8 typ_a_adr 23 TR17:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18a9 18a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR17:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18aa 18aa typ_a_adr 21 TR17:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ab 18ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ac 18ac typ_a_adr 24 TR17:04 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ad 18ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR17:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ae 18ae typ_a_adr 20 TR17:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18af 18af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18b0 18b0 typ_a_adr 25 TR17:05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18b1 18b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR17:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18b2 18b2 typ_a_adr 21 TR17:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18b3 18b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR17:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18b4 18b4 typ_a_adr 22 TR17:02 typ_alu_func 12 NOT_A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 18b5 18b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18b6 18b6 typ_a_adr 20 TR17:00 typ_alu_func 12 NOT_A_OR_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18b7 18b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18b8 18b8 typ_a_adr 23 TR17:03 typ_alu_func 12 NOT_A_OR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18b9 18b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ba 18ba typ_a_adr 21 TR17:01 typ_alu_func 12 NOT_A_OR_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18bb 18bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18bc 18bc typ_a_adr 24 TR17:04 typ_alu_func 12 NOT_A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18bd 18bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18be 18be typ_a_adr 20 TR17:00 typ_alu_func 12 NOT_A_OR_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18bf 18bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18c0 18c0 typ_a_adr 25 TR17:05 typ_alu_func 12 NOT_A_OR_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18c1 18c1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18c2 18c2 typ_a_adr 21 TR17:01 typ_alu_func 12 NOT_A_OR_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18c3 18c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18c4 18c4 typ_a_adr 22 TR17:02 typ_alu_func 17 A_OR_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 18c5 18c5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18c6 18c6 typ_a_adr 20 TR17:00 typ_alu_func 17 A_OR_NOT_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18c7 18c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18c8 18c8 typ_a_adr 23 TR17:03 typ_alu_func 17 A_OR_NOT_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18c9 18c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ca 18ca typ_a_adr 21 TR17:01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18cb 18cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR17:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18cc 18cc typ_a_adr 24 TR17:04 typ_alu_func 17 A_OR_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18cd 18cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ce 18ce typ_a_adr 20 TR17:00 typ_alu_func 17 A_OR_NOT_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18cf 18cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR17:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18d0 18d0 typ_a_adr 25 TR17:05 typ_alu_func 17 A_OR_NOT_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18d1 18d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR17:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18d2 18d2 typ_a_adr 21 TR17:01 typ_alu_func 17 A_OR_NOT_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18d3 18d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR17:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18d4 18d4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_rand 1 INC_LOOP_COUNTER 18d5 18d5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 18d6 18d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 18d7 18d7 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18d8 18d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18d9 18d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 18da 18da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR18:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18db 18db seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18dc 18dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR18:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 18dd 18dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18de 18de seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18df 18df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR17:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18e0 18e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e1 18e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e2 18e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR17:0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18e3 18e3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e4 18e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e5 18e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 30 TR17:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18e6 18e6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e7 18e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18e8 18e8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 31 TR17:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18e9 18e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ea 18ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18eb 18eb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR17:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ec 18ec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ed 18ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ee 18ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR17:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18ef 18ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_rand 1 INC_LOOP_COUNTER 18f0 18f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 18f1 18f1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 18f2 18f2 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR18:01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18f3 18f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR18:01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18f4 18f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 18f5 18f5 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 27 TR18:07 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18f6 18f6 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 27 TR18:07 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 18f7 18f7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR18:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 18f8 18f8 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18f9 18f9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18fa 18fa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR17:14 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18fb 18fb seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18fc 18fc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18fd 18fd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR17:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 18fe 18fe seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 18ff 18ff seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1900 1900 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR17:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1901 1901 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1902 1902 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1903 1903 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR17:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1904 1904 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1905 1905 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1906 1906 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR17:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1907 1907 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1908 1908 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1909 1909 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR17:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 190a 190a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 190b 190b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR16:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 190c 190c seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 190d 190d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR16:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 190e 190e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 190f 190f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR16:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1910 1910 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1911 1911 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 30 TR16:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1912 1912 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1913 1913 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR16:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1914 1914 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1915 1915 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR16:14 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1916 1916 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1917 1917 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR16:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1918 1918 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1919 1919 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR16:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 191a 191a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 191b 191b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR16:0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 191c 191c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 191d 191d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 31 TR16:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 191e 191e seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 191f 191f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR16:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1920 1920 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1921 1921 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR16:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1922 1922 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1923 1923 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1924 1924 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1925 1925 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1926 1926 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1927 1927 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1928 1928 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1929 1929 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 192a 192a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR16:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 192b 192b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 192c 192c seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 192d 192d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR16:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 192e 192e seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 192f 192f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1930 1930 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR17:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1931 1931 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1932 1932 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1933 1933 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR17:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1934 1934 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1935 1935 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1936 1936 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR16:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1937 1937 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1938 1938 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 1 A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1939 1939 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR16:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 193a 193a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 193b 193b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 193c 193c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR16:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 193d 193d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 193e 193e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 193f 193f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR16:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1940 1940 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1941 1941 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1942 1942 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR17:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1943 1943 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1944 1944 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1945 1945 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR17:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1946 1946 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1947 1947 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1948 1948 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR16:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1949 1949 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 194a 194a seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 194b 194b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR16:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 194c 194c seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 194d 194d seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 194e 194e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR16:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 194f 194f seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1950 1950 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 1 A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1951 1951 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR16:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1952 1952 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1953 1953 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1954 1954 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR16:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1955 1955 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1956 1956 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1957 1957 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR16:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1958 1958 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1959 1959 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 195a 195a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR16:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 195b 195b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 195c 195c seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 195d 195d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR16:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 195e 195e seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 195f 195f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1960 1960 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR17:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1961 1961 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1962 1962 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1963 1963 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR17:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1964 1964 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1965 1965 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1966 1966 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR16:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1967 1967 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1968 1968 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1969 1969 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR16:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 196a 196a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 196b 196b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 196c 196c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 196d 196d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 196e 196e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 196f 196f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1970 1970 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1971 1971 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1972 1972 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR17:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1973 1973 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1974 1974 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1975 1975 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR17:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1976 1976 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1977 1977 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1978 1978 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR16:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1979 1979 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 197a 197a seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 197b 197b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR16:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 197c 197c seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 197d 197d seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 197e 197e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR17:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 197f 197f seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1980 1980 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1981 1981 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR17:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1982 1982 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 1983 1983 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1984 1984 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1985 1985 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1986 1986 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1987 1987 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR17:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1988 1988 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1989 1989 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 198a 198a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR17:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 198b 198b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 198c 198c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 198d 198d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR16:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 198e 198e seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 198f 198f seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1990 1990 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR16:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1991 1991 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1992 1992 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1993 1993 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR16:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1994 1994 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1995 1995 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1996 1996 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR17:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1997 1997 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1998 1998 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 6 A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1999 1999 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR16:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 199a 199a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 199b 199b seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 199c 199c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR16:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 199d 199d seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 199e 199e seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 199f 199f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR16:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19a0 19a0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a1 19a1 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a2 19a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR16:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19a3 19a3 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a4 19a4 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a5 19a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR17:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19a6 19a6 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a7 19a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19a8 19a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR17:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19a9 19a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19aa 19aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19ab 19ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19ac 19ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19ad 19ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19ae 19ae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR16:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19af 19af seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b0 19b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 6 A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b1 19b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR17:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19b2 19b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 val_rand 1 INC_LOOP_COUNTER 19b3 19b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b4 19b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR16:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19b5 19b5 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b6 19b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b7 19b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR17:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19b8 19b8 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19b9 19b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19ba 19ba seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR17:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19bb 19bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19bc 19bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19bd 19bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR16:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19be 19be seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19bf 19bf seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c0 19c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR16:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19c1 19c1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c2 19c2 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c3 19c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19c4 19c4 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c5 19c5 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c6 19c6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR16:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19c7 19c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c8 19c8 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 20 TR17:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19c9 19c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR16:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19ca 19ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19cb 19cb seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19cc 19cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19cd 19cd seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19ce 19ce seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19cf 19cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR16:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19d0 19d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR17:03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d1 19d1 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR17:03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d2 19d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR16:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19d3 19d3 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d4 19d4 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d5 19d5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR16:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19d6 19d6 seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 24 TR17:04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d7 19d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 24 TR17:04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19d8 19d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR17:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19d9 19d9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19da 19da seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19db 19db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR16:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19dc 19dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 25 TR17:05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19dd 19dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 25 TR17:05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19de 19de seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR16:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 19df 19df seq_br_type 0 Branch False; Flow J cc=False 0x19e3 seq_branch_adr 19e3 0x19e3 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19e0 19e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 21 TR17:01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 19e1 19e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x19e3 seq_br_type 1 Branch True seq_branch_adr 19e3 0x19e3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR17:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 19e2 19e2 seq_br_type 3 Unconditional Branch; Flow J 0x1a00 seq_branch_adr 1a00 0x1a00 19e3 19e3 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 19e4 19e4 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 19e5 19e5 <halt> ; Flow R 19e6 19e6 <halt> ; Flow R 19e7 19e7 <halt> ; Flow R 19e8 19e8 <halt> ; Flow R 19e9 19e9 <halt> ; Flow R 19ea 19ea <halt> ; Flow R 19eb 19eb <halt> ; Flow R 19ec 19ec <halt> ; Flow R 19ed 19ed <halt> ; Flow R 19ee 19ee <halt> ; Flow R 19ef 19ef <halt> ; Flow R 19f0 19f0 <halt> ; Flow R 19f1 19f1 <halt> ; Flow R 19f2 19f2 <halt> ; Flow R 19f3 19f3 <halt> ; Flow R 19f4 19f4 <halt> ; Flow R 19f5 19f5 <halt> ; Flow R 19f6 19f6 <halt> ; Flow R 19f7 19f7 <halt> ; Flow R 19f8 19f8 <halt> ; Flow R 19f9 19f9 <halt> ; Flow R 19fa 19fa <halt> ; Flow R 19fb 19fb <halt> ; Flow R 19fc 19fc <halt> ; Flow R 19fd 19fd <halt> ; Flow R 19fe 19fe <halt> ; Flow R 19ff 19ff <halt> ; Flow R 1a00 1a00 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 1a01 1a01 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 29 TR12:09 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 0 NO_OP 1a02 1a02 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR1a:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1a03 1a03 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 3c TR1a:1c typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand 0 NO_OP 1a04 1a04 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 3c TR1a:1c typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand 0 NO_OP 1a05 1a05 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR1a:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1a06 1a06 seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a07 1a07 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a08 1a08 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR18:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a09 1a09 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 23 TR18:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a0a 1a0a seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 23 TR18:03 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a0b 1a0b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR18:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a0c 1a0c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 2e TR18:0e typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a0d 1a0d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 2e TR18:0e typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a0e 1a0e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a0f 1a0f seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 2f TR18:0f typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a10 1a10 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 2f TR18:0f typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a11 1a11 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a12 1a12 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 1a13 1a13 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 0 NO_OP 1a14 1a14 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR18:0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a15 1a15 seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 22 TR18:02 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a16 1a16 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 22 TR18:02 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a17 1a17 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR18:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a18 1a18 seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 3c TR1a:1c typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand 0 NO_OP 1a19 1a19 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 3c TR1a:1c typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand 0 NO_OP 1a1a 1a1a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a1b 1a1b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 2c TR18:0c typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a1c 1a1c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 2c TR18:0c typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a1d 1a1d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a1e 1a1e seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 2d TR18:0d typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a1f 1a1f seq_br_type 0 Branch False; Flow J cc=False 0x1bf9 seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 2d TR18:0d typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 0 NO_OP 1a20 1a20 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR18:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a21 1a21 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a22 1a22 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a23 1a23 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a24 1a24 seq_cond_sel 26 TYP.TRUE (early) 1a25 1a25 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a26 1a26 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a27 1a27 seq_cond_sel 25 TYP.FALSE (early) 1a28 1a28 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a29 1a29 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a2a 1a2a seq_cond_sel 25 TYP.FALSE (early) 1a2b 1a2b seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a2c 1a2c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a2d 1a2d seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a2e 1a2e seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a2f 1a2f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a30 1a30 seq_cond_sel 26 TYP.TRUE (early) 1a31 1a31 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a32 1a32 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a33 1a33 seq_cond_sel 25 TYP.FALSE (early) 1a34 1a34 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a35 1a35 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a36 1a36 seq_cond_sel 25 TYP.FALSE (early) 1a37 1a37 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a38 1a38 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a39 1a39 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a3a 1a3a seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a3b 1a3b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a3c 1a3c seq_cond_sel 26 TYP.TRUE (early) 1a3d 1a3d seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a3e 1a3e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a3f 1a3f seq_cond_sel 25 TYP.FALSE (early) 1a40 1a40 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a41 1a41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a42 1a42 seq_cond_sel 25 TYP.FALSE (early) 1a43 1a43 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a44 1a44 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a45 1a45 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a46 1a46 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a47 1a47 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a48 1a48 seq_cond_sel 26 TYP.TRUE (early) 1a49 1a49 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a4a 1a4a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a4b 1a4b seq_cond_sel 25 TYP.FALSE (early) 1a4c 1a4c seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a4d 1a4d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a4e 1a4e seq_cond_sel 25 TYP.FALSE (early) 1a4f 1a4f seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR18:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1a50 1a50 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a51 1a51 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a52 1a52 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a53 1a53 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a54 1a54 seq_cond_sel 26 TYP.TRUE (early) 1a55 1a55 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a56 1a56 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a57 1a57 seq_cond_sel 25 TYP.FALSE (early) 1a58 1a58 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a59 1a59 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a5a 1a5a seq_cond_sel 25 TYP.FALSE (early) 1a5b 1a5b seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a5c 1a5c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a5d 1a5d seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a5e 1a5e seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a5f 1a5f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a60 1a60 seq_cond_sel 26 TYP.TRUE (early) 1a61 1a61 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a62 1a62 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1a63 1a63 seq_cond_sel 25 TYP.FALSE (early) 1a64 1a64 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a65 1a65 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a66 1a66 seq_cond_sel 25 TYP.FALSE (early) 1a67 1a67 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 1a68 1a68 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1a69 1a69 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a6a 1a6a seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a6b 1a6b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a6c 1a6c seq_cond_sel 26 TYP.TRUE (early) 1a6d 1a6d seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a6e 1a6e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a6f 1a6f seq_cond_sel 25 TYP.FALSE (early) 1a70 1a70 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a71 1a71 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a72 1a72 seq_cond_sel 25 TYP.FALSE (early) 1a73 1a73 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a74 1a74 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a75 1a75 seq_cond_sel 26 TYP.TRUE (early) val_rand 1 INC_LOOP_COUNTER 1a76 1a76 seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a77 1a77 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a78 1a78 seq_cond_sel 26 TYP.TRUE (early) 1a79 1a79 seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a7a 1a7a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR16:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a7b 1a7b seq_cond_sel 25 TYP.FALSE (early) 1a7c 1a7c seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a7d 1a7d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a7e 1a7e seq_cond_sel 25 TYP.FALSE (early) 1a7f 1a7f seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1a80 1a80 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR17:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a81 1a81 typ_a_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B val_rand 1 INC_LOOP_COUNTER 1a82 1a82 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR16:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a83 1a83 typ_a_adr 22 TR17:02 typ_alu_func 13 ONES typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a84 1a84 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR16:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a85 1a85 typ_a_adr 22 TR17:02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a86 1a86 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1a87 1a87 typ_a_adr 22 TR17:02 typ_alu_func 1a PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a88 1a88 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR16:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a89 1a89 typ_a_adr 22 TR17:02 typ_alu_func 10 NOT_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a8a 1a8a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR16:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a8b 1a8b typ_a_adr 22 TR17:02 typ_alu_func 15 NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a8c 1a8c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR16:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a8d 1a8d typ_a_adr 22 TR17:02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a8e 1a8e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR16:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a8f 1a8f typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a90 1a90 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR16:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a91 1a91 typ_a_adr 22 TR17:02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a92 1a92 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR16:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a93 1a93 typ_a_adr 22 TR17:02 typ_alu_func 11 A_NAND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a94 1a94 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR16:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a95 1a95 typ_a_adr 22 TR17:02 typ_alu_func 14 A_NOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a96 1a96 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR16:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1a97 1a97 typ_a_adr 22 TR17:02 typ_alu_func 16 A_XNOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a98 1a98 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR15:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1a99 1a99 typ_a_adr 22 TR17:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a9a 1a9a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR15:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1a9b 1a9b typ_a_adr 22 TR17:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a9c 1a9c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR15:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1a9d 1a9d typ_a_adr 22 TR17:02 typ_alu_func 12 NOT_A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1a9e 1a9e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR15:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1a9f 1a9f typ_a_adr 22 TR17:02 typ_alu_func 17 A_OR_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aa0 1aa0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR15:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aa1 1aa1 typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 6 CHECK_CLASS_A_??_B 1aa2 1aa2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1aa3 1aa3 typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 6 CHECK_CLASS_A_??_B 1aa4 1aa4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR15:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aa5 1aa5 typ_a_adr 22 TR17:02 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aa6 1aa6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR15:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aa7 1aa7 typ_a_adr 22 TR17:02 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aa8 1aa8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 27 TR15:07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aa9 1aa9 typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aaa 1aaa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR15:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aab 1aab typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aac 1aac seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR15:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aad 1aad typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1aae 1aae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR15:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aaf 1aaf typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ab0 1ab0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR15:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ab1 1ab1 seq_cond_sel 26 TYP.TRUE (early) 1ab2 1ab2 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ab3 1ab3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ab4 1ab4 seq_cond_sel 25 TYP.FALSE (early) 1ab5 1ab5 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ab6 1ab6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR16:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1ab7 1ab7 seq_cond_sel 26 TYP.TRUE (early) 1ab8 1ab8 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ab9 1ab9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR16:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1aba 1aba seq_cond_sel 25 TYP.FALSE (early) 1abb 1abb seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1abc 1abc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1abd 1abd seq_cond_sel 26 TYP.TRUE (early) 1abe 1abe seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1abf 1abf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ac0 1ac0 seq_cond_sel 25 TYP.FALSE (early) 1ac1 1ac1 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func c PASS_A_ELSE_INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ac2 1ac2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 30 TR17:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ac3 1ac3 seq_cond_sel 26 TYP.TRUE (early) 1ac4 1ac4 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ac5 1ac5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 30 TR17:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ac6 1ac6 seq_cond_sel 25 TYP.FALSE (early) 1ac7 1ac7 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func d INC_A_ELSE_PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ac8 1ac8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ac9 1ac9 seq_cond_sel 26 TYP.TRUE (early) 1aca 1aca seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1acb 1acb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1acc 1acc seq_cond_sel 25 TYP.FALSE (early) 1acd 1acd seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func e PASS_A_ELSE_DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ace 1ace seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR17:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1acf 1acf seq_cond_sel 26 TYP.TRUE (early) 1ad0 1ad0 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ad1 1ad1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR17:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ad2 1ad2 seq_cond_sel 25 TYP.FALSE (early) 1ad3 1ad3 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func f DEC_A_ELSE__PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ad4 1ad4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ad5 1ad5 seq_cond_sel 26 TYP.TRUE (early) 1ad6 1ad6 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ad7 1ad7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR15:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ad8 1ad8 seq_cond_sel 25 TYP.FALSE (early) 1ad9 1ad9 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ada 1ada seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR15:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1adb 1adb seq_cond_sel 26 TYP.TRUE (early) 1adc 1adc seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1add 1add seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR15:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ade 1ade seq_cond_sel 25 TYP.FALSE (early) 1adf 1adf seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 6 CHECK_CLASS_A_??_B 1ae0 1ae0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 28 TR15:08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ae1 1ae1 typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_rand 1 INC_LOOP_COUNTER 1ae2 1ae2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2c TR15:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ae3 1ae3 typ_alu_func 13 ONES typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1ae4 1ae4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR15:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ae5 1ae5 typ_a_adr 22 TR17:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1ae6 1ae6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1ae7 1ae7 typ_alu_func 1a PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1ae8 1ae8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ae9 1ae9 typ_a_adr 22 TR17:02 typ_alu_func 10 NOT_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1aea 1aea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR15:0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aeb 1aeb typ_alu_func 15 NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1aec 1aec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 30 TR15:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aed 1aed typ_a_adr 22 TR17:02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1aee 1aee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 31 TR15:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aef 1aef typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1af0 1af0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR15:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1af1 1af1 typ_a_adr 22 TR17:02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1af2 1af2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR15:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1af3 1af3 typ_a_adr 22 TR17:02 typ_alu_func 11 A_NAND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1af4 1af4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR15:14 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1af5 1af5 typ_a_adr 22 TR17:02 typ_alu_func 14 A_NOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1af6 1af6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR15:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1af7 1af7 typ_a_adr 22 TR17:02 typ_alu_func 16 A_XNOR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1af8 1af8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR15:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1af9 1af9 typ_a_adr 22 TR17:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1afa 1afa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR15:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1afb 1afb typ_a_adr 22 TR17:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1afc 1afc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR15:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1afd 1afd typ_a_adr 22 TR17:02 typ_alu_func 12 NOT_A_OR_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1afe 1afe seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR15:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1aff 1aff typ_a_adr 22 TR17:02 typ_alu_func 17 A_OR_NOT_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b00 1b00 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR15:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b01 1b01 typ_a_adr 22 TR18:02 typ_alu_func 7 INC_A typ_b_adr 22 TR18:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 5 CHECK_CLASS_B_LIT 1b02 1b02 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b03 1b03 typ_a_adr 29 TR12:09 typ_alu_func 1c DEC_A typ_b_adr 29 TR12:09 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 5 CHECK_CLASS_B_LIT 1b04 1b04 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR15:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b05 1b05 typ_a_adr 22 TR17:02 typ_alu_func 3 LEFT_I_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b06 1b06 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3b TR15:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b07 1b07 typ_a_adr 22 TR17:02 typ_alu_func 4 LEFT_I_A_INC typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b08 1b08 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3c TR15:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b09 1b09 typ_a_adr 22 TR17:02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b0a 1b0a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR15:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b0b 1b0b typ_a_adr 22 TR17:02 typ_alu_func 2 INC_A_PLUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b0c 1b0c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3e TR15:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b0d 1b0d typ_a_adr 22 TR17:02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b0e 1b0e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR15:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b0f 1b0f typ_a_adr 22 TR17:02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b10 1b10 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR14:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1b11 1b11 seq_cond_sel 26 TYP.TRUE (early) 1b12 1b12 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b13 1b13 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b14 1b14 seq_cond_sel 25 TYP.FALSE (early) 1b15 1b15 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b16 1b16 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b17 1b17 seq_cond_sel 26 TYP.TRUE (early) 1b18 1b18 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b19 1b19 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b1a 1b1a seq_cond_sel 25 TYP.FALSE (early) 1b1b 1b1b seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func b PASS_B_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b1c 1b1c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b1d 1b1d seq_cond_sel 26 TYP.TRUE (early) 1b1e 1b1e seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func c PASS_A_ELSE_INC_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b1f 1b1f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b20 1b20 seq_cond_sel 25 TYP.FALSE (early) 1b21 1b21 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func c PASS_A_ELSE_INC_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b22 1b22 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR14:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1b23 1b23 seq_cond_sel 26 TYP.TRUE (early) 1b24 1b24 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func d INC_A_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b25 1b25 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR14:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1b26 1b26 seq_cond_sel 25 TYP.FALSE (early) 1b27 1b27 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func d INC_A_ELSE_PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b28 1b28 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b29 1b29 seq_cond_sel 26 TYP.TRUE (early) 1b2a 1b2a seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func e PASS_A_ELSE_DEC_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b2b 1b2b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b2c 1b2c seq_cond_sel 25 TYP.FALSE (early) 1b2d 1b2d seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func e PASS_A_ELSE_DEC_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b2e 1b2e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR14:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1b2f 1b2f seq_cond_sel 26 TYP.TRUE (early) 1b30 1b30 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func f DEC_A_ELSE__PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b31 1b31 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR14:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1b32 1b32 seq_cond_sel 25 TYP.FALSE (early) 1b33 1b33 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func f DEC_A_ELSE__PASS_A typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b34 1b34 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b35 1b35 seq_cond_sel 26 TYP.TRUE (early) 1b36 1b36 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b37 1b37 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR15:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b38 1b38 seq_cond_sel 25 TYP.FALSE (early) 1b39 1b39 seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 8 PLUS_ELSE_MINUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b3a 1b3a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR15:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b3b 1b3b seq_cond_sel 26 TYP.TRUE (early) 1b3c 1b3c seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b3d 1b3d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR15:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b3e 1b3e seq_cond_sel 25 TYP.FALSE (early) 1b3f 1b3f seq_en_micro 0 typ_a_adr 22 TR17:02 typ_alu_func 9 MINUS_ELSE_PLUS typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 1b40 1b40 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3d TR15:1d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1b41 1b41 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 1b42 1b42 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1b43 1b43 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 1b44 1b44 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1b45 1b45 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 1b46 1b46 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf9 seq_br_type 0 Branch False seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b47 1b47 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1b48 1b48 typ_a_adr 25 TR18:05 typ_alu_func 10 NOT_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 1b49 1b49 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf9 seq_br_type 0 Branch False seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b4a 1b4a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 1b4b 1b4b typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 1b4c 1b4c seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b4d 1b4d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 25 TR18:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b4e 1b4e typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 1b4f 1b4f seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b50 1b50 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b51 1b51 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b52 1b52 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b53 1b53 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 35 TR1a:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b54 1b54 typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b55 1b55 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b56 1b56 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b57 1b57 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b58 1b58 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b59 1b59 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2b TR1a:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b5a 1b5a typ_a_adr 3f TR18:1f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 1b5b 1b5b seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b5c 1b5c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 3f TR18:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b5d 1b5d typ_a_adr 20 TR1a:00 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b5e 1b5e seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b5f 1b5f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 20 TR1a:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b60 1b60 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b61 1b61 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b62 1b62 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 37 TR1a:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b63 1b63 typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b64 1b64 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b65 1b65 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 3c TR1a:1c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b66 1b66 typ_a_adr 2c TR1a:0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b67 1b67 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b68 1b68 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2c TR1a:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b69 1b69 typ_a_adr 2a TR1a:0a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b6a 1b6a seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b6b 1b6b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2a TR1a:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1b6c 1b6c typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 1b6d 1b6d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1b6e 1b6e seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf9 seq_br_type 0 Branch False seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 17 LOOP_COUNTER typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 1b6f 1b6f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1b70 1b70 seq_b_timing 0 Early Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 1b71 1b71 seq_br_type 1 Branch True; Flow J cc=True 0x1b70 seq_branch_adr 1b70 0x1b70 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1b72 1b72 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR1a:09 typ_frame 1a 1b73 1b73 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf9 seq_br_type 0 Branch False seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1b74 1b74 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 1b75 1b75 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf9 seq_br_type 0 Branch False seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 1b76 1b76 typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1b77 1b77 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1b78 1b78 seq_b_timing 0 Early Condition; Flow J cc=False 0x1b77 seq_br_type 0 Branch False seq_branch_adr 1b77 0x1b77 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1b79 1b79 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b7a 1b7a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1b7b 1b7b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR18:06 typ_frame 18 1b7c 1b7c val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_frame 14 val_rand 1 INC_LOOP_COUNTER 1b7d 1b7d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 4 CHECK_CLASS_A_LIT 1b7e 1b7e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 32 VR19:12 val_alu_func 7 INC_A val_frame 19 1b7f 1b7f seq_br_type 1 Branch True; Flow J cc=True 0x1b81 seq_branch_adr 1b81 0x1b81 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 20 TR18:00 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR18:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 4 CHECK_CLASS_A_LIT 1b80 1b80 seq_br_type 3 Unconditional Branch; Flow J 0x1bf9 seq_branch_adr 1bf9 0x1bf9 1b81 1b81 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1b83 seq_br_type 1 Branch True seq_branch_adr 1b83 0x1b83 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 6 A_MINUS_B val_b_adr 30 VR14:10 val_frame 14 1b82 1b82 seq_br_type 3 Unconditional Branch; Flow J 0x1bf9 seq_branch_adr 1bf9 0x1bf9 val_a_adr 30 VR14:10 val_alu_func 1 A_PLUS_B val_b_adr 30 VR14:10 val_frame 14 1b83 1b83 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR12:09 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 4 CHECK_CLASS_A_LIT 1b84 1b84 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b85 1b85 typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_rand 1 INC_LOOP_COUNTER 1b86 1b86 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1b87 1b87 typ_a_adr 22 TR18:02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1b88 1b88 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1b89 1b89 typ_a_adr 20 TR17:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b8a 1b8a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b8b 1b8b typ_a_adr 21 TR17:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b8c 1b8c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b8d 1b8d typ_a_adr 22 TR17:02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b8e 1b8e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b8f 1b8f typ_a_adr 23 TR17:03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b90 1b90 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b91 1b91 typ_a_adr 24 TR17:04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b92 1b92 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b93 1b93 typ_a_adr 25 TR17:05 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 1b94 1b94 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1b95 1b95 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 1b96 1b96 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1b97 1b97 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1b98 1b98 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1b99 1b99 seq_b_timing 0 Early Condition; Flow J cc=False 0x1b97 seq_br_type 0 Branch False seq_branch_adr 1b97 0x1b97 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1b9a 1b9a ioc_load_wdr 0 typ_b_adr 29 TR12:09 typ_frame 12 val_rand 1 INC_LOOP_COUNTER 1b9b 1b9b typ_c_adr 3e GP01 1b9c 1b9c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1b9d 1b9d ioc_load_wdr 0 typ_b_adr 22 TR18:02 typ_frame 18 1b9e 1b9e typ_c_adr 3e GP01 1b9f 1b9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1ba0 1ba0 ioc_load_wdr 0 typ_b_adr 20 TR17:00 typ_frame 17 1ba1 1ba1 typ_c_adr 3e GP01 1ba2 1ba2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ba3 1ba3 ioc_load_wdr 0 typ_b_adr 21 TR17:01 typ_frame 17 1ba4 1ba4 typ_c_adr 3e GP01 1ba5 1ba5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ba6 1ba6 ioc_load_wdr 0 typ_b_adr 22 TR17:02 typ_frame 17 1ba7 1ba7 typ_c_adr 3e GP01 1ba8 1ba8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1ba9 1ba9 ioc_load_wdr 0 typ_b_adr 23 TR17:03 typ_frame 17 1baa 1baa typ_c_adr 3e GP01 1bab 1bab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bac 1bac ioc_load_wdr 0 typ_b_adr 24 TR17:04 typ_frame 17 1bad 1bad typ_c_adr 3e GP01 1bae 1bae seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1baf 1baf ioc_load_wdr 0 typ_b_adr 25 TR17:05 typ_frame 17 1bb0 1bb0 typ_c_adr 3e GP01 1bb1 1bb1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bb2 1bb2 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 1bb3 1bb3 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1bb4 1bb4 ioc_load_wdr 0 typ_b_adr 05 GP05 1bb5 1bb5 typ_c_adr 3e GP01 1bb6 1bb6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1bb7 1bb7 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bb4 seq_br_type 0 Branch False seq_branch_adr 1bb4 0x1bb4 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1bb8 1bb8 ioc_fiubs 2 typ typ_a_adr 29 TR12:09 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 12 val_rand 1 INC_LOOP_COUNTER 1bb9 1bb9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 1bba 1bba ioc_fiubs 2 typ typ_a_adr 22 TR18:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 18 1bbb 1bbb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR18:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1bbc 1bbc ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bbd 1bbd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR17:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bbe 1bbe ioc_fiubs 2 typ typ_a_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bbf 1bbf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR17:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bc0 1bc0 ioc_fiubs 2 typ typ_a_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bc1 1bc1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR17:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bc2 1bc2 ioc_fiubs 2 typ typ_a_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bc3 1bc3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR17:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bc4 1bc4 ioc_fiubs 2 typ typ_a_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bc5 1bc5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR17:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bc6 1bc6 ioc_fiubs 2 typ typ_a_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 17 1bc7 1bc7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR17:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 17 1bc8 1bc8 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 1bc9 1bc9 typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a 1bca 1bca ioc_fiubs 2 typ typ_a_adr 05 GP05 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 1bcb 1bcb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1bcc 1bcc seq_b_timing 0 Early Condition; Flow J cc=False 0x1bca seq_br_type 0 Branch False seq_branch_adr 1bca 0x1bca seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1bcd 1bcd ioc_fiubs 2 typ typ_a_adr 22 TR18:02 typ_alu_func 1a PASS_B typ_b_adr 20 TR18:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 18 typ_rand c WRITE_OUTER_FRAME val_rand 1 INC_LOOP_COUNTER 1bce 1bce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1bcf 1bcf ioc_fiubs 2 typ typ_a_adr 20 TR18:00 typ_alu_func 1a PASS_B typ_b_adr 22 TR18:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 18 typ_rand c WRITE_OUTER_FRAME 1bd0 1bd0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR15:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1bd1 1bd1 ioc_fiubs 2 typ typ_a_adr 22 TR17:02 typ_alu_func 1a PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bd2 1bd2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR16:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1bd3 1bd3 ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bd4 1bd4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1bd5 1bd5 ioc_fiubs 2 typ typ_a_adr 22 TR17:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bd6 1bd6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3a TR16:1a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1bd7 1bd7 ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bd8 1bd8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR15:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1bd9 1bd9 ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bda 1bda seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR15:0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1bdb 1bdb ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bdc 1bdc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR15:16 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1bdd 1bdd ioc_fiubs 2 typ typ_a_adr 28 TR1a:08 typ_alu_func 1a PASS_B typ_b_adr 27 TR1a:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1a typ_rand c WRITE_OUTER_FRAME 1bde 1bde seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR1a:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1bdf 1bdf ioc_fiubs 2 typ typ_a_adr 25 TR1a:05 typ_alu_func 1a PASS_B typ_b_adr 24 TR1a:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1a typ_rand c WRITE_OUTER_FRAME 1be0 1be0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR1a:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1be1 1be1 ioc_fiubs 2 typ typ_a_adr 22 TR18:02 typ_alu_func 1a PASS_B typ_b_adr 20 TR18:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand c WRITE_OUTER_FRAME val_rand 1 INC_LOOP_COUNTER 1be2 1be2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR15:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1be3 1be3 ioc_fiubs 2 typ typ_a_adr 20 TR18:00 typ_alu_func 1a PASS_B typ_b_adr 22 TR18:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand c WRITE_OUTER_FRAME 1be4 1be4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1be5 1be5 ioc_fiubs 2 typ typ_a_adr 22 TR17:02 typ_alu_func 1a PASS_B typ_b_adr 20 TR17:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1be6 1be6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR15:0e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 15 1be7 1be7 ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 22 TR17:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1be8 1be8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR16:18 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 16 1be9 1be9 ioc_fiubs 2 typ typ_a_adr 22 TR17:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR17:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bea 1bea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR14:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1beb 1beb ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 23 TR17:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bec 1bec seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR14:04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1bed 1bed ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bee 1bee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR14:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1bef 1bef ioc_fiubs 2 typ typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 25 TR17:05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 1bf0 1bf0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR14:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 14 1bf1 1bf1 ioc_fiubs 2 typ typ_a_adr 28 TR1a:08 typ_alu_func 1a PASS_B typ_b_adr 22 TR1a:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand c WRITE_OUTER_FRAME 1bf2 1bf2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR1a:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1a 1bf3 1bf3 ioc_fiubs 2 typ typ_a_adr 25 TR1a:05 typ_alu_func 1a PASS_B typ_b_adr 3f TR1a:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1a typ_rand c WRITE_OUTER_FRAME 1bf4 1bf4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 18 1bf5 1bf5 typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 val_rand 1 INC_LOOP_COUNTER 1bf6 1bf6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1bf7 1bf7 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bf6 seq_br_type 0 Branch False seq_branch_adr 1bf6 0x1bf6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 1bf8 1bf8 seq_br_type a Unconditional Return; Flow R 1bf9 1bf9 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 1bfa 1bfa ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 1bfb 1bfb <halt> ; Flow R 1bfc 1bfc <halt> ; Flow R 1bfd 1bfd <halt> ; Flow R 1bfe 1bfe <halt> ; Flow R 1bff 1bff <halt> ; Flow R 1c00 ; -------------------------------------------------------------------------------------- 1c00 ; Comes from: 1c00 ; 0e2b C from color 0x0800 1c00 ; 0e5e C from color 0x0e09 1c00 ; -------------------------------------------------------------------------------------- 1c00 1c00 fiu_mem_start 13 start_available_query ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR18:01 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3a VR14:1a val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c01 1c01 seq_en_micro 0 1c02 1c02 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR13:0c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 13 1c03 1c03 fiu_mem_start 17 scavenger_write; Flow J cc=False 0x1c02 fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c02 0x1c02 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_b_adr 2b VR13:0b val_frame 13 val_rand 2 DEC_LOOP_COUNTER 1c04 1c04 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x1c01 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c01 0x1c01 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 3a VR14:1a val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c05 1c05 seq_en_micro 0 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c06 1c06 seq_en_micro 0 typ_a_adr 39 TR12:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 21 VR14:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c07 1c07 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 1c08 1c08 seq_br_type 1 Branch True; Flow J cc=True 0x1c07 seq_branch_adr 1c07 0x1c07 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3f VR14:1f val_frame 14 val_rand 1 INC_LOOP_COUNTER 1c09 1c09 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES 1c0a 1c0a seq_en_micro 0 val_a_adr 3c VR14:1c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c0b 1c0b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c0c 1c0c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1c0f seq_br_type 1 Branch True seq_branch_adr 1c0f 0x1c0f seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR12:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR14:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c0d 1c0d seq_b_timing 0 Early Condition; Flow J cc=False 0x1c0b seq_br_type 0 Branch False seq_branch_adr 1c0b 0x1c0b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_csa_cntl 4 DEC_CSA_BOTTOM val_rand 2 DEC_LOOP_COUNTER 1c0e 1c0e seq_br_type 7 Unconditional Call; Flow C 0x1d41 seq_branch_adr 1d41 0x1d41 seq_en_micro 0 1c0f 1c0f seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c10 1c10 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d43 seq_br_type 5 Call True seq_branch_adr 1d43 0x1d43 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1c11 1c11 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d43 seq_br_type 5 Call True seq_branch_adr 1d43 0x1d43 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 29 TR12:09 typ_frame 12 1c12 1c12 ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 13 ONES typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c13 1c13 seq_en_micro 0 typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1c14 1c14 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1c15 1c15 seq_en_micro 0 typ_csa_cntl 4 DEC_CSA_BOTTOM 1c16 1c16 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c17 1c17 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d45 seq_br_type 5 Call True seq_branch_adr 1d45 0x1d45 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c18 1c18 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c15 seq_br_type 0 Branch False seq_branch_adr 1c15 0x1c15 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c19 1c19 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c1a 1c1a seq_en_micro 0 typ_csa_cntl 4 DEC_CSA_BOTTOM 1c1b 1c1b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c1c 1c1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d47 seq_br_type 5 Call True seq_branch_adr 1d47 0x1d47 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR13:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 20 VR14:00 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c1d 1c1d seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c1e 1c1e seq_en_micro 0 typ_a_adr 3f TR13:1f typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 20 VR14:00 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1c1f 1c1f seq_en_micro 0 val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 1c20 1c20 seq_en_micro 0 typ_csa_cntl 5 INC_CSA_BOTTOM 1c21 1c21 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c22 1c22 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d49 seq_br_type 5 Call True seq_branch_adr 1d49 0x1d49 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c23 1c23 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c20 seq_br_type 0 Branch False seq_branch_adr 1c20 0x1c20 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c24 1c24 seq_en_micro 0 typ_csa_cntl 5 INC_CSA_BOTTOM 1c25 1c25 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c26 1c26 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d49 seq_br_type 5 Call True seq_branch_adr 1d49 0x1d49 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR12:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR14:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c27 1c27 seq_en_micro 0 typ_csa_cntl 5 INC_CSA_BOTTOM val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c28 1c28 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 15 BOT typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 15 BOT val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c29 1c29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d4d seq_br_type 5 Call True seq_branch_adr 1d4d 0x1d4d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR12:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR14:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c2a 1c2a seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c2b 1c2b seq_en_micro 0 typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1c2c 1c2c seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1c2d 1c2d seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 14 BOT - 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 14 BOT - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c2e 1c2e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d4b seq_br_type 5 Call True seq_branch_adr 1d4b 0x1d4b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c2f 1c2f seq_b_timing 0 Early Condition; Flow J cc=False 0x1c2d seq_br_type 0 Branch False seq_branch_adr 1c2d 0x1c2d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c30 1c30 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 14 BOT - 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 14 BOT - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c31 1c31 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d4b seq_br_type 5 Call True seq_branch_adr 1d4b 0x1d4b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR12:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR14:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c32 1c32 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c33 1c33 seq_en_micro 0 typ_a_adr 25 TR18:05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3f VR14:1f val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1c34 1c34 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1c35 1c35 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c36 1c36 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d4f seq_br_type 5 Call True seq_branch_adr 1d4f 0x1d4f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c37 1c37 seq_en_micro 0 typ_csa_cntl 3 POP_CSA 1c38 1c38 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c35 seq_br_type 0 Branch False seq_branch_adr 1c35 0x1c35 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c39 1c39 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c3a 1c3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d4f seq_br_type 5 Call True seq_branch_adr 1d4f 0x1d4f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c3b 1c3b seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c3c 1c3c seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c3d 1c3d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d51 seq_br_type 5 Call True seq_branch_adr 1d51 0x1d51 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c3e 1c3e seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c3f 1c3f seq_en_micro 0 typ_a_adr 39 TR12:19 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 21 VR14:01 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1c40 1c40 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1c41 1c41 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c42 1c42 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d53 seq_br_type 5 Call True seq_branch_adr 1d53 0x1d53 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c43 1c43 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 1c44 1c44 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c41 seq_br_type 0 Branch False seq_branch_adr 1c41 0x1c41 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c45 1c45 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c46 1c46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d53 seq_br_type 5 Call True seq_branch_adr 1d53 0x1d53 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c47 1c47 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c48 1c48 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c49 1c49 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d55 seq_br_type 5 Call True seq_branch_adr 1d55 0x1d55 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c4a 1c4a seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c4b 1c4b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 11 TOP + 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 11 TOP + 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4c 1c4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR12:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR14:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1c4d 1c4d seq_en_micro 0 typ_a_adr 25 TR18:05 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3f VR14:1f val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c4e 1c4e seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4f 1c4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c50 1c50 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c51 1c51 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c52 1c52 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c53 1c53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c54 1c54 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1c TOP - 4 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c55 1c55 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c56 1c56 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1b TOP - 5 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c57 1c57 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c58 1c58 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1a TOP - 6 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c59 1c59 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c5a 1c5a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 19 TOP - 7 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 19 TOP - 7 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c5b 1c5b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c5c 1c5c seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 18 TOP - 8 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 18 TOP - 8 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c5d 1c5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d57 seq_br_type 5 Call True seq_branch_adr 1d57 0x1d57 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c5e 1c5e seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c5f 1c5f seq_en_micro 0 typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 27 VR1a:07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 1c60 1c60 seq_en_micro 0 val_a_adr 3b VR1a:1b val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 1a 1c61 1c61 seq_en_micro 0 val_a_adr 3b VR1a:1b val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1a 1c62 1c62 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 03 GP03 val_alu_func 0 PASS_A 1c63 1c63 ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 1c64 1c64 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1c67 seq_br_type 1 Branch True seq_branch_adr 1c67 0x1c67 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1c65 1c65 seq_b_timing 0 Early Condition; Flow J cc=True 0x1d35 seq_br_type 1 Branch True seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1c66 1c66 seq_br_type 3 Unconditional Branch; Flow J 0x1c68 seq_branch_adr 1c68 0x1c68 seq_en_micro 0 1c67 1c67 seq_b_timing 0 Early Condition; Flow J cc=False 0x1d35 seq_br_type 0 Branch False seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1c68 1c68 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c62 seq_br_type 0 Branch False seq_branch_adr 1c62 0x1c62 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c69 1c69 seq_en_micro 0 val_a_adr 27 VR1a:07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 1c6a 1c6a seq_b_timing 0 Early Condition; Flow J cc=False 0x1c61 seq_br_type 0 Branch False seq_branch_adr 1c61 0x1c61 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c6b 1c6b ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL 1c6c 1c6c seq_en_micro 0 1c6d 1c6d seq_b_timing 0 Early Condition; Flow J cc=False 0x1d35 seq_br_type 0 Branch False seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1c6e 1c6e ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR1a:1b val_alu_func 0 PASS_A val_frame 1a 1c6f 1c6f seq_en_micro 0 1c70 1c70 seq_b_timing 0 Early Condition; Flow J cc=True 0x1d35 seq_br_type 1 Branch True seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 val_a_adr 39 VR13:19 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1c71 1c71 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR1a:0f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame 1a val_rand 9 PASS_A_HIGH 1c72 1c72 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1c73 1c73 seq_b_timing 0 Early Condition; Flow C cc=False 0x1d35 seq_br_type 4 Call False seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c74 1c74 fiu_tivi_src c mar_0xc; Flow J cc=False 0x1c72 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c72 0x1c72 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 1c75 1c75 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c76 1c76 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 13 ONES 1c77 1c77 ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1c78 1c78 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 3e VR13:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 1c79 1c79 ioc_load_wdr 0 seq_en_micro 0 val_b_adr 3d VR13:1d val_frame 13 1c7a 1c7a seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 21 VR14:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c7b 1c7b seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1c7c 1c7c fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1c7d 1c7d ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 1c7e 1c7e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR13:1c val_frame 13 val_rand 1 INC_LOOP_COUNTER 1c7f 1c7f fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1c7d seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c7d 0x1c7d seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1c80 1c80 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c81 seq_br_type 0 Branch False seq_branch_adr 1c81 0x1c81 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 1c81 1c81 seq_en_micro 0 typ_csa_cntl 4 DEC_CSA_BOTTOM 1c82 1c82 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1c83 1c83 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR12:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 21 VR14:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c84 1c84 seq_en_micro 0 1c85 1c85 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c86 1c86 seq_br_type 1 Branch True; Flow J cc=True 0x1c84 seq_branch_adr 1c84 0x1c84 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR13:1c val_frame 13 val_rand 1 INC_LOOP_COUNTER 1c87 1c87 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR12:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 21 VR14:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c88 1c88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d37 seq_br_type 5 Call True seq_branch_adr 1d37 0x1d37 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c89 1c89 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d37 seq_br_type 5 Call True seq_branch_adr 1d37 0x1d37 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1c8a 1c8a seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c8b 1c8b seq_br_type 1 Branch True; Flow J cc=True 0x1c88 seq_branch_adr 1c88 0x1c88 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR13:1c val_frame 13 val_rand 1 INC_LOOP_COUNTER 1c8c 1c8c ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1c8d 1c8d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 val_a_adr 21 VR14:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c8e 1c8e fiu_tivi_src c mar_0xc; Flow C cc=True 0x1d33 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1c8f 1c8f seq_br_type 4 Call False; Flow C cc=False 0x1d33 seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_rand 1 INC_LOOP_COUNTER 1c90 1c90 seq_br_type 1 Branch True; Flow J cc=True 0x1c8f seq_branch_adr 1c8f 0x1c8f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR13:1c val_frame 13 1c91 1c91 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c92 1c92 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR12:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 21 VR14:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1c93 1c93 ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 1c94 1c94 fiu_mem_start 2 start-rd seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1c95 1c95 seq_en_micro 0 1c96 1c96 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c97 1c97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 1c98 1c98 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1c99 1c99 seq_br_type 1 Branch True; Flow J cc=True 0x1c94 seq_branch_adr 1c94 0x1c94 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 3c VR13:1c val_frame 13 1c9a 1c9a seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1c9b 1c9b seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 2e TR13:0e typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1c9c 1c9c seq_en_micro 0 1c9d 1c9d ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1c9e 1c9e fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1c9f 1c9f ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 1ca0 1ca0 seq_b_timing 0 Early Condition; Flow J cc=False 0x1c9e seq_br_type 0 Branch False seq_branch_adr 1c9e 0x1c9e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_rand 2 DEC_LOOP_COUNTER 1ca1 1ca1 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1ca2 1ca2 seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ca3 1ca3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3b seq_br_type 5 Call True seq_branch_adr 1d3b 0x1d3b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ca4 1ca4 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1ca5 1ca5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3b seq_br_type 5 Call True seq_branch_adr 1d3b 0x1d3b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 1ca6 1ca6 seq_br_type 1 Branch True; Flow J cc=True 0x1ca2 seq_branch_adr 1ca2 0x1ca2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR19:16 val_frame 19 val_rand 1 INC_LOOP_COUNTER 1ca7 1ca7 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1ca8 1ca8 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 13 ONES 1ca9 1ca9 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 2e TR13:0e typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1caa 1caa seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1cab 1cab ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR13:1f val_frame 13 1cac 1cac fiu_mem_start 2 start-rd seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1cad 1cad seq_en_micro 0 1cae 1cae ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1caf 1caf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3d seq_br_type 5 Call True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1cb0 1cb0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3d seq_br_type 5 Call True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1cb1 1cb1 seq_b_timing 0 Early Condition; Flow J cc=False 0x1cac seq_br_type 0 Branch False seq_branch_adr 1cac 0x1cac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 1cb2 1cb2 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1cb3 1cb3 seq_en_micro 0 1cb4 1cb4 seq_br_type 7 Unconditional Call; Flow C 0x1d00 seq_branch_adr 1d00 0x1d00 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR13:1b val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 13 1cb5 1cb5 seq_br_type 7 Unconditional Call; Flow C 0x1d00 seq_branch_adr 1d00 0x1d00 seq_en_micro 0 val_a_adr 3b VR13:1b val_alu_func 1 A_PLUS_B val_b_adr 3a VR13:1a val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 13 1cb6 1cb6 seq_br_type 7 Unconditional Call; Flow C 0x1d00 seq_branch_adr 1d00 0x1d00 seq_en_micro 0 val_a_adr 3b VR13:1b val_alu_func 1 A_PLUS_B val_b_adr 39 VR13:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 13 1cb7 1cb7 seq_br_type 7 Unconditional Call; Flow C 0x1d00 seq_branch_adr 1d00 0x1d00 seq_en_micro 0 val_a_adr 3b VR13:1b val_alu_func 1 A_PLUS_B val_b_adr 38 VR13:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 13 1cb8 1cb8 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1cb9 1cb9 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 1a PASS_B val_b_adr 36 VR13:16 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 1cba 1cba seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1cbb 1cbb seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_b_adr 05 GP05 1cbc 1cbc seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_b_adr 05 GP05 1cbd 1cbd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cbe 1cbe seq_br_type 4 Call False; Flow C cc=False 0x1d33 seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cbf 1cbf seq_b_timing 0 Early Condition; Flow C cc=False 0x1d35 seq_br_type 4 Call False seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1cc0 1cc0 ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 38 TR12:18 typ_csa_cntl 1 START_POP_DOWN typ_frame 12 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cc1 1cc1 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1cc2 1cc2 ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cc3 1cc3 seq_br_type 4 Call False; Flow C cc=False 0x1d33 seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cc4 1cc4 seq_b_timing 0 Early Condition; Flow C cc=False 0x1d35 seq_br_type 4 Call False seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1cc5 1cc5 ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 3b TR13:1b typ_csa_cntl 1 START_POP_DOWN typ_frame 13 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 36 VR13:16 val_frame 13 1cc6 1cc6 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1cc7 1cc7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cc8 1cc8 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL 1cc9 1cc9 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 1a PASS_B val_b_adr 36 VR13:16 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 1cca 1cca seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1ccb 1ccb seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_b_adr 05 GP05 1ccc 1ccc seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_b_adr 05 GP05 1ccd 1ccd ioc_adrbs 1 val ; Flow J cc=True 0x1cd0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1cd0 0x1cd0 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 38 TR12:18 typ_csa_cntl 1 START_POP_DOWN typ_frame 12 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cce 1cce seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1ccf 1ccf seq_br_type 7 Unconditional Call; Flow C 0x1d3f seq_branch_adr 1d3f 0x1d3f seq_en_micro 0 1cd0 1cd0 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1cd1 1cd1 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 1 START_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 36 VR13:16 val_frame 13 1cd2 1cd2 seq_en_micro 0 1cd3 1cd3 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1cd4 1cd4 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL 1cd5 1cd5 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cd6 1cd6 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1cd7 1cd7 seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1cd8 1cd8 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1cd9 1cd9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cda 1cda seq_b_timing 0 Early Condition; Flow J cc=False 0x1cd8 seq_br_type 0 Branch False seq_branch_adr 1cd8 0x1cd8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1cdb 1cdb ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 38 TR12:18 typ_csa_cntl 1 START_POP_DOWN typ_frame 12 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cdc 1cdc seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1cdd 1cdd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cde 1cde seq_b_timing 0 Early Condition; Flow J cc=False 0x1cdd seq_br_type 0 Branch False seq_branch_adr 1cdd 0x1cdd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1cdf 1cdf ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1ce0 1ce0 ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 35 VR13:15 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 val_rand 9 PASS_A_HIGH 1ce1 1ce1 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1ce2 1ce2 seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1ce3 1ce3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1ce4 1ce4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1ce5 1ce5 seq_b_timing 0 Early Condition; Flow J cc=False 0x1ce3 seq_br_type 0 Branch False seq_branch_adr 1ce3 0x1ce3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1ce6 1ce6 ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 38 TR12:18 typ_csa_cntl 1 START_POP_DOWN typ_frame 12 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1ce7 1ce7 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1ce8 1ce8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1ce9 1ce9 seq_b_timing 0 Early Condition; Flow J cc=False 0x1ce8 seq_br_type 0 Branch False seq_branch_adr 1ce8 0x1ce8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1cea 1cea ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1ceb 1ceb seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1cec 1cec seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1ced 1ced seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1cee 1cee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cef 1cef seq_b_timing 0 Early Condition; Flow J cc=False 0x1ced seq_br_type 0 Branch False seq_branch_adr 1ced 0x1ced seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1cf0 1cf0 ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 38 TR12:18 typ_csa_cntl 1 START_POP_DOWN typ_frame 12 val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cf1 1cf1 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1cf2 1cf2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d33 seq_br_type 5 Call True seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cf3 1cf3 seq_b_timing 0 Early Condition; Flow J cc=False 0x1cf2 seq_br_type 0 Branch False seq_branch_adr 1cf2 0x1cf2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1cf4 1cf4 seq_en_micro 0 val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1cf5 1cf5 ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR13:17 val_frame 13 1cf6 1cf6 seq_en_micro 0 typ_csa_cntl 3 POP_CSA 1cf7 1cf7 seq_en_micro 0 1cf8 1cf8 seq_b_timing 0 Early Condition; Flow C cc=True 0x1d35 seq_br_type 5 Call True seq_branch_adr 1d35 0x1d35 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 1cf9 1cf9 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 37 TR12:17 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 12 val_alu_func 1a PASS_B val_b_adr 3c VR13:1c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 13 1cfa 1cfa fiu_mem_start 2 start-rd; Flow C cc=False 0x1d33 seq_br_type 4 Call False seq_branch_adr 1d33 0x1d33 seq_cond_sel 63 CSA_HIT seq_en_micro 0 1cfb 1cfb seq_en_micro 0 1cfc 1cfc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1d39 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 3c VR13:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 1cfd 1cfd ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1d39 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 37 TR12:17 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1cfe 1cfe seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 20 VR01:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1 1cff 1cff seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1d00 ; -------------------------------------------------------------------------------------- 1d00 ; Comes from: 1d00 ; 1cb4 C from color 0x1c00 1d00 ; 1cb5 C from color 0x1c00 1d00 ; 1cb6 C from color 0x1c00 1d00 ; 1cb7 C from color 0x1c00 1d00 ; -------------------------------------------------------------------------------------- 1d00 1d00 ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 13 ONES typ_csa_cntl 0 LOAD_CONTROL_TOP val_alu_func 1a PASS_B val_b_adr 33 VR13:13 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1d01 1d01 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR13:1b val_frame 13 1d02 1d02 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_b_adr 30 VR14:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1d03 1d03 fiu_mem_start 4 continue; Flow J cc=False 0x1d03 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d03 0x1d03 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_alu_func 7 INC_A val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1d04 1d04 ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 7 INC_A val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d05 1d05 ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 34 TR14:14 typ_alu_func 7 INC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 14 val_alu_func 1a PASS_B val_b_adr 08 GP08 1d06 1d06 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1d07 1d07 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1d08 1d08 seq_b_timing 0 Early Condition; Flow J cc=False 0x1d07 seq_br_type 0 Branch False seq_branch_adr 1d07 0x1d07 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d09 1d09 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 08 GP08 1d0a 1d0a fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 1d0b 1d0b ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 34 VR13:14 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1d0c 1d0c ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 1d0d 1d0d fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1a PASS_B val_b_adr 3b VR13:1b val_frame 13 val_rand 1 INC_LOOP_COUNTER 1d0e 1d0e fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1d0f 1d0f fiu_mem_start 4 continue; Flow J cc=False 0x1d0f ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d0f 0x1d0f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1d10 1d10 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d11 1d11 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d12 1d12 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 34 VR13:14 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 1d13 1d13 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 1d14 1d14 seq_en_micro 0 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1d15 1d15 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d19 seq_br_type 1 Branch True seq_branch_adr 1d19 0x1d19 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 34 VR13:14 val_frame 13 1d16 1d16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3d seq_br_type 5 Call True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1d17 1d17 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d3d seq_br_type 5 Call True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d18 1d18 seq_br_type 3 Unconditional Branch; Flow J 0x1d15 seq_branch_adr 1d15 0x1d15 seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1d19 1d19 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1d1a 1d1a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 7 INC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d1b 1d1b seq_b_timing 0 Early Condition; Flow J cc=False 0x1d19 seq_br_type 0 Branch False seq_branch_adr 1d19 0x1d19 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 7 INC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1d1c 1d1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1d1d 1d1d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 7 INC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d1e 1d1e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 7 INC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1d1f 1d1f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1d39 seq_br_type 5 Call True seq_branch_adr 1d39 0x1d39 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d20 1d20 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 36 VR19:16 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1d21 1d21 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 34 VR13:14 val_alu_func 1a PASS_B val_b_adr 3b VR13:1b val_frame 13 1d22 1d22 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x1d22 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d22 0x1d22 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 29 TR12:09 typ_frame 12 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1d23 1d23 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 29 TR12:09 typ_frame 12 1d24 1d24 seq_en_micro 0 1d25 1d25 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 36 VR19:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1d26 1d26 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x1d3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1d3b 0x1d3b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d27 1d27 seq_b_timing 0 Early Condition; Flow J cc=False 0x1d26 seq_br_type 0 Branch False seq_branch_adr 1d26 0x1d26 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_rand 2 DEC_LOOP_COUNTER 1d28 1d28 ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3b VR13:1b val_alu_func 13 ONES val_frame 13 1d29 1d29 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 08 GP08 1d2a 1d2a ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 36 VR19:16 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1d2b 1d2b fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 34 VR13:14 val_frame 13 val_rand 1 INC_LOOP_COUNTER 1d2c 1d2c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 06 GP06 1d2d 1d2d ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 7 INC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d2e 1d2e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1d3d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d2f 1d2f fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x1d2c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d2c 0x1d2c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 1d30 1d30 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d31 1d31 <halt> ; Flow R 1d32 1d32 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d33 ; -------------------------------------------------------------------------------------- 1d33 ; Comes from: 1d33 ; 1c8d C True from color 0x1c00 1d33 ; 1c8e C True from color 0x1c00 1d33 ; 1c8f C False from color 0x1c00 1d33 ; 1cbe C False from color 0x1c00 1d33 ; 1cc3 C False from color 0x1c00 1d33 ; 1cc7 C True from color 0x1c00 1d33 ; 1cd9 C True from color 0x1c00 1d33 ; 1cdd C True from color 0x1c00 1d33 ; 1ce4 C True from color 0x1c00 1d33 ; 1ce8 C True from color 0x1c00 1d33 ; 1cee C True from color 0x1c00 1d33 ; 1cf2 C True from color 0x1c00 1d33 ; 1cfa C False from color 0x1c00 1d33 ; -------------------------------------------------------------------------------------- 1d33 1d33 <halt> ; Flow R 1d34 1d34 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d35 1d35 <halt> ; Flow R 1d36 1d36 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d37 ; -------------------------------------------------------------------------------------- 1d37 ; Comes from: 1d37 ; 1c88 C True from color 0x1c00 1d37 ; 1c89 C True from color 0x1c00 1d37 ; -------------------------------------------------------------------------------------- 1d37 1d37 <halt> ; Flow R 1d38 1d38 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d39 ; -------------------------------------------------------------------------------------- 1d39 ; Comes from: 1d39 ; 1c97 C True from color 0x1c00 1d39 ; 1c98 C True from color 0x1c00 1d39 ; 1cfc C True from color 0x1c00 1d39 ; 1cfd C True from color 0x1c00 1d39 ; 1d19 C True from color 0x1d00 1d39 ; 1d1a C True from color 0x1d00 1d39 ; 1d1c C True from color 0x1d00 1d39 ; 1d1d C True from color 0x1d00 1d39 ; 1d1e C True from color 0x1d00 1d39 ; 1d1f C True from color 0x1d00 1d39 ; -------------------------------------------------------------------------------------- 1d39 1d39 <halt> ; Flow R 1d3a 1d3a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d3b ; -------------------------------------------------------------------------------------- 1d3b ; Comes from: 1d3b ; 1ca3 C True from color 0x1c00 1d3b ; 1ca5 C True from color 0x1c00 1d3b ; 1d26 C True from color 0x1d00 1d3b ; -------------------------------------------------------------------------------------- 1d3b 1d3b <halt> ; Flow R 1d3c 1d3c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d3d ; -------------------------------------------------------------------------------------- 1d3d ; Comes from: 1d3d ; 1caf C True from color 0x1c00 1d3d ; 1cb0 C True from color 0x1c00 1d3d ; 1d16 C True from color 0x1d00 1d3d ; 1d17 C True from color 0x1d00 1d3d ; 1d2e C True from color 0x1d00 1d3d ; -------------------------------------------------------------------------------------- 1d3d 1d3d <halt> ; Flow R 1d3e 1d3e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d3f ; -------------------------------------------------------------------------------------- 1d3f ; Comes from: 1d3f ; 1ccf C from color 0x1c00 1d3f ; -------------------------------------------------------------------------------------- 1d3f 1d3f <halt> ; Flow R 1d40 1d40 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d41 ; -------------------------------------------------------------------------------------- 1d41 ; Comes from: 1d41 ; 1c0e C from color 0x1c00 1d41 ; -------------------------------------------------------------------------------------- 1d41 1d41 <halt> ; Flow R 1d42 1d42 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d43 ; -------------------------------------------------------------------------------------- 1d43 ; Comes from: 1d43 ; 1c10 C True from color 0x1c00 1d43 ; 1c11 C True from color 0x1c00 1d43 ; -------------------------------------------------------------------------------------- 1d43 1d43 <halt> ; Flow R 1d44 1d44 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d45 ; -------------------------------------------------------------------------------------- 1d45 ; Comes from: 1d45 ; 1c17 C True from color 0x1c00 1d45 ; -------------------------------------------------------------------------------------- 1d45 1d45 <halt> ; Flow R 1d46 1d46 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d47 ; -------------------------------------------------------------------------------------- 1d47 ; Comes from: 1d47 ; 1c1c C True from color 0x1c00 1d47 ; -------------------------------------------------------------------------------------- 1d47 1d47 <halt> ; Flow R 1d48 1d48 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d49 ; -------------------------------------------------------------------------------------- 1d49 ; Comes from: 1d49 ; 1c22 C True from color 0x1c00 1d49 ; 1c26 C True from color 0x1c00 1d49 ; -------------------------------------------------------------------------------------- 1d49 1d49 <halt> ; Flow R 1d4a 1d4a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d4b ; -------------------------------------------------------------------------------------- 1d4b ; Comes from: 1d4b ; 1c2e C True from color 0x1c00 1d4b ; 1c31 C True from color 0x1c00 1d4b ; -------------------------------------------------------------------------------------- 1d4b 1d4b <halt> ; Flow R 1d4c 1d4c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d4d ; -------------------------------------------------------------------------------------- 1d4d ; Comes from: 1d4d ; 1c29 C True from color 0x1c00 1d4d ; -------------------------------------------------------------------------------------- 1d4d 1d4d <halt> ; Flow R 1d4e 1d4e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d4f ; -------------------------------------------------------------------------------------- 1d4f ; Comes from: 1d4f ; 1c36 C True from color 0x1c00 1d4f ; 1c3a C True from color 0x1c00 1d4f ; -------------------------------------------------------------------------------------- 1d4f 1d4f <halt> ; Flow R 1d50 1d50 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d51 ; -------------------------------------------------------------------------------------- 1d51 ; Comes from: 1d51 ; 1c3d C True from color 0x1c00 1d51 ; -------------------------------------------------------------------------------------- 1d51 1d51 <halt> ; Flow R 1d52 1d52 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d53 ; -------------------------------------------------------------------------------------- 1d53 ; Comes from: 1d53 ; 1c42 C True from color 0x1c00 1d53 ; 1c46 C True from color 0x1c00 1d53 ; -------------------------------------------------------------------------------------- 1d53 1d53 <halt> ; Flow R 1d54 1d54 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d55 ; -------------------------------------------------------------------------------------- 1d55 ; Comes from: 1d55 ; 1c49 C True from color 0x1c00 1d55 ; -------------------------------------------------------------------------------------- 1d55 1d55 <halt> ; Flow R 1d56 1d56 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d57 ; -------------------------------------------------------------------------------------- 1d57 ; Comes from: 1d57 ; 1c4c C True from color 0x1c00 1d57 ; 1c4f C True from color 0x1c00 1d57 ; 1c51 C True from color 0x1c00 1d57 ; 1c53 C True from color 0x1c00 1d57 ; 1c55 C True from color 0x1c00 1d57 ; 1c57 C True from color 0x1c00 1d57 ; 1c59 C True from color 0x1c00 1d57 ; 1c5b C True from color 0x1c00 1d57 ; 1c5d C True from color 0x1c00 1d57 ; -------------------------------------------------------------------------------------- 1d57 1d57 <halt> ; Flow R 1d58 1d58 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1d59 1d59 <halt> ; Flow R 1d5a 1d5a <halt> ; Flow R 1d5b 1d5b <halt> ; Flow R 1d5c 1d5c <halt> ; Flow R 1d5d 1d5d <halt> ; Flow R 1d5e 1d5e <halt> ; Flow R 1d5f 1d5f <halt> ; Flow R 1d60 1d60 <halt> ; Flow R 1d61 1d61 <halt> ; Flow R 1d62 1d62 <halt> ; Flow R 1d63 1d63 <halt> ; Flow R 1d64 1d64 <halt> ; Flow R 1d65 1d65 <halt> ; Flow R 1d66 1d66 <halt> ; Flow R 1d67 1d67 <halt> ; Flow R 1d68 1d68 <halt> ; Flow R 1d69 1d69 <halt> ; Flow R 1d6a 1d6a <halt> ; Flow R 1d6b 1d6b <halt> ; Flow R 1d6c 1d6c <halt> ; Flow R 1d6d 1d6d <halt> ; Flow R 1d6e 1d6e <halt> ; Flow R 1d6f 1d6f <halt> ; Flow R 1d70 1d70 <halt> ; Flow R 1d71 1d71 <halt> ; Flow R 1d72 1d72 <halt> ; Flow R 1d73 1d73 <halt> ; Flow R 1d74 1d74 <halt> ; Flow R 1d75 1d75 <halt> ; Flow R 1d76 1d76 <halt> ; Flow R 1d77 1d77 <halt> ; Flow R 1d78 1d78 <halt> ; Flow R 1d79 1d79 <halt> ; Flow R 1d7a 1d7a <halt> ; Flow R 1d7b 1d7b <halt> ; Flow R 1d7c 1d7c <halt> ; Flow R 1d7d 1d7d <halt> ; Flow R 1d7e 1d7e <halt> ; Flow R 1d7f 1d7f <halt> ; Flow R 1d80 1d80 <halt> ; Flow R 1d81 1d81 <halt> ; Flow R 1d82 1d82 <halt> ; Flow R 1d83 1d83 <halt> ; Flow R 1d84 1d84 <halt> ; Flow R 1d85 1d85 <halt> ; Flow R 1d86 1d86 <halt> ; Flow R 1d87 1d87 <halt> ; Flow R 1d88 1d88 <halt> ; Flow R 1d89 1d89 <halt> ; Flow R 1d8a 1d8a <halt> ; Flow R 1d8b 1d8b <halt> ; Flow R 1d8c 1d8c <halt> ; Flow R 1d8d 1d8d <halt> ; Flow R 1d8e 1d8e <halt> ; Flow R 1d8f 1d8f <halt> ; Flow R 1d90 1d90 <halt> ; Flow R 1d91 1d91 <halt> ; Flow R 1d92 1d92 <halt> ; Flow R 1d93 1d93 <halt> ; Flow R 1d94 1d94 <halt> ; Flow R 1d95 1d95 <halt> ; Flow R 1d96 1d96 <halt> ; Flow R 1d97 1d97 <halt> ; Flow R 1d98 1d98 <halt> ; Flow R 1d99 1d99 <halt> ; Flow R 1d9a 1d9a <halt> ; Flow R 1d9b 1d9b <halt> ; Flow R 1d9c 1d9c <halt> ; Flow R 1d9d 1d9d <halt> ; Flow R 1d9e 1d9e <halt> ; Flow R 1d9f 1d9f <halt> ; Flow R 1da0 1da0 <halt> ; Flow R 1da1 1da1 <halt> ; Flow R 1da2 1da2 <halt> ; Flow R 1da3 1da3 <halt> ; Flow R 1da4 1da4 <halt> ; Flow R 1da5 1da5 <halt> ; Flow R 1da6 1da6 <halt> ; Flow R 1da7 1da7 <halt> ; Flow R 1da8 1da8 <halt> ; Flow R 1da9 1da9 <halt> ; Flow R 1daa 1daa <halt> ; Flow R 1dab 1dab <halt> ; Flow R 1dac 1dac <halt> ; Flow R 1dad 1dad <halt> ; Flow R 1dae 1dae <halt> ; Flow R 1daf 1daf <halt> ; Flow R 1db0 1db0 <halt> ; Flow R 1db1 1db1 <halt> ; Flow R 1db2 1db2 <halt> ; Flow R 1db3 1db3 <halt> ; Flow R 1db4 1db4 <halt> ; Flow R 1db5 1db5 <halt> ; Flow R 1db6 1db6 <halt> ; Flow R 1db7 1db7 <halt> ; Flow R 1db8 1db8 <halt> ; Flow R 1db9 1db9 <halt> ; Flow R 1dba 1dba <halt> ; Flow R 1dbb 1dbb <halt> ; Flow R 1dbc 1dbc <halt> ; Flow R 1dbd 1dbd <halt> ; Flow R 1dbe 1dbe <halt> ; Flow R 1dbf 1dbf <halt> ; Flow R 1dc0 1dc0 <halt> ; Flow R 1dc1 1dc1 <halt> ; Flow R 1dc2 1dc2 <halt> ; Flow R 1dc3 1dc3 <halt> ; Flow R 1dc4 1dc4 <halt> ; Flow R 1dc5 1dc5 <halt> ; Flow R 1dc6 1dc6 <halt> ; Flow R 1dc7 1dc7 <halt> ; Flow R 1dc8 1dc8 <halt> ; Flow R 1dc9 1dc9 <halt> ; Flow R 1dca 1dca <halt> ; Flow R 1dcb 1dcb <halt> ; Flow R 1dcc 1dcc <halt> ; Flow R 1dcd 1dcd <halt> ; Flow R 1dce 1dce <halt> ; Flow R 1dcf 1dcf <halt> ; Flow R 1dd0 1dd0 <halt> ; Flow R 1dd1 1dd1 <halt> ; Flow R 1dd2 1dd2 <halt> ; Flow R 1dd3 1dd3 <halt> ; Flow R 1dd4 1dd4 <halt> ; Flow R 1dd5 1dd5 <halt> ; Flow R 1dd6 1dd6 <halt> ; Flow R 1dd7 1dd7 <halt> ; Flow R 1dd8 1dd8 <halt> ; Flow R 1dd9 1dd9 <halt> ; Flow R 1dda 1dda <halt> ; Flow R 1ddb 1ddb <halt> ; Flow R 1ddc 1ddc <halt> ; Flow R 1ddd 1ddd <halt> ; Flow R 1dde 1dde <halt> ; Flow R 1ddf 1ddf <halt> ; Flow R 1de0 1de0 <halt> ; Flow R 1de1 1de1 <halt> ; Flow R 1de2 1de2 <halt> ; Flow R 1de3 1de3 <halt> ; Flow R 1de4 1de4 <halt> ; Flow R 1de5 1de5 <halt> ; Flow R 1de6 1de6 <halt> ; Flow R 1de7 1de7 <halt> ; Flow R 1de8 1de8 <halt> ; Flow R 1de9 1de9 <halt> ; Flow R 1dea 1dea <halt> ; Flow R 1deb 1deb <halt> ; Flow R 1dec 1dec <halt> ; Flow R 1ded 1ded <halt> ; Flow R 1dee 1dee <halt> ; Flow R 1def 1def <halt> ; Flow R 1df0 1df0 <halt> ; Flow R 1df1 1df1 <halt> ; Flow R 1df2 1df2 <halt> ; Flow R 1df3 1df3 <halt> ; Flow R 1df4 1df4 <halt> ; Flow R 1df5 1df5 <halt> ; Flow R 1df6 1df6 <halt> ; Flow R 1df7 1df7 <halt> ; Flow R 1df8 1df8 <halt> ; Flow R 1df9 1df9 <halt> ; Flow R 1dfa 1dfa <halt> ; Flow R 1dfb 1dfb <halt> ; Flow R 1dfc 1dfc <halt> ; Flow R 1dfd 1dfd <halt> ; Flow R 1dfe 1dfe <halt> ; Flow R 1dff 1dff <halt> ; Flow R 1e00 1e00 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e01 1e01 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 1e02 1e02 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e03 1e03 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_b_adr 03 GP03 val_b_adr 30 VR14:10 val_frame 14 1e04 1e04 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 5c Load_current_name+Load_save_offset+? typ_b_adr 04 GP04 val_b_adr 30 VR14:10 val_frame 14 1e05 1e05 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 1e06 1e06 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 1e07 1e07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x219c seq_br_type 5 Call True seq_branch_adr 219c 0x219c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e08 1e08 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET typ_a_adr 24 TR18:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1e09 1e09 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x219d seq_br_type 5 Call True seq_branch_adr 219d 0x219d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e0a 1e0a typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1e0b 1e0b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1e02 seq_br_type 0 Branch False seq_branch_adr 1e02 0x1e02 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 3 LEFT_I_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1e0c 1e0c typ_a_adr 21 TR18:01 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 1e0d 1e0d typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 1e0e 1e0e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e0f 1e0f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_b_adr 03 GP03 val_b_adr 30 VR14:10 val_frame 14 1e10 1e10 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 5c Load_current_name+Load_save_offset+? typ_b_adr 04 GP04 val_b_adr 30 VR14:10 val_frame 14 1e11 1e11 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET typ_a_adr 27 TR14:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 14 1e12 1e12 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 27 TR14:07 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 14 1e13 1e13 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x219c seq_br_type 5 Call True seq_branch_adr 219c 0x219c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e14 1e14 ioc_tvbs 5 seq+seq seq_int_reads 4 SAVE OFFSET typ_a_adr 24 TR18:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 18 1e15 1e15 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 24 TR18:04 typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 18 1e16 1e16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x219d seq_br_type 5 Call True seq_branch_adr 219d 0x219d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 0b GP0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e17 1e17 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1e18 1e18 seq_br_type 1 Branch True; Flow J cc=True 0x1e0e seq_branch_adr 1e0e 0x1e0e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1e19 1e19 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e1a 1e1a typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1e1b 1e1b val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 19 1e1c 1e1c val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1e1d 1e1d seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 2a TR14:0a typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 14 val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1e1e 1e1e seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e1f 1e1f ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 1e20 1e20 seq_br_type 1 Branch True; Flow J cc=True 0x1e23 seq_branch_adr 1e23 0x1e23 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0a GP0a 1e21 1e21 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2199 seq_br_type 5 Call True seq_branch_adr 2199 0x2199 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1e22 1e22 seq_br_type 3 Unconditional Branch; Flow J 0x1e24 seq_branch_adr 1e24 0x1e24 1e23 1e23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2199 seq_br_type 5 Call True seq_branch_adr 2199 0x2199 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1e24 1e24 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e1f seq_br_type 0 Branch False seq_branch_adr 1e1f 0x1e1f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT val_rand 1 INC_LOOP_COUNTER 1e25 1e25 val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e26 1e26 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e2a seq_br_type 1 Branch True seq_branch_adr 1e2a 0x1e2a seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1e27 1e27 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1e1d seq_br_type 0 Branch False seq_branch_adr 1e1d 0x1e1d seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2a VR13:0a val_frame 13 1e28 1e28 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 19 1e29 1e29 seq_br_type 3 Unconditional Branch; Flow J 0x1e1d seq_branch_adr 1e1d 0x1e1d val_a_adr 0a GP0a val_alu_func 1c DEC_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU 1e2a 1e2a fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR19:11 val_alu_func 10 NOT_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1e2b 1e2b val_a_adr 2f VR14:0f val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 1e2c 1e2c val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1e2d 1e2d seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 2a TR14:0a typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 14 val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1e2e 1e2e seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e2f 1e2f ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 14 1e30 1e30 seq_br_type 1 Branch True; Flow J cc=True 0x1e33 seq_branch_adr 1e33 0x1e33 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0a GP0a 1e31 1e31 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2199 seq_br_type 5 Call True seq_branch_adr 2199 0x2199 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1e32 1e32 seq_br_type 3 Unconditional Branch; Flow J 0x1e34 seq_branch_adr 1e34 0x1e34 1e33 1e33 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2199 seq_br_type 5 Call True seq_branch_adr 2199 0x2199 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 14 1e34 1e34 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e2f seq_br_type 0 Branch False seq_branch_adr 1e2f 0x1e2f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT val_rand 1 INC_LOOP_COUNTER 1e35 1e35 val_a_adr 03 GP03 val_alu_func 4 LEFT_I_A_INC val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e36 1e36 seq_br_type 0 Branch False; Flow J cc=False 0x1e3b seq_branch_adr 1e3b 0x1e3b seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1e37 1e37 val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 2f VR14:0f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 1e38 1e38 seq_br_type 1 Branch True; Flow J cc=True 0x1e2d seq_branch_adr 1e2d 0x1e2d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 2f VR14:0f val_frame 14 1e39 1e39 val_a_adr 2f VR14:0f val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 1e3a 1e3a seq_br_type 3 Unconditional Branch; Flow J 0x1e2d seq_branch_adr 1e2d 0x1e2d val_a_adr 0a GP0a val_alu_func 1c DEC_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU 1e3b 1e3b seq_br_type 3 Unconditional Branch; Flow J 0x1e3c seq_branch_adr 1e3c 0x1e3c 1e3c 1e3c typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e3d 1e3d seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_b_adr 32 VR19:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1e3e 1e3e seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 03 GP03 val_b_adr 03 GP03 1e3f 1e3f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 03 GP03 val_b_adr 03 GP03 1e40 1e40 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e41 1e41 seq_br_type 5 Call True; Flow C cc=True 0x21a4 seq_branch_adr 21a4 0x21a4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 10 NOT_A 1e42 1e42 ioc_tvbs 5 seq+seq; Flow J cc=True 0x1e40 seq_br_type 1 Branch True seq_branch_adr 1e40 0x1e40 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 1e43 1e43 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 2d TR14:0d typ_frame 14 val_b_adr 28 VR13:08 val_frame 13 1e44 1e44 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e45 1e45 seq_br_type 5 Call True; Flow C cc=True 0x21a5 seq_branch_adr 21a5 0x21a5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 10 NOT_A val_alu_func 1a PASS_B val_b_adr 03 GP03 1e46 1e46 ioc_tvbs 5 seq+seq; Flow J cc=True 0x1e44 seq_br_type 1 Branch True seq_branch_adr 1e44 0x1e44 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 4 SAVE OFFSET seq_random 15 ? val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 1e47 1e47 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 22 TR18:02 typ_frame 18 val_b_adr 32 VR19:12 val_frame 19 1e48 1e48 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e49 1e49 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e4a 1e4a seq_int_reads 0 TYP VAL BUS seq_random 63 Load_ibuff+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e4b 1e4b ioc_tvbs 5 seq+seq; Flow C cc=True 0x21aa seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21aa 0x21aa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 14 1e4c 1e4c seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 1e4d 1e4d seq_int_reads 0 TYP VAL BUS seq_random 63 Load_ibuff+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e4e 1e4e ioc_tvbs 5 seq+seq; Flow C cc=True 0x21ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21ab 0x21ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION val_a_adr 2f VR14:0f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 14 1e4f 1e4f seq_br_type 3 Unconditional Branch; Flow J 0x1e53 seq_branch_adr 1e53 0x1e53 1e50 ; -------------------------------------------------------------------------------------- 1e50 ; 0x0fc0-0x0fff Execute_Immediate Equal,uimmediate 1e50 ; -------------------------------------------------------------------------------------- 1e50 MACRO_Execute_Immediate_Equal,uimmediate: 1e50 1e50 dispatch_brk_class 0 ; Flow J 0x1e45 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 1e50 seq_br_type 3 Unconditional Branch seq_branch_adr 1e45 0x1e45 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e51 1e51 <halt> ; Flow R 1e52 ; -------------------------------------------------------------------------------------- 1e52 ; 0x0000 Action Illegal,>R 1e52 ; 0x0001 Illegal - 1e52 ; -------------------------------------------------------------------------------------- 1e52 MACRO_Action_Illegal,>R: 1e52 MACRO_Illegal_-: 1e52 1e52 dispatch_brk_class 0 ; Flow J 0x1e41 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 1e52 seq_br_type 3 Unconditional Branch seq_branch_adr 1e41 0x1e41 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e53 1e53 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e54 1e54 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1e55 1e55 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 2f VR19:0f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 1e56 1e56 seq_br_type 7 Unconditional Call; Flow C 0x1e61 seq_branch_adr 1e61 0x1e61 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1e57 1e57 seq_b_timing 0 Early Condition; Flow C cc=False 0x21a7 seq_br_type 4 Call False seq_branch_adr 21a7 0x21a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1e58 1e58 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1e59 1e59 typ_a_adr 33 TR14:13 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 14 val_a_adr 3e VR14:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1e5a 1e5a seq_br_type 7 Unconditional Call; Flow C 0x1e61 seq_branch_adr 1e61 0x1e61 val_a_adr 27 VR13:07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 1e5b 1e5b seq_b_timing 0 Early Condition; Flow C cc=False 0x21a7 seq_br_type 4 Call False seq_branch_adr 21a7 0x21a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1e5c 1e5c typ_alu_func 13 ONES typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1e5d 1e5d typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 1e5e 1e5e seq_br_type 7 Unconditional Call; Flow C 0x1e61 seq_branch_adr 1e61 0x1e61 val_a_adr 26 VR13:06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 1e5f 1e5f seq_b_timing 0 Early Condition; Flow C cc=False 0x21a7 seq_br_type 4 Call False seq_branch_adr 21a7 0x21a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1e60 1e60 seq_br_type 3 Unconditional Branch; Flow J 0x1e6a seq_branch_adr 1e6a 0x1e6a 1e61 ; -------------------------------------------------------------------------------------- 1e61 ; Comes from: 1e61 ; 1e56 C from color 0x08e7 1e61 ; 1e5a C from color 0x08e7 1e61 ; 1e5e C from color 0x08e7 1e61 ; -------------------------------------------------------------------------------------- 1e61 1e61 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 1e62 1e62 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 3e TR13:1e typ_frame 13 val_b_adr 25 VR13:05 val_frame 13 1e63 1e63 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1e64 ; -------------------------------------------------------------------------------------- 1e64 ; 0x0350 Declare_Type Array,Defined,Bounds_With_Object 1e64 ; -------------------------------------------------------------------------------------- 1e64 MACRO_Declare_Type_Array,Defined,Bounds_With_Object: 1e64 1e64 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1e64 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL typ_rand d SET_PASS_PRIVACY_BIT val_rand 2 DEC_LOOP_COUNTER 1e65 1e65 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? 1e66 ; -------------------------------------------------------------------------------------- 1e66 ; 0x0351 Declare_Type Array,Defined,Visible,Bounds_With_Object 1e66 ; -------------------------------------------------------------------------------------- 1e66 MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object: 1e66 1e66 dispatch_brk_class 0 ; Flow C cc=False 0x21a8 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1e66 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 21a8 0x21a8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 13 ONES typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT 1e67 1e67 fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow R fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1e68 ; -------------------------------------------------------------------------------------- 1e68 ; 0x0352 Illegal - 1e68 ; -------------------------------------------------------------------------------------- 1e68 MACRO_Illegal_-: 1e68 1e68 dispatch_brk_class 0 ; Flow C cc=True 0x21a7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1e68 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21a7 0x21a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1e69 1e69 seq_br_type a Unconditional Return; Flow R 1e6a 1e6a val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e6b 1e6b typ_alu_func 1a PASS_B typ_b_adr 2b TR14:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1e6c 1e6c seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 7 INC_A val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1e6d 1e6d seq_int_reads 0 TYP VAL BUS seq_random 3e ? typ_a_adr 2e TR14:0e typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 val_b_adr 30 VR14:10 val_frame 14 1e6e 1e6e seq_br_type 1 Branch True; Flow J cc=True 0x1e6c seq_branch_adr 1e6c 0x1e6c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR13:02 val_frame 13 1e6f 1e6f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 2f TR14:0f typ_frame 14 val_b_adr 24 VR13:04 val_frame 13 1e70 1e70 typ_a_adr 2a TR14:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 1e71 1e71 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1e72 ; -------------------------------------------------------------------------------------- 1e72 ; 0xe000-0xfe3f Load llvl,ldelta 1e72 ; -------------------------------------------------------------------------------------- 1e72 MACRO_Load_llvl,ldelta: 1e72 1e72 dispatch_brk_class 0 ; Flow J cc=True 0x1e74 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1e72 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1e74 0x1e74 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1e73 1e73 seq_br_type 3 Unconditional Branch; Flow J 0x1e71 seq_branch_adr 1e71 0x1e71 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1e74 1e74 seq_br_type 3 Unconditional Branch; Flow J 0x1e75 seq_branch_adr 1e75 0x1e75 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1e75 1e75 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21ac seq_br_type 5 Call True seq_branch_adr 21ac 0x21ac seq_cond_sel 44 SEQ.TOS_LATCH_valid seq_int_reads 0 TYP VAL BUS seq_random 60 Validate_tos_optimizer+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e76 1e76 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21ad seq_br_type 5 Call True seq_branch_adr 21ad 0x21ad seq_cond_sel 44 SEQ.TOS_LATCH_valid 1e77 1e77 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 2c TR14:0c typ_frame 14 val_b_adr 23 VR13:03 val_frame 13 1e78 1e78 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1e79 1e79 <halt> ; Flow R 1e7a 1e7a seq_br_type 3 Unconditional Branch; Flow J 0x1e79 seq_branch_adr 1e79 0x1e79 1e7b 1e7b <halt> ; Flow R 1e7c ; -------------------------------------------------------------------------------------- 1e7c ; 0xd000-0xd03f Store llvl,ldelta 1e7c ; -------------------------------------------------------------------------------------- 1e7c MACRO_Store_llvl,ldelta: 1e7c 1e7c dispatch_brk_class 0 ; Flow C cc=False 0x21ae dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1e7c dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 21ae 0x21ae seq_cond_sel 44 SEQ.TOS_LATCH_valid 1e7d 1e7d seq_br_type 3 Unconditional Branch; Flow J 0x1e7f seq_branch_adr 1e7f 0x1e7f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1e7e 1e7e <halt> ; Flow R 1e7f 1e7f val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e80 1e80 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1e81 1e81 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR12:04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 1e82 1e82 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_mar_cntl 4 RESTORE_MAR 1e83 1e83 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl 4 RESTORE_MAR val_alu_func 13 ONES 1e84 1e84 seq_en_micro 0 1e85 1e85 seq_b_timing 1 Latch Condition; Flow C cc=False 0x21af seq_br_type 4 Call False seq_branch_adr 21af 0x21af 1e86 1e86 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e87 1e87 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 22 TR18:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_alu_func 1a PASS_B val_b_adr 30 VR14:10 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 1e88 1e88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b0 seq_br_type 5 Call True seq_branch_adr 21b0 0x21b0 seq_cond_sel 57 SEQ.FIELD_NUM_ERR seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 32 VR19:12 val_frame 19 1e89 1e89 typ_alu_func 1a PASS_B typ_b_adr 29 TR12:09 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 32 VR19:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 19 1e8a 1e8a seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 03 GP03 1e8b 1e8b seq_br_type 3 Unconditional Branch; Flow J 0x1e8c seq_branch_adr 1e8c 0x1e8c 1e8c 1e8c val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1e8d 1e8d seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1e8e 1e8e seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 34 TR12:14 typ_frame 12 val_b_adr 3e VR12:1e val_frame 12 1e8f 1e8f val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 14 1e90 1e90 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1e91 1e91 <halt> ; Flow R 1e92 ; -------------------------------------------------------------------------------------- 1e92 ; 0x0010 Halt InMicrocode 1e92 ; -------------------------------------------------------------------------------------- 1e92 MACRO_Halt_InMicrocode: 1e92 1e92 dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1e92 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1e93 1e93 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1e94 1e94 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 19 1e95 1e95 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1e96 1e96 <halt> ; Flow R 1e97 1e97 <halt> ; Flow R 1e98 ; -------------------------------------------------------------------------------------- 1e98 ; 0x0011 QQUnknown InMicrocode 1e98 ; -------------------------------------------------------------------------------------- 1e98 MACRO_1e98_QQUnknown_InMicrocode: 1e98 1e98 dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1e98 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1e99 1e99 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_frame 19 1e9a 1e9a val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1e9b 1e9b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1e9c 1e9c <halt> ; Flow R 1e9d 1e9d <halt> ; Flow R 1e9e ; -------------------------------------------------------------------------------------- 1e9e ; 0x0012 QQUnknown InMicrocode 1e9e ; -------------------------------------------------------------------------------------- 1e9e MACRO_1e9e_QQUnknown_InMicrocode: 1e9e 1e9e dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e9e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1e9f 1e9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_frame 1a 1ea0 1ea0 val_a_adr 31 VR1a:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1ea1 1ea1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1ea2 1ea2 <halt> ; Flow R 1ea3 1ea3 <halt> ; Flow R 1ea4 ; -------------------------------------------------------------------------------------- 1ea4 ; 0x0013 QQUnknown InMicrocode 1ea4 ; -------------------------------------------------------------------------------------- 1ea4 MACRO_1ea4_QQUnknown_InMicrocode: 1ea4 1ea4 dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1ea4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ea5 1ea5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 31 VR1a:11 val_frame 1a 1ea6 1ea6 val_a_adr 3e VR14:1e val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 14 1ea7 1ea7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1ea8 1ea8 <halt> ; Flow R 1ea9 1ea9 <halt> ; Flow R 1eaa ; -------------------------------------------------------------------------------------- 1eaa ; 0x0014 QQUnknown InMicrocode 1eaa ; -------------------------------------------------------------------------------------- 1eaa MACRO_1eaa_QQUnknown_InMicrocode: 1eaa 1eaa dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1eaa seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1eab 1eab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 3e VR14:1e val_frame 14 1eac 1eac val_a_adr 34 VR14:14 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 14 1ead 1ead fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1eae 1eae <halt> ; Flow R 1eaf 1eaf <halt> ; Flow R 1eb0 ; -------------------------------------------------------------------------------------- 1eb0 ; 0x0015 QQUnknown InMicrocode 1eb0 ; -------------------------------------------------------------------------------------- 1eb0 MACRO_1eb0_QQUnknown_InMicrocode: 1eb0 1eb0 dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1eb0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1eb1 1eb1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 34 VR14:14 val_frame 14 1eb2 1eb2 val_a_adr 2f VR19:0f val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 19 1eb3 1eb3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1eb4 1eb4 <halt> ; Flow R 1eb5 1eb5 <halt> ; Flow R 1eb6 ; -------------------------------------------------------------------------------------- 1eb6 ; 0x0016 QQUnknown InMicrocode 1eb6 ; -------------------------------------------------------------------------------------- 1eb6 MACRO_1eb6_QQUnknown_InMicrocode: 1eb6 1eb6 dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1eb6 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1eb7 1eb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 2f VR19:0f val_frame 19 1eb8 1eb8 val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1eb9 1eb9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 14 1eba 1eba <halt> ; Flow R 1ebb 1ebb <halt> ; Flow R 1ebc ; -------------------------------------------------------------------------------------- 1ebc ; 0x0017 QQUnknown InMicrocode 1ebc ; -------------------------------------------------------------------------------------- 1ebc MACRO_1ebc_QQUnknown_InMicrocode: 1ebc 1ebc dispatch_brk_class 0 ; Flow C cc=True 0x21b1 dispatch_csa_valid 7 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 1ebc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ebd 1ebd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b1 seq_br_type 5 Call True seq_branch_adr 21b1 0x21b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 2d VR1a:0d val_frame 1a 1ebe 1ebe seq_br_type 3 Unconditional Branch; Flow J 0x1ebf seq_branch_adr 1ebf 0x1ebf typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1ebf 1ebf typ_csa_cntl 2 PUSH_CSA val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1ec0 1ec0 typ_csa_cntl 2 PUSH_CSA 1ec1 1ec1 typ_csa_cntl 2 PUSH_CSA 1ec2 1ec2 typ_csa_cntl 2 PUSH_CSA 1ec3 1ec3 typ_csa_cntl 2 PUSH_CSA 1ec4 1ec4 typ_csa_cntl 2 PUSH_CSA 1ec5 1ec5 typ_csa_cntl 2 PUSH_CSA 1ec6 1ec6 typ_csa_cntl 2 PUSH_CSA 1ec7 1ec7 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1ec8 1ec8 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR12:12 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1ec9 1ec9 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 14 1eca 1eca fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1ecb 1ecb <halt> ; Flow R 1ecc ; -------------------------------------------------------------------------------------- 1ecc ; 0x0020 Illegal - 1ecc ; -------------------------------------------------------------------------------------- 1ecc MACRO_Illegal_-: 1ecc 1ecc dispatch_brk_class 0 ; Flow C cc=True 0x21b2 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1ecc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ecd 1ecd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b2 seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ece 1ece val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 19 1ecf 1ecf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1ed0 1ed0 <halt> ; Flow R 1ed1 1ed1 <halt> ; Flow R 1ed2 ; -------------------------------------------------------------------------------------- 1ed2 ; 0x0021 Illegal - 1ed2 ; -------------------------------------------------------------------------------------- 1ed2 MACRO_Illegal_-: 1ed2 1ed2 dispatch_brk_class 0 ; Flow C cc=True 0x21b2 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1ed2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ed3 1ed3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b2 seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_frame 19 1ed4 1ed4 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1ed5 1ed5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1ed6 1ed6 <halt> ; Flow R 1ed7 1ed7 <halt> ; Flow R 1ed8 ; -------------------------------------------------------------------------------------- 1ed8 ; 0x0022 Illegal - 1ed8 ; -------------------------------------------------------------------------------------- 1ed8 MACRO_Illegal_-: 1ed8 1ed8 dispatch_brk_class 0 ; Flow C cc=True 0x21b2 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1ed8 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ed9 1ed9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b2 seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_frame 1a 1eda 1eda val_a_adr 31 VR1a:11 val_alu_func 0 PASS_A val_c_adr 35 GP0a val_c_mux_sel 2 ALU val_frame 1a 1edb 1edb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 1edc 1edc <halt> ; Flow R 1edd 1edd <halt> ; Flow R 1ede ; -------------------------------------------------------------------------------------- 1ede ; 0x0023 Illegal - 1ede ; -------------------------------------------------------------------------------------- 1ede MACRO_Illegal_-: 1ede 1ede dispatch_brk_class 0 ; Flow C cc=True 0x21b2 dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 1ede seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1edf 1edf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x21b2 seq_br_type 5 Call True seq_branch_adr 21b2 0x21b2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0a GP0a val_alu_func 19 X_XOR_B val_b_adr 31 VR1a:11 val_frame 1a 1ee0 1ee0 seq_br_type 3 Unconditional Branch; Flow J 0x1ee1 seq_branch_adr 1ee1 0x1ee1 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1ee1 1ee1 seq_random 0a ? val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1ee2 1ee2 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1ee3 1ee3 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 31 TR12:11 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1ee4 1ee4 typ_a_adr 2b TR14:0b typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 14 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1ee5 1ee5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 14 1ee6 1ee6 <halt> ; Flow R 1ee7 1ee7 <halt> ; Flow R 1ee8 ; -------------------------------------------------------------------------------------- 1ee8 ; 0x8000-0x803f Call llvl,ldelta 1ee8 ; -------------------------------------------------------------------------------------- 1ee8 MACRO_Call_llvl,ldelta: 1ee8 1ee8 dispatch_brk_class 0 ; Flow C cc=True 0x21b3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ee8 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b3 0x21b3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ee9 1ee9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 14 1eea 1eea fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 14 1eeb 1eeb <halt> ; Flow R 1eec ; -------------------------------------------------------------------------------------- 1eec ; 0x8200-0x823f Call llvl,ldelta 1eec ; -------------------------------------------------------------------------------------- 1eec MACRO_Call_llvl,ldelta: 1eec 1eec dispatch_brk_class 0 ; Flow C cc=True 0x21b3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1eec seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b3 0x21b3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1eed 1eed seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 7 INC_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1eee 1eee fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 14 1eef 1eef <halt> ; Flow R 1ef0 ; -------------------------------------------------------------------------------------- 1ef0 ; 0x8400-0x843f Call llvl,ldelta 1ef0 ; -------------------------------------------------------------------------------------- 1ef0 MACRO_Call_llvl,ldelta: 1ef0 1ef0 dispatch_brk_class 0 ; Flow C cc=True 0x21b3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ef0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b3 0x21b3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ef1 1ef1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 7 INC_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1ef2 1ef2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 14 1ef3 1ef3 <halt> ; Flow R 1ef4 ; -------------------------------------------------------------------------------------- 1ef4 ; 0x8600-0x863f Call llvl,ldelta 1ef4 ; -------------------------------------------------------------------------------------- 1ef4 MACRO_Call_llvl,ldelta: 1ef4 1ef4 dispatch_brk_class 0 ; Flow C cc=True 0x21b3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ef4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b3 0x21b3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1ef5 1ef5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1ef6 1ef6 seq_br_type 3 Unconditional Branch; Flow J 0x1ef7 seq_branch_adr 1ef7 0x1ef7 1ef7 1ef7 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 1ef8 1ef8 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1ef9 1ef9 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 30 TR12:10 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1efa 1efa seq_int_reads 0 TYP VAL BUS typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1efb 1efb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 14 1efc 1efc <halt> ; Flow R 1efd 1efd <halt> ; Flow R 1efe ; -------------------------------------------------------------------------------------- 1efe ; 0xa000-0xa03f Reference zdelta 1efe ; -------------------------------------------------------------------------------------- 1efe MACRO_Reference_zdelta: 1efe 1efe dispatch_brk_class 0 ; Flow C cc=True 0x21b5 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1efe dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b5 0x21b5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1eff 1eff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 14 1f00 1f00 <halt> ; Flow R 1f01 1f01 <halt> ; Flow R 1f02 ; -------------------------------------------------------------------------------------- 1f02 ; 0xa200-0xa23f Store_Unchecked llvl,ldelta 1f02 ; -------------------------------------------------------------------------------------- 1f02 MACRO_Store_Unchecked_llvl,ldelta: 1f02 1f02 dispatch_brk_class 0 ; Flow C cc=True 0x21b5 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1f02 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b5 0x21b5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1f03 1f03 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 1f04 1f04 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 14 1f05 1f05 <halt> ; Flow R 1f06 ; -------------------------------------------------------------------------------------- 1f06 ; 0xa400-0xa43f Store_Unchecked llvl,ldelta 1f06 ; -------------------------------------------------------------------------------------- 1f06 MACRO_Store_Unchecked_llvl,ldelta: 1f06 1f06 dispatch_brk_class 0 ; Flow C cc=True 0x21b5 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1f06 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b5 0x21b5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1f07 1f07 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 14 1f08 1f08 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 29 TR12:09 typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 30 VR14:10 val_frame 14 1f09 1f09 <halt> ; Flow R 1f0a ; -------------------------------------------------------------------------------------- 1f0a ; 0xa600-0xa63f Store_Unchecked llvl,ldelta 1f0a ; -------------------------------------------------------------------------------------- 1f0a MACRO_Store_Unchecked_llvl,ldelta: 1f0a 1f0a dispatch_brk_class 0 ; Flow C cc=True 0x21b5 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1f0a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 21b5 0x21b5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 30 VR14:10 val_frame 14 1f0b 1f0b seq_br_type 3 Unconditional Branch; Flow J 0x2000 seq_branch_adr 2000 0x2000 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 14 1f0c 1f0c <halt> ; Flow R 1f0d 1f0d <halt> ; Flow R 1f0e 1f0e <halt> ; Flow R 1f0f 1f0f <halt> ; Flow R 1f10 1f10 <halt> ; Flow R 1f11 1f11 <halt> ; Flow R 1f12 1f12 <halt> ; Flow R 1f13 1f13 <halt> ; Flow R 1f14 1f14 <halt> ; Flow R 1f15 1f15 <halt> ; Flow R 1f16 1f16 <halt> ; Flow R 1f17 1f17 <halt> ; Flow R 1f18 1f18 <halt> ; Flow R 1f19 1f19 <halt> ; Flow R 1f1a 1f1a <halt> ; Flow R 1f1b 1f1b <halt> ; Flow R 1f1c 1f1c <halt> ; Flow R 1f1d 1f1d <halt> ; Flow R 1f1e 1f1e <halt> ; Flow R 1f1f 1f1f <halt> ; Flow R 1f20 1f20 <halt> ; Flow R 1f21 1f21 <halt> ; Flow R 1f22 1f22 <halt> ; Flow R 1f23 1f23 <halt> ; Flow R 1f24 1f24 <halt> ; Flow R 1f25 1f25 <halt> ; Flow R 1f26 1f26 <halt> ; Flow R 1f27 1f27 <halt> ; Flow R 1f28 1f28 <halt> ; Flow R 1f29 1f29 <halt> ; Flow R 1f2a 1f2a <halt> ; Flow R 1f2b 1f2b <halt> ; Flow R 1f2c 1f2c <halt> ; Flow R 1f2d 1f2d <halt> ; Flow R 1f2e 1f2e <halt> ; Flow R 1f2f 1f2f <halt> ; Flow R 1f30 1f30 <halt> ; Flow R 1f31 1f31 <halt> ; Flow R 1f32 1f32 <halt> ; Flow R 1f33 1f33 <halt> ; Flow R 1f34 1f34 <halt> ; Flow R 1f35 1f35 <halt> ; Flow R 1f36 1f36 <halt> ; Flow R 1f37 1f37 <halt> ; Flow R 1f38 1f38 <halt> ; Flow R 1f39 1f39 <halt> ; Flow R 1f3a 1f3a <halt> ; Flow R 1f3b 1f3b <halt> ; Flow R 1f3c 1f3c <halt> ; Flow R 1f3d 1f3d <halt> ; Flow R 1f3e 1f3e <halt> ; Flow R 1f3f 1f3f <halt> ; Flow R 1f40 1f40 <halt> ; Flow R 1f41 1f41 <halt> ; Flow R 1f42 1f42 <halt> ; Flow R 1f43 1f43 <halt> ; Flow R 1f44 1f44 <halt> ; Flow R 1f45 1f45 <halt> ; Flow R 1f46 1f46 <halt> ; Flow R 1f47 1f47 <halt> ; Flow R 1f48 1f48 <halt> ; Flow R 1f49 1f49 <halt> ; Flow R 1f4a 1f4a <halt> ; Flow R 1f4b 1f4b <halt> ; Flow R 1f4c 1f4c <halt> ; Flow R 1f4d 1f4d <halt> ; Flow R 1f4e 1f4e <halt> ; Flow R 1f4f 1f4f <halt> ; Flow R 1f50 1f50 <halt> ; Flow R 1f51 1f51 <halt> ; Flow R 1f52 1f52 <halt> ; Flow R 1f53 1f53 <halt> ; Flow R 1f54 1f54 <halt> ; Flow R 1f55 1f55 <halt> ; Flow R 1f56 1f56 <halt> ; Flow R 1f57 1f57 <halt> ; Flow R 1f58 1f58 <halt> ; Flow R 1f59 1f59 <halt> ; Flow R 1f5a 1f5a <halt> ; Flow R 1f5b 1f5b <halt> ; Flow R 1f5c 1f5c <halt> ; Flow R 1f5d 1f5d <halt> ; Flow R 1f5e 1f5e <halt> ; Flow R 1f5f 1f5f <halt> ; Flow R 1f60 1f60 <halt> ; Flow R 1f61 1f61 <halt> ; Flow R 1f62 1f62 <halt> ; Flow R 1f63 1f63 <halt> ; Flow R 1f64 1f64 <halt> ; Flow R 1f65 1f65 <halt> ; Flow R 1f66 1f66 <halt> ; Flow R 1f67 1f67 <halt> ; Flow R 1f68 1f68 <halt> ; Flow R 1f69 1f69 <halt> ; Flow R 1f6a 1f6a <halt> ; Flow R 1f6b 1f6b <halt> ; Flow R 1f6c 1f6c <halt> ; Flow R 1f6d 1f6d <halt> ; Flow R 1f6e 1f6e <halt> ; Flow R 1f6f 1f6f <halt> ; Flow R 1f70 1f70 <halt> ; Flow R 1f71 1f71 <halt> ; Flow R 1f72 1f72 <halt> ; Flow R 1f73 1f73 <halt> ; Flow R 1f74 1f74 <halt> ; Flow R 1f75 1f75 <halt> ; Flow R 1f76 1f76 <halt> ; Flow R 1f77 1f77 <halt> ; Flow R 1f78 1f78 <halt> ; Flow R 1f79 1f79 <halt> ; Flow R 1f7a 1f7a <halt> ; Flow R 1f7b 1f7b <halt> ; Flow R 1f7c 1f7c <halt> ; Flow R 1f7d 1f7d <halt> ; Flow R 1f7e 1f7e <halt> ; Flow R 1f7f 1f7f <halt> ; Flow R 1f80 1f80 <halt> ; Flow R 1f81 1f81 <halt> ; Flow R 1f82 1f82 <halt> ; Flow R 1f83 1f83 <halt> ; Flow R 1f84 1f84 <halt> ; Flow R 1f85 1f85 <halt> ; Flow R 1f86 1f86 <halt> ; Flow R 1f87 1f87 <halt> ; Flow R 1f88 1f88 <halt> ; Flow R 1f89 1f89 <halt> ; Flow R 1f8a 1f8a <halt> ; Flow R 1f8b 1f8b <halt> ; Flow R 1f8c 1f8c <halt> ; Flow R 1f8d 1f8d <halt> ; Flow R 1f8e 1f8e <halt> ; Flow R 1f8f 1f8f <halt> ; Flow R 1f90 1f90 <halt> ; Flow R 1f91 1f91 <halt> ; Flow R 1f92 1f92 <halt> ; Flow R 1f93 1f93 <halt> ; Flow R 1f94 1f94 <halt> ; Flow R 1f95 1f95 <halt> ; Flow R 1f96 1f96 <halt> ; Flow R 1f97 1f97 <halt> ; Flow R 1f98 1f98 <halt> ; Flow R 1f99 1f99 <halt> ; Flow R 1f9a 1f9a <halt> ; Flow R 1f9b 1f9b <halt> ; Flow R 1f9c 1f9c <halt> ; Flow R 1f9d 1f9d <halt> ; Flow R 1f9e 1f9e <halt> ; Flow R 1f9f 1f9f <halt> ; Flow R 1fa0 1fa0 <halt> ; Flow R 1fa1 1fa1 <halt> ; Flow R 1fa2 1fa2 <halt> ; Flow R 1fa3 1fa3 <halt> ; Flow R 1fa4 1fa4 <halt> ; Flow R 1fa5 1fa5 <halt> ; Flow R 1fa6 1fa6 <halt> ; Flow R 1fa7 1fa7 <halt> ; Flow R 1fa8 1fa8 <halt> ; Flow R 1fa9 1fa9 <halt> ; Flow R 1faa 1faa <halt> ; Flow R 1fab 1fab <halt> ; Flow R 1fac 1fac <halt> ; Flow R 1fad 1fad <halt> ; Flow R 1fae 1fae <halt> ; Flow R 1faf 1faf <halt> ; Flow R 1fb0 1fb0 <halt> ; Flow R 1fb1 1fb1 <halt> ; Flow R 1fb2 1fb2 <halt> ; Flow R 1fb3 1fb3 <halt> ; Flow R 1fb4 1fb4 <halt> ; Flow R 1fb5 1fb5 <halt> ; Flow R 1fb6 1fb6 <halt> ; Flow R 1fb7 1fb7 <halt> ; Flow R 1fb8 1fb8 <halt> ; Flow R 1fb9 1fb9 <halt> ; Flow R 1fba 1fba <halt> ; Flow R 1fbb 1fbb <halt> ; Flow R 1fbc 1fbc <halt> ; Flow R 1fbd 1fbd <halt> ; Flow R 1fbe 1fbe <halt> ; Flow R 1fbf 1fbf <halt> ; Flow R 1fc0 1fc0 <halt> ; Flow R 1fc1 1fc1 <halt> ; Flow R 1fc2 1fc2 <halt> ; Flow R 1fc3 1fc3 <halt> ; Flow R 1fc4 1fc4 <halt> ; Flow R 1fc5 1fc5 <halt> ; Flow R 1fc6 1fc6 <halt> ; Flow R 1fc7 1fc7 <halt> ; Flow R 1fc8 1fc8 <halt> ; Flow R 1fc9 1fc9 <halt> ; Flow R 1fca 1fca <halt> ; Flow R 1fcb 1fcb <halt> ; Flow R 1fcc 1fcc <halt> ; Flow R 1fcd 1fcd <halt> ; Flow R 1fce 1fce <halt> ; Flow R 1fcf 1fcf <halt> ; Flow R 1fd0 1fd0 <halt> ; Flow R 1fd1 1fd1 <halt> ; Flow R 1fd2 1fd2 <halt> ; Flow R 1fd3 1fd3 <halt> ; Flow R 1fd4 1fd4 <halt> ; Flow R 1fd5 1fd5 <halt> ; Flow R 1fd6 1fd6 <halt> ; Flow R 1fd7 1fd7 <halt> ; Flow R 1fd8 1fd8 <halt> ; Flow R 1fd9 1fd9 <halt> ; Flow R 1fda 1fda <halt> ; Flow R 1fdb 1fdb <halt> ; Flow R 1fdc 1fdc <halt> ; Flow R 1fdd 1fdd <halt> ; Flow R 1fde 1fde <halt> ; Flow R 1fdf 1fdf <halt> ; Flow R 1fe0 1fe0 <halt> ; Flow R 1fe1 1fe1 <halt> ; Flow R 1fe2 1fe2 <halt> ; Flow R 1fe3 1fe3 <halt> ; Flow R 1fe4 1fe4 <halt> ; Flow R 1fe5 1fe5 <halt> ; Flow R 1fe6 1fe6 <halt> ; Flow R 1fe7 1fe7 <halt> ; Flow R 1fe8 1fe8 <halt> ; Flow R 1fe9 1fe9 <halt> ; Flow R 1fea 1fea <halt> ; Flow R 1feb 1feb <halt> ; Flow R 1fec 1fec <halt> ; Flow R 1fed 1fed <halt> ; Flow R 1fee 1fee <halt> ; Flow R 1fef 1fef <halt> ; Flow R 1ff0 1ff0 <halt> ; Flow R 1ff1 1ff1 <halt> ; Flow R 1ff2 1ff2 <halt> ; Flow R 1ff3 1ff3 <halt> ; Flow R 1ff4 1ff4 <halt> ; Flow R 1ff5 1ff5 <halt> ; Flow R 1ff6 1ff6 <halt> ; Flow R 1ff7 1ff7 <halt> ; Flow R 1ff8 1ff8 <halt> ; Flow R 1ff9 1ff9 <halt> ; Flow R 1ffa 1ffa <halt> ; Flow R 1ffb 1ffb <halt> ; Flow R 1ffc 1ffc <halt> ; Flow R 1ffd 1ffd <halt> ; Flow R 1ffe 1ffe <halt> ; Flow R 1fff 1fff <halt> ; Flow R 2000 2000 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 2001 2001 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_alu_func 1a PASS_B typ_b_adr 29 TR12:09 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 2002 2002 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 30 TR14:10 typ_frame 14 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_b_adr 21 VR13:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2003 2003 seq_b_timing 0 Early Condition; Flow J cc=True 0x2007 seq_br_type 1 Branch True seq_branch_adr 2007 0x2007 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 16 ? val_rand 2 DEC_LOOP_COUNTER 2004 2004 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2005 0x2005 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 28 TR14:08 typ_alu_func 0 PASS_A typ_frame 14 typ_mar_cntl e LOAD_MAR_CONTROL 2005 2005 seq_br_type 3 Unconditional Branch; Flow J 0x2003 seq_branch_adr 2003 0x2003 2006 ; -------------------------------------------------------------------------------------- 2006 ; 0x4000-0x403f Illegal - 2006 ; -------------------------------------------------------------------------------------- 2006 MACRO_Illegal_-: 2006 2006 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_uadr 2006 ioc_random 14 clear cpu running seq_en_micro 0 seq_random 01 Halt+? 2007 2007 ioc_fiubs 2 typ typ_a_adr 21 TR18:01 typ_frame 18 2008 2008 ioc_fiubs 2 typ ; Flow J cc=True 0x2009 ; Flow J cc=#0x0 0x200a seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 200a 0x200a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_frame 18 2009 2009 ioc_fiubs 2 typ ; Flow J 0x200c seq_br_type 3 Unconditional Branch seq_branch_adr 200c 0x200c typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_frame 18 200a 200a <halt> ; Flow R 200b 200b <halt> ; Flow R 200c 200c ioc_fiubs 2 typ ; Flow J cc=True 0x200d ; Flow J cc=#0x0 0x200e seq_br_type b Case False seq_branch_adr 200e 0x200e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_frame 18 200d 200d <halt> ; Flow R 200e 200e <halt> ; Flow R 200f 200f seq_br_type 3 Unconditional Branch; Flow J 0x2010 seq_branch_adr 2010 0x2010 2010 2010 seq_br_type 3 Unconditional Branch; Flow J 0x2011 seq_branch_adr 2011 0x2011 2011 2011 val_a_adr 20 VR04:00 val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 4 2012 2012 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc val_a_adr 20 VR13:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 13 2013 2013 typ_a_adr 2f TR12:0f typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR1a:1d val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 1a 2014 2014 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 2015 2015 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2016 2016 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2017 2017 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2018 2018 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2019 2019 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 201a 201a seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 201b 201b seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 201c 201c seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 201d 201d typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 201e 201e seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 201f 201f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2020 2020 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2021 2021 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2022 2022 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2023 2023 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2024 2024 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2025 2025 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2026 2026 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2027 2027 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2028 2028 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2029 2029 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 202a 202a seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 202b 202b val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 202c 202c typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 202d 202d seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 202e 202e seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 202f 202f seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2030 2030 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2031 2031 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2032 2032 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2033 2033 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2034 2034 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2035 2035 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2036 2036 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2037 2037 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2038 2038 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2039 2039 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 203a 203a seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 203b 203b typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 203c 203c seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 203d 203d seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 203e 203e seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 203f 203f seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2040 2040 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2041 2041 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2042 2042 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2043 2043 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2044 2044 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2045 2045 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2046 2046 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2047 2047 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2048 2048 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2049 2049 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204a 204a typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 204b 204b seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 204c 204c seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 204d 204d seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 204e 204e seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204f 204f typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2050 2050 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2051 2051 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2052 2052 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2053 2053 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2054 2054 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2055 2055 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2056 2056 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2057 2057 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 2058 2058 seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2059 2059 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 205a 205a seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 205b 205b seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 205c 205c seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 205d 205d seq_br_type 7 Unconditional Call; Flow C 0x20ab seq_branch_adr 20ab 0x20ab val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 205e 205e val_a_adr 28 VR14:08 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 205f 205f typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2060 2060 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 2061 2061 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2062 2062 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2063 2063 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2064 2064 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2065 2065 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2066 2066 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2067 2067 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2068 2068 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2069 2069 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 206a 206a seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 206b 206b seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 206c 206c seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 206d 206d seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 206e 206e typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 206f 206f seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2070 2070 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2071 2071 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2072 2072 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2073 2073 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2074 2074 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2075 2075 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2076 2076 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2077 2077 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2078 2078 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2079 2079 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 207a 207a seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 207b 207b seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 207c 207c val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 207d 207d typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 207e 207e seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 207f 207f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2080 2080 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2081 2081 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2082 2082 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2083 2083 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2084 2084 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2085 2085 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2086 2086 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2087 2087 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2088 2088 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2089 2089 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 208a 208a seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 208b 208b seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 208c 208c typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 208d 208d seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 208e 208e seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 208f 208f seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2090 2090 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2091 2091 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2092 2092 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2093 2093 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2094 2094 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 2095 2095 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2096 2096 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 2097 2097 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2098 2098 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2099 2099 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 209a 209a seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 209b 209b typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 209c 209c seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 209d 209d seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 209e 209e seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 209f 209f seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20a0 20a0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 20a1 20a1 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 20a2 20a2 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 20a3 20a3 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 20a4 20a4 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20a5 20a5 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR12:0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3c VR14:1c val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 14 20a6 20a6 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_a_adr 04 GP04 val_alu_func 3 LEFT_I_A val_b_adr 30 VR14:10 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 20a7 20a7 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 13 ONES typ_b_adr 0e GP0e typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 2a VR1a:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 20a8 20a8 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? val_b_adr 30 VR14:10 val_frame 14 20a9 20a9 seq_br_type 7 Unconditional Call; Flow C 0x20bc seq_branch_adr 20bc 0x20bc val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20aa 20aa seq_br_type a Unconditional Return; Flow R 20ab ; -------------------------------------------------------------------------------------- 20ab ; Comes from: 20ab ; 2017 C from color 0x200f 20ab ; 201c C from color 0x200f 20ab ; 2021 C from color 0x200f 20ab ; 203a C from color 0x200f 20ab ; 203f C from color 0x200f 20ab ; 2044 C from color 0x200f 20ab ; 2049 C from color 0x200f 20ab ; 204e C from color 0x200f 20ab ; 2053 C from color 0x200f 20ab ; 2058 C from color 0x200f 20ab ; 205d C from color 0x200f 20ab ; -------------------------------------------------------------------------------------- 20ab 20ab val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 22 VR13:02 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 13 20ac 20ac seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20ad 20ad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20ae 20ae seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 3c VR14:1c val_frame 14 20af 20af seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? typ_alu_func 13 ONES typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_b_adr 03 GP03 20b0 20b0 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 19 20b1 20b1 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20b2 20b2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20b3 20b3 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 19 20b4 20b4 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20b5 20b5 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 4 LEFT_I_A_INC val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20b6 20b6 seq_br_type 1 Branch True; Flow J cc=True 0x20b8 seq_branch_adr 20b8 0x20b8 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3f VR12:1f val_frame 12 20b7 20b7 val_a_adr 20 VR13:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 20b8 20b8 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 39 VR13:19 val_frame 13 20b9 20b9 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? typ_alu_func 13 ONES typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_b_adr 03 GP03 20ba 20ba fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20bb 20bb seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x20b5 seq_br_type 8 Return True seq_branch_adr 20b5 0x20b5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 20bc ; -------------------------------------------------------------------------------------- 20bc ; Comes from: 20bc ; 2063 C from color 0x200f 20bc ; 2068 C from color 0x200f 20bc ; 206d C from color 0x200f 20bc ; 2086 C from color 0x200f 20bc ; 208b C from color 0x200f 20bc ; 2090 C from color 0x200f 20bc ; 2095 C from color 0x200f 20bc ; 209a C from color 0x200f 20bc ; 209f C from color 0x200f 20bc ; 20a4 C from color 0x200f 20bc ; 20a9 C from color 0x200f 20bc ; -------------------------------------------------------------------------------------- 20bc 20bc val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 22 VR13:02 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 13 20bd 20bd seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20be 20be fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20bf 20bf seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 3c VR14:1c val_frame 14 20c0 20c0 seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_b_adr 03 GP03 20c1 20c1 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 19 20c2 20c2 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20c3 20c3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20c4 20c4 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 31 VR19:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 19 20c5 20c5 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 0e GP0e 20c6 20c6 typ_alu_func 13 ONES typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 3 LEFT_I_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20c7 20c7 seq_br_type 1 Branch True; Flow J cc=True 0x20c9 seq_branch_adr 20c9 0x20c9 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3f VR12:1f val_frame 12 20c8 20c8 val_a_adr 28 VR14:08 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 14 20c9 20c9 seq_int_reads 0 TYP VAL BUS seq_random 5f Load_current_lex+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 39 VR13:19 val_frame 13 20ca 20ca seq_int_reads 0 TYP VAL BUS seq_random 67 Load_break_mask+? typ_alu_func 13 ONES typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_b_adr 03 GP03 20cb 20cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 33 GP0c val_c_mux_sel 2 ALU 20cc 20cc seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x20c6 seq_br_type 8 Return True seq_branch_adr 20c6 0x20c6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 20cd 20cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20ce 20ce seq_br_type 3 Unconditional Branch; Flow J 0x20ae seq_branch_adr 20ae 0x20ae 20cf 20cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20d0 20d0 seq_br_type 3 Unconditional Branch; Flow J 0x20b3 seq_branch_adr 20b3 0x20b3 20d1 20d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20d2 20d2 seq_br_type 3 Unconditional Branch; Flow J 0x20bb seq_branch_adr 20bb 0x20bb 20d3 20d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20d4 20d4 seq_br_type 3 Unconditional Branch; Flow J 0x20bf seq_branch_adr 20bf 0x20bf 20d5 20d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20d6 20d6 seq_br_type 3 Unconditional Branch; Flow J 0x20c4 seq_branch_adr 20c4 0x20c4 20d7 20d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x217d seq_br_type 5 Call True seq_branch_adr 217d 0x217d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 0c GP0c val_alu_func 0 PASS_A 20d8 20d8 seq_br_type 3 Unconditional Branch; Flow J 0x20cc seq_branch_adr 20cc 0x20cc 20d9 20d9 <halt> ; Flow R 20da ; -------------------------------------------------------------------------------------- 20da ; 0x0100 Execute Exception,Raise,>R 20da ; -------------------------------------------------------------------------------------- 20da MACRO_Execute_Exception,Raise,>R: 20da 20da dispatch_brk_class f ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20da seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 20db 20db <halt> ; Flow R 20dc ; -------------------------------------------------------------------------------------- 20dc ; 0x0101 Execute Exception,Reraise,>R 20dc ; -------------------------------------------------------------------------------------- 20dc MACRO_Execute_Exception,Reraise,>R: 20dc 20dc dispatch_brk_class f ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20dc seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 20dd 20dd <halt> ; Flow R 20de ; -------------------------------------------------------------------------------------- 20de ; 0x0102 Illegal - 20de ; -------------------------------------------------------------------------------------- 20de MACRO_Illegal_-: 20de 20de dispatch_brk_class f ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20de seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 20df 20df <halt> ; Flow R 20e0 ; -------------------------------------------------------------------------------------- 20e0 ; 0x01f0 Illegal - 20e0 ; -------------------------------------------------------------------------------------- 20e0 MACRO_Illegal_-: 20e0 20e0 dispatch_brk_class f ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20e0 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 20e1 20e1 <halt> ; Flow R 20e2 ; -------------------------------------------------------------------------------------- 20e2 ; 0x01f1 Illegal - 20e2 ; -------------------------------------------------------------------------------------- 20e2 MACRO_Illegal_-: 20e2 20e2 dispatch_brk_class f ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20e2 seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 20e3 20e3 <halt> ; Flow R 20e4 ; -------------------------------------------------------------------------------------- 20e4 ; 0x01f2 Illegal - 20e4 ; -------------------------------------------------------------------------------------- 20e4 MACRO_Illegal_-: 20e4 20e4 dispatch_brk_class f ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20e4 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 20e5 20e5 <halt> ; Flow R 20e6 ; -------------------------------------------------------------------------------------- 20e6 ; 0x0110 Execute Any,Is_Initialization_Repeated 20e6 ; -------------------------------------------------------------------------------------- 20e6 MACRO_Execute_Any,Is_Initialization_Repeated: 20e6 20e6 dispatch_brk_class b ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20e6 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 20e7 20e7 <halt> ; Flow R 20e8 ; -------------------------------------------------------------------------------------- 20e8 ; 0x0111 Execute Any,Has_Repeated_Initialization 20e8 ; -------------------------------------------------------------------------------------- 20e8 MACRO_Execute_Any,Has_Repeated_Initialization: 20e8 20e8 dispatch_brk_class b ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20e8 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 20e9 20e9 <halt> ; Flow R 20ea ; -------------------------------------------------------------------------------------- 20ea ; 0x0112 Execute Any,Make_Constrained 20ea ; -------------------------------------------------------------------------------------- 20ea MACRO_Execute_Any,Make_Constrained: 20ea 20ea dispatch_brk_class b ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20ea seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 20eb 20eb <halt> ; Flow R 20ec ; -------------------------------------------------------------------------------------- 20ec ; 0x0200 Illegal - 20ec ; -------------------------------------------------------------------------------------- 20ec MACRO_Illegal_-: 20ec 20ec dispatch_brk_class b ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20ec seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 20ed 20ed <halt> ; Flow R 20ee ; -------------------------------------------------------------------------------------- 20ee ; 0x0201 Illegal - 20ee ; -------------------------------------------------------------------------------------- 20ee MACRO_Illegal_-: 20ee 20ee dispatch_brk_class b ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20ee seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 20ef 20ef <halt> ; Flow R 20f0 ; -------------------------------------------------------------------------------------- 20f0 ; 0x0202 Illegal - 20f0 ; -------------------------------------------------------------------------------------- 20f0 MACRO_Illegal_-: 20f0 20f0 dispatch_brk_class b ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20f0 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 20f1 20f1 <halt> ; Flow R 20f2 ; -------------------------------------------------------------------------------------- 20f2 ; 0x0120 Execute Any,Is_Value 20f2 ; -------------------------------------------------------------------------------------- 20f2 MACRO_Execute_Any,Is_Value: 20f2 20f2 dispatch_brk_class d ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20f2 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 20f3 20f3 <halt> ; Flow R 20f4 ; -------------------------------------------------------------------------------------- 20f4 ; 0x0121 Execute Any,Is_Default 20f4 ; -------------------------------------------------------------------------------------- 20f4 MACRO_Execute_Any,Is_Default: 20f4 20f4 dispatch_brk_class d ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20f4 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 20f5 20f5 <halt> ; Flow R 20f6 ; -------------------------------------------------------------------------------------- 20f6 ; 0x0122 Execute Any,Make_Root_Type 20f6 ; -------------------------------------------------------------------------------------- 20f6 MACRO_Execute_Any,Make_Root_Type: 20f6 20f6 dispatch_brk_class d ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20f6 seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 20f7 20f7 <halt> ; Flow R 20f8 ; -------------------------------------------------------------------------------------- 20f8 ; 0x0210 Execute Heap_Access,Get_Segment 20f8 ; -------------------------------------------------------------------------------------- 20f8 MACRO_Execute_Heap_Access,Get_Segment: 20f8 20f8 dispatch_brk_class d ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20f8 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 20f9 20f9 <halt> ; Flow R 20fa ; -------------------------------------------------------------------------------------- 20fa ; 0x0211 Execute Heap_Access,Convert_Reference 20fa ; -------------------------------------------------------------------------------------- 20fa MACRO_Execute_Heap_Access,Convert_Reference: 20fa 20fa dispatch_brk_class d ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20fa seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 20fb 20fb <halt> ; Flow R 20fc ; -------------------------------------------------------------------------------------- 20fc ; 0x0212 Execute Heap_Access,Address 20fc ; -------------------------------------------------------------------------------------- 20fc MACRO_Execute_Heap_Access,Address: 20fc 20fc dispatch_brk_class d ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20fc seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 20fd 20fd <halt> ; Flow R 20fe ; -------------------------------------------------------------------------------------- 20fe ; 0x0170 Illegal - 20fe ; -------------------------------------------------------------------------------------- 20fe MACRO_Illegal_-: 20fe 20fe dispatch_brk_class 8 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 20fe seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 20ff 20ff <halt> ; Flow R 2100 ; -------------------------------------------------------------------------------------- 2100 ; 0x0171 Illegal - 2100 ; -------------------------------------------------------------------------------------- 2100 MACRO_Illegal_-: 2100 2100 dispatch_brk_class 8 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2100 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2101 2101 <halt> ; Flow R 2102 ; -------------------------------------------------------------------------------------- 2102 ; 0x0172 Illegal - 2102 ; -------------------------------------------------------------------------------------- 2102 MACRO_Illegal_-: 2102 2102 dispatch_brk_class 8 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2102 seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 2103 2103 <halt> ; Flow R 2104 ; -------------------------------------------------------------------------------------- 2104 ; 0x0260 Execute Discrete,In_Type 2104 ; -------------------------------------------------------------------------------------- 2104 MACRO_Execute_Discrete,In_Type: 2104 2104 dispatch_brk_class 8 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2104 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2105 2105 <halt> ; Flow R 2106 ; -------------------------------------------------------------------------------------- 2106 ; 0x0261 Execute Discrete,Not_In_Range 2106 ; -------------------------------------------------------------------------------------- 2106 MACRO_Execute_Discrete,Not_In_Range: 2106 2106 dispatch_brk_class 8 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2106 seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 2107 2107 <halt> ; Flow R 2108 ; -------------------------------------------------------------------------------------- 2108 ; 0x0262 Execute Discrete,In_Range 2108 ; -------------------------------------------------------------------------------------- 2108 MACRO_Execute_Discrete,In_Range: 2108 2108 dispatch_brk_class 8 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2108 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2109 2109 <halt> ; Flow R 210a ; -------------------------------------------------------------------------------------- 210a ; 0x0180 Illegal - 210a ; -------------------------------------------------------------------------------------- 210a MACRO_Illegal_-: 210a 210a dispatch_brk_class 7 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 210a seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 210b 210b <halt> ; Flow R 210c ; -------------------------------------------------------------------------------------- 210c ; 0x0181 Illegal - 210c ; -------------------------------------------------------------------------------------- 210c MACRO_Illegal_-: 210c 210c dispatch_brk_class 7 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 210c seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 210d 210d <halt> ; Flow R 210e ; -------------------------------------------------------------------------------------- 210e ; 0x0182 Illegal - 210e ; -------------------------------------------------------------------------------------- 210e MACRO_Illegal_-: 210e 210e dispatch_brk_class 7 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 210e seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 210f 210f <halt> ; Flow R 2110 ; -------------------------------------------------------------------------------------- 2110 ; 0x0270 Execute Discrete,Divide 2110 ; -------------------------------------------------------------------------------------- 2110 MACRO_Execute_Discrete,Divide: 2110 2110 dispatch_brk_class 7 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2110 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2111 2111 <halt> ; Flow R 2112 ; -------------------------------------------------------------------------------------- 2112 ; 0x0271 Execute Discrete,Times 2112 ; -------------------------------------------------------------------------------------- 2112 MACRO_Execute_Discrete,Times: 2112 2112 dispatch_brk_class 7 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2112 seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 2113 2113 <halt> ; Flow R 2114 ; -------------------------------------------------------------------------------------- 2114 ; 0x0272 Execute Discrete,Minus 2114 ; -------------------------------------------------------------------------------------- 2114 MACRO_Execute_Discrete,Minus: 2114 2114 dispatch_brk_class 7 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2114 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2115 2115 <halt> ; Flow R 2116 ; -------------------------------------------------------------------------------------- 2116 ; 0x0190 Illegal - 2116 ; -------------------------------------------------------------------------------------- 2116 MACRO_Illegal_-: 2116 2116 dispatch_brk_class 3 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2116 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 2117 2117 <halt> ; Flow R 2118 ; -------------------------------------------------------------------------------------- 2118 ; 0x0191 Illegal - 2118 ; -------------------------------------------------------------------------------------- 2118 MACRO_Illegal_-: 2118 2118 dispatch_brk_class 3 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2118 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2119 2119 <halt> ; Flow R 211a ; -------------------------------------------------------------------------------------- 211a ; 0x0192 Illegal - 211a ; -------------------------------------------------------------------------------------- 211a MACRO_Illegal_-: 211a 211a dispatch_brk_class 3 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 211a seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 211b 211b <halt> ; Flow R 211c ; -------------------------------------------------------------------------------------- 211c ; 0x0280 Illegal - 211c ; -------------------------------------------------------------------------------------- 211c MACRO_Illegal_-: 211c 211c dispatch_brk_class 3 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 211c seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 211d 211d <halt> ; Flow R 211e ; -------------------------------------------------------------------------------------- 211e ; 0x0281 Illegal - 211e ; -------------------------------------------------------------------------------------- 211e MACRO_Illegal_-: 211e 211e dispatch_brk_class 3 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 211e seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 211f 211f <halt> ; Flow R 2120 ; -------------------------------------------------------------------------------------- 2120 ; 0x0282 Illegal - 2120 ; -------------------------------------------------------------------------------------- 2120 MACRO_Illegal_-: 2120 2120 dispatch_brk_class 3 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2120 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2121 2121 <halt> ; Flow R 2122 ; -------------------------------------------------------------------------------------- 2122 ; 0x01a0 Illegal - 2122 ; -------------------------------------------------------------------------------------- 2122 MACRO_Illegal_-: 2122 2122 dispatch_brk_class 5 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2122 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 2123 2123 <halt> ; Flow R 2124 ; -------------------------------------------------------------------------------------- 2124 ; 0x01a1 Illegal - 2124 ; -------------------------------------------------------------------------------------- 2124 MACRO_Illegal_-: 2124 2124 dispatch_brk_class 5 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2124 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2125 2125 <halt> ; Flow R 2126 ; -------------------------------------------------------------------------------------- 2126 ; 0x01a2 Illegal - 2126 ; -------------------------------------------------------------------------------------- 2126 MACRO_Illegal_-: 2126 2126 dispatch_brk_class 5 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2126 seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 2127 2127 <halt> ; Flow R 2128 ; -------------------------------------------------------------------------------------- 2128 ; 0x0290 Illegal - 2128 ; -------------------------------------------------------------------------------------- 2128 MACRO_Illegal_-: 2128 2128 dispatch_brk_class 5 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2128 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2129 2129 <halt> ; Flow R 212a ; -------------------------------------------------------------------------------------- 212a ; 0x0291 Illegal - 212a ; -------------------------------------------------------------------------------------- 212a MACRO_Illegal_-: 212a 212a dispatch_brk_class 5 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 212a seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 212b 212b <halt> ; Flow R 212c ; -------------------------------------------------------------------------------------- 212c ; 0x0292 Illegal - 212c ; -------------------------------------------------------------------------------------- 212c MACRO_Illegal_-: 212c 212c dispatch_brk_class 5 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 212c seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 212d 212d <halt> ; Flow R 212e ; -------------------------------------------------------------------------------------- 212e ; 0x01b0 Illegal - 212e ; -------------------------------------------------------------------------------------- 212e MACRO_Illegal_-: 212e 212e dispatch_brk_class 1 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 212e seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 212f 212f <halt> ; Flow R 2130 ; -------------------------------------------------------------------------------------- 2130 ; 0x01b1 Illegal - 2130 ; -------------------------------------------------------------------------------------- 2130 MACRO_Illegal_-: 2130 2130 dispatch_brk_class 1 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2130 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2131 2131 <halt> ; Flow R 2132 ; -------------------------------------------------------------------------------------- 2132 ; 0x01b2 Illegal - 2132 ; -------------------------------------------------------------------------------------- 2132 MACRO_Illegal_-: 2132 2132 dispatch_brk_class 1 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2132 seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 2133 2133 <halt> ; Flow R 2134 ; -------------------------------------------------------------------------------------- 2134 ; 0x02a0 Declare_Subprogram Null_Subprogram 2134 ; -------------------------------------------------------------------------------------- 2134 MACRO_Declare_Subprogram_Null_Subprogram: 2134 2134 dispatch_brk_class 1 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2134 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2135 2135 <halt> ; Flow R 2136 ; -------------------------------------------------------------------------------------- 2136 ; 0x02a1 Illegal - 2136 ; -------------------------------------------------------------------------------------- 2136 MACRO_Illegal_-: 2136 2136 dispatch_brk_class 1 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2136 seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 2137 2137 <halt> ; Flow R 2138 ; -------------------------------------------------------------------------------------- 2138 ; 0x02a2 Declare_Subprogram For_Accept,With_Address 2138 ; -------------------------------------------------------------------------------------- 2138 MACRO_Declare_Subprogram_For_Accept,With_Address: 2138 2138 dispatch_brk_class 1 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2138 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2139 2139 <halt> ; Flow R 213a ; -------------------------------------------------------------------------------------- 213a ; 0x01c0 Execute Vector,Greater_Equal 213a ; -------------------------------------------------------------------------------------- 213a MACRO_Execute_Vector,Greater_Equal: 213a 213a dispatch_brk_class 6 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 213a seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 213b 213b <halt> ; Flow R 213c ; -------------------------------------------------------------------------------------- 213c ; 0x01c1 Execute Vector,Less 213c ; -------------------------------------------------------------------------------------- 213c MACRO_Execute_Vector,Less: 213c 213c dispatch_brk_class 6 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 213c seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 213d 213d <halt> ; Flow R 213e ; -------------------------------------------------------------------------------------- 213e ; 0x01c2 Execute Vector,Greater 213e ; -------------------------------------------------------------------------------------- 213e MACRO_Execute_Vector,Greater: 213e 213e dispatch_brk_class 6 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 213e seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 213f 213f <halt> ; Flow R 2140 ; -------------------------------------------------------------------------------------- 2140 ; 0x02b0 Illegal - 2140 ; -------------------------------------------------------------------------------------- 2140 MACRO_Illegal_-: 2140 2140 dispatch_brk_class 6 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2140 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2141 2141 <halt> ; Flow R 2142 ; -------------------------------------------------------------------------------------- 2142 ; 0x02b1 Illegal - 2142 ; -------------------------------------------------------------------------------------- 2142 MACRO_Illegal_-: 2142 2142 dispatch_brk_class 6 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2142 seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 2143 2143 <halt> ; Flow R 2144 ; -------------------------------------------------------------------------------------- 2144 ; 0x02b2 Illegal - 2144 ; -------------------------------------------------------------------------------------- 2144 MACRO_Illegal_-: 2144 2144 dispatch_brk_class 6 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2144 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2145 2145 <halt> ; Flow R 2146 ; -------------------------------------------------------------------------------------- 2146 ; 0x01d0 Execute Vector,Complement 2146 ; -------------------------------------------------------------------------------------- 2146 MACRO_Execute_Vector,Complement: 2146 2146 dispatch_brk_class 2 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2146 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 2147 2147 <halt> ; Flow R 2148 ; -------------------------------------------------------------------------------------- 2148 ; 0x01d1 Execute Vector,Xor 2148 ; -------------------------------------------------------------------------------------- 2148 MACRO_Execute_Vector,Xor: 2148 2148 dispatch_brk_class 2 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2148 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2149 2149 <halt> ; Flow R 214a ; -------------------------------------------------------------------------------------- 214a ; 0x01d2 Execute Vector,Or 214a ; -------------------------------------------------------------------------------------- 214a MACRO_Execute_Vector,Or: 214a 214a dispatch_brk_class 2 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 214a seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 214b 214b <halt> ; Flow R 214c ; -------------------------------------------------------------------------------------- 214c ; 0x02c0 Illegal - 214c ; -------------------------------------------------------------------------------------- 214c MACRO_Illegal_-: 214c 214c dispatch_brk_class 2 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 214c seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 214d 214d <halt> ; Flow R 214e ; -------------------------------------------------------------------------------------- 214e ; 0x02c1 Illegal - 214e ; -------------------------------------------------------------------------------------- 214e MACRO_Illegal_-: 214e 214e dispatch_brk_class 2 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 214e seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 214f 214f <halt> ; Flow R 2150 ; -------------------------------------------------------------------------------------- 2150 ; 0x02c2 Illegal - 2150 ; -------------------------------------------------------------------------------------- 2150 MACRO_Illegal_-: 2150 2150 dispatch_brk_class 2 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2150 seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 2151 2151 <halt> ; Flow R 2152 ; -------------------------------------------------------------------------------------- 2152 ; 0x01e0 Illegal - 2152 ; -------------------------------------------------------------------------------------- 2152 MACRO_Illegal_-: 2152 2152 dispatch_brk_class 4 ; Flow J 0x20cd dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2152 seq_br_type 3 Unconditional Branch seq_branch_adr 20cd 0x20cd 2153 2153 <halt> ; Flow R 2154 ; -------------------------------------------------------------------------------------- 2154 ; 0x01e1 Illegal - 2154 ; -------------------------------------------------------------------------------------- 2154 MACRO_Illegal_-: 2154 2154 dispatch_brk_class 4 ; Flow J 0x20cf dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2154 seq_br_type 3 Unconditional Branch seq_branch_adr 20cf 0x20cf 2155 2155 <halt> ; Flow R 2156 ; -------------------------------------------------------------------------------------- 2156 ; 0x01e2 Illegal - 2156 ; -------------------------------------------------------------------------------------- 2156 MACRO_Illegal_-: 2156 2156 dispatch_brk_class 4 ; Flow J 0x20d1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2156 seq_br_type 3 Unconditional Branch seq_branch_adr 20d1 0x20d1 2157 2157 <halt> ; Flow R 2158 ; -------------------------------------------------------------------------------------- 2158 ; 0x02d0 Illegal - 2158 ; -------------------------------------------------------------------------------------- 2158 MACRO_Illegal_-: 2158 2158 dispatch_brk_class 4 ; Flow J 0x20d3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2158 seq_br_type 3 Unconditional Branch seq_branch_adr 20d3 0x20d3 2159 2159 <halt> ; Flow R 215a ; -------------------------------------------------------------------------------------- 215a ; 0x02d1 Illegal - 215a ; -------------------------------------------------------------------------------------- 215a MACRO_Illegal_-: 215a 215a dispatch_brk_class 4 ; Flow J 0x20d5 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 215a seq_br_type 3 Unconditional Branch seq_branch_adr 20d5 0x20d5 215b 215b <halt> ; Flow R 215c ; -------------------------------------------------------------------------------------- 215c ; 0x02d2 Illegal - 215c ; -------------------------------------------------------------------------------------- 215c MACRO_Illegal_-: 215c 215c dispatch_brk_class 4 ; Flow J 0x20d7 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 215c seq_br_type 3 Unconditional Branch seq_branch_adr 20d7 0x20d7 215d 215d <halt> ; Flow R 215e ; -------------------------------------------------------------------------------------- 215e ; 0x0400-0x043f Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 215e ; -------------------------------------------------------------------------------------- 215e MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 215e 215e dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 215e 215f 215f <halt> ; Flow R 2160 ; -------------------------------------------------------------------------------------- 2160 ; 0x0440-0x047f Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 2160 ; -------------------------------------------------------------------------------------- 2160 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 2160 2160 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2160 2161 2161 <halt> ; Flow R 2162 ; -------------------------------------------------------------------------------------- 2162 ; 0x0480-0x04bf Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 2162 ; -------------------------------------------------------------------------------------- 2162 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 2162 2162 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2162 2163 2163 <halt> ; Flow R 2164 ; -------------------------------------------------------------------------------------- 2164 ; 0x04c0-0x04ff Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 2164 ; -------------------------------------------------------------------------------------- 2164 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 2164 2164 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2164 2165 2165 <halt> ; Flow R 2166 ; -------------------------------------------------------------------------------------- 2166 ; 0x0500-0x053f Execute_Immediate Set_Value_Visible,uimmediate 2166 ; -------------------------------------------------------------------------------------- 2166 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 2166 2166 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2166 2167 2167 <halt> ; Flow R 2168 ; -------------------------------------------------------------------------------------- 2168 ; 0x0540-0x057f Execute_Immediate Set_Value_Visible,uimmediate 2168 ; -------------------------------------------------------------------------------------- 2168 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 2168 2168 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2168 2169 2169 <halt> ; Flow R 216a ; -------------------------------------------------------------------------------------- 216a ; 0x0580-0x05bf Execute_Immediate Set_Value_Visible,uimmediate 216a ; -------------------------------------------------------------------------------------- 216a MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 216a 216a dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 216a 216b 216b <halt> ; Flow R 216c ; -------------------------------------------------------------------------------------- 216c ; 0x05c0-0x05ff Execute_Immediate Set_Value_Visible,uimmediate 216c ; -------------------------------------------------------------------------------------- 216c MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 216c 216c dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 216c 216d 216d <halt> ; Flow R 216e ; -------------------------------------------------------------------------------------- 216e ; 0x0600-0x063f Execute_Immediate Set_Value_Unchecked,uimmediate 216e ; -------------------------------------------------------------------------------------- 216e MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 216e 216e dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 216e 216f 216f <halt> ; Flow R 2170 ; -------------------------------------------------------------------------------------- 2170 ; 0x0640-0x067f Execute_Immediate Set_Value_Unchecked,uimmediate 2170 ; -------------------------------------------------------------------------------------- 2170 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 2170 2170 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2170 2171 2171 <halt> ; Flow R 2172 ; -------------------------------------------------------------------------------------- 2172 ; 0x0680-0x06bf Execute_Immediate Set_Value_Unchecked,uimmediate 2172 ; -------------------------------------------------------------------------------------- 2172 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 2172 2172 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2172 2173 2173 <halt> ; Flow R 2174 ; -------------------------------------------------------------------------------------- 2174 ; 0x06c0-0x06ff Execute_Immediate Set_Value_Unchecked,uimmediate 2174 ; -------------------------------------------------------------------------------------- 2174 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 2174 2174 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2174 2175 2175 <halt> ; Flow R 2176 ; -------------------------------------------------------------------------------------- 2176 ; 0x0700-0x073f Execute_Immediate Set_Value,uimmediate 2176 ; -------------------------------------------------------------------------------------- 2176 MACRO_Execute_Immediate_Set_Value,uimmediate: 2176 2176 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2176 2177 2177 <halt> ; Flow R 2178 ; -------------------------------------------------------------------------------------- 2178 ; 0x0740-0x077f Execute_Immediate Set_Value,uimmediate 2178 ; -------------------------------------------------------------------------------------- 2178 MACRO_Execute_Immediate_Set_Value,uimmediate: 2178 2178 dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 2178 2179 2179 <halt> ; Flow R 217a ; -------------------------------------------------------------------------------------- 217a ; 0x0780-0x07bf Execute_Immediate Set_Value,uimmediate 217a ; -------------------------------------------------------------------------------------- 217a MACRO_Execute_Immediate_Set_Value,uimmediate: 217a 217a dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 217a 217b 217b <halt> ; Flow R 217c ; -------------------------------------------------------------------------------------- 217c ; 0x07c0-0x07ff Execute_Immediate Set_Value,uimmediate 217c ; -------------------------------------------------------------------------------------- 217c MACRO_Execute_Immediate_Set_Value,uimmediate: 217c 217c dispatch_brk_class 4 dispatch_csa_valid 0 dispatch_uadr 217c 217d ; -------------------------------------------------------------------------------------- 217d ; Comes from: 217d ; 0148 C True from color ML_break_class 217d ; 20cd C True from color 0x20ae 217d ; 20cf C True from color 0x20b3 217d ; 20d1 C True from color 0x20b3 217d ; 20d3 C True from color 0x20bf 217d ; 20d5 C True from color 0x20c4 217d ; 20d7 C True from color 0x20c4 217d ; -------------------------------------------------------------------------------------- 217d 217d seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 217e ; -------------------------------------------------------------------------------------- 217e ; Comes from: 217e ; 0860 C True from color 0x0800 217e ; 0861 C False from color 0x0800 217e ; 0862 C True from color 0x0800 217e ; 0865 C True from color 0x0800 217e ; 0866 C True from color 0x0800 217e ; 0868 C from color 0x0800 217e ; 0869 C True from color 0x0800 217e ; 086a C True from color 0x0800 217e ; 086d C from color 0x0800 217e ; 086e C True from color 0x0800 217e ; 086f C False from color 0x0800 217e ; 0871 C from color 0x0800 217e ; 0873 C False from color 0x0800 217e ; 0875 C from color 0x0800 217e ; 0877 C False from color 0x0800 217e ; 0878 C False from color 0x0800 217e ; 087a C from color 0x0800 217e ; 087b C True from color 0x0800 217e ; 087c C False from color 0x0800 217e ; 087e C from color 0x0800 217e ; 087f C False from color 0x0800 217e ; 0881 C from color 0x0800 217e ; 0882 C False from color 0x0800 217e ; 0884 C from color 0x0800 217e ; 0886 C from color 0x0800 217e ; 0887 C False from color 0x0800 217e ; 0888 C False from color 0x0800 217e ; 088a C from color 0x0800 217e ; 088b C False from color 0x0800 217e ; 088d C from color 0x0800 217e ; 088e C True from color 0x0800 217e ; 0890 C from color 0x0800 217e ; 0892 C from color 0x0800 217e ; 0893 C False from color 0x0800 217e ; 0894 C False from color 0x0800 217e ; 0896 C from color 0x0800 217e ; 0897 C False from color 0x0800 217e ; 0899 C from color 0x0800 217e ; 089a C True from color 0x0800 217e ; 089c C from color 0x0800 217e ; 089e C from color 0x0800 217e ; 089f C True from color 0x0800 217e ; 08a0 C False from color 0x0800 217e ; 08a2 C from color 0x0800 217e ; 08a3 C False from color 0x0800 217e ; 08a5 C from color 0x0800 217e ; 08a6 C False from color 0x0800 217e ; 08a8 C from color 0x0800 217e ; 08aa C from color 0x0800 217e ; 08ab C False from color 0x0800 217e ; 08ac C True from color 0x0800 217e ; 08ae C from color 0x0800 217e ; 08af C False from color 0x0800 217e ; 08b1 C from color 0x0800 217e ; 08b2 C False from color 0x0800 217e ; 08b4 C from color 0x0800 217e ; 08b6 C from color 0x0800 217e ; 08b7 C False from color 0x0800 217e ; 08b8 C True from color 0x0800 217e ; 08ba C from color 0x0800 217e ; 08bb C False from color 0x0800 217e ; 08bd C from color 0x0800 217e ; 08be C False from color 0x0800 217e ; 08c0 C from color 0x0800 217e ; 08c1 C True from color 0x0800 217e ; 08c3 C from color 0x0800 217e ; 08c5 C from color 0x0800 217e ; 08c6 C False from color 0x0800 217e ; 08c7 C False from color 0x0800 217e ; 08c9 C from color 0x0800 217e ; 08cb C from color 0x0800 217e ; 08cc C False from color 0x0800 217e ; 08ce C from color 0x0800 217e ; 08cf C True from color 0x0800 217e ; 08d1 C from color 0x0800 217e ; 08d2 C True from color 0x0800 217e ; 08d3 C True from color 0x0800 217e ; 08d5 C from color 0x0800 217e ; 08d7 C from color 0x0800 217e ; 08d8 C False from color 0x0800 217e ; 08d9 C False from color 0x0800 217e ; 08db C from color 0x0800 217e ; 08dd C from color 0x0800 217e ; 08de C False from color 0x0800 217e ; 08e0 C from color 0x0800 217e ; 08e1 C True from color 0x0800 217e ; 08e3 C from color 0x0800 217e ; 08e4 C True from color 0x0800 217e ; -------------------------------------------------------------------------------------- 217e 217e seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 217f ; -------------------------------------------------------------------------------------- 217f ; Comes from: 217f ; 08fa C True from color 0x08e7 217f ; 0902 C True from color 0x08e7 217f ; 090d C True from color 0x08e7 217f ; 090f C True from color 0x08e7 217f ; 0919 C True from color 0x08e7 217f ; 091b C True from color 0x08e7 217f ; -------------------------------------------------------------------------------------- 217f 217f seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2180 ; -------------------------------------------------------------------------------------- 2180 ; Comes from: 2180 ; 08ea C True from color 0x08e7 2180 ; 08f1 C True from color 0x08e7 2180 ; -------------------------------------------------------------------------------------- 2180 2180 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2181 ; -------------------------------------------------------------------------------------- 2181 ; Comes from: 2181 ; 08ec C True from color 0x08e7 2181 ; -------------------------------------------------------------------------------------- 2181 2181 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2182 ; -------------------------------------------------------------------------------------- 2182 ; Comes from: 2182 ; 08ee C True from color 0x08e7 2182 ; -------------------------------------------------------------------------------------- 2182 2182 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2183 ; -------------------------------------------------------------------------------------- 2183 ; Comes from: 2183 ; 0907 C True from color 0x08e7 2183 ; 0924 C True from color 0x08e7 2183 ; -------------------------------------------------------------------------------------- 2183 2183 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2184 ; -------------------------------------------------------------------------------------- 2184 ; Comes from: 2184 ; 0928 C True from color 0x08e7 2184 ; -------------------------------------------------------------------------------------- 2184 2184 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2185 ; -------------------------------------------------------------------------------------- 2185 ; Comes from: 2185 ; 0955 C True from color 0x08e7 2185 ; 0959 C True from color 0x08e7 2185 ; 0961 C True from color 0x08e7 2185 ; 0968 C True from color 0x08e7 2185 ; -------------------------------------------------------------------------------------- 2185 2185 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2186 ; -------------------------------------------------------------------------------------- 2186 ; Comes from: 2186 ; 08fc C True from color 0x08e7 2186 ; 0904 C True from color 0x08e7 2186 ; 0911 C True from color 0x08e7 2186 ; 0913 C True from color 0x08e7 2186 ; 091d C True from color 0x08e7 2186 ; 091f C True from color 0x08e7 2186 ; -------------------------------------------------------------------------------------- 2186 2186 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2187 ; -------------------------------------------------------------------------------------- 2187 ; Comes from: 2187 ; 08f3 C True from color 0x08e7 2187 ; -------------------------------------------------------------------------------------- 2187 2187 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2188 ; -------------------------------------------------------------------------------------- 2188 ; Comes from: 2188 ; 08f5 C True from color 0x08e7 2188 ; -------------------------------------------------------------------------------------- 2188 2188 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2189 ; -------------------------------------------------------------------------------------- 2189 ; Comes from: 2189 ; 0908 C True from color 0x08e7 2189 ; -------------------------------------------------------------------------------------- 2189 2189 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218a ; -------------------------------------------------------------------------------------- 218a ; Comes from: 218a ; 096b C True from color 0x08e7 218a ; 096f C True from color 0x08e7 218a ; 0973 C True from color 0x08e7 218a ; 0979 C True from color 0x08e7 218a ; 0982 C True from color 0x08e7 218a ; 0997 C True from color 0x08e7 218a ; 09a0 C True from color 0x08e7 218a ; -------------------------------------------------------------------------------------- 218a 218a seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218b ; -------------------------------------------------------------------------------------- 218b ; Comes from: 218b ; 096c C True from color 0x08e7 218b ; 0971 C True from color 0x08e7 218b ; 0974 C True from color 0x08e7 218b ; 097b C True from color 0x08e7 218b ; 0985 C True from color 0x08e7 218b ; 0999 C True from color 0x08e7 218b ; 09a3 C True from color 0x08e7 218b ; -------------------------------------------------------------------------------------- 218b 218b seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218c ; -------------------------------------------------------------------------------------- 218c ; Comes from: 218c ; 0989 C True from color 0x08e7 218c ; -------------------------------------------------------------------------------------- 218c 218c seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218d ; -------------------------------------------------------------------------------------- 218d ; Comes from: 218d ; 098c C True from color 0x08e7 218d ; 0990 C True from color 0x08e7 218d ; -------------------------------------------------------------------------------------- 218d 218d seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218e ; -------------------------------------------------------------------------------------- 218e ; Comes from: 218e ; 098d C True from color 0x08e7 218e ; 0992 C True from color 0x08e7 218e ; -------------------------------------------------------------------------------------- 218e 218e seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 218f ; -------------------------------------------------------------------------------------- 218f ; Comes from: 218f ; 09a8 C True from color 0x08e7 218f ; 09a9 C True from color 0x08e7 218f ; -------------------------------------------------------------------------------------- 218f 218f seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2190 ; -------------------------------------------------------------------------------------- 2190 ; Comes from: 2190 ; 09ab C True from color 0x08e7 2190 ; -------------------------------------------------------------------------------------- 2190 2190 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2191 ; -------------------------------------------------------------------------------------- 2191 ; Comes from: 2191 ; 09b6 C True from color 0x08e7 2191 ; -------------------------------------------------------------------------------------- 2191 2191 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2192 2192 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2193 ; -------------------------------------------------------------------------------------- 2193 ; Comes from: 2193 ; 09c2 C True from color 0x08e7 2193 ; 09ca C True from color 0x08e7 2193 ; 09d3 C True from color 0x08e7 2193 ; 09db C True from color 0x08e7 2193 ; -------------------------------------------------------------------------------------- 2193 2193 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2194 ; -------------------------------------------------------------------------------------- 2194 ; Comes from: 2194 ; 09e1 C True from color 0x08e7 2194 ; 09e5 C True from color 0x08e7 2194 ; 09ea C True from color 0x08e7 2194 ; 09f3 C True from color 0x08e7 2194 ; -------------------------------------------------------------------------------------- 2194 2194 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2195 ; -------------------------------------------------------------------------------------- 2195 ; Comes from: 2195 ; 09b4 C True from color 0x08e7 2195 ; 09c0 C True from color 0x08e7 2195 ; -------------------------------------------------------------------------------------- 2195 2195 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2196 ; -------------------------------------------------------------------------------------- 2196 ; Comes from: 2196 ; 09bb C False from color 0x08e7 2196 ; -------------------------------------------------------------------------------------- 2196 2196 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2197 ; -------------------------------------------------------------------------------------- 2197 ; Comes from: 2197 ; 092c C True from color 0x08e7 2197 ; 092f C True from color 0x08e7 2197 ; 0932 C True from color 0x08e7 2197 ; 0935 C True from color 0x08e7 2197 ; 093a C True from color 0x08e7 2197 ; 0940 C True from color 0x08e7 2197 ; 0947 C True from color 0x08e7 2197 ; 094e C True from color 0x08e7 2197 ; -------------------------------------------------------------------------------------- 2197 2197 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2198 2198 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 2199 ; -------------------------------------------------------------------------------------- 2199 ; Comes from: 2199 ; 1e21 C True from color 0x08e7 2199 ; 1e23 C True from color 0x08e7 2199 ; 1e31 C True from color 0x08e7 2199 ; 1e33 C True from color 0x08e7 2199 ; -------------------------------------------------------------------------------------- 2199 2199 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219a 219a seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219b 219b seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219c ; -------------------------------------------------------------------------------------- 219c ; Comes from: 219c ; 1e07 C True from color 0x08e7 219c ; 1e13 C True from color 0x08e7 219c ; -------------------------------------------------------------------------------------- 219c 219c seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219d ; -------------------------------------------------------------------------------------- 219d ; Comes from: 219d ; 1e09 C True from color 0x08e7 219d ; 1e16 C True from color 0x08e7 219d ; -------------------------------------------------------------------------------------- 219d 219d seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219e 219e seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 219f 219f seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a0 ; -------------------------------------------------------------------------------------- 21a0 ; Comes from: 21a0 ; 09ac C True from color 0x08e7 21a0 ; -------------------------------------------------------------------------------------- 21a0 21a0 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a1 ; -------------------------------------------------------------------------------------- 21a1 ; Comes from: 21a1 ; 09ad C True from color 0x08e7 21a1 ; -------------------------------------------------------------------------------------- 21a1 21a1 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a2 ; -------------------------------------------------------------------------------------- 21a2 ; Comes from: 21a2 ; 09ae C True from color 0x08e7 21a2 ; -------------------------------------------------------------------------------------- 21a2 21a2 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a3 ; -------------------------------------------------------------------------------------- 21a3 ; Comes from: 21a3 ; 09af C True from color 0x08e7 21a3 ; -------------------------------------------------------------------------------------- 21a3 21a3 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a4 ; -------------------------------------------------------------------------------------- 21a4 ; Comes from: 21a4 ; 1e41 C True from color 0x08e7 21a4 ; -------------------------------------------------------------------------------------- 21a4 21a4 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a5 ; -------------------------------------------------------------------------------------- 21a5 ; Comes from: 21a5 ; 1e45 C True from color 0x08e7 21a5 ; -------------------------------------------------------------------------------------- 21a5 21a5 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a6 ; -------------------------------------------------------------------------------------- 21a6 ; Comes from: 21a6 ; 0145 C True from color ML_IBUF_empty 21a6 ; -------------------------------------------------------------------------------------- 21a6 21a6 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a7 ; -------------------------------------------------------------------------------------- 21a7 ; Comes from: 21a7 ; 1e57 C False from color 0x08e7 21a7 ; 1e5b C False from color 0x08e7 21a7 ; 1e5f C False from color 0x08e7 21a7 ; 1e68 C True from color MACRO_Illegal_- 21a7 ; -------------------------------------------------------------------------------------- 21a7 21a7 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a8 ; -------------------------------------------------------------------------------------- 21a8 ; Comes from: 21a8 ; 1e66 C False from color MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object 21a8 ; -------------------------------------------------------------------------------------- 21a8 21a8 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21a9 ; -------------------------------------------------------------------------------------- 21a9 ; Comes from: 21a9 ; 0141 C True from color ML_IBUF_empty 21a9 ; -------------------------------------------------------------------------------------- 21a9 21a9 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21aa ; -------------------------------------------------------------------------------------- 21aa ; Comes from: 21aa ; 1e4b C True from color 0x08e7 21aa ; -------------------------------------------------------------------------------------- 21aa 21aa seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21ab ; -------------------------------------------------------------------------------------- 21ab ; Comes from: 21ab ; 1e4e C True from color 0x08e7 21ab ; -------------------------------------------------------------------------------------- 21ab 21ab seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21ac ; -------------------------------------------------------------------------------------- 21ac ; Comes from: 21ac ; 1e75 C True from color 0x08e7 21ac ; -------------------------------------------------------------------------------------- 21ac 21ac seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21ad ; -------------------------------------------------------------------------------------- 21ad ; Comes from: 21ad ; 1e76 C True from color 0x08e7 21ad ; -------------------------------------------------------------------------------------- 21ad 21ad seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21ae ; -------------------------------------------------------------------------------------- 21ae ; Comes from: 21ae ; 1e7c C False from color MACRO_Store_llvl,ldelta 21ae ; -------------------------------------------------------------------------------------- 21ae 21ae seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 21af ; -------------------------------------------------------------------------------------- 21af ; Comes from: 21af ; 1e85 C False from color MACRO_Store_llvl,ldelta 21af ; -------------------------------------------------------------------------------------- 21af 21af seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b0 ; -------------------------------------------------------------------------------------- 21b0 ; Comes from: 21b0 ; 1e88 C True from color MACRO_Store_llvl,ldelta 21b0 ; -------------------------------------------------------------------------------------- 21b0 21b0 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b1 ; -------------------------------------------------------------------------------------- 21b1 ; Comes from: 21b1 ; 0178 C True from color ML_CSA_overflow 21b1 ; 1e92 C True from color MACRO_Halt_InMicrocode 21b1 ; 1e93 C True from color MACRO_Halt_InMicrocode 21b1 ; 1e98 C True from color MACRO_1e98_QQUnknown_InMicrocode 21b1 ; 1e99 C True from color MACRO_1e98_QQUnknown_InMicrocode 21b1 ; 1e9e C True from color MACRO_1e9e_QQUnknown_InMicrocode 21b1 ; 1e9f C True from color MACRO_1e9e_QQUnknown_InMicrocode 21b1 ; 1ea4 C True from color MACRO_1ea4_QQUnknown_InMicrocode 21b1 ; 1ea5 C True from color MACRO_1ea4_QQUnknown_InMicrocode 21b1 ; 1eaa C True from color MACRO_1eaa_QQUnknown_InMicrocode 21b1 ; 1eab C True from color MACRO_1eaa_QQUnknown_InMicrocode 21b1 ; 1eb0 C True from color MACRO_1eb0_QQUnknown_InMicrocode 21b1 ; 1eb1 C True from color MACRO_1eb0_QQUnknown_InMicrocode 21b1 ; 1eb6 C True from color MACRO_1eb6_QQUnknown_InMicrocode 21b1 ; 1eb7 C True from color MACRO_1eb6_QQUnknown_InMicrocode 21b1 ; 1ebc C True from color MACRO_1ebc_QQUnknown_InMicrocode 21b1 ; 1ebd C True from color MACRO_1ebc_QQUnknown_InMicrocode 21b1 ; -------------------------------------------------------------------------------------- 21b1 21b1 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b2 ; -------------------------------------------------------------------------------------- 21b2 ; Comes from: 21b2 ; 0170 C True from color ML_CSA_Underflow 21b2 ; 1ecc C True from color MACRO_Illegal_- 21b2 ; 1ecd C True from color MACRO_Illegal_- 21b2 ; 1ed2 C True from color MACRO_Illegal_- 21b2 ; 1ed3 C True from color MACRO_Illegal_- 21b2 ; 1ed8 C True from color MACRO_Illegal_- 21b2 ; 1ed9 C True from color MACRO_Illegal_- 21b2 ; 1ede C True from color MACRO_Illegal_- 21b2 ; 1edf C True from color MACRO_Illegal_- 21b2 ; -------------------------------------------------------------------------------------- 21b2 21b2 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b3 ; -------------------------------------------------------------------------------------- 21b3 ; Comes from: 21b3 ; 0160 C True from color ML_Resolve Reference 21b3 ; 1ee8 C True from color MACRO_Call_llvl,ldelta 21b3 ; 1eec C True from color MACRO_Call_llvl,ldelta 21b3 ; 1ef0 C True from color MACRO_Call_llvl,ldelta 21b3 ; 1ef4 C True from color MACRO_Call_llvl,ldelta 21b3 ; -------------------------------------------------------------------------------------- 21b3 21b3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 21b4 21b4 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b5 ; -------------------------------------------------------------------------------------- 21b5 ; Comes from: 21b5 ; 0158 C True from color ML_TOS_INVLD 21b5 ; 1efe C True from color MACRO_Reference_zdelta 21b5 ; 1f02 C True from color MACRO_Store_Unchecked_llvl,ldelta 21b5 ; 1f06 C True from color MACRO_Store_Unchecked_llvl,ldelta 21b5 ; 1f0a C True from color MACRO_Store_Unchecked_llvl,ldelta 21b5 ; -------------------------------------------------------------------------------------- 21b5 21b5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 21b6 21b6 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b7 ; -------------------------------------------------------------------------------------- 21b7 ; Comes from: 21b7 ; 0805 C from color 0x0800 21b7 ; 0807 C True from color 0x0800 21b7 ; 080a C from color 0x0800 21b7 ; 080c C False from color 0x0800 21b7 ; 0810 C True from color 0x0800 21b7 ; 0812 C True from color 0x0800 21b7 ; 0814 C True from color 0x0800 21b7 ; 0817 C from color 0x0800 21b7 ; 0819 C False from color 0x0800 21b7 ; 081d C True from color 0x0800 21b7 ; 0820 C from color 0x0800 21b7 ; 0823 C False from color 0x0800 21b7 ; 0827 C True from color 0x0800 21b7 ; 082a C from color 0x0800 21b7 ; 082d C False from color 0x0800 21b7 ; 0831 C True from color 0x0800 21b7 ; 0834 C from color 0x0800 21b7 ; 0837 C False from color 0x0800 21b7 ; 083a C from color 0x0800 21b7 ; 083b C True from color 0x0800 21b7 ; 083e C from color 0x0800 21b7 ; 083f C from color 0x0800 21b7 ; 0841 C False from color 0x0800 21b7 ; 0845 C True from color 0x0800 21b7 ; 0848 C from color 0x0800 21b7 ; 084b C False from color 0x0800 21b7 ; 084f C True from color 0x0800 21b7 ; 0852 C from color 0x0800 21b7 ; 0857 C False from color 0x0800 21b7 ; -------------------------------------------------------------------------------------- 21b7 21b7 seq_br_type 3 Unconditional Branch; Flow J 0x200 seq_branch_adr 0200 0x0200 seq_en_micro 0 21b8 21b8 <halt> ; Flow R 21b9 21b9 <halt> ; Flow R 21ba 21ba <halt> ; Flow R 21bb 21bb <halt> ; Flow R 21bc 21bc <halt> ; Flow R 21bd 21bd <halt> ; Flow R 21be 21be <halt> ; Flow R 21bf 21bf <halt> ; Flow R 21c0 21c0 <halt> ; Flow R 21c1 21c1 <halt> ; Flow R 21c2 21c2 <halt> ; Flow R 21c3 21c3 <halt> ; Flow R 21c4 21c4 <halt> ; Flow R 21c5 21c5 <halt> ; Flow R 21c6 21c6 <halt> ; Flow R 21c7 21c7 <halt> ; Flow R 21c8 21c8 <halt> ; Flow R 21c9 21c9 <halt> ; Flow R 21ca 21ca <halt> ; Flow R 21cb 21cb <halt> ; Flow R 21cc 21cc <halt> ; Flow R 21cd 21cd <halt> ; Flow R 21ce 21ce <halt> ; Flow R 21cf 21cf <halt> ; Flow R 21d0 21d0 <halt> ; Flow R 21d1 21d1 <halt> ; Flow R 21d2 21d2 <halt> ; Flow R 21d3 21d3 <halt> ; Flow R 21d4 21d4 <halt> ; Flow R 21d5 21d5 <halt> ; Flow R 21d6 21d6 <halt> ; Flow R 21d7 21d7 <halt> ; Flow R 21d8 21d8 <halt> ; Flow R 21d9 21d9 <halt> ; Flow R 21da 21da <halt> ; Flow R 21db 21db <halt> ; Flow R 21dc 21dc <halt> ; Flow R 21dd 21dd <halt> ; Flow R 21de 21de <halt> ; Flow R 21df 21df <halt> ; Flow R 21e0 21e0 <halt> ; Flow R 21e1 21e1 <halt> ; Flow R 21e2 21e2 <halt> ; Flow R 21e3 21e3 <halt> ; Flow R 21e4 21e4 <halt> ; Flow R 21e5 21e5 <halt> ; Flow R 21e6 21e6 <halt> ; Flow R 21e7 21e7 <halt> ; Flow R 21e8 21e8 <halt> ; Flow R 21e9 21e9 <halt> ; Flow R 21ea 21ea <halt> ; Flow R 21eb 21eb <halt> ; Flow R 21ec 21ec <halt> ; Flow R 21ed 21ed <halt> ; Flow R 21ee 21ee <halt> ; Flow R 21ef 21ef <halt> ; Flow R 21f0 21f0 <halt> ; Flow R 21f1 21f1 <halt> ; Flow R 21f2 21f2 <halt> ; Flow R 21f3 21f3 <halt> ; Flow R 21f4 21f4 <halt> ; Flow R 21f5 21f5 <halt> ; Flow R 21f6 21f6 <halt> ; Flow R 21f7 21f7 <halt> ; Flow R 21f8 21f8 <halt> ; Flow R 21f9 21f9 <halt> ; Flow R 21fa 21fa <halt> ; Flow R 21fb 21fb <halt> ; Flow R 21fc 21fc <halt> ; Flow R 21fd 21fd <halt> ; Flow R 21fe 21fe <halt> ; Flow R 21ff 21ff <halt> ; Flow R 2200 ; -------------------------------------------------------------------------------------- 2200 ; Comes from: 2200 ; 0e21 C from color 0x0800 2200 ; 0e44 C from color 0x0e02 2200 ; 0e47 C from color 0x0e03 2200 ; 0e4a C from color 0x0e04 2200 ; 0e4d C from color 0x0e05 2200 ; 0e52 C from color 0x0800 2200 ; 0e57 C from color 0x0e07 2200 ; 0e5a C from color 0x0e08 2200 ; 0e5d C from color 0x0e09 2200 ; 0e60 C from color 0x0e0a 2200 ; 0e63 C from color 0x0e0b 2200 ; 0e66 C from color 0x0e0c 2200 ; 0e69 C from color 0x0e0d 2200 ; 0e6c C from color 0x0e0e 2200 ; 0e6f C from color 0x0e0f 2200 ; 0e72 C from color 0x0e10 2200 ; 0e75 C from color 0x0e11 2200 ; 0e78 C from color 0x0e12 2200 ; 0e7b C from color 0x0e13 2200 ; 0e7e C from color 0x0e14 2200 ; 0e81 C from color 0x0e15 2200 ; 0e84 C from color 0x0e16 2200 ; 0e87 C from color 0x0e17 2200 ; 0e8a C from color 0x0e18 2200 ; 0e8d C from color 0x0e19 2200 ; 0e90 C from color 0x0e1a 2200 ; 0e93 C from color 0x0e1b 2200 ; 0e96 C from color 0x0e1c 2200 ; 0e99 C from color 0x0e1d 2200 ; 0e9c C from color 0x0e1e 2200 ; 0e9f C from color 0x0e1f 2200 ; 0ea2 C from color 0x0e20 2200 ; -------------------------------------------------------------------------------------- 2200 2200 fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR18:02 typ_frame 18 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 32 VR19:12 val_alu_func 0 PASS_A val_b_adr 32 VR19:12 val_frame 19 2201 2201 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 2202 2202 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 seq_random 0a ? val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2203 2203 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 32 VR19:12 val_frame 19 val_rand 2 DEC_LOOP_COUNTER 2204 2204 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 29 TR12:09 typ_frame 12 val_b_adr 30 VR14:10 val_frame 14 2205 2205 seq_en_micro 0 seq_random 55 ? 2206 2206 seq_b_timing 0 Early Condition; Flow J cc=False 0x2203 seq_br_type 0 Branch False seq_branch_adr 2203 0x2203 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 2207 2207 fiu_mem_start 13 start_available_query ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR18:01 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3a VR14:1a val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2208 2208 seq_en_micro 0 2209 2209 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR13:0c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 13 220a 220a fiu_mem_start 17 scavenger_write; Flow J cc=False 0x2209 fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2209 0x2209 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_b_adr 2b VR13:0b val_frame 13 val_rand 2 DEC_LOOP_COUNTER 220b 220b fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x2208 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2208 0x2208 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 3a VR14:1a val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 220c 220c seq_en_micro 0 220d 220d fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 2d TR12:0d typ_frame 12 typ_mar_cntl 4 RESTORE_MAR 220e 220e ioc_random f disable delay timer seq_en_micro 0 220f 220f ioc_random d disable slice timer seq_en_micro 0 2210 2210 ioc_random b clear delay event seq_en_micro 0 2211 2211 ioc_random a clear slice event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 2212 2212 <halt> ; Flow R 2213 2213 <halt> ; Flow R 2214 2214 <halt> ; Flow R 2215 2215 <halt> ; Flow R 2216 2216 <halt> ; Flow R 2217 2217 <halt> ; Flow R 2218 2218 <halt> ; Flow R 2219 2219 <halt> ; Flow R 221a 221a <halt> ; Flow R 221b 221b <halt> ; Flow R 221c 221c <halt> ; Flow R 221d 221d <halt> ; Flow R 221e 221e <halt> ; Flow R 221f 221f <halt> ; Flow R 2220 2220 <halt> ; Flow R 2221 2221 <halt> ; Flow R 2222 2222 <halt> ; Flow R 2223 2223 <halt> ; Flow R 2224 2224 <halt> ; Flow R 2225 2225 <halt> ; Flow R 2226 2226 <halt> ; Flow R 2227 2227 <halt> ; Flow R 2228 2228 <halt> ; Flow R 2229 2229 <halt> ; Flow R 222a 222a <halt> ; Flow R 222b 222b <halt> ; Flow R 222c 222c <halt> ; Flow R 222d 222d <halt> ; Flow R 222e 222e <halt> ; Flow R 222f 222f <halt> ; Flow R 2230 2230 <halt> ; Flow R 2231 2231 <halt> ; Flow R 2232 2232 <halt> ; Flow R 2233 2233 <halt> ; Flow R 2234 2234 <halt> ; Flow R 2235 2235 <halt> ; Flow R 2236 2236 <halt> ; Flow R 2237 2237 <halt> ; Flow R 2238 2238 <halt> ; Flow R 2239 2239 <halt> ; Flow R 223a 223a <halt> ; Flow R 223b 223b <halt> ; Flow R 223c 223c <halt> ; Flow R 223d 223d <halt> ; Flow R 223e 223e <halt> ; Flow R 223f 223f <halt> ; Flow R 2240 2240 <halt> ; Flow R 2241 2241 <halt> ; Flow R 2242 2242 <halt> ; Flow R 2243 2243 <halt> ; Flow R 2244 2244 <halt> ; Flow R 2245 2245 <halt> ; Flow R 2246 2246 <halt> ; Flow R 2247 2247 <halt> ; Flow R 2248 2248 <halt> ; Flow R 2249 2249 <halt> ; Flow R 224a 224a <halt> ; Flow R 224b 224b <halt> ; Flow R 224c 224c <halt> ; Flow R 224d 224d <halt> ; Flow R 224e 224e <halt> ; Flow R 224f 224f <halt> ; Flow R 2250 2250 <halt> ; Flow R 2251 2251 <halt> ; Flow R 2252 2252 <halt> ; Flow R 2253 2253 <halt> ; Flow R 2254 2254 <halt> ; Flow R 2255 2255 <halt> ; Flow R 2256 2256 <halt> ; Flow R 2257 2257 <halt> ; Flow R 2258 2258 <halt> ; Flow R 2259 2259 <halt> ; Flow R 225a 225a <halt> ; Flow R 225b 225b <halt> ; Flow R 225c 225c <halt> ; Flow R 225d 225d <halt> ; Flow R 225e 225e <halt> ; Flow R 225f 225f <halt> ; Flow R 2260 2260 <halt> ; Flow R 2261 2261 <halt> ; Flow R 2262 2262 <halt> ; Flow R 2263 2263 <halt> ; Flow R 2264 2264 <halt> ; Flow R 2265 2265 <halt> ; Flow R 2266 2266 <halt> ; Flow R 2267 2267 <halt> ; Flow R 2268 2268 <halt> ; Flow R 2269 2269 <halt> ; Flow R 226a 226a <halt> ; Flow R 226b 226b <halt> ; Flow R 226c 226c <halt> ; Flow R 226d 226d <halt> ; Flow R 226e 226e <halt> ; Flow R 226f 226f <halt> ; Flow R 2270 2270 <halt> ; Flow R 2271 2271 <halt> ; Flow R 2272 2272 <halt> ; Flow R 2273 2273 <halt> ; Flow R 2274 2274 <halt> ; Flow R 2275 2275 <halt> ; Flow R 2276 2276 <halt> ; Flow R 2277 2277 <halt> ; Flow R 2278 2278 <halt> ; Flow R 2279 2279 <halt> ; Flow R 227a 227a <halt> ; Flow R 227b 227b <halt> ; Flow R 227c 227c <halt> ; Flow R 227d 227d <halt> ; Flow R 227e 227e <halt> ; Flow R 227f 227f <halt> ; Flow R 2280 2280 <halt> ; Flow R 2281 2281 <halt> ; Flow R 2282 2282 <halt> ; Flow R 2283 2283 <halt> ; Flow R 2284 2284 <halt> ; Flow R 2285 2285 <halt> ; Flow R 2286 2286 <halt> ; Flow R 2287 2287 <halt> ; Flow R 2288 2288 <halt> ; Flow R 2289 2289 <halt> ; Flow R 228a 228a <halt> ; Flow R 228b 228b <halt> ; Flow R 228c 228c <halt> ; Flow R 228d 228d <halt> ; Flow R 228e 228e <halt> ; Flow R 228f 228f <halt> ; Flow R 2290 2290 <halt> ; Flow R 2291 2291 <halt> ; Flow R 2292 2292 <halt> ; Flow R 2293 2293 <halt> ; Flow R 2294 2294 <halt> ; Flow R 2295 2295 <halt> ; Flow R 2296 2296 <halt> ; Flow R 2297 2297 <halt> ; Flow R 2298 2298 <halt> ; Flow R 2299 2299 <halt> ; Flow R 229a 229a <halt> ; Flow R 229b 229b <halt> ; Flow R 229c 229c <halt> ; Flow R 229d 229d <halt> ; Flow R 229e 229e <halt> ; Flow R 229f 229f <halt> ; Flow R 22a0 22a0 <halt> ; Flow R 22a1 22a1 <halt> ; Flow R 22a2 22a2 <halt> ; Flow R 22a3 22a3 <halt> ; Flow R 22a4 22a4 <halt> ; Flow R 22a5 22a5 <halt> ; Flow R 22a6 22a6 <halt> ; Flow R 22a7 22a7 <halt> ; Flow R 22a8 22a8 <halt> ; Flow R 22a9 22a9 <halt> ; Flow R 22aa 22aa <halt> ; Flow R 22ab 22ab <halt> ; Flow R 22ac 22ac <halt> ; Flow R 22ad 22ad <halt> ; Flow R 22ae 22ae <halt> ; Flow R 22af 22af <halt> ; Flow R 22b0 22b0 <halt> ; Flow R 22b1 22b1 <halt> ; Flow R 22b2 22b2 <halt> ; Flow R 22b3 22b3 <halt> ; Flow R 22b4 22b4 <halt> ; Flow R 22b5 22b5 <halt> ; Flow R 22b6 22b6 <halt> ; Flow R 22b7 22b7 <halt> ; Flow R 22b8 22b8 <halt> ; Flow R 22b9 22b9 <halt> ; Flow R 22ba 22ba <halt> ; Flow R 22bb 22bb <halt> ; Flow R 22bc 22bc <halt> ; Flow R 22bd 22bd <halt> ; Flow R 22be 22be <halt> ; Flow R 22bf 22bf <halt> ; Flow R 22c0 22c0 <halt> ; Flow R 22c1 22c1 <halt> ; Flow R 22c2 22c2 <halt> ; Flow R 22c3 22c3 <halt> ; Flow R 22c4 22c4 <halt> ; Flow R 22c5 22c5 <halt> ; Flow R 22c6 22c6 <halt> ; Flow R 22c7 22c7 <halt> ; Flow R 22c8 22c8 <halt> ; Flow R 22c9 22c9 <halt> ; Flow R 22ca 22ca <halt> ; Flow R 22cb 22cb <halt> ; Flow R 22cc 22cc <halt> ; Flow R 22cd 22cd <halt> ; Flow R 22ce 22ce <halt> ; Flow R 22cf 22cf <halt> ; Flow R 22d0 22d0 <halt> ; Flow R 22d1 22d1 <halt> ; Flow R 22d2 22d2 <halt> ; Flow R 22d3 22d3 <halt> ; Flow R 22d4 22d4 <halt> ; Flow R 22d5 22d5 <halt> ; Flow R 22d6 22d6 <halt> ; Flow R 22d7 22d7 <halt> ; Flow R 22d8 22d8 <halt> ; Flow R 22d9 22d9 <halt> ; Flow R 22da 22da <halt> ; Flow R 22db 22db <halt> ; Flow R 22dc 22dc <halt> ; Flow R 22dd 22dd <halt> ; Flow R 22de 22de <halt> ; Flow R 22df 22df <halt> ; Flow R 22e0 22e0 <halt> ; Flow R 22e1 22e1 <halt> ; Flow R 22e2 22e2 <halt> ; Flow R 22e3 22e3 <halt> ; Flow R 22e4 22e4 <halt> ; Flow R 22e5 22e5 <halt> ; Flow R 22e6 22e6 <halt> ; Flow R 22e7 22e7 <halt> ; Flow R 22e8 22e8 <halt> ; Flow R 22e9 22e9 <halt> ; Flow R 22ea 22ea <halt> ; Flow R 22eb 22eb <halt> ; Flow R 22ec 22ec <halt> ; Flow R 22ed 22ed <halt> ; Flow R 22ee 22ee <halt> ; Flow R 22ef 22ef <halt> ; Flow R 22f0 22f0 <halt> ; Flow R 22f1 22f1 <halt> ; Flow R 22f2 22f2 <halt> ; Flow R 22f3 22f3 <halt> ; Flow R 22f4 22f4 <halt> ; Flow R 22f5 22f5 <halt> ; Flow R 22f6 22f6 <halt> ; Flow R 22f7 22f7 <halt> ; Flow R 22f8 22f8 <halt> ; Flow R 22f9 22f9 <halt> ; Flow R 22fa 22fa <halt> ; Flow R 22fb 22fb <halt> ; Flow R 22fc 22fc <halt> ; Flow R 22fd 22fd <halt> ; Flow R 22fe 22fe <halt> ; Flow R 22ff 22ff <halt> ; Flow R 2300 2300 <halt> ; Flow R 2301 2301 <halt> ; Flow R 2302 2302 <halt> ; Flow R 2303 2303 <halt> ; Flow R 2304 2304 <halt> ; Flow R 2305 2305 <halt> ; Flow R 2306 2306 <halt> ; Flow R 2307 2307 <halt> ; Flow R 2308 2308 <halt> ; Flow R 2309 2309 <halt> ; Flow R 230a 230a <halt> ; Flow R 230b 230b <halt> ; Flow R 230c 230c <halt> ; Flow R 230d 230d <halt> ; Flow R 230e 230e <halt> ; Flow R 230f 230f <halt> ; Flow R 2310 2310 <halt> ; Flow R 2311 2311 <halt> ; Flow R 2312 2312 <halt> ; Flow R 2313 2313 <halt> ; Flow R 2314 2314 <halt> ; Flow R 2315 2315 <halt> ; Flow R 2316 2316 <halt> ; Flow R 2317 2317 <halt> ; Flow R 2318 2318 <halt> ; Flow R 2319 2319 <halt> ; Flow R 231a 231a <halt> ; Flow R 231b 231b <halt> ; Flow R 231c 231c <halt> ; Flow R 231d 231d <halt> ; Flow R 231e 231e <halt> ; Flow R 231f 231f <halt> ; Flow R 2320 2320 <halt> ; Flow R 2321 2321 <halt> ; Flow R 2322 2322 <halt> ; Flow R 2323 2323 <halt> ; Flow R 2324 2324 <halt> ; Flow R 2325 2325 <halt> ; Flow R 2326 2326 <halt> ; Flow R 2327 2327 <halt> ; Flow R 2328 2328 <halt> ; Flow R 2329 2329 <halt> ; Flow R 232a 232a <halt> ; Flow R 232b 232b <halt> ; Flow R 232c 232c <halt> ; Flow R 232d 232d <halt> ; Flow R 232e 232e <halt> ; Flow R 232f 232f <halt> ; Flow R 2330 2330 <halt> ; Flow R 2331 2331 <halt> ; Flow R 2332 2332 <halt> ; Flow R 2333 2333 <halt> ; Flow R 2334 2334 <halt> ; Flow R 2335 2335 <halt> ; Flow R 2336 2336 <halt> ; Flow R 2337 2337 <halt> ; Flow R 2338 2338 <halt> ; Flow R 2339 2339 <halt> ; Flow R 233a 233a <halt> ; Flow R 233b 233b <halt> ; Flow R 233c 233c <halt> ; Flow R 233d 233d <halt> ; Flow R 233e 233e <halt> ; Flow R 233f 233f <halt> ; Flow R 2340 2340 <halt> ; Flow R 2341 2341 <halt> ; Flow R 2342 2342 <halt> ; Flow R 2343 2343 <halt> ; Flow R 2344 2344 <halt> ; Flow R 2345 2345 <halt> ; Flow R 2346 2346 <halt> ; Flow R 2347 2347 <halt> ; Flow R 2348 2348 <halt> ; Flow R 2349 2349 <halt> ; Flow R 234a 234a <halt> ; Flow R 234b 234b <halt> ; Flow R 234c 234c <halt> ; Flow R 234d 234d <halt> ; Flow R 234e 234e <halt> ; Flow R 234f 234f <halt> ; Flow R 2350 2350 <halt> ; Flow R 2351 2351 <halt> ; Flow R 2352 2352 <halt> ; Flow R 2353 2353 <halt> ; Flow R 2354 2354 <halt> ; Flow R 2355 2355 <halt> ; Flow R 2356 2356 <halt> ; Flow R 2357 2357 <halt> ; Flow R 2358 2358 <halt> ; Flow R 2359 2359 <halt> ; Flow R 235a 235a <halt> ; Flow R 235b 235b <halt> ; Flow R 235c 235c <halt> ; Flow R 235d 235d <halt> ; Flow R 235e 235e <halt> ; Flow R 235f 235f <halt> ; Flow R 2360 2360 <halt> ; Flow R 2361 2361 <halt> ; Flow R 2362 2362 <halt> ; Flow R 2363 2363 <halt> ; Flow R 2364 2364 <halt> ; Flow R 2365 2365 <halt> ; Flow R 2366 2366 <halt> ; Flow R 2367 2367 <halt> ; Flow R 2368 2368 <halt> ; Flow R 2369 2369 <halt> ; Flow R 236a 236a <halt> ; Flow R 236b 236b <halt> ; Flow R 236c 236c <halt> ; Flow R 236d 236d <halt> ; Flow R 236e 236e <halt> ; Flow R 236f 236f <halt> ; Flow R 2370 2370 <halt> ; Flow R 2371 2371 <halt> ; Flow R 2372 2372 <halt> ; Flow R 2373 2373 <halt> ; Flow R 2374 2374 <halt> ; Flow R 2375 2375 <halt> ; Flow R 2376 2376 <halt> ; Flow R 2377 2377 <halt> ; Flow R 2378 2378 <halt> ; Flow R 2379 2379 <halt> ; Flow R 237a 237a <halt> ; Flow R 237b 237b <halt> ; Flow R 237c 237c <halt> ; Flow R 237d 237d <halt> ; Flow R 237e 237e <halt> ; Flow R 237f 237f <halt> ; Flow R 2380 2380 <halt> ; Flow R 2381 2381 <halt> ; Flow R 2382 2382 <halt> ; Flow R 2383 2383 <halt> ; Flow R 2384 2384 <halt> ; Flow R 2385 2385 <halt> ; Flow R 2386 2386 <halt> ; Flow R 2387 2387 <halt> ; Flow R 2388 2388 <halt> ; Flow R 2389 2389 <halt> ; Flow R 238a 238a <halt> ; Flow R 238b 238b <halt> ; Flow R 238c 238c <halt> ; Flow R 238d 238d <halt> ; Flow R 238e 238e <halt> ; Flow R 238f 238f <halt> ; Flow R 2390 2390 <halt> ; Flow R 2391 2391 <halt> ; Flow R 2392 2392 <halt> ; Flow R 2393 2393 <halt> ; Flow R 2394 2394 <halt> ; Flow R 2395 2395 <halt> ; Flow R 2396 2396 <halt> ; Flow R 2397 2397 <halt> ; Flow R 2398 2398 <halt> ; Flow R 2399 2399 <halt> ; Flow R 239a 239a <halt> ; Flow R 239b 239b <halt> ; Flow R 239c 239c <halt> ; Flow R 239d 239d <halt> ; Flow R 239e 239e <halt> ; Flow R 239f 239f <halt> ; Flow R 23a0 23a0 <halt> ; Flow R 23a1 23a1 <halt> ; Flow R 23a2 23a2 <halt> ; Flow R 23a3 23a3 <halt> ; Flow R 23a4 23a4 <halt> ; Flow R 23a5 23a5 <halt> ; Flow R 23a6 23a6 <halt> ; Flow R 23a7 23a7 <halt> ; Flow R 23a8 23a8 <halt> ; Flow R 23a9 23a9 <halt> ; Flow R 23aa 23aa <halt> ; Flow R 23ab 23ab <halt> ; Flow R 23ac 23ac <halt> ; Flow R 23ad 23ad <halt> ; Flow R 23ae 23ae <halt> ; Flow R 23af 23af <halt> ; Flow R 23b0 23b0 <halt> ; Flow R 23b1 23b1 <halt> ; Flow R 23b2 23b2 <halt> ; Flow R 23b3 23b3 <halt> ; Flow R 23b4 23b4 <halt> ; Flow R 23b5 23b5 <halt> ; Flow R 23b6 23b6 <halt> ; Flow R 23b7 23b7 <halt> ; Flow R 23b8 23b8 <halt> ; Flow R 23b9 23b9 <halt> ; Flow R 23ba 23ba <halt> ; Flow R 23bb 23bb <halt> ; Flow R 23bc 23bc <halt> ; Flow R 23bd 23bd <halt> ; Flow R 23be 23be <halt> ; Flow R 23bf 23bf <halt> ; Flow R 23c0 23c0 <halt> ; Flow R 23c1 23c1 <halt> ; Flow R 23c2 23c2 <halt> ; Flow R 23c3 23c3 <halt> ; Flow R 23c4 23c4 <halt> ; Flow R 23c5 23c5 <halt> ; Flow R 23c6 23c6 <halt> ; Flow R 23c7 23c7 <halt> ; Flow R 23c8 23c8 <halt> ; Flow R 23c9 23c9 <halt> ; Flow R 23ca 23ca <halt> ; Flow R 23cb 23cb <halt> ; Flow R 23cc 23cc <halt> ; Flow R 23cd 23cd <halt> ; Flow R 23ce 23ce <halt> ; Flow R 23cf 23cf <halt> ; Flow R 23d0 23d0 <halt> ; Flow R 23d1 23d1 <halt> ; Flow R 23d2 23d2 <halt> ; Flow R 23d3 23d3 <halt> ; Flow R 23d4 23d4 <halt> ; Flow R 23d5 23d5 <halt> ; Flow R 23d6 23d6 <halt> ; Flow R 23d7 23d7 <halt> ; Flow R 23d8 23d8 <halt> ; Flow R 23d9 23d9 <halt> ; Flow R 23da 23da <halt> ; Flow R 23db 23db <halt> ; Flow R 23dc 23dc <halt> ; Flow R 23dd 23dd <halt> ; Flow R 23de 23de <halt> ; Flow R 23df 23df <halt> ; Flow R 23e0 23e0 <halt> ; Flow R 23e1 23e1 <halt> ; Flow R 23e2 23e2 <halt> ; Flow R 23e3 23e3 <halt> ; Flow R 23e4 23e4 <halt> ; Flow R 23e5 23e5 <halt> ; Flow R 23e6 23e6 <halt> ; Flow R 23e7 23e7 <halt> ; Flow R 23e8 23e8 <halt> ; Flow R 23e9 23e9 <halt> ; Flow R 23ea 23ea <halt> ; Flow R 23eb 23eb <halt> ; Flow R 23ec 23ec <halt> ; Flow R 23ed 23ed <halt> ; Flow R 23ee 23ee <halt> ; Flow R 23ef 23ef <halt> ; Flow R 23f0 23f0 <halt> ; Flow R 23f1 23f1 <halt> ; Flow R 23f2 23f2 <halt> ; Flow R 23f3 23f3 <halt> ; Flow R 23f4 23f4 <halt> ; Flow R 23f5 23f5 <halt> ; Flow R 23f6 23f6 <halt> ; Flow R 23f7 23f7 <halt> ; Flow R 23f8 23f8 <halt> ; Flow R 23f9 23f9 <halt> ; Flow R 23fa 23fa <halt> ; Flow R 23fb 23fb <halt> ; Flow R 23fc 23fc <halt> ; Flow R 23fd 23fd <halt> ; Flow R 23fe 23fe <halt> ; Flow R 23ff 23ff <halt> ; Flow R 2400 ; -------------------------------------------------------------------------------------- 2400 ; Comes from: 2400 ; 0e3b C from color 0x0800 2400 ; 0e8e C from color 0x0e19 2400 ; -------------------------------------------------------------------------------------- 2400 2400 typ_c_adr 1d TR05:02 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2401 2401 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 05 GP05 val_alu_func 0 PASS_A 2402 2402 <default> 2403 2403 seq_br_type 0 Branch False; Flow J cc=False 0x2405 seq_branch_adr 2405 0x2405 seq_cond_sel 6b CACHE_MISS~ 2404 2404 typ_a_adr 22 TR05:02 typ_alu_func 7 INC_A typ_c_adr 1d TR05:02 typ_c_mux_sel 0 ALU typ_frame 5 2405 2405 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 30 VR1a:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 1a 2406 2406 seq_br_type 1 Branch True; Flow J cc=True 0x2401 seq_branch_adr 2401 0x2401 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 30 VR19:10 val_frame 19 2407 2407 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 13 ONES val_c_adr 1e VR05:01 val_c_mux_sel 2 ALU val_frame 5 2408 2408 val_alu_func 13 ONES val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2409 2409 typ_a_adr 30 TR1a:10 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 2d VR19:0d val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 19 240a 240a fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 21 TR18:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED 240b 240b ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 240c 240c typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 240d 240d fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 21 TR18:01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED 240e 240e typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 240f 240f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2410 2410 ioc_tvbs c mem+mem+csa+dummy val_a_adr 0e GP0e val_alu_func 7 INC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2411 2411 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 2412 2412 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2463 seq_br_type 1 Branch True seq_branch_adr 2463 0x2463 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0e GP0e val_alu_func 0 PASS_A 2413 2413 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2461 seq_br_type 1 Branch True seq_branch_adr 2461 0x2461 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2414 2414 val_alu_func 13 ONES val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2415 2415 ioc_random 10 load checkbit register typ_b_adr 2c TR12:0c typ_frame 12 2416 2416 fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 2d TR1a:0d typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1a typ_mar_cntl f LOAD_MAR_RESERVED 2417 2417 ioc_load_wdr 0 ioc_random 18 drive diagnostic checkbits typ_b_adr 04 GP04 val_b_adr 04 GP04 2418 2418 typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 2419 2419 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 21 TR18:01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED 241a 241a <default> 241b 241b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 241c 241c ioc_tvbs c mem+mem+csa+dummy val_a_adr 0e GP0e val_alu_func 7 INC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU 241d 241d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2463 seq_br_type 1 Branch True seq_branch_adr 2463 0x2463 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 0e GP0e val_alu_func 0 PASS_A 241e 241e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 241f 241f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 30 VR14:10 val_alu_func 7 INC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 14 2420 2420 typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 2421 2421 ioc_random 10 load checkbit register typ_b_adr 2c TR12:0c typ_frame 12 val_a_adr 3a VR1a:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2422 2422 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2423 2423 fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 35 TR1a:15 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1a typ_mar_cntl f LOAD_MAR_RESERVED 2424 2424 ioc_load_wdr 0 ioc_random 18 drive diagnostic checkbits typ_b_adr 04 GP04 val_b_adr 04 GP04 2425 2425 <default> 2426 2426 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 21 TR18:01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED 2427 2427 <default> 2428 2428 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2429 2429 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 242a 242a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245f seq_br_type 1 Branch True seq_branch_adr 245f 0x245f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 242b 242b val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 242c 242c seq_b_timing 0 Early Condition; Flow J cc=False 0x2423 seq_br_type 0 Branch False seq_branch_adr 2423 0x2423 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_rand 2 DEC_LOOP_COUNTER 242d 242d typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 33 VR1a:13 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1a 242e 242e typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 242f 242f ioc_random 10 load checkbit register typ_b_adr 2c TR12:0c typ_frame 12 val_a_adr 3a VR1a:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2430 2430 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2431 2431 fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 35 TR1a:15 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1a typ_mar_cntl b LOAD_MAR_DATA 2432 2432 ioc_load_wdr 0 ioc_random 18 drive diagnostic checkbits typ_b_adr 04 GP04 val_b_adr 04 GP04 2433 2433 <default> 2434 2434 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 21 TR18:01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA 2435 2435 <default> 2436 2436 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2437 2437 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 2438 2438 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245f seq_br_type 1 Branch True seq_branch_adr 245f 0x245f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2439 2439 val_a_adr 04 GP04 val_alu_func 4 LEFT_I_A_INC val_c_adr 3b GP04 val_c_mux_sel 2 ALU 243a 243a seq_b_timing 0 Early Condition; Flow J cc=False 0x2431 seq_br_type 0 Branch False seq_branch_adr 2431 0x2431 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_rand 2 DEC_LOOP_COUNTER 243b 243b typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 243c 243c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_mux_sel 2 ALU 243d 243d typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 243e 243e typ_a_adr 22 TR12:02 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 19 VR05:06 val_c_mux_sel 2 ALU val_frame 5 243f 243f typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 19 TR05:06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2440 2440 typ_a_adr 2c TR12:0c typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 2441 2441 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 26 TR05:06 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 2442 2442 ioc_random 10 load checkbit register typ_b_adr 05 GP05 2443 2443 fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_alu_func 1a PASS_B typ_b_adr 32 TR14:12 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA 2444 2444 ioc_load_wdr 0 ioc_random 18 drive diagnostic checkbits typ_b_adr 04 GP04 val_b_adr 04 GP04 2445 2445 <default> 2446 2446 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA 2447 2447 <default> 2448 2448 ioc_tvbs c mem+mem+csa+dummy 2449 2449 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 244a 244a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245f seq_br_type 1 Branch True seq_branch_adr 245f 0x245f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 26 VR05:06 val_frame 5 244b 244b typ_a_adr 26 TR05:06 typ_alu_func 3 LEFT_I_A typ_c_adr 19 TR05:06 typ_c_mux_sel 0 ALU typ_frame 5 244c 244c val_a_adr 26 VR05:06 val_alu_func 1c DEC_A val_c_adr 19 VR05:06 val_c_mux_sel 2 ALU val_frame 5 244d 244d seq_b_timing 0 Early Condition; Flow J cc=False 0x2440 seq_br_type 0 Branch False seq_branch_adr 2440 0x2440 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 244e 244e fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA 244f 244f typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 2450 2450 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2451 2451 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245d seq_br_type 1 Branch True seq_branch_adr 245d 0x245d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 2452 2452 typ_a_adr 2f TR1a:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 2e VR19:0e val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 19 2453 2453 ioc_random 10 load checkbit register typ_b_adr 2c TR12:0c typ_frame 12 val_a_adr 3a VR1a:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2454 2454 fiu_mem_start e start_physical_wr ioc_adrbs 1 val typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1a typ_mar_cntl f LOAD_MAR_RESERVED 2455 2455 ioc_load_wdr 0 ioc_random 18 drive diagnostic checkbits typ_b_adr 04 GP04 val_b_adr 04 GP04 2456 2456 typ_a_adr 20 TR05:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 2457 2457 fiu_mem_start d start_physical_rd ioc_adrbs 1 val typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl f LOAD_MAR_RESERVED 2458 2458 <default> 2459 2459 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 245a 245a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x245c seq_br_type 1 Branch True seq_branch_adr 245c 0x245c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 0e GP0e typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f 245b 245b seq_br_type a Unconditional Return; Flow R val_c_adr 1e VR05:01 val_c_mux_sel 2 ALU val_frame 5 245c 245c ioc_fiubs 2 typ ; Flow R ioc_random 14 clear cpu running seq_random 01 Halt+? typ_a_adr 0f GP0f val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 5 245d 245d ioc_fiubs 2 typ typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2a TR13:0a typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 13 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 5 245e 245e ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 5 245f 245f val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 1a 2460 2460 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 2461 2461 val_a_adr 2f VR19:0f val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 19 2462 2462 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 2463 2463 val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 13 2464 2464 ioc_random 14 clear cpu running; Flow R seq_random 01 Halt+? val_a_adr 0d GP0d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 5 2465 2465 <halt> ; Flow R 2466 2466 <halt> ; Flow R 2467 2467 <halt> ; Flow R 2468 2468 <halt> ; Flow R 2469 2469 <halt> ; Flow R 246a 246a <halt> ; Flow R 246b 246b <halt> ; Flow R 246c 246c <halt> ; Flow R 246d 246d <halt> ; Flow R 246e 246e <halt> ; Flow R 246f 246f <halt> ; Flow R 2470 2470 <halt> ; Flow R 2471 2471 <halt> ; Flow R 2472 2472 <halt> ; Flow R 2473 2473 <halt> ; Flow R 2474 2474 <halt> ; Flow R 2475 2475 <halt> ; Flow R 2476 2476 <halt> ; Flow R 2477 2477 <halt> ; Flow R 2478 2478 <halt> ; Flow R 2479 2479 <halt> ; Flow R 247a 247a <halt> ; Flow R 247b 247b <halt> ; Flow R 247c 247c <halt> ; Flow R 247d 247d <halt> ; Flow R 247e 247e <halt> ; Flow R 247f 247f <halt> ; Flow R 2480 2480 <halt> ; Flow R 2481 2481 <halt> ; Flow R 2482 2482 <halt> ; Flow R 2483 2483 <halt> ; Flow R 2484 2484 <halt> ; Flow R 2485 2485 <halt> ; Flow R 2486 2486 <halt> ; Flow R 2487 2487 <halt> ; Flow R 2488 2488 <halt> ; Flow R 2489 2489 <halt> ; Flow R 248a 248a <halt> ; Flow R 248b 248b <halt> ; Flow R 248c 248c <halt> ; Flow R 248d 248d <halt> ; Flow R 248e 248e <halt> ; Flow R 248f 248f <halt> ; Flow R 2490 2490 <halt> ; Flow R 2491 2491 <halt> ; Flow R 2492 2492 <halt> ; Flow R 2493 2493 <halt> ; Flow R 2494 2494 <halt> ; Flow R 2495 2495 <halt> ; Flow R 2496 2496 <halt> ; Flow R 2497 2497 <halt> ; Flow R 2498 2498 <halt> ; Flow R 2499 2499 <halt> ; Flow R 249a 249a <halt> ; Flow R 249b 249b <halt> ; Flow R 249c 249c <halt> ; Flow R 249d 249d <halt> ; Flow R 249e 249e <halt> ; Flow R 249f 249f <halt> ; Flow R 24a0 24a0 <halt> ; Flow R 24a1 24a1 <halt> ; Flow R 24a2 24a2 <halt> ; Flow R 24a3 24a3 <halt> ; Flow R 24a4 24a4 <halt> ; Flow R 24a5 24a5 <halt> ; Flow R 24a6 24a6 <halt> ; Flow R 24a7 24a7 <halt> ; Flow R 24a8 24a8 <halt> ; Flow R 24a9 24a9 <halt> ; Flow R 24aa 24aa <halt> ; Flow R 24ab 24ab <halt> ; Flow R 24ac 24ac <halt> ; Flow R 24ad 24ad <halt> ; Flow R 24ae 24ae <halt> ; Flow R 24af 24af <halt> ; Flow R 24b0 24b0 <halt> ; Flow R 24b1 24b1 <halt> ; Flow R 24b2 24b2 <halt> ; Flow R 24b3 24b3 <halt> ; Flow R 24b4 24b4 <halt> ; Flow R 24b5 24b5 <halt> ; Flow R 24b6 24b6 <halt> ; Flow R 24b7 24b7 <halt> ; Flow R 24b8 24b8 <halt> ; Flow R 24b9 24b9 <halt> ; Flow R 24ba 24ba <halt> ; Flow R 24bb 24bb <halt> ; Flow R 24bc 24bc <halt> ; Flow R 24bd 24bd <halt> ; Flow R 24be 24be <halt> ; Flow R 24bf 24bf <halt> ; Flow R 24c0 24c0 <halt> ; Flow R 24c1 24c1 <halt> ; Flow R 24c2 24c2 <halt> ; Flow R 24c3 24c3 <halt> ; Flow R 24c4 24c4 <halt> ; Flow R 24c5 24c5 <halt> ; Flow R 24c6 24c6 <halt> ; Flow R 24c7 24c7 <halt> ; Flow R 24c8 24c8 <halt> ; Flow R 24c9 24c9 <halt> ; Flow R 24ca 24ca <halt> ; Flow R 24cb 24cb <halt> ; Flow R 24cc 24cc <halt> ; Flow R 24cd 24cd <halt> ; Flow R 24ce 24ce <halt> ; Flow R 24cf 24cf <halt> ; Flow R 24d0 24d0 <halt> ; Flow R 24d1 24d1 <halt> ; Flow R 24d2 24d2 <halt> ; Flow R 24d3 24d3 <halt> ; Flow R 24d4 24d4 <halt> ; Flow R 24d5 24d5 <halt> ; Flow R 24d6 24d6 <halt> ; Flow R 24d7 24d7 <halt> ; Flow R 24d8 24d8 <halt> ; Flow R 24d9 24d9 <halt> ; Flow R 24da 24da <halt> ; Flow R 24db 24db <halt> ; Flow R 24dc 24dc <halt> ; Flow R 24dd 24dd <halt> ; Flow R 24de 24de <halt> ; Flow R 24df 24df <halt> ; Flow R 24e0 24e0 <halt> ; Flow R 24e1 24e1 <halt> ; Flow R 24e2 24e2 <halt> ; Flow R 24e3 24e3 <halt> ; Flow R 24e4 24e4 <halt> ; Flow R 24e5 24e5 <halt> ; Flow R 24e6 24e6 <halt> ; Flow R 24e7 24e7 <halt> ; Flow R 24e8 24e8 <halt> ; Flow R 24e9 24e9 <halt> ; Flow R 24ea 24ea <halt> ; Flow R 24eb 24eb <halt> ; Flow R 24ec 24ec <halt> ; Flow R 24ed 24ed <halt> ; Flow R 24ee 24ee <halt> ; Flow R 24ef 24ef <halt> ; Flow R 24f0 24f0 <halt> ; Flow R 24f1 24f1 <halt> ; Flow R 24f2 24f2 <halt> ; Flow R 24f3 24f3 <halt> ; Flow R 24f4 24f4 <halt> ; Flow R 24f5 24f5 <halt> ; Flow R 24f6 24f6 <halt> ; Flow R 24f7 24f7 <halt> ; Flow R 24f8 24f8 <halt> ; Flow R 24f9 24f9 <halt> ; Flow R 24fa 24fa <halt> ; Flow R 24fb 24fb <halt> ; Flow R 24fc 24fc <halt> ; Flow R 24fd 24fd <halt> ; Flow R 24fe 24fe <halt> ; Flow R 24ff 24ff <halt> ; Flow R 2500 2500 <halt> ; Flow R 2501 2501 <halt> ; Flow R 2502 2502 <halt> ; Flow R 2503 2503 <halt> ; Flow R 2504 2504 <halt> ; Flow R 2505 2505 <halt> ; Flow R 2506 2506 <halt> ; Flow R 2507 2507 <halt> ; Flow R 2508 2508 <halt> ; Flow R 2509 2509 <halt> ; Flow R 250a 250a <halt> ; Flow R 250b 250b <halt> ; Flow R 250c 250c <halt> ; Flow R 250d 250d <halt> ; Flow R 250e 250e <halt> ; Flow R 250f 250f <halt> ; Flow R 2510 2510 <halt> ; Flow R 2511 2511 <halt> ; Flow R 2512 2512 <halt> ; Flow R 2513 2513 <halt> ; Flow R 2514 2514 <halt> ; Flow R 2515 2515 <halt> ; Flow R 2516 2516 <halt> ; Flow R 2517 2517 <halt> ; Flow R 2518 2518 <halt> ; Flow R 2519 2519 <halt> ; Flow R 251a 251a <halt> ; Flow R 251b 251b <halt> ; Flow R 251c 251c <halt> ; Flow R 251d 251d <halt> ; Flow R 251e 251e <halt> ; Flow R 251f 251f <halt> ; Flow R 2520 2520 <halt> ; Flow R 2521 2521 <halt> ; Flow R 2522 2522 <halt> ; Flow R 2523 2523 <halt> ; Flow R 2524 2524 <halt> ; Flow R 2525 2525 <halt> ; Flow R 2526 2526 <halt> ; Flow R 2527 2527 <halt> ; Flow R 2528 2528 <halt> ; Flow R 2529 2529 <halt> ; Flow R 252a 252a <halt> ; Flow R 252b 252b <halt> ; Flow R 252c 252c <halt> ; Flow R 252d 252d <halt> ; Flow R 252e 252e <halt> ; Flow R 252f 252f <halt> ; Flow R 2530 2530 <halt> ; Flow R 2531 2531 <halt> ; Flow R 2532 2532 <halt> ; Flow R 2533 2533 <halt> ; Flow R 2534 2534 <halt> ; Flow R 2535 2535 <halt> ; Flow R 2536 2536 <halt> ; Flow R 2537 2537 <halt> ; Flow R 2538 2538 <halt> ; Flow R 2539 2539 <halt> ; Flow R 253a 253a <halt> ; Flow R 253b 253b <halt> ; Flow R 253c 253c <halt> ; Flow R 253d 253d <halt> ; Flow R 253e 253e <halt> ; Flow R 253f 253f <halt> ; Flow R 2540 2540 <halt> ; Flow R 2541 2541 <halt> ; Flow R 2542 2542 <halt> ; Flow R 2543 2543 <halt> ; Flow R 2544 2544 <halt> ; Flow R 2545 2545 <halt> ; Flow R 2546 2546 <halt> ; Flow R 2547 2547 <halt> ; Flow R 2548 2548 <halt> ; Flow R 2549 2549 <halt> ; Flow R 254a 254a <halt> ; Flow R 254b 254b <halt> ; Flow R 254c 254c <halt> ; Flow R 254d 254d <halt> ; Flow R 254e 254e <halt> ; Flow R 254f 254f <halt> ; Flow R 2550 2550 <halt> ; Flow R 2551 2551 <halt> ; Flow R 2552 2552 <halt> ; Flow R 2553 2553 <halt> ; Flow R 2554 2554 <halt> ; Flow R 2555 2555 <halt> ; Flow R 2556 2556 <halt> ; Flow R 2557 2557 <halt> ; Flow R 2558 2558 <halt> ; Flow R 2559 2559 <halt> ; Flow R 255a 255a <halt> ; Flow R 255b 255b <halt> ; Flow R 255c 255c <halt> ; Flow R 255d 255d <halt> ; Flow R 255e 255e <halt> ; Flow R 255f 255f <halt> ; Flow R 2560 2560 <halt> ; Flow R 2561 2561 <halt> ; Flow R 2562 2562 <halt> ; Flow R 2563 2563 <halt> ; Flow R 2564 2564 <halt> ; Flow R 2565 2565 <halt> ; Flow R 2566 2566 <halt> ; Flow R 2567 2567 <halt> ; Flow R 2568 2568 <halt> ; Flow R 2569 2569 <halt> ; Flow R 256a 256a <halt> ; Flow R 256b 256b <halt> ; Flow R 256c 256c <halt> ; Flow R 256d 256d <halt> ; Flow R 256e 256e <halt> ; Flow R 256f 256f <halt> ; Flow R 2570 2570 <halt> ; Flow R 2571 2571 <halt> ; Flow R 2572 2572 <halt> ; Flow R 2573 2573 <halt> ; Flow R 2574 2574 <halt> ; Flow R 2575 2575 <halt> ; Flow R 2576 2576 <halt> ; Flow R 2577 2577 <halt> ; Flow R 2578 2578 <halt> ; Flow R 2579 2579 <halt> ; Flow R 257a 257a <halt> ; Flow R 257b 257b <halt> ; Flow R 257c 257c <halt> ; Flow R 257d 257d <halt> ; Flow R 257e 257e <halt> ; Flow R 257f 257f <halt> ; Flow R 2580 2580 <halt> ; Flow R 2581 2581 <halt> ; Flow R 2582 2582 <halt> ; Flow R 2583 2583 <halt> ; Flow R 2584 2584 <halt> ; Flow R 2585 2585 <halt> ; Flow R 2586 2586 <halt> ; Flow R 2587 2587 <halt> ; Flow R 2588 2588 <halt> ; Flow R 2589 2589 <halt> ; Flow R 258a 258a <halt> ; Flow R 258b 258b <halt> ; Flow R 258c 258c <halt> ; Flow R 258d 258d <halt> ; Flow R 258e 258e <halt> ; Flow R 258f 258f <halt> ; Flow R 2590 2590 <halt> ; Flow R 2591 2591 <halt> ; Flow R 2592 2592 <halt> ; Flow R 2593 2593 <halt> ; Flow R 2594 2594 <halt> ; Flow R 2595 2595 <halt> ; Flow R 2596 2596 <halt> ; Flow R 2597 2597 <halt> ; Flow R 2598 2598 <halt> ; Flow R 2599 2599 <halt> ; Flow R 259a 259a <halt> ; Flow R 259b 259b <halt> ; Flow R 259c 259c <halt> ; Flow R 259d 259d <halt> ; Flow R 259e 259e <halt> ; Flow R 259f 259f <halt> ; Flow R 25a0 25a0 <halt> ; Flow R 25a1 25a1 <halt> ; Flow R 25a2 25a2 <halt> ; Flow R 25a3 25a3 <halt> ; Flow R 25a4 25a4 <halt> ; Flow R 25a5 25a5 <halt> ; Flow R 25a6 25a6 <halt> ; Flow R 25a7 25a7 <halt> ; Flow R 25a8 25a8 <halt> ; Flow R 25a9 25a9 <halt> ; Flow R 25aa 25aa <halt> ; Flow R 25ab 25ab <halt> ; Flow R 25ac 25ac <halt> ; Flow R 25ad 25ad <halt> ; Flow R 25ae 25ae <halt> ; Flow R 25af 25af <halt> ; Flow R 25b0 25b0 <halt> ; Flow R 25b1 25b1 <halt> ; Flow R 25b2 25b2 <halt> ; Flow R 25b3 25b3 <halt> ; Flow R 25b4 25b4 <halt> ; Flow R 25b5 25b5 <halt> ; Flow R 25b6 25b6 <halt> ; Flow R 25b7 25b7 <halt> ; Flow R 25b8 25b8 <halt> ; Flow R 25b9 25b9 <halt> ; Flow R 25ba 25ba <halt> ; Flow R 25bb 25bb <halt> ; Flow R 25bc 25bc <halt> ; Flow R 25bd 25bd <halt> ; Flow R 25be 25be <halt> ; Flow R 25bf 25bf <halt> ; Flow R 25c0 25c0 <halt> ; Flow R 25c1 25c1 <halt> ; Flow R 25c2 25c2 <halt> ; Flow R 25c3 25c3 <halt> ; Flow R 25c4 25c4 <halt> ; Flow R 25c5 25c5 <halt> ; Flow R 25c6 25c6 <halt> ; Flow R 25c7 25c7 <halt> ; Flow R 25c8 25c8 <halt> ; Flow R 25c9 25c9 <halt> ; Flow R 25ca 25ca <halt> ; Flow R 25cb 25cb <halt> ; Flow R 25cc 25cc <halt> ; Flow R 25cd 25cd <halt> ; Flow R 25ce 25ce <halt> ; Flow R 25cf 25cf <halt> ; Flow R 25d0 25d0 <halt> ; Flow R 25d1 25d1 <halt> ; Flow R 25d2 25d2 <halt> ; Flow R 25d3 25d3 <halt> ; Flow R 25d4 25d4 <halt> ; Flow R 25d5 25d5 <halt> ; Flow R 25d6 25d6 <halt> ; Flow R 25d7 25d7 <halt> ; Flow R 25d8 25d8 <halt> ; Flow R 25d9 25d9 <halt> ; Flow R 25da 25da <halt> ; Flow R 25db 25db <halt> ; Flow R 25dc 25dc <halt> ; Flow R 25dd 25dd <halt> ; Flow R 25de 25de <halt> ; Flow R 25df 25df <halt> ; Flow R 25e0 25e0 <halt> ; Flow R 25e1 25e1 <halt> ; Flow R 25e2 25e2 <halt> ; Flow R 25e3 25e3 <halt> ; Flow R 25e4 25e4 <halt> ; Flow R 25e5 25e5 <halt> ; Flow R 25e6 25e6 <halt> ; Flow R 25e7 25e7 <halt> ; Flow R 25e8 25e8 <halt> ; Flow R 25e9 25e9 <halt> ; Flow R 25ea 25ea <halt> ; Flow R 25eb 25eb <halt> ; Flow R 25ec 25ec <halt> ; Flow R 25ed 25ed <halt> ; Flow R 25ee 25ee <halt> ; Flow R 25ef 25ef <halt> ; Flow R 25f0 25f0 <halt> ; Flow R 25f1 25f1 <halt> ; Flow R 25f2 25f2 <halt> ; Flow R 25f3 25f3 <halt> ; Flow R 25f4 25f4 <halt> ; Flow R 25f5 25f5 <halt> ; Flow R 25f6 25f6 <halt> ; Flow R 25f7 25f7 <halt> ; Flow R 25f8 25f8 <halt> ; Flow R 25f9 25f9 <halt> ; Flow R 25fa 25fa <halt> ; Flow R 25fb 25fb <halt> ; Flow R 25fc 25fc <halt> ; Flow R 25fd 25fd <halt> ; Flow R 25fe 25fe <halt> ; Flow R 25ff 25ff <halt> ; Flow R 2600 ; -------------------------------------------------------------------------------------- 2600 ; Comes from: 2600 ; 0e2d C from color 0x0800 2600 ; 0e4f C from color 0x0e05 2600 ; 0e64 C from color 0x0e0b 2600 ; -------------------------------------------------------------------------------------- 2600 2600 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2601 2601 seq_br_type 7 Unconditional Call; Flow C 0x26d4 seq_branch_adr 26d4 0x26d4 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2602 2602 seq_br_type 7 Unconditional Call; Flow C 0x26d4 seq_branch_adr 26d4 0x26d4 typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2603 2603 typ_b_adr 29 TR12:09 typ_frame 12 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2604 2604 seq_br_type 7 Unconditional Call; Flow C 0x26d4 seq_branch_adr 26d4 0x26d4 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2605 2605 seq_br_type 7 Unconditional Call; Flow C 0x26d4 seq_branch_adr 26d4 0x26d4 typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2606 2606 typ_a_adr 24 TR12:04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 12 2607 2607 seq_br_type 7 Unconditional Call; Flow C 0x26d9 seq_branch_adr 26d9 0x26d9 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2608 2608 seq_br_type 7 Unconditional Call; Flow C 0x26d9 seq_branch_adr 26d9 0x26d9 typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2609 2609 typ_a_adr 27 TR12:07 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 12 260a 260a seq_br_type 7 Unconditional Call; Flow C 0x26d9 seq_branch_adr 26d9 0x26d9 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 260b 260b seq_br_type 7 Unconditional Call; Flow C 0x26d9 seq_branch_adr 26d9 0x26d9 typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 260c 260c typ_b_adr 29 TR12:09 typ_frame 12 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 260d 260d typ_a_adr 24 TR12:04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 12 260e 260e seq_br_type 1 Branch True; Flow J cc=True 0x2610 seq_branch_adr 2610 0x2610 seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late) typ_a_adr 09 GP09 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 260f 260f seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 2610 2610 seq_br_type 1 Branch True; Flow J cc=True 0x2612 seq_branch_adr 2612 0x2612 seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late) typ_b_adr 09 GP09 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2611 2611 seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 2612 2612 typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2613 2613 typ_a_adr 27 TR12:07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 12 2614 2614 seq_br_type 1 Branch True; Flow J cc=True 0x2616 seq_branch_adr 2616 0x2616 seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late) typ_a_adr 09 GP09 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 2615 2615 seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 2616 2616 seq_br_type 1 Branch True; Flow J cc=True 0x2618 seq_branch_adr 2618 0x2618 seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late) typ_b_adr 09 GP09 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2617 2617 seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 2618 2618 typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_a_adr 32 VR1a:12 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2619 2619 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 23 TR12:03 typ_b_adr 29 TR12:09 typ_frame 12 261a 261a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 29 TR12:09 typ_b_adr 23 TR12:03 typ_frame 12 261b 261b seq_br_type 1 Branch True; Flow J cc=True 0x261d seq_branch_adr 261d 0x261d seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 29 TR12:09 typ_b_adr 29 TR12:09 typ_frame 12 261c 261c seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 261d 261d seq_br_type 1 Branch True; Flow J cc=True 0x261f seq_branch_adr 261f 0x261f seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 27 TR12:07 typ_b_adr 29 TR12:09 typ_frame 12 261e 261e seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 261f 261f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 26 TR12:06 typ_b_adr 29 TR12:09 typ_frame 12 2620 2620 seq_br_type 1 Branch True; Flow J cc=True 0x2622 seq_branch_adr 2622 0x2622 seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 29 TR12:09 typ_b_adr 27 TR12:07 typ_frame 12 2621 2621 seq_br_type 3 Unconditional Branch; Flow J 0x26df seq_branch_adr 26df 0x26df 2622 2622 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 29 TR12:09 typ_b_adr 26 TR12:06 typ_frame 12 2623 2623 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 27 TR12:07 typ_b_adr 24 TR12:04 typ_frame 12 2624 2624 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 24 TR12:04 typ_b_adr 27 TR12:07 typ_frame 12 2625 2625 seq_br_type 1 Branch True; Flow J cc=True 0x2626 seq_branch_adr 2626 0x2626 seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late) typ_a_adr 27 TR12:07 typ_b_adr 27 TR12:07 typ_frame 12 2626 2626 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3e VR14:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2627 2627 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2628 2628 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 24 TR18:04 typ_frame 18 typ_rand d SET_PASS_PRIVACY_BIT 2629 2629 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 24 TR18:04 typ_b_adr 08 GP08 typ_frame 18 262a 262a seq_b_timing 0 Early Condition; Flow J cc=False 0x2628 seq_br_type 0 Branch False seq_branch_adr 2628 0x2628 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 262b 262b typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 262c 262c typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 262d 262d seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 24 TR18:04 typ_frame 18 typ_rand d SET_PASS_PRIVACY_BIT 262e 262e seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 24 TR18:04 typ_b_adr 08 GP08 typ_frame 18 262f 262f seq_b_timing 0 Early Condition; Flow J cc=False 0x262d seq_br_type 0 Branch False seq_branch_adr 262d 0x262d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2630 2630 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 2631 2631 typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2632 2632 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 29 TR12:09 typ_frame 12 typ_rand d SET_PASS_PRIVACY_BIT 2633 2633 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 08 GP08 typ_frame 12 2634 2634 seq_b_timing 0 Early Condition; Flow J cc=False 0x2632 seq_br_type 0 Branch False seq_branch_adr 2632 0x2632 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2635 2635 typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 2636 2636 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 2637 2637 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 29 TR12:09 typ_frame 12 typ_rand d SET_PASS_PRIVACY_BIT 2638 2638 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 08 GP08 typ_frame 12 2639 2639 seq_b_timing 0 Early Condition; Flow J cc=False 0x2637 seq_br_type 0 Branch False seq_branch_adr 2637 0x2637 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 263a 263a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 24 TR18:04 typ_b_adr 24 TR18:04 typ_frame 18 263b 263b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 29 TR12:09 typ_frame 12 263c 263c typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 34 VR14:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 263d 263d typ_a_adr 27 TR14:07 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 14 263e 263e typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1a 263f 263f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 06 GP06 typ_rand d SET_PASS_PRIVACY_BIT 2640 2640 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 08 GP08 2641 2641 seq_b_timing 0 Early Condition; Flow J cc=False 0x263f seq_br_type 0 Branch False seq_branch_adr 263f 0x263f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2642 2642 typ_a_adr 3c TR1a:1c typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1a 2643 2643 typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 2644 2644 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 06 GP06 typ_rand d SET_PASS_PRIVACY_BIT 2645 2645 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 08 GP08 2646 2646 seq_b_timing 0 Early Condition; Flow J cc=False 0x2644 seq_br_type 0 Branch False seq_branch_adr 2644 0x2644 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2647 2647 typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 2648 2648 typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1a 2649 2649 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 29 TR12:09 typ_frame 12 typ_rand d SET_PASS_PRIVACY_BIT 264a 264a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 08 GP08 typ_frame 12 264b 264b seq_b_timing 0 Early Condition; Flow J cc=False 0x2649 seq_br_type 0 Branch False seq_branch_adr 2649 0x2649 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 264c 264c typ_a_adr 36 TR12:16 typ_alu_func 10 NOT_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 264d 264d typ_a_adr 39 TR13:19 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 264e 264e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 29 TR12:09 typ_frame 12 typ_rand d SET_PASS_PRIVACY_BIT 264f 264f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 08 GP08 typ_frame 12 2650 2650 seq_b_timing 0 Early Condition; Flow J cc=False 0x264e seq_br_type 0 Branch False seq_branch_adr 264e 0x264e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2651 2651 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 06 GP06 2652 2652 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 29 TR12:09 typ_b_adr 29 TR12:09 typ_frame 12 2653 2653 typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2654 2654 typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2655 2655 typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 2656 2656 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 34 VR14:14 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2657 2657 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2658 2658 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 23 TR12:03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 2659 2659 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 34 VR14:14 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 265a 265a seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 265b 265b typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 29 TR18:09 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 265c 265c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 34 VR14:14 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 265d 265d seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 265e 265e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 23 TR12:03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 265f 265f seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 34 VR14:14 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2660 2660 seq_br_type 0 Branch False; Flow J cc=False 0x26df seq_branch_adr 26df 0x26df seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 val_a_adr 2d VR1a:0d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2661 2661 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2662 2662 seq_b_timing 0 Early Condition; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) 2663 2663 seq_b_timing 0 Early Condition; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) 2664 2664 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER 2665 2665 seq_b_timing 0 Early Condition; Flow J cc=False 0x26df seq_br_type 0 Branch False seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) 2666 2666 seq_b_timing 0 Early Condition; Flow J cc=False 0x26df seq_br_type 0 Branch False seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) 2667 2667 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT 2668 2668 seq_b_timing 0 Early Condition; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER 2669 2669 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP 266a 266a seq_b_timing 0 Early Condition; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER 266b 266b seq_en_micro 0 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP 266c 266c seq_b_timing 0 Early Condition; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 34 TYP.PASS_PRIVACY_BIT (early) 266d 266d typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 266e 266e seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 18 266f 266f typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2670 2670 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 2671 2671 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2672 2672 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 12 2673 2673 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2674 2674 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 2675 2675 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2676 2676 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 12 2677 2677 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2678 2678 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 2679 2679 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 267a 267a seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 24 TR18:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 18 267b 267b typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 267c 267c seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 267d 267d typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 267e 267e seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 23 TR12:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 12 267f 267f seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2680 2680 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 2681 2681 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2682 2682 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 18 2683 2683 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2684 2684 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 2685 2685 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2686 2686 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 24 TR12:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 12 2687 2687 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2688 2688 seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 2689 2689 seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 268a 268a seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 24 TR18:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 18 268b 268b seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_a_adr 10 TOP typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP val_a_adr 3d VR14:1d val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 268c 268c seq_br_type 7 Unconditional Call; Flow C 0x26c9 seq_branch_adr 26c9 0x26c9 268d 268d seq_br_type 7 Unconditional Call; Flow C 0x26d0 seq_branch_adr 26d0 0x26d0 typ_b_adr 10 TOP typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 268e 268e typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 268f 268f seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 18 2690 2690 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2691 2691 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 2692 2692 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2693 2693 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 12 2694 2694 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2695 2695 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 2696 2696 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2697 2697 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 12 2698 2698 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 2699 2699 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca 269a 269a seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 269b 269b seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 24 TR18:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 18 269c 269c typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 269d 269d seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 269e 269e typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 269f 269f seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 23 TR12:03 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 12 26a0 26a0 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26a1 26a1 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca 26a2 26a2 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26a3 26a3 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR18:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 18 26a4 26a4 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26a5 26a5 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca 26a6 26a6 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26a7 26a7 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR12:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 12 26a8 26a8 seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26a9 26a9 seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca 26aa 26aa seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26ab 26ab seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 24 TR18:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 18 26ac 26ac seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_a_adr 1f TOP - 1 typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP val_a_adr 2e VR13:0e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26ad 26ad seq_br_type 7 Unconditional Call; Flow C 0x26ca seq_branch_adr 26ca 0x26ca 26ae 26ae seq_br_type 7 Unconditional Call; Flow C 0x26d2 seq_branch_adr 26d2 0x26d2 typ_b_adr 1f TOP - 1 typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP val_a_adr 34 VR13:14 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26af 26af seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_a_adr 34 VR13:14 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 26b0 26b0 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 24 TR18:04 typ_b_adr 24 TR18:04 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26b1 26b1 seq_br_type 7 Unconditional Call; Flow C 0x26c8 seq_branch_adr 26c8 0x26c8 typ_a_adr 24 TR12:04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 26b2 26b2 seq_br_type 7 Unconditional Call; Flow C 0x26ce seq_branch_adr 26ce 0x26ce typ_a_adr 03 GP03 typ_b_adr 24 TR18:04 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26b3 26b3 typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_a_adr 36 VR19:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 26b4 26b4 typ_a_adr 24 TR12:04 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 26b5 26b5 seq_br_type 7 Unconditional Call; Flow C 0x26c7 seq_branch_adr 26c7 0x26c7 typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 26b6 26b6 seq_br_type 7 Unconditional Call; Flow C 0x26cc seq_branch_adr 26cc 0x26cc typ_a_adr 04 GP04 typ_b_adr 22 TR18:02 typ_frame 18 typ_priv_check 0 CHECK_BINARY_EQ 26b7 26b7 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb 26b8 26b8 seq_br_type 7 Unconditional Call; Flow C 0x26c7 seq_branch_adr 26c7 0x26c7 typ_a_adr 24 TR12:04 typ_b_adr 23 TR12:03 typ_frame 12 typ_priv_check 0 CHECK_BINARY_EQ 26b9 26b9 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 26ba 26ba seq_br_type 7 Unconditional Call; Flow C 0x26cc seq_branch_adr 26cc 0x26cc typ_a_adr 23 TR12:03 typ_b_adr 03 GP03 typ_frame 12 typ_priv_check 0 CHECK_BINARY_EQ 26bb 26bb seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_b_adr 22 TR18:02 typ_frame 18 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_a_adr 36 VR19:16 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 26bc 26bc seq_br_type 7 Unconditional Call; Flow C 0x26c8 seq_branch_adr 26c8 0x26c8 typ_a_adr 24 TR18:04 typ_b_adr 24 TR18:04 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26bd 26bd seq_br_type 7 Unconditional Call; Flow C 0x26ce seq_branch_adr 26ce 0x26ce typ_a_adr 22 TR18:02 typ_b_adr 22 TR18:02 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26be 26be seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_a_adr 24 TR18:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 18 26bf 26bf typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 12 26c0 26c0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_priv_check 1 CHECK_BINARY_OP 26c1 26c1 seq_br_type 7 Unconditional Call; Flow C 0x26cb seq_branch_adr 26cb 0x26cb typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER 26c2 26c2 typ_a_adr 22 TR18:02 typ_b_adr 22 TR18:02 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26c3 26c3 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT typ_rand 2 DEC_LOOP_COUNTER 26c4 26c4 seq_br_type 7 Unconditional Call; Flow C 0x26c8 seq_branch_adr 26c8 0x26c8 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT 26c5 26c5 typ_a_adr 22 TR18:02 typ_b_adr 22 TR18:02 typ_frame 18 typ_priv_check 1 CHECK_BINARY_OP 26c6 26c6 seq_br_type a Unconditional Return; Flow R 26c7 ; -------------------------------------------------------------------------------------- 26c7 ; Comes from: 26c7 ; 26b5 C from color UE_BIN_EQ 26c7 ; 26b8 C from color UE_BIN_EQ 26c7 ; -------------------------------------------------------------------------------------- 26c7 26c7 seq_br_type a Unconditional Return; Flow R typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26c8 ; -------------------------------------------------------------------------------------- 26c8 ; Comes from: 26c8 ; 26b1 C from color UE_BIN_EQ 26c8 ; 26bc C from color UE_BIN_EQ 26c8 ; 26c4 C from color UE_BIN_EQ 26c8 ; -------------------------------------------------------------------------------------- 26c8 26c8 seq_br_type a Unconditional Return; Flow R typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26c9 ; -------------------------------------------------------------------------------------- 26c9 ; Comes from: 26c9 ; 2676 C from color UE_BIN_EQ 26c9 ; 2678 C from color UE_BIN_EQ 26c9 ; 267e C from color UE_BIN_EQ 26c9 ; 2680 C from color UE_BIN_EQ 26c9 ; 2682 C from color UE_BIN_EQ 26c9 ; 2684 C from color UE_BIN_EQ 26c9 ; 2686 C from color UE_BIN_EQ 26c9 ; 2688 C from color UE_BIN_EQ 26c9 ; 268a C from color UE_BIN_EQ 26c9 ; 268c C from color UE_BIN_EQ 26c9 ; -------------------------------------------------------------------------------------- 26c9 26c9 seq_br_type a Unconditional Return; Flow R typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26ca ; -------------------------------------------------------------------------------------- 26ca ; Comes from: 26ca ; 2697 C from color UE_BIN_EQ 26ca ; 2699 C from color UE_BIN_EQ 26ca ; 269f C from color UE_BIN_EQ 26ca ; 26a1 C from color UE_BIN_EQ 26ca ; 26a3 C from color UE_BIN_EQ 26ca ; 26a5 C from color UE_BIN_EQ 26ca ; 26a7 C from color UE_BIN_EQ 26ca ; 26a9 C from color UE_BIN_EQ 26ca ; 26ab C from color UE_BIN_EQ 26ca ; 26ad C from color UE_BIN_EQ 26ca ; -------------------------------------------------------------------------------------- 26ca 26ca seq_br_type a Unconditional Return; Flow R typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26cb ; -------------------------------------------------------------------------------------- 26cb ; Comes from: 26cb ; 2600 C from color UE_BIN_EQ 26cb ; 266e C from color UE_BIN_EQ 26cb ; 2670 C from color UE_BIN_EQ 26cb ; 2672 C from color UE_BIN_EQ 26cb ; 2674 C from color UE_BIN_EQ 26cb ; 267a C from color UE_BIN_EQ 26cb ; 267c C from color UE_BIN_EQ 26cb ; 268f C from color UE_BIN_EQ 26cb ; 2691 C from color UE_BIN_EQ 26cb ; 2693 C from color UE_BIN_EQ 26cb ; 2695 C from color UE_BIN_EQ 26cb ; 269b C from color UE_BIN_EQ 26cb ; 269d C from color UE_BIN_EQ 26cb ; 26af C from color UE_BIN_EQ 26cb ; 26b0 C from color UE_BIN_EQ 26cb ; 26b7 C from color UE_BIN_EQ 26cb ; 26bb C from color UE_BIN_EQ 26cb ; 26be C from color UE_BIN_EQ 26cb ; 26c1 C from color UE_BIN_EQ 26cb ; -------------------------------------------------------------------------------------- 26cb 26cb seq_br_type a Unconditional Return; Flow R typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26cc 26cc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR19:11 val_frame 19 26cd 26cd seq_br_type a Unconditional Return; Flow R val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26ce 26ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 32 VR1a:12 val_frame 1a 26cf 26cf seq_br_type a Unconditional Return; Flow R val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26d0 26d0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 3d VR14:1d val_frame 14 26d1 26d1 seq_br_type a Unconditional Return; Flow R val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26d2 26d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 3e VR14:1e val_frame 14 26d3 26d3 seq_br_type a Unconditional Return; Flow R val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 14 26d4 26d4 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 26d5 26d5 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 24 TR12:04 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 6 CHECK_CLASS_A_??_B 26d6 26d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late) typ_a_adr 09 GP09 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 26d7 26d7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_b_adr 09 GP09 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 26d8 26d8 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x26d5 seq_br_type 8 Return True seq_branch_adr 26d5 0x26d5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 26d9 26d9 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 13 26da 26da typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 24 TR12:04 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 12 typ_rand 6 CHECK_CLASS_A_??_B 26db 26db typ_b_adr 09 GP09 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26dc 26dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late) typ_a_adr 06 GP06 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 26dd 26dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26df seq_br_type 1 Branch True seq_branch_adr 26df 0x26df seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late) typ_a_adr 08 GP08 typ_alu_func 3 LEFT_I_A typ_b_adr 06 GP06 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 26de 26de seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x26da seq_br_type 8 Return True seq_branch_adr 26da 0x26da seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 26df 26df val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 26e0 26e0 <halt> ; Flow R 26e1 26e1 <halt> ; Flow R 26e2 26e2 <halt> ; Flow R 26e3 26e3 <halt> ; Flow R 26e4 26e4 <halt> ; Flow R 26e5 26e5 <halt> ; Flow R 26e6 26e6 <halt> ; Flow R 26e7 26e7 <halt> ; Flow R 26e8 26e8 <halt> ; Flow R 26e9 26e9 <halt> ; Flow R 26ea 26ea <halt> ; Flow R 26eb 26eb <halt> ; Flow R 26ec 26ec <halt> ; Flow R 26ed 26ed <halt> ; Flow R 26ee 26ee <halt> ; Flow R 26ef 26ef <halt> ; Flow R 26f0 26f0 <halt> ; Flow R 26f1 26f1 <halt> ; Flow R 26f2 26f2 <halt> ; Flow R 26f3 26f3 <halt> ; Flow R 26f4 26f4 <halt> ; Flow R 26f5 26f5 <halt> ; Flow R 26f6 26f6 <halt> ; Flow R 26f7 26f7 <halt> ; Flow R 26f8 26f8 <halt> ; Flow R 26f9 26f9 <halt> ; Flow R 26fa 26fa <halt> ; Flow R 26fb 26fb <halt> ; Flow R 26fc 26fc <halt> ; Flow R 26fd 26fd <halt> ; Flow R 26fe 26fe <halt> ; Flow R 26ff 26ff <halt> ; Flow R 2700 2700 <halt> ; Flow R 2701 2701 <halt> ; Flow R 2702 2702 <halt> ; Flow R 2703 2703 <halt> ; Flow R 2704 2704 <halt> ; Flow R 2705 2705 <halt> ; Flow R 2706 2706 <halt> ; Flow R 2707 2707 <halt> ; Flow R 2708 2708 <halt> ; Flow R 2709 2709 <halt> ; Flow R 270a 270a <halt> ; Flow R 270b 270b <halt> ; Flow R 270c 270c <halt> ; Flow R 270d 270d <halt> ; Flow R 270e 270e <halt> ; Flow R 270f 270f <halt> ; Flow R 2710 2710 <halt> ; Flow R 2711 2711 <halt> ; Flow R 2712 2712 <halt> ; Flow R 2713 2713 <halt> ; Flow R 2714 2714 <halt> ; Flow R 2715 2715 <halt> ; Flow R 2716 2716 <halt> ; Flow R 2717 2717 <halt> ; Flow R 2718 2718 <halt> ; Flow R 2719 2719 <halt> ; Flow R 271a 271a <halt> ; Flow R 271b 271b <halt> ; Flow R 271c 271c <halt> ; Flow R 271d 271d <halt> ; Flow R 271e 271e <halt> ; Flow R 271f 271f <halt> ; Flow R 2720 2720 <halt> ; Flow R 2721 2721 <halt> ; Flow R 2722 2722 <halt> ; Flow R 2723 2723 <halt> ; Flow R 2724 2724 <halt> ; Flow R 2725 2725 <halt> ; Flow R 2726 2726 <halt> ; Flow R 2727 2727 <halt> ; Flow R 2728 2728 <halt> ; Flow R 2729 2729 <halt> ; Flow R 272a 272a <halt> ; Flow R 272b 272b <halt> ; Flow R 272c 272c <halt> ; Flow R 272d 272d <halt> ; Flow R 272e 272e <halt> ; Flow R 272f 272f <halt> ; Flow R 2730 2730 <halt> ; Flow R 2731 2731 <halt> ; Flow R 2732 2732 <halt> ; Flow R 2733 2733 <halt> ; Flow R 2734 2734 <halt> ; Flow R 2735 2735 <halt> ; Flow R 2736 2736 <halt> ; Flow R 2737 2737 <halt> ; Flow R 2738 2738 <halt> ; Flow R 2739 2739 <halt> ; Flow R 273a 273a <halt> ; Flow R 273b 273b <halt> ; Flow R 273c 273c <halt> ; Flow R 273d 273d <halt> ; Flow R 273e 273e <halt> ; Flow R 273f 273f <halt> ; Flow R 2740 2740 <halt> ; Flow R 2741 2741 <halt> ; Flow R 2742 2742 <halt> ; Flow R 2743 2743 <halt> ; Flow R 2744 2744 <halt> ; Flow R 2745 2745 <halt> ; Flow R 2746 2746 <halt> ; Flow R 2747 2747 <halt> ; Flow R 2748 2748 <halt> ; Flow R 2749 2749 <halt> ; Flow R 274a 274a <halt> ; Flow R 274b 274b <halt> ; Flow R 274c 274c <halt> ; Flow R 274d 274d <halt> ; Flow R 274e 274e <halt> ; Flow R 274f 274f <halt> ; Flow R 2750 2750 <halt> ; Flow R 2751 2751 <halt> ; Flow R 2752 2752 <halt> ; Flow R 2753 2753 <halt> ; Flow R 2754 2754 <halt> ; Flow R 2755 2755 <halt> ; Flow R 2756 2756 <halt> ; Flow R 2757 2757 <halt> ; Flow R 2758 2758 <halt> ; Flow R 2759 2759 <halt> ; Flow R 275a 275a <halt> ; Flow R 275b 275b <halt> ; Flow R 275c 275c <halt> ; Flow R 275d 275d <halt> ; Flow R 275e 275e <halt> ; Flow R 275f 275f <halt> ; Flow R 2760 2760 <halt> ; Flow R 2761 2761 <halt> ; Flow R 2762 2762 <halt> ; Flow R 2763 2763 <halt> ; Flow R 2764 2764 <halt> ; Flow R 2765 2765 <halt> ; Flow R 2766 2766 <halt> ; Flow R 2767 2767 <halt> ; Flow R 2768 2768 <halt> ; Flow R 2769 2769 <halt> ; Flow R 276a 276a <halt> ; Flow R 276b 276b <halt> ; Flow R 276c 276c <halt> ; Flow R 276d 276d <halt> ; Flow R 276e 276e <halt> ; Flow R 276f 276f <halt> ; Flow R 2770 2770 <halt> ; Flow R 2771 2771 <halt> ; Flow R 2772 2772 <halt> ; Flow R 2773 2773 <halt> ; Flow R 2774 2774 <halt> ; Flow R 2775 2775 <halt> ; Flow R 2776 2776 <halt> ; Flow R 2777 2777 <halt> ; Flow R 2778 2778 <halt> ; Flow R 2779 2779 <halt> ; Flow R 277a 277a <halt> ; Flow R 277b 277b <halt> ; Flow R 277c 277c <halt> ; Flow R 277d 277d <halt> ; Flow R 277e 277e <halt> ; Flow R 277f 277f <halt> ; Flow R 2780 2780 <halt> ; Flow R 2781 2781 <halt> ; Flow R 2782 2782 <halt> ; Flow R 2783 2783 <halt> ; Flow R 2784 2784 <halt> ; Flow R 2785 2785 <halt> ; Flow R 2786 2786 <halt> ; Flow R 2787 2787 <halt> ; Flow R 2788 2788 <halt> ; Flow R 2789 2789 <halt> ; Flow R 278a 278a <halt> ; Flow R 278b 278b <halt> ; Flow R 278c 278c <halt> ; Flow R 278d 278d <halt> ; Flow R 278e 278e <halt> ; Flow R 278f 278f <halt> ; Flow R 2790 2790 <halt> ; Flow R 2791 2791 <halt> ; Flow R 2792 2792 <halt> ; Flow R 2793 2793 <halt> ; Flow R 2794 2794 <halt> ; Flow R 2795 2795 <halt> ; Flow R 2796 2796 <halt> ; Flow R 2797 2797 <halt> ; Flow R 2798 2798 <halt> ; Flow R 2799 2799 <halt> ; Flow R 279a 279a <halt> ; Flow R 279b 279b <halt> ; Flow R 279c 279c <halt> ; Flow R 279d 279d <halt> ; Flow R 279e 279e <halt> ; Flow R 279f 279f <halt> ; Flow R 27a0 27a0 <halt> ; Flow R 27a1 27a1 <halt> ; Flow R 27a2 27a2 <halt> ; Flow R 27a3 27a3 <halt> ; Flow R 27a4 27a4 <halt> ; Flow R 27a5 27a5 <halt> ; Flow R 27a6 27a6 <halt> ; Flow R 27a7 27a7 <halt> ; Flow R 27a8 27a8 <halt> ; Flow R 27a9 27a9 <halt> ; Flow R 27aa 27aa <halt> ; Flow R 27ab 27ab <halt> ; Flow R 27ac 27ac <halt> ; Flow R 27ad 27ad <halt> ; Flow R 27ae 27ae <halt> ; Flow R 27af 27af <halt> ; Flow R 27b0 27b0 <halt> ; Flow R 27b1 27b1 <halt> ; Flow R 27b2 27b2 <halt> ; Flow R 27b3 27b3 <halt> ; Flow R 27b4 27b4 <halt> ; Flow R 27b5 27b5 <halt> ; Flow R 27b6 27b6 <halt> ; Flow R 27b7 27b7 <halt> ; Flow R 27b8 27b8 <halt> ; Flow R 27b9 27b9 <halt> ; Flow R 27ba 27ba <halt> ; Flow R 27bb 27bb <halt> ; Flow R 27bc 27bc <halt> ; Flow R 27bd 27bd <halt> ; Flow R 27be 27be <halt> ; Flow R 27bf 27bf <halt> ; Flow R 27c0 27c0 <halt> ; Flow R 27c1 27c1 <halt> ; Flow R 27c2 27c2 <halt> ; Flow R 27c3 27c3 <halt> ; Flow R 27c4 27c4 <halt> ; Flow R 27c5 27c5 <halt> ; Flow R 27c6 27c6 <halt> ; Flow R 27c7 27c7 <halt> ; Flow R 27c8 27c8 <halt> ; Flow R 27c9 27c9 <halt> ; Flow R 27ca 27ca <halt> ; Flow R 27cb 27cb <halt> ; Flow R 27cc 27cc <halt> ; Flow R 27cd 27cd <halt> ; Flow R 27ce 27ce <halt> ; Flow R 27cf 27cf <halt> ; Flow R 27d0 27d0 <halt> ; Flow R 27d1 27d1 <halt> ; Flow R 27d2 27d2 <halt> ; Flow R 27d3 27d3 <halt> ; Flow R 27d4 27d4 <halt> ; Flow R 27d5 27d5 <halt> ; Flow R 27d6 27d6 <halt> ; Flow R 27d7 27d7 <halt> ; Flow R 27d8 27d8 <halt> ; Flow R 27d9 27d9 <halt> ; Flow R 27da 27da <halt> ; Flow R 27db 27db <halt> ; Flow R 27dc 27dc <halt> ; Flow R 27dd 27dd <halt> ; Flow R 27de 27de <halt> ; Flow R 27df 27df <halt> ; Flow R 27e0 27e0 <halt> ; Flow R 27e1 27e1 <halt> ; Flow R 27e2 27e2 <halt> ; Flow R 27e3 27e3 <halt> ; Flow R 27e4 27e4 <halt> ; Flow R 27e5 27e5 <halt> ; Flow R 27e6 27e6 <halt> ; Flow R 27e7 27e7 <halt> ; Flow R 27e8 27e8 <halt> ; Flow R 27e9 27e9 <halt> ; Flow R 27ea 27ea <halt> ; Flow R 27eb 27eb <halt> ; Flow R 27ec 27ec <halt> ; Flow R 27ed 27ed <halt> ; Flow R 27ee 27ee <halt> ; Flow R 27ef 27ef <halt> ; Flow R 27f0 27f0 <halt> ; Flow R 27f1 27f1 <halt> ; Flow R 27f2 27f2 <halt> ; Flow R 27f3 27f3 <halt> ; Flow R 27f4 27f4 <halt> ; Flow R 27f5 27f5 <halt> ; Flow R 27f6 27f6 <halt> ; Flow R 27f7 27f7 <halt> ; Flow R 27f8 27f8 <halt> ; Flow R 27f9 27f9 <halt> ; Flow R 27fa 27fa <halt> ; Flow R 27fb 27fb <halt> ; Flow R 27fc 27fc <halt> ; Flow R 27fd 27fd <halt> ; Flow R 27fe 27fe <halt> ; Flow R 27ff 27ff <halt> ; Flow R 2800 ; -------------------------------------------------------------------------------------- 2800 ; Comes from: 2800 ; 0e2e C from color 0x0800 2800 ; 0e50 C from color 0x0e05 2800 ; 0e67 C from color 0x0e0c 2800 ; -------------------------------------------------------------------------------------- 2800 2800 seq_br_type 7 Unconditional Call; Flow C 0x29e4 seq_branch_adr 29e4 0x29e4 val_a_adr 30 VR14:10 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 2801 2801 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 2802 2802 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 1 2803 2803 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 2 2804 2804 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 4 2805 2805 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 8 2806 2806 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 10 2807 2807 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 2808 2808 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 2809 2809 typ_a_adr 2f TR18:0f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 280a 280a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 1 280b 280b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 2 280c 280c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 4 280d 280d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 8 280e 280e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 10 280f 280f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 2810 2810 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 2811 2811 seq_br_type 1 Branch True; Flow J cc=True 0x2813 seq_branch_adr 2813 0x2813 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2812 2812 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2813 2813 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2814 2814 seq_br_type 1 Branch True; Flow J cc=True 0x2816 seq_branch_adr 2816 0x2816 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 1 2815 2815 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2816 2816 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2817 2817 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2818 2818 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2819 2819 seq_br_type 1 Branch True; Flow J cc=True 0x281b seq_branch_adr 281b 0x281b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 2 281a 281a seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 281b 281b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 281c 281c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 281d 281d typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 281e 281e seq_br_type 1 Branch True; Flow J cc=True 0x2820 seq_branch_adr 2820 0x2820 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 4 281f 281f seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2820 2820 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2821 2821 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2822 2822 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2823 2823 seq_br_type 1 Branch True; Flow J cc=True 0x2825 seq_branch_adr 2825 0x2825 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 8 2824 2824 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2825 2825 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2826 2826 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2827 2827 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2828 2828 seq_br_type 1 Branch True; Flow J cc=True 0x282a seq_branch_adr 282a 0x282a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame 10 2829 2829 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 282a 282a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 282b 282b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 282c 282c typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 282d 282d seq_br_type 1 Branch True; Flow J cc=True 0x282f seq_branch_adr 282f 0x282f seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 282e 282e seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 282f 282f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2830 2830 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2831 2831 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2832 2832 seq_br_type 1 Branch True; Flow J cc=True 0x2834 seq_branch_adr 2834 0x2834 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 2833 2833 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2834 2834 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 2835 2835 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 1 2836 2836 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 2 2837 2837 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 4 2838 2838 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 8 2839 2839 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 10 283a 283a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 283b 283b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 283c 283c typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 283d 283d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 1 283e 283e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 2 283f 283f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 4 2840 2840 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 8 2841 2841 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 10 2842 2842 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 2843 2843 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 2844 2844 seq_br_type 1 Branch True; Flow J cc=True 0x2846 seq_branch_adr 2846 0x2846 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 2845 2845 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2846 2846 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2847 2847 seq_br_type 1 Branch True; Flow J cc=True 0x2849 seq_branch_adr 2849 0x2849 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 1 2848 2848 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2849 2849 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 284a 284a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 284b 284b typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 284c 284c seq_br_type 1 Branch True; Flow J cc=True 0x284e seq_branch_adr 284e 0x284e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 2 284d 284d seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 284e 284e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 284f 284f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2850 2850 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2851 2851 seq_br_type 1 Branch True; Flow J cc=True 0x2853 seq_branch_adr 2853 0x2853 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 4 2852 2852 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2853 2853 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 2854 2854 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2855 2855 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2856 2856 seq_br_type 1 Branch True; Flow J cc=True 0x2858 seq_branch_adr 2858 0x2858 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 8 2857 2857 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2858 2858 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 2859 2859 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 285a 285a typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 285b 285b seq_br_type 1 Branch True; Flow J cc=True 0x285d seq_branch_adr 285d 0x285d seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_frame 10 285c 285c seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 285d 285d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 285e 285e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 285f 285f typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2860 2860 seq_br_type 1 Branch True; Flow J cc=True 0x2862 seq_branch_adr 2862 0x2862 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 2861 2861 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2862 2862 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 2863 2863 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2864 2864 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2865 2865 seq_br_type 1 Branch True; Flow J cc=True 0x2867 seq_branch_adr 2867 0x2867 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 2866 2866 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2867 2867 typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 31 VR19:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 2868 2868 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1e 2869 2869 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1d 286a 286a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1b 286b 286b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 17 286c 286c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame f 286d 286d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 typ_frame 1f 286e 286e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1f 286f 286f typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2870 2870 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1e 2871 2871 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1d 2872 2872 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1b 2873 2873 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 17 2874 2874 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame f 2875 2875 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 typ_frame 1f 2876 2876 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2877 2877 seq_br_type 1 Branch True; Flow J cc=True 0x2879 seq_branch_adr 2879 0x2879 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2878 2878 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2879 2879 typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 287a 287a seq_br_type 1 Branch True; Flow J cc=True 0x287c seq_branch_adr 287c 0x287c seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1e 287b 287b seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 287c 287c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 287d 287d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 287e 287e typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 287f 287f seq_br_type 1 Branch True; Flow J cc=True 0x2881 seq_branch_adr 2881 0x2881 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1d 2880 2880 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2881 2881 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2882 2882 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2883 2883 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2884 2884 seq_br_type 1 Branch True; Flow J cc=True 0x2886 seq_branch_adr 2886 0x2886 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1b 2885 2885 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2886 2886 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2887 2887 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2888 2888 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2889 2889 seq_br_type 1 Branch True; Flow J cc=True 0x288b seq_branch_adr 288b 0x288b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 17 288a 288a seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 288b 288b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 288c 288c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 288d 288d typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 288e 288e seq_br_type 1 Branch True; Flow J cc=True 0x2890 seq_branch_adr 2890 0x2890 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame f 288f 288f seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2890 2890 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2891 2891 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2892 2892 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2893 2893 seq_br_type 1 Branch True; Flow J cc=True 0x2895 seq_branch_adr 2895 0x2895 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 1 typ_frame 1f 2894 2894 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 2895 2895 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 2896 2896 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 0 typ_frame 1f 2897 2897 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2898 2898 seq_br_type 1 Branch True; Flow J cc=True 0x289a seq_branch_adr 289a 0x289a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2899 2899 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 289a 289a typ_a_adr 3c TR1a:1c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a val_a_adr 32 VR1a:12 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 289b 289b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1e 289c 289c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1d 289d 289d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1b 289e 289e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 17 289f 289f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame f 28a0 28a0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1f 28a1 28a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 28a2 28a2 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 28a3 28a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1e 28a4 28a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1d 28a5 28a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1b 28a6 28a6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 17 28a7 28a7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame f 28a8 28a8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1f 28a9 28a9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 28aa 28aa seq_br_type 1 Branch True; Flow J cc=True 0x28ac seq_branch_adr 28ac 0x28ac seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28ab 28ab seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28ac 28ac typ_a_adr 03 GP03 typ_alu_func 3 LEFT_I_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28ad 28ad seq_br_type 1 Branch True; Flow J cc=True 0x28af seq_branch_adr 28af 0x28af seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1e 28ae 28ae seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28af 28af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28b0 28b0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28b1 28b1 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28b2 28b2 seq_br_type 1 Branch True; Flow J cc=True 0x28b4 seq_branch_adr 28b4 0x28b4 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1d 28b3 28b3 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28b4 28b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28b5 28b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28b6 28b6 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28b7 28b7 seq_br_type 1 Branch True; Flow J cc=True 0x28b9 seq_branch_adr 28b9 0x28b9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1b 28b8 28b8 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28b9 28b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28ba 28ba seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28bb 28bb typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28bc 28bc seq_br_type 1 Branch True; Flow J cc=True 0x28be seq_branch_adr 28be 0x28be seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 17 28bd 28bd seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28be 28be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28bf 28bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28c0 28c0 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28c1 28c1 seq_br_type 1 Branch True; Flow J cc=True 0x28c3 seq_branch_adr 28c3 0x28c3 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame f 28c2 28c2 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28c3 28c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28c4 28c4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28c5 28c5 typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28c6 28c6 seq_br_type 1 Branch True; Flow J cc=True 0x28c8 seq_branch_adr 28c8 0x28c8 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1f 28c7 28c7 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28c8 28c8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 28c9 28c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1f 28ca 28ca typ_a_adr 03 GP03 typ_alu_func 4 LEFT_I_A_INC typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 28cb 28cb seq_br_type 1 Branch True; Flow J cc=True 0x28cd seq_branch_adr 28cd 0x28cd seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 28cc 28cc seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28cd 28cd typ_a_adr 2f TR18:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 32 VR1a:12 val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1a 28ce 28ce typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 28cf 28cf seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_frame 1 28d0 28d0 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_b_adr 03 GP03 typ_frame 1 28d1 28d1 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_c_lit 0 typ_frame 1f 28d2 28d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x28d4 seq_br_type 0 Branch False seq_branch_adr 28d4 0x28d4 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) typ_a_adr 04 GP04 typ_b_adr 04 GP04 28d3 28d3 seq_br_type 3 Unconditional Branch; Flow J 0x29e9 seq_branch_adr 29e9 0x29e9 28d4 28d4 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3e VR14:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 28d5 28d5 seq_br_type 7 Unconditional Call; Flow C 0x29e3 seq_branch_adr 29e3 0x29e3 28d6 28d6 typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1b typ_rand b CARRY IN = Q BIT FROM VAL 28d7 28d7 seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 28d8 28d8 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 28d9 28d9 seq_br_type 7 Unconditional Call; Flow C 0x29e4 seq_branch_adr 29e4 0x29e4 28da 28da typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1b typ_rand b CARRY IN = Q BIT FROM VAL 28db 28db seq_br_type 7 Unconditional Call; Flow C 0x29e7 seq_branch_adr 29e7 0x29e7 28dc 28dc typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 3e VR14:1e val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 28dd 28dd seq_br_type 7 Unconditional Call; Flow C 0x29e3 seq_branch_adr 29e3 0x29e3 28de 28de typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1b typ_rand a PASS_B_HIGH 28df 28df seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 28e0 28e0 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 28e1 28e1 seq_br_type 7 Unconditional Call; Flow C 0x29e4 seq_branch_adr 29e4 0x29e4 28e2 28e2 typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1b typ_rand a PASS_B_HIGH 28e3 28e3 seq_br_type 7 Unconditional Call; Flow C 0x29e7 seq_branch_adr 29e7 0x29e7 28e4 28e4 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 2f VR19:0f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 28e5 28e5 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 14 28e6 28e6 seq_br_type 7 Unconditional Call; Flow C 0x29e3 seq_branch_adr 29e3 0x29e3 28e7 28e7 typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_rand 9 PASS_A_HIGH 28e8 28e8 seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 28e9 28e9 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 28ea 28ea typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 14 28eb 28eb seq_br_type 7 Unconditional Call; Flow C 0x29e4 seq_branch_adr 29e4 0x29e4 28ec 28ec typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_rand 9 PASS_A_HIGH 28ed 28ed seq_br_type 7 Unconditional Call; Flow C 0x29e7 seq_branch_adr 29e7 0x29e7 28ee 28ee typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 val_a_adr 2f VR19:0f val_alu_func 7 INC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 19 28ef 28ef typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 14 28f0 28f0 seq_br_type 7 Unconditional Call; Flow C 0x29e3 seq_branch_adr 29e3 0x29e3 28f1 28f1 typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1b typ_rand 8 SPARE_0x08 28f2 28f2 seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 28f3 28f3 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 28f4 28f4 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 18 28f5 28f5 seq_br_type 7 Unconditional Call; Flow C 0x29e3 seq_branch_adr 29e3 0x29e3 28f6 28f6 typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1b typ_rand 8 SPARE_0x08 28f7 28f7 seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 28f8 28f8 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 28f9 28f9 typ_a_adr 31 TR14:11 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 14 28fa 28fa seq_br_type 7 Unconditional Call; Flow C 0x29e4 seq_branch_adr 29e4 0x29e4 28fb 28fb typ_a_adr 03 GP03 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1b typ_rand 8 SPARE_0x08 28fc 28fc seq_br_type 7 Unconditional Call; Flow C 0x29e7 seq_branch_adr 29e7 0x29e7 28fd 28fd typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR14:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 14 28fe 28fe seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 28ff 28ff typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2900 2900 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 2901 2901 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2902 2902 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 2903 2903 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2904 2904 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 2905 2905 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2906 2906 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 2907 2907 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2908 2908 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 2909 2909 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 290a 290a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 290b 290b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 290c 290c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var typ_b_adr 03 GP03 290d 290d typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 290e 290e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 290f 290f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2910 2910 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 2911 2911 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2912 2912 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 2913 2913 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2914 2914 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 2915 2915 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2916 2916 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 2917 2917 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2918 2918 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 2919 2919 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 291a 291a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 291b 291b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 291c 291c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 1 291d 291d typ_a_adr 2b TR13:0b typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 291e 291e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 291f 291f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2920 2920 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 2921 2921 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2922 2922 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 2923 2923 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2924 2924 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 2925 2925 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2926 2926 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 2927 2927 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2928 2928 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 2929 2929 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 292a 292a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 292b 292b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 292c 292c seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 2 292d 292d typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 292e 292e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 292f 292f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2930 2930 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 2931 2931 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2932 2932 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 2933 2933 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2934 2934 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 2935 2935 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2936 2936 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 2937 2937 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2938 2938 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 2939 2939 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 293a 293a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 293b 293b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 293c 293c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 03 GP03 typ_frame 3 293d 293d typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 293e 293e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 293f 293f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2940 2940 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 2941 2941 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2942 2942 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 2943 2943 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2944 2944 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 2945 2945 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2946 2946 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 2947 2947 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2948 2948 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 2949 2949 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 294a 294a seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 294b 294b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 294c 294c seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 03 GP03 typ_frame 4 294d 294d typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 294e 294e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 294f 294f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2950 2950 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 2951 2951 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2952 2952 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 2953 2953 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2954 2954 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 2955 2955 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2956 2956 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 2957 2957 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2958 2958 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 2959 2959 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 295a 295a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 295b 295b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 295c 295c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 5 295d 295d typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 295e 295e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 295f 295f typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2960 2960 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2961 2961 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2962 2962 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2963 2963 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2964 2964 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2965 2965 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2966 2966 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2967 2967 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2968 2968 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2969 2969 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 296a 296a seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 296b 296b typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 296c 296c seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 296d 296d typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 296e 296e typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 296f 296f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2970 2970 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR1a:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2971 2971 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_b_adr 03 GP03 typ_frame 6 2972 2972 typ_a_adr 37 TR14:17 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2973 2973 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 2974 2974 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2975 2975 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 2976 2976 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2977 2977 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 2978 2978 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2979 2979 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 297a 297a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 297b 297b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 297c 297c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 297d 297d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 297e 297e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 297f 297f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 2980 2980 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2981 2981 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 7 2982 2982 typ_a_adr 2c TR13:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2983 2983 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 2984 2984 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2985 2985 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 2986 2986 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2987 2987 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 2988 2988 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2989 2989 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 298a 298a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 298b 298b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 298c 298c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 298d 298d seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 298e 298e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 298f 298f seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 2990 2990 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2991 2991 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 03 GP03 typ_frame 8 2992 2992 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2993 2993 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 2994 2994 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2995 2995 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 2996 2996 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2997 2997 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 2998 2998 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2999 2999 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 299a 299a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 299b 299b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 299c 299c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 299d 299d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 299e 299e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 299f 299f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 29a0 29a0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29a1 29a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 9 29a2 29a2 typ_a_adr 33 TR14:13 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29a3 29a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29a4 29a4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29a5 29a5 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29a6 29a6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29a7 29a7 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29a8 29a8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29a9 29a9 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29aa 29aa typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29ab 29ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29ac 29ac typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29ad 29ad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29ae 29ae typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29af 29af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29b0 29b0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29b1 29b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a) Subprogram_For_Call Entry_Var Subprogram_For_Call_Elaborated Select_Var Subprogram_For_Call_Visible Family_Var Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram Delay_Alternative Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_frame a 29b2 29b2 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29b3 29b3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29b4 29b4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29b5 29b5 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29b6 29b6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29b7 29b7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29b8 29b8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29b9 29b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29ba 29ba typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29bb 29bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29bc 29bc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29bd 29bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29be 29be typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29bf 29bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29c0 29c0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29c1 29c1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame b 29c2 29c2 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29c3 29c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29c4 29c4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29c5 29c5 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29c6 29c6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29c7 29c7 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29c8 29c8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29c9 29c9 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29ca 29ca typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29cb 29cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29cc 29cc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29cd 29cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29ce 29ce typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29cf 29cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29d0 29d0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29d1 29d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c) Control_State Slice_Stuff Static_Connection Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_frame c 29d2 29d2 typ_a_adr 2a TR13:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 29d3 29d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29d4 29d4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 29d5 29d5 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29d6 29d6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29d7 29d7 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29d8 29d8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29d9 29d9 seq_br_type 0 Branch False; Flow J cc=False 0x29e9 seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29da 29da typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29db 29db seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29dc 29dc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29dd 29dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29de 29de typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29df 29df seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29e0 29e0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 29e1 29e1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_frame d 29e2 29e2 seq_br_type 3 Unconditional Branch; Flow J 0x2a00 seq_branch_adr 2a00 0x2a00 29e3 ; -------------------------------------------------------------------------------------- 29e3 ; Comes from: 29e3 ; 28d5 C from color UE_CLASS 29e3 ; 28dd C from color UE_CLASS 29e3 ; 28e6 C from color UE_CLASS 29e3 ; 28f0 C from color UE_CLASS 29e3 ; 28f5 C from color UE_CLASS 29e3 ; -------------------------------------------------------------------------------------- 29e3 29e3 seq_br_type a Unconditional Return; Flow R typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 29e4 ; -------------------------------------------------------------------------------------- 29e4 ; Comes from: 29e4 ; 2800 C from color UE_CLASS 29e4 ; 28d9 C from color UE_CLASS 29e4 ; 28e1 C from color UE_CLASS 29e4 ; 28eb C from color UE_CLASS 29e4 ; 28fa C from color UE_CLASS 29e4 ; -------------------------------------------------------------------------------------- 29e4 29e4 seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 29e5 29e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 10 NOT_A 29e6 29e6 seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 29e7 29e7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x29e9 seq_br_type 1 Branch True seq_branch_adr 29e9 0x29e9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 29e8 29e8 seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 29e9 29e9 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 29ea 29ea <halt> ; Flow R 29eb 29eb <halt> ; Flow R 29ec 29ec <halt> ; Flow R 29ed 29ed <halt> ; Flow R 29ee 29ee <halt> ; Flow R 29ef 29ef <halt> ; Flow R 29f0 29f0 <halt> ; Flow R 29f1 29f1 <halt> ; Flow R 29f2 29f2 <halt> ; Flow R 29f3 29f3 <halt> ; Flow R 29f4 29f4 <halt> ; Flow R 29f5 29f5 <halt> ; Flow R 29f6 29f6 <halt> ; Flow R 29f7 29f7 <halt> ; Flow R 29f8 29f8 <halt> ; Flow R 29f9 29f9 <halt> ; Flow R 29fa 29fa <halt> ; Flow R 29fb 29fb <halt> ; Flow R 29fc 29fc <halt> ; Flow R 29fd 29fd <halt> ; Flow R 29fe 29fe <halt> ; Flow R 29ff 29ff <halt> ; Flow R 2a00 2a00 typ_a_adr 2a TR14:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a01 2a01 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a02 2a02 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a03 2a03 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a04 2a04 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a05 2a05 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a06 2a06 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a07 2a07 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a08 2a08 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a09 2a09 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a0a 2a0a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a0b 2a0b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a0c 2a0c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a0d 2a0d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a0e 2a0e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a0f 2a0f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_frame e 2a10 2a10 typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 2a11 2a11 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a12 2a12 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a13 2a13 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a14 2a14 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a15 2a15 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a16 2a16 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a17 2a17 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a18 2a18 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a19 2a19 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a1a 2a1a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a1b 2a1b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a1c 2a1c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a1d 2a1d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a1e 2a1e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a1f 2a1f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame f 2a20 2a20 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2a21 2a21 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a22 2a22 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a23 2a23 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a24 2a24 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a25 2a25 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a26 2a26 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a27 2a27 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a28 2a28 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a29 2a29 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a2a 2a2a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a2b 2a2b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a2c 2a2c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a2d 2a2d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a2e 2a2e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a2f 2a2f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_frame 10 2a30 2a30 typ_a_adr 33 TR14:13 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a31 2a31 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a32 2a32 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a33 2a33 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a34 2a34 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a35 2a35 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a36 2a36 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a37 2a37 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a38 2a38 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a39 2a39 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a3a 2a3a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a3b 2a3b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a3c 2a3c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a3d 2a3d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a3e 2a3e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a3f 2a3f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 03 GP03 typ_frame 11 2a40 2a40 typ_a_adr 2e TR13:0e typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2a41 2a41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a42 2a42 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a43 2a43 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a44 2a44 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a45 2a45 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a46 2a46 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a47 2a47 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a48 2a48 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a49 2a49 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a4a 2a4a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a4b 2a4b seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a4c 2a4c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a4d 2a4d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a4e 2a4e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a4f 2a4f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12) Entry_Var Family_Var Delay_Alternative Familiy_Alternative typ_b_adr 03 GP03 typ_frame 12 2a50 2a50 typ_a_adr 2a TR13:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2a51 2a51 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a52 2a52 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a53 2a53 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a54 2a54 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a55 2a55 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a56 2a56 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a57 2a57 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a58 2a58 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a59 2a59 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a5a 2a5a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a5b 2a5b seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a5c 2a5c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a5d 2a5d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a5e 2a5e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a5f 2a5f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13) Module_Key typ_b_adr 03 GP03 typ_frame 13 2a60 2a60 typ_a_adr 2d TR13:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2a61 2a61 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a62 2a62 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a63 2a63 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a64 2a64 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a65 2a65 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a66 2a66 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a67 2a67 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a68 2a68 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a69 2a69 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a6a 2a6a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a6b 2a6b seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a6c 2a6c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a6d 2a6d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a6e 2a6e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a6f 2a6f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 2a70 2a70 typ_a_adr 2f TR13:0f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2a71 2a71 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a72 2a72 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a73 2a73 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a74 2a74 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a75 2a75 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a76 2a76 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a77 2a77 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a78 2a78 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a79 2a79 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a7a 2a7a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a7b 2a7b seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a7c 2a7c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a7d 2a7d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a7e 2a7e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a7f 2a7f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key typ_b_adr 03 GP03 typ_frame 15 2a80 2a80 typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 2a81 2a81 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a82 2a82 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a83 2a83 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a84 2a84 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a85 2a85 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a86 2a86 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a87 2a87 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a88 2a88 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a89 2a89 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a8a 2a8a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a8b 2a8b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a8c 2a8c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a8d 2a8d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a8e 2a8e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a8f 2a8f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_frame 16 2a90 2a90 typ_a_adr 2a TR13:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2a91 2a91 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a92 2a92 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2a93 2a93 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a94 2a94 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a95 2a95 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a96 2a96 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a97 2a97 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a98 2a98 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a99 2a99 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a9a 2a9a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a9b 2a9b seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a9c 2a9c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a9d 2a9d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2a9e 2a9e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2a9f 2a9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key typ_b_adr 03 GP03 typ_frame 17 2aa0 2aa0 typ_a_adr 37 TR13:17 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2aa1 2aa1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var typ_b_adr 03 GP03 typ_frame 18 2aa2 2aa2 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2aa3 2aa3 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var typ_b_adr 03 GP03 typ_frame 18 2aa4 2aa4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2aa5 2aa5 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var typ_b_adr 03 GP03 typ_frame 18 2aa6 2aa6 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2aa7 2aa7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var typ_b_adr 03 GP03 typ_frame 18 2aa8 2aa8 typ_a_adr 33 TR14:13 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2aa9 2aa9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2aaa 2aaa typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2aab 2aab seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2aac 2aac typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2aad 2aad seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2aae 2aae typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2aaf 2aaf seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2ab0 2ab0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ab1 2ab1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2ab2 2ab2 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ab3 2ab3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2ab4 2ab4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ab5 2ab5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2ab6 2ab6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ab7 2ab7 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 03 GP03 typ_frame 1b 2ab8 2ab8 typ_a_adr 33 TR14:13 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ab9 2ab9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2aba 2aba typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2abb 2abb seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2abc 2abc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2abd 2abd seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2abe 2abe typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2abf 2abf seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2ac0 2ac0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ac1 2ac1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2ac2 2ac2 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ac3 2ac3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2ac4 2ac4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ac5 2ac5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2ac6 2ac6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ac7 2ac7 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2ac8 2ac8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ac9 2ac9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 03 GP03 typ_frame 1c 2aca 2aca typ_a_adr 35 TR14:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2acb 2acb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2acc 2acc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2acd 2acd seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ace 2ace typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2acf 2acf seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ad0 2ad0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ad1 2ad1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ad2 2ad2 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ad3 2ad3 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ad4 2ad4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ad5 2ad5 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ad6 2ad6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ad7 2ad7 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ad8 2ad8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2ad9 2ad9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 03 GP03 typ_frame 1d 2ada 2ada typ_a_adr 37 TR1a:17 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2adb 2adb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1e 2adc 2adc typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2add 2add seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1e 2ade 2ade typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR1a:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2adf 2adf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1e 2ae0 2ae0 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2ae1 2ae1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1e 2ae2 2ae2 typ_a_adr 20 TR1a:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2ae3 2ae3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1f 2ae4 2ae4 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2ae5 2ae5 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1f 2ae6 2ae6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR1a:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2ae7 2ae7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1f 2ae8 2ae8 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2ae9 2ae9 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_frame 1f 2aea 2aea typ_a_adr 3f TR18:1f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2aeb 2aeb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 2aec 2aec typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2aed 2aed seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 2aee 2aee typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR18:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2aef 2aef seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 2af0 2af0 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2af1 2af1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 2af2 2af2 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2af3 2af3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21) Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_state2 Subarray_Var Family_Var Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Scheduling_Allocation Variant_Record_Var Delay_Alternative Package_Var Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1 2af4 2af4 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2af5 2af5 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21) Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_state2 Subarray_Var Family_Var Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Scheduling_Allocation Variant_Record_Var Delay_Alternative Package_Var Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1 2af6 2af6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2b TR1a:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2af7 2af7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21) Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_state2 Subarray_Var Family_Var Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Scheduling_Allocation Variant_Record_Var Delay_Alternative Package_Var Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1 2af8 2af8 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2af9 2af9 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21) Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_state2 Subarray_Var Family_Var Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Scheduling_Allocation Variant_Record_Var Delay_Alternative Package_Var Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1 2afa 2afa typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2afb 2afb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Ref Deletion_Key Entry_Var Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Ref Select_Var Auxiliary_Mark Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_For_Call_Visible_Elaborated Heap_Access_Ref Default_Var Activation_Link Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 2 2afc 2afc typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2afd 2afd seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Ref Deletion_Key Entry_Var Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Ref Select_Var Auxiliary_Mark Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_For_Call_Visible_Elaborated Heap_Access_Ref Default_Var Activation_Link Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 2 2afe 2afe typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2aff 2aff seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Ref Deletion_Key Entry_Var Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Ref Select_Var Auxiliary_Mark Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_For_Call_Visible_Elaborated Heap_Access_Ref Default_Var Activation_Link Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 2 2b00 2b00 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b01 2b01 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Ref Deletion_Key Entry_Var Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Ref Select_Var Auxiliary_Mark Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_For_Call_Visible_Elaborated Heap_Access_Ref Default_Var Activation_Link Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 2 2b02 2b02 typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b03 2b03 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23) Subprogram_Ref_For_Call Word3_Flag Subprogram_For_Call Mark_Word_Flag Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Activation_Link Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Accept_Link Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 3 2b04 2b04 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b05 2b05 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23) Subprogram_Ref_For_Call Word3_Flag Subprogram_For_Call Mark_Word_Flag Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Activation_Link Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Accept_Link Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 3 2b06 2b06 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR1a:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b07 2b07 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23) Subprogram_Ref_For_Call Word3_Flag Subprogram_For_Call Mark_Word_Flag Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Activation_Link Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Accept_Link Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 3 2b08 2b08 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b09 2b09 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23) Subprogram_Ref_For_Call Word3_Flag Subprogram_For_Call Mark_Word_Flag Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Auxiliary_Mark Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Activation_Link Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Accept_Link Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 3 2b0a 2b0a typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b0b 2b0b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 4 2b0c 2b0c typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b0d 2b0d seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 4 2b0e 2b0e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b0f 2b0f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 4 2b10 2b10 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b11 2b11 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 4 2b12 2b12 typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 2b13 2b13 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25) Discrete_Var Control_State Subprogram_Ref_For_Call Word3_Flag Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 5 2b14 2b14 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR1a:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b15 2b15 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25) Discrete_Var Control_State Subprogram_Ref_For_Call Word3_Flag Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 5 2b16 2b16 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b17 2b17 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25) Discrete_Var Control_State Subprogram_Ref_For_Call Word3_Flag Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 5 2b18 2b18 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR1a:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b19 2b19 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25) Discrete_Var Control_State Subprogram_Ref_For_Call Word3_Flag Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Float_Var Slice_Stuff Variable_Ref Float_Ref Deletion_Key Entry_Var Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 5 2b1a 2b1a typ_a_adr 39 TR14:19 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b1b 2b1b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b1c 2b1c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b1d 2b1d seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b1e 2b1e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b1f 2b1f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b20 2b20 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b21 2b21 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b22 2b22 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b23 2b23 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b24 2b24 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b25 2b25 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b26 2b26 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b27 2b27 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b28 2b28 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b29 2b29 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame a 2b2a 2b2a typ_a_adr 35 TR14:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b2b 2b2b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_b_adr 03 GP03 typ_c_lit 2 typ_frame f 2b2c 2b2c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b2d 2b2d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_b_adr 03 GP03 typ_c_lit 2 typ_frame f 2b2e 2b2e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 37 TR1a:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b2f 2b2f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_b_adr 03 GP03 typ_c_lit 2 typ_frame f 2b30 2b30 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b31 2b31 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_b_adr 03 GP03 typ_c_lit 2 typ_frame f 2b32 2b32 typ_a_adr 2a TR13:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b33 2b33 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b34 2b34 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b35 2b35 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b36 2b36 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b37 2b37 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b38 2b38 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b39 2b39 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b3a 2b3a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b3b 2b3b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b3c 2b3c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b3d 2b3d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b3e 2b3e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b3f 2b3f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b40 2b40 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b41 2b41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 12 2b42 2b42 typ_a_adr 2a TR14:0a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b43 2b43 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b44 2b44 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b45 2b45 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b46 2b46 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b47 2b47 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b48 2b48 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b49 2b49 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b4a 2b4a typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b4b 2b4b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b4c 2b4c typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b4d 2b4d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b4e 2b4e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b4f 2b4f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b50 2b50 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b51 2b51 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 13 2b52 2b52 typ_a_adr 21 TR18:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b53 2b53 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1e 2b54 2b54 typ_a_adr 35 TR13:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b55 2b55 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1e 2b56 2b56 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b57 2b57 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1e 2b58 2b58 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b59 2b59 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1e 2b5a 2b5a typ_a_adr 35 TR1a:15 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b5b 2b5b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f) Subprogram_Ref_For_Call Subprogram_For_Call Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2b5c 2b5c typ_a_adr 36 TR13:16 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b5d 2b5d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f) Subprogram_Ref_For_Call Subprogram_For_Call Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2b5e 2b5e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b5f 2b5f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f) Subprogram_Ref_For_Call Subprogram_For_Call Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2b60 2b60 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b61 2b61 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f) Subprogram_Ref_For_Call Subprogram_For_Call Variable_Ref Entry_Var Subprogram_Ref_For_Call_Elaborated Subprogram_For_Call_Elaborated Select_Var Subprogram_Ref_For_Call_Visible Subprogram_For_Call_Visible Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Default_Var Accept_Subprogram_Ref Accept_Subprogram Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Utility_Subprogram Familiy_Alternative Null_Subprogram Exception_Var typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f 2b62 2b62 typ_a_adr 32 TR14:12 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b63 2b63 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40) Word3_Flag Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 1 2b64 2b64 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b65 2b65 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40) Word3_Flag Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 1 2b66 2b66 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b67 2b67 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40) Word3_Flag Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 1 2b68 2b68 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b69 2b69 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40) Word3_Flag Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 03 GP03 typ_c_lit 1 2b6a 2b6a typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b6b 2b6b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1 2b6c 2b6c typ_a_adr 32 TR13:12 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b6d 2b6d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1 2b6e 2b6e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b6f 2b6f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1 2b70 2b70 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b71 2b71 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 1 2b72 2b72 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b73 2b73 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42) Float_Var Slice_Stuff Variable_Ref Task_Var Dependence_Link Micro_state2 Heap_Access_Var Scheduling_Allocation Package_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 2 2b74 2b74 typ_a_adr 34 TR13:14 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b75 2b75 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42) Float_Var Slice_Stuff Variable_Ref Task_Var Dependence_Link Micro_state2 Heap_Access_Var Scheduling_Allocation Package_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 2 2b76 2b76 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b77 2b77 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42) Float_Var Slice_Stuff Variable_Ref Task_Var Dependence_Link Micro_state2 Heap_Access_Var Scheduling_Allocation Package_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 2 2b78 2b78 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b79 2b79 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42) Float_Var Slice_Stuff Variable_Ref Task_Var Dependence_Link Micro_state2 Heap_Access_Var Scheduling_Allocation Package_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 2 2b7a 2b7a typ_a_adr 34 TR14:14 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b7b 2b7b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43) Float_Ref Deletion_Key Entry_Var Task_Ref Select_Var Auxiliary_Mark Subarray_Var Family_Var Heap_Access_Ref Default_Var Activation_Link Variant_Record_Var Delay_Alternative Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 3 2b7c 2b7c typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b7d 2b7d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43) Float_Ref Deletion_Key Entry_Var Task_Ref Select_Var Auxiliary_Mark Subarray_Var Family_Var Heap_Access_Ref Default_Var Activation_Link Variant_Record_Var Delay_Alternative Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 3 2b7e 2b7e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2d TR1a:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b7f 2b7f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43) Float_Ref Deletion_Key Entry_Var Task_Ref Select_Var Auxiliary_Mark Subarray_Var Family_Var Heap_Access_Ref Default_Var Activation_Link Variant_Record_Var Delay_Alternative Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 3 2b80 2b80 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b81 2b81 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43) Float_Ref Deletion_Key Entry_Var Task_Ref Select_Var Auxiliary_Mark Subarray_Var Family_Var Heap_Access_Ref Default_Var Activation_Link Variant_Record_Var Delay_Alternative Accept_Link Vector_Var Familiy_Alternative Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 3 2b82 2b82 typ_a_adr 3f TR18:1f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b83 2b83 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 4 2b84 2b84 typ_a_adr 30 TR13:10 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b85 2b85 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 4 2b86 2b86 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR18:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b87 2b87 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 4 2b88 2b88 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b89 2b89 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 4 2b8a 2b8a typ_a_adr 20 TR1a:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2b8b 2b8b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Utility_Subprogram Vector_Var Familiy_Alternative typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 5 2b8c 2b8c typ_a_adr 31 TR13:11 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2b8d 2b8d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Utility_Subprogram Vector_Var Familiy_Alternative typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 5 2b8e 2b8e typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR18:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b8f 2b8f seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Utility_Subprogram Vector_Var Familiy_Alternative typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 5 2b90 2b90 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b91 2b91 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45) Micro_State1 Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Micro_state2 Subarray_Var Family_Var Utility_Subprogram Vector_Var Familiy_Alternative typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 5 2b92 2b92 typ_a_adr 36 TR14:16 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b93 2b93 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46) Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 6 2b94 2b94 typ_a_adr 2c TR18:0c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b95 2b95 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46) Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 6 2b96 2b96 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 3f TR18:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b97 2b97 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46) Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 6 2b98 2b98 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2b99 2b99 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46) Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Activation_Link Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 6 2b9a 2b9a typ_a_adr 3b TR18:1b typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b9b 2b9b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47) Matrix_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 7 2b9c 2b9c typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2b9d 2b9d seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47) Matrix_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 7 2b9e 2b9e typ_a_adr 3c TR18:1c typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2b9f 2b9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47) Matrix_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 7 2ba0 2ba0 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2ba1 2ba1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47) Matrix_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 7 2ba2 2ba2 typ_a_adr 2b TR1a:0b typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2ba3 2ba3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 2ba4 2ba4 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2ba5 2ba5 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 2ba6 2ba6 typ_a_adr 3f TR18:1f typ_alu_func 19 X_XOR_B typ_b_adr 3e TR18:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2ba7 2ba7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 2ba8 2ba8 typ_a_adr 3f TR18:1f typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2ba9 2ba9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 2baa 2baa typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2bab 2bab seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 2bac 2bac typ_a_adr 3d TR18:1d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2bad 2bad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame a 2bae 2bae typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2baf 2baf seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame a 2bb0 2bb0 typ_a_adr 37 TR14:17 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bb1 2bb1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame a 2bb2 2bb2 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2bb3 2bb3 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame a 2bb4 2bb4 typ_a_adr 3a TR13:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2bb5 2bb5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bb6 2bb6 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2bb7 2bb7 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bb8 2bb8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bb9 2bb9 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bba 2bba typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bbb 2bbb seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bbc 2bbc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bbd 2bbd seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bbe 2bbe typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 35 TR14:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bbf 2bbf seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bc0 2bc0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 36 TR14:16 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bc1 2bc1 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bc2 2bc2 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 38 TR14:18 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bc3 2bc3 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 2 2bc4 2bc4 typ_a_adr 2d TR1a:0d typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2bc5 2bc5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bc6 2bc6 typ_a_adr 33 TR13:13 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2bc7 2bc7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bc8 2bc8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR14:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bc9 2bc9 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bca 2bca typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 33 TR14:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bcb 2bcb seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bcc 2bcc typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2bcd 2bcd seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bce 2bce typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 34 TR14:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 14 2bcf 2bcf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 4 2bd0 2bd0 typ_a_adr 29 TR12:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 2bd1 2bd1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 5 2bd2 2bd2 typ_a_adr 38 TR13:18 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 2bd3 2bd3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 5 2bd4 2bd4 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR1a:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1a 2bd5 2bd5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 5 2bd6 2bd6 typ_a_adr 03 GP03 typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2bd7 2bd7 seq_br_type 0 Branch False; Flow J cc=False 0x2be1 seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 5 2bd8 2bd8 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR18:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 18 2bd9 2bd9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 5 2bda 2bda seq_br_type a Unconditional Return; Flow R 2bdb 2bdb seq_br_type a Unconditional Return; Flow R typ_alu_func 13 ONES typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2bdc 2bdc seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2bdd 2bdd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 10 NOT_A 2bde 2bde seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2bdf 2bdf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be1 seq_br_type 1 Branch True seq_branch_adr 2be1 0x2be1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 2be0 2be0 seq_br_type a Unconditional Return; Flow R typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2be1 2be1 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU 2be2 2be2 <halt> ; Flow R 2be3 2be3 ioc_fiubs 2 typ ioc_load_wdr 0 2be4 2be4 ioc_fiubs 2 typ ioc_load_wdr 0 2be5 2be5 ioc_fiubs 2 typ ioc_load_wdr 0 2be6 2be6 ioc_fiubs 2 typ ioc_load_wdr 0 2be7 2be7 ioc_fiubs 2 typ ioc_load_wdr 0 2be8 2be8 ioc_fiubs 2 typ ioc_load_wdr 0 2be9 2be9 ioc_fiubs 2 typ ioc_load_wdr 0 2bea 2bea ioc_fiubs 2 typ ioc_load_wdr 0 2beb 2beb ioc_fiubs 2 typ ioc_load_wdr 0 2bec 2bec ioc_fiubs 2 typ ioc_load_wdr 0 2bed 2bed ioc_fiubs 2 typ ioc_load_wdr 0 2bee 2bee ioc_fiubs 2 typ ioc_load_wdr 0 2bef 2bef ioc_fiubs 2 typ ioc_load_wdr 0 2bf0 2bf0 ioc_fiubs 2 typ ioc_load_wdr 0 2bf1 2bf1 ioc_fiubs 2 typ ioc_load_wdr 0 2bf2 2bf2 ioc_fiubs 2 typ ioc_load_wdr 0 2bf3 2bf3 ioc_fiubs 2 typ ioc_load_wdr 0 2bf4 2bf4 ioc_fiubs 2 typ ioc_load_wdr 0 2bf5 2bf5 ioc_fiubs 2 typ ioc_load_wdr 0 2bf6 2bf6 ioc_fiubs 2 typ ioc_load_wdr 0 2bf7 2bf7 ioc_fiubs 2 typ ioc_load_wdr 0 2bf8 2bf8 ioc_fiubs 2 typ ioc_load_wdr 0 2bf9 2bf9 ioc_fiubs 2 typ ioc_load_wdr 0 2bfa 2bfa ioc_fiubs 2 typ ioc_load_wdr 0 2bfb 2bfb ioc_fiubs 2 typ ioc_load_wdr 0 2bfc 2bfc ioc_fiubs 2 typ ioc_load_wdr 0 2bfd 2bfd ioc_fiubs 2 typ ioc_load_wdr 0 2bfe 2bfe ioc_fiubs 2 typ ioc_load_wdr 0 2bff 2bff ioc_fiubs 2 typ ioc_load_wdr 0 2c00 2c00 <default>
PyReveng3/R1000.Disassembly disass_ucode.py /tmp/_aa_r1k_dfs/r1k_dfs/be/be4f866b7.tmp.0.18486 /tmp/_aa_r1k_dfs/r1k_dfs/be/be4f866b7.tmp.1.18487
FN /tmp/_aa_r1k_dfs/r1k_dfs/be/be4f866b7.tmp.0.18486
CX <__main__.R1kUcode object at 0x2836e7e247d0> CX.M <word_mem 0x100-0x2c01, @14 bits, 0 attr>
Case table at 0x0819 lacks width <leaf 0x84e-0x84f R1KUCODE>
Case table at 0x0819 lacks width <leaf 0x853-0x854 R1KUCODE>
Case table at 0x200a lacks width <leaf 0x2008-0x2009 R1KUCODE>
Case table at 0x200e lacks width <leaf 0x200c-0x200d R1KUCODE>
? None <leaf 0x2c00-0x2c01 R1KUCODE>
fiu_fill_mode_src 1 {1}
fiu_len_fill_lit 1 {127}
fiu_length_src 1 {1}
fiu_load_mdr 1 {0}
fiu_load_tar 1 {0}
fiu_load_var 1 {0}
fiu_mem_start 1 {2}
fiu_offs_lit 1 {0}
fiu_offset_src 1 {1}
fiu_op_sel 1 {0}
fiu_rdata_src 1 {1}
fiu_tivi_src 1 {0}
fiu_vmux_sel 1 {2}
ioc_adrbs 1 {3}
ioc_fiubs 1 {3}
ioc_load_wdr 1 {1}
ioc_parity 1 {1}
ioc_random 1 {0}
ioc_tvbs 1 {0}
seq_latch 1 {0}
seq_lex_adr 1 {0}
typ_c_lit 1 {3}
typ_c_source 1 {1}
typ_mar_cntl 1 {14}
typ_priv_check 1 {7}
val_c_source 1 {1}
val_m_a_src 1 {3}
val_m_b_src 1 {3}
Stranger in color <Color 113 0x188-0x161e #33> <Stretch 1057 3927> <Color 697 0x400-0x1533 #1804>
Stranger in color <Color 143 0x1a8-0x2be2 #973> <Stretch 1acc 6604> <Color 708 0x600-0x1bfa #1495>
Stranger in color <Color 149 0x1b0-0x26e0 #228> <Stretch 1acc 6604> <Color 708 0x600-0x1bfa #1495>
Stranger in color <Color 220 0x200-0x21b7 #61> <Stretch 1acc 6604> <Color 708 0x600-0x1bfa #1495>
Stranger in color <Color 697 0x400-0x1533 #1804> <Stretch 661 1377> <Color 708 0x600-0x1bfa #1495>
Stranger in color <Color 708 0x600-0x1bfa #1495> <Stretch 1057 3927> <Color 697 0x400-0x1533 #1804>
Stranger in color <Color 718 0x800-0xe56 #274> <Stretch b5c 2652> <Color 770 0xb5c-0xb5c #1>
Stranger in color <Color 719 0x8e7-0x1e78 #382> <Stretch 1acc 6604> <Color 708 0x600-0x1bfa #1495>
Stranger in color <Color 1446 0xe02-0xe46 #4> <Stretch e03 3331> <Color 1447 0xe03-0xe49 #4>
Stranger in color <Color 1447 0xe03-0xe49 #4> <Stretch e04 3332> <Color 1448 0xe04-0xe4c #4>
Stranger in color <Color 1448 0xe04-0xe4c #4> <Stretch e05 3333> <Color 1449 0xe05-0xe51 #6>
Stranger in color <Color 1449 0xe05-0xe51 #6> <Stretch e06 3334> <Color 718 0x800-0xe56 #274>
Stranger in color <Color 1450 0xe07-0xe59 #4> <Stretch e08 3336> <Color 1451 0xe08-0xe5c #4>
Stranger in color <Color 1451 0xe08-0xe5c #4> <Stretch e09 3337> <Color 1452 0xe09-0xe5f #4>
Stranger in color <Color 1452 0xe09-0xe5f #4> <Stretch e0a 3338> <Color 1453 0xe0a-0xe62 #4>
Stranger in color <Color 1453 0xe0a-0xe62 #4> <Stretch e0b 3339> <Color 1454 0xe0b-0xe65 #4>
Stranger in color <Color 1454 0xe0b-0xe65 #4> <Stretch e0c 3340> <Color 1455 0xe0c-0xe68 #4>
Stranger in color <Color 1455 0xe0c-0xe68 #4> <Stretch e0d 3341> <Color 1456 0xe0d-0xe6b #4>
Stranger in color <Color 1456 0xe0d-0xe6b #4> <Stretch e0e 3342> <Color 1457 0xe0e-0xe6e #4>
Stranger in color <Color 1457 0xe0e-0xe6e #4> <Stretch e0f 3343> <Color 1458 0xe0f-0xe71 #4>
Stranger in color <Color 1458 0xe0f-0xe71 #4> <Stretch e10 3344> <Color 1459 0xe10-0xe74 #4>
Stranger in color <Color 1459 0xe10-0xe74 #4> <Stretch e11 3345> <Color 1460 0xe11-0xe77 #4>
Stranger in color <Color 1460 0xe11-0xe77 #4> <Stretch e12 3346> <Color 1461 0xe12-0xe7a #4>
Stranger in color <Color 1461 0xe12-0xe7a #4> <Stretch e13 3347> <Color 1462 0xe13-0xe7d #4>
Stranger in color <Color 1462 0xe13-0xe7d #4> <Stretch e14 3348> <Color 1463 0xe14-0xe80 #4>
Stranger in color <Color 1463 0xe14-0xe80 #4> <Stretch e15 3349> <Color 1464 0xe15-0xe83 #4>
Stranger in color <Color 1464 0xe15-0xe83 #4> <Stretch e16 3350> <Color 1465 0xe16-0xe86 #4>
Stranger in color <Color 1465 0xe16-0xe86 #4> <Stretch e17 3351> <Color 1466 0xe17-0xe89 #4>
Stranger in color <Color 1466 0xe17-0xe89 #4> <Stretch e18 3352> <Color 1467 0xe18-0xe8c #4>
Stranger in color <Color 1467 0xe18-0xe8c #4> <Stretch e19 3353> <Color 1468 0xe19-0xe8f #4>
Stranger in color <Color 1468 0xe19-0xe8f #4> <Stretch e1a 3354> <Color 1469 0xe1a-0xe92 #4>
Stranger in color <Color 1469 0xe1a-0xe92 #4> <Stretch e1b 3355> <Color 1470 0xe1b-0xe95 #4>
Stranger in color <Color 1470 0xe1b-0xe95 #4> <Stretch e1c 3356> <Color 1471 0xe1c-0xe98 #4>
Stranger in color <Color 1471 0xe1c-0xe98 #4> <Stretch e1d 3357> <Color 1472 0xe1d-0xe9b #4>
Stranger in color <Color 1472 0xe1d-0xe9b #4> <Stretch e1e 3358> <Color 1473 0xe1e-0xe9e #4>
Stranger in color <Color 1473 0xe1e-0xe9e #4> <Stretch e1f 3359> <Color 1474 0xe1f-0xea1 #4>
Stranger in color <Color 1474 0xe1f-0xea1 #4> <Stretch e20 3360> <Color 1475 0xe20-0xea4 #4>
Stranger in color <Color 1475 0xe20-0xea4 #4> <Stretch e21 3361> <Color 718 0x800-0xe56 #274>
Stranger in color <Color 2569 0x1c00-0x1d35 #257> <Stretch 1d00 7168> <Color 2570 0x1d00-0x1d30 #49>
Stranger in color <Color 2785 0x1e7c-0x1e90 #20> <Stretch 1e7e 7550> <Color 2786 0x1e7e-0x1e7e #1>
Stranger in color <Color 2839 0x1f0a-0x200e #15> <Stretch 1f88 7816> <Color 2964 0x1f88-0x1f88 #1>
Stranger in color <Color 3088 0x20ae-0x2152 #18> <Stretch 20b3 8115> <Color 3089 0x20b3-0x2156 #35>
Stranger in color <Color 3089 0x20b3-0x2156 #35> <Stretch 20bc 8124> <Color 3090 0x20bc-0x20be #3>
Stranger in color <Color 3091 0x20bf-0x2158 #18> <Stretch 20c4 8132> <Color 3092 0x20c4-0x215c #35>
Stranger in color <Color 3092 0x20c4-0x215c #35> <Stretch 20cd 8141> <Color 3088 0x20ae-0x2152 #18>
PFX /tmp/_aa_r1k_dfs/r1k_dfs/be/be4f866b7.tmp